2 * Carsten Langgaard, carstenl@mips.com
3 * Copyright (C) 1999,2000 MIPS Technologies, Inc. All rights reserved.
5 * This program is free software; you can distribute it and/or modify it
6 * under the terms of the GNU General Public License (Version 2) as
7 * published by the Free Software Foundation.
9 * This program is distributed in the hope it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
14 * You should have received a copy of the GNU General Public License along
15 * with this program; if not, write to the Free Software Foundation, Inc.,
16 * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
18 * Setting up the clock on the MIPS boards.
21 #include <linux/types.h>
22 #include <linux/init.h>
23 #include <linux/kernel_stat.h>
24 #include <linux/sched.h>
25 #include <linux/spinlock.h>
26 #include <linux/interrupt.h>
27 #include <linux/time.h>
28 #include <linux/timex.h>
29 #include <linux/mc146818rtc.h>
31 #include <asm/mipsregs.h>
32 #include <asm/mipsmtregs.h>
33 #include <asm/hardirq.h>
35 #include <asm/div64.h>
38 #include <asm/mc146818-time.h>
39 #include <asm/msc01_ic.h>
41 #include <asm/mips-boards/generic.h>
42 #include <asm/mips-boards/prom.h>
44 #ifdef CONFIG_MIPS_ATLAS
45 #include <asm/mips-boards/atlasint.h>
47 #ifdef CONFIG_MIPS_MALTA
48 #include <asm/mips-boards/maltaint.h>
50 #ifdef CONFIG_MIPS_SEAD
51 #include <asm/mips-boards/seadint.h>
54 unsigned long cpu_khz;
56 #define CPUCTR_IMASKBIT (0x100 << MIPSCPU_INT_CPUCTR)
58 static int mips_cpu_timer_irq;
59 extern void smtc_timer_broadcast(int);
61 static void mips_timer_dispatch(void)
63 do_IRQ(mips_cpu_timer_irq);
67 * Redeclare until I get around mopping the timer code insanity on MIPS.
69 extern int null_perf_irq(void);
71 extern int (*perf_irq)(void);
73 irqreturn_t mips_timer_interrupt(int irq, void *dev_id)
75 int cpu = smp_processor_id();
77 #ifdef CONFIG_MIPS_MT_SMTC
79 * In an SMTC system, one Count/Compare set exists per VPE.
80 * Which TC within a VPE gets the interrupt is essentially
81 * random - we only know that it shouldn't be one with
82 * IXMT set. Whichever TC gets the interrupt needs to
83 * send special interprocessor interrupts to the other
84 * TCs to make sure that they schedule, etc.
86 * That code is specific to the SMTC kernel, not to
87 * the a particular platform, so it's invoked from
88 * the general MIPS timer_interrupt routine.
94 * We could be here due to timer interrupt,
95 * perf counter overflow, or both.
97 if (read_c0_cause() & (1 << 26))
100 if (read_c0_cause() & (1 << 30)) {
101 /* If timer interrupt, make it de-assert */
102 write_c0_compare (read_c0_count() - 1);
104 * DVPE is necessary so long as cross-VPE interrupts
105 * are done via read-modify-write of Cause register.
108 clear_c0_cause(CPUCTR_IMASKBIT);
111 * There are things we only want to do once per tick
112 * in an "MP" system. One TC of each VPE will take
113 * the actual timer interrupt. The others will get
114 * timer broadcast IPIs. We use whoever it is that takes
115 * the tick on VPE 0 to run the full timer_interrupt().
117 if (cpu_data[cpu].vpe_id == 0) {
118 timer_interrupt(irq, NULL);
119 smtc_timer_broadcast(cpu_data[cpu].vpe_id);
121 write_c0_compare(read_c0_count() +
122 (mips_hpt_frequency/HZ));
123 local_timer_interrupt(irq, dev_id);
124 smtc_timer_broadcast(cpu_data[cpu].vpe_id);
127 #else /* CONFIG_MIPS_MT_SMTC */
128 int r2 = cpu_has_mips_r2;
132 * CPU 0 handles the global timer interrupt job and process
133 * accounting resets count/compare registers to trigger next
136 if (!r2 || (read_c0_cause() & (1 << 26)))
140 /* we keep interrupt disabled all the time */
141 if (!r2 || (read_c0_cause() & (1 << 30)))
142 timer_interrupt(irq, NULL);
144 /* Everyone else needs to reset the timer int here as
145 ll_local_timer_interrupt doesn't */
147 * FIXME: need to cope with counter underflow.
148 * More support needs to be added to kernel/time for
149 * counter/timer interrupts on multiple CPU's
151 write_c0_compare(read_c0_count() + (mips_hpt_frequency/HZ));
154 * Other CPUs should do profiling and process accounting
156 local_timer_interrupt(irq, dev_id);
159 #endif /* CONFIG_MIPS_MT_SMTC */
164 * Estimate CPU frequency. Sets mips_hpt_frequency as a side-effect
166 static unsigned int __init estimate_cpu_frequency(void)
168 unsigned int prid = read_c0_prid() & 0xffff00;
171 #if defined(CONFIG_MIPS_SEAD) || defined(CONFIG_MIPS_SIM)
173 * The SEAD board doesn't have a real time clock, so we can't
174 * really calculate the timer frequency
175 * For now we hardwire the SEAD board frequency to 12MHz.
178 if ((prid == (PRID_COMP_MIPS | PRID_IMP_20KC)) ||
179 (prid == (PRID_COMP_MIPS | PRID_IMP_25KF)))
184 #if defined(CONFIG_MIPS_ATLAS) || defined(CONFIG_MIPS_MALTA)
188 local_irq_save(flags);
190 /* Start counter exactly on falling edge of update flag */
191 while (CMOS_READ(RTC_REG_A) & RTC_UIP);
192 while (!(CMOS_READ(RTC_REG_A) & RTC_UIP));
194 /* Start r4k counter. */
195 start = read_c0_count();
197 /* Read counter exactly on falling edge of update flag */
198 while (CMOS_READ(RTC_REG_A) & RTC_UIP);
199 while (!(CMOS_READ(RTC_REG_A) & RTC_UIP));
201 count = read_c0_count() - start;
203 /* restore interrupts */
204 local_irq_restore(flags);
207 mips_hpt_frequency = count;
208 if ((prid != (PRID_COMP_MIPS | PRID_IMP_20KC)) &&
209 (prid != (PRID_COMP_MIPS | PRID_IMP_25KF)))
212 count += 5000; /* round */
213 count -= count%10000;
218 unsigned long __init mips_rtc_get_time(void)
220 return mc146818_get_cmos_time();
223 void __init mips_time_init(void)
225 unsigned int est_freq;
227 /* Set Data mode - binary. */
228 CMOS_WRITE(CMOS_READ(RTC_CONTROL) | RTC_DM_BINARY, RTC_CONTROL);
230 est_freq = estimate_cpu_frequency ();
232 printk("CPU frequency %d.%02d MHz\n", est_freq/1000000,
233 (est_freq%1000000)*100/1000000);
235 cpu_khz = est_freq / 1000;
237 mips_scroll_message();
240 void __init plat_timer_setup(struct irqaction *irq)
242 #ifdef MSC01E_INT_BASE
244 set_vi_handler (MSC01E_INT_CPUCTR, mips_timer_dispatch);
245 mips_cpu_timer_irq = MSC01E_INT_BASE + MSC01E_INT_CPUCTR;
250 set_vi_handler (MIPSCPU_INT_CPUCTR, mips_timer_dispatch);
251 mips_cpu_timer_irq = MIPSCPU_INT_BASE + MIPSCPU_INT_CPUCTR;
255 /* we are using the cpu counter for timer interrupts */
256 irq->handler = mips_timer_interrupt; /* we use our own handler */
257 #ifdef CONFIG_MIPS_MT_SMTC
258 setup_irq_smtc(mips_cpu_timer_irq, irq, CPUCTR_IMASKBIT);
260 setup_irq(mips_cpu_timer_irq, irq);
261 #endif /* CONFIG_MIPS_MT_SMTC */
264 /* irq_desc(riptor) is a global resource, when the interrupt overlaps
265 on seperate cpu's the first one tries to handle the second interrupt.
266 The effect is that the int remains disabled on the second cpu.
267 Mark the interrupt with IRQ_PER_CPU to avoid any confusion */
268 irq_desc[mips_cpu_timer_irq].status |= IRQ_PER_CPU;
269 set_irq_handler(mips_cpu_timer_irq, handle_percpu_irq);