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[linux-3.10.git] / arch / mips / mips-boards / generic / time.c
1 /*
2  * Carsten Langgaard, carstenl@mips.com
3  * Copyright (C) 1999,2000 MIPS Technologies, Inc.  All rights reserved.
4  *
5  *  This program is free software; you can distribute it and/or modify it
6  *  under the terms of the GNU General Public License (Version 2) as
7  *  published by the Free Software Foundation.
8  *
9  *  This program is distributed in the hope it will be useful, but WITHOUT
10  *  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11  *  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
12  *  for more details.
13  *
14  *  You should have received a copy of the GNU General Public License along
15  *  with this program; if not, write to the Free Software Foundation, Inc.,
16  *  59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
17  *
18  * Setting up the clock on the MIPS boards.
19  */
20
21 #include <linux/types.h>
22 #include <linux/init.h>
23 #include <linux/kernel_stat.h>
24 #include <linux/sched.h>
25 #include <linux/spinlock.h>
26 #include <linux/interrupt.h>
27 #include <linux/time.h>
28 #include <linux/timex.h>
29 #include <linux/mc146818rtc.h>
30
31 #include <asm/mipsregs.h>
32 #include <asm/mipsmtregs.h>
33 #include <asm/hardirq.h>
34 #include <asm/i8253.h>
35 #include <asm/irq.h>
36 #include <asm/div64.h>
37 #include <asm/cpu.h>
38 #include <asm/time.h>
39 #include <asm/mc146818-time.h>
40 #include <asm/msc01_ic.h>
41
42 #include <asm/mips-boards/generic.h>
43 #include <asm/mips-boards/prom.h>
44
45 #ifdef CONFIG_MIPS_ATLAS
46 #include <asm/mips-boards/atlasint.h>
47 #endif
48 #ifdef CONFIG_MIPS_MALTA
49 #include <asm/mips-boards/maltaint.h>
50 #endif
51 #ifdef CONFIG_MIPS_SEAD
52 #include <asm/mips-boards/seadint.h>
53 #endif
54
55 unsigned long cpu_khz;
56
57 static int mips_cpu_timer_irq;
58 extern int cp0_perfcount_irq;
59
60 static void mips_timer_dispatch(void)
61 {
62         do_IRQ(mips_cpu_timer_irq);
63 }
64
65 static void mips_perf_dispatch(void)
66 {
67         do_IRQ(cp0_perfcount_irq);
68 }
69
70 /*
71  * Estimate CPU frequency.  Sets mips_hpt_frequency as a side-effect
72  */
73 static unsigned int __init estimate_cpu_frequency(void)
74 {
75         unsigned int prid = read_c0_prid() & 0xffff00;
76         unsigned int count;
77
78 #if defined(CONFIG_MIPS_SEAD) || defined(CONFIG_MIPS_SIM)
79         /*
80          * The SEAD board doesn't have a real time clock, so we can't
81          * really calculate the timer frequency
82          * For now we hardwire the SEAD board frequency to 12MHz.
83          */
84
85         if ((prid == (PRID_COMP_MIPS | PRID_IMP_20KC)) ||
86             (prid == (PRID_COMP_MIPS | PRID_IMP_25KF)))
87                 count = 12000000;
88         else
89                 count = 6000000;
90 #endif
91 #if defined(CONFIG_MIPS_ATLAS) || defined(CONFIG_MIPS_MALTA)
92         unsigned long flags;
93         unsigned int start;
94
95         local_irq_save(flags);
96
97         /* Start counter exactly on falling edge of update flag */
98         while (CMOS_READ(RTC_REG_A) & RTC_UIP);
99         while (!(CMOS_READ(RTC_REG_A) & RTC_UIP));
100
101         /* Start r4k counter. */
102         start = read_c0_count();
103
104         /* Read counter exactly on falling edge of update flag */
105         while (CMOS_READ(RTC_REG_A) & RTC_UIP);
106         while (!(CMOS_READ(RTC_REG_A) & RTC_UIP));
107
108         count = read_c0_count() - start;
109
110         /* restore interrupts */
111         local_irq_restore(flags);
112 #endif
113
114         mips_hpt_frequency = count;
115         if ((prid != (PRID_COMP_MIPS | PRID_IMP_20KC)) &&
116             (prid != (PRID_COMP_MIPS | PRID_IMP_25KF)))
117                 count *= 2;
118
119         count += 5000;    /* round */
120         count -= count%10000;
121
122         return count;
123 }
124
125 unsigned long read_persistent_clock(void)
126 {
127         return mc146818_get_cmos_time();
128 }
129
130 void __init plat_time_init(void)
131 {
132         unsigned int est_freq;
133
134         /* Set Data mode - binary. */
135         CMOS_WRITE(CMOS_READ(RTC_CONTROL) | RTC_DM_BINARY, RTC_CONTROL);
136
137         est_freq = estimate_cpu_frequency();
138
139         printk("CPU frequency %d.%02d MHz\n", est_freq/1000000,
140                (est_freq%1000000)*100/1000000);
141
142         cpu_khz = est_freq / 1000;
143
144         mips_scroll_message();
145 #ifdef CONFIG_I8253             /* Only Malta has a PIT */
146         setup_pit_timer();
147 #endif
148 }
149
150 //static irqreturn_t mips_perf_interrupt(int irq, void *dev_id)
151 //{
152 //      return perf_irq();
153 //}
154
155 //static struct irqaction perf_irqaction = {
156 //      .handler = mips_perf_interrupt,
157 //      .flags = IRQF_DISABLED | IRQF_PERCPU,
158 //      .name = "performance",
159 //};
160
161 void __init plat_perf_setup(void)
162 {
163 //      struct irqaction *irq = &perf_irqaction;
164
165         cp0_perfcount_irq = -1;
166
167 #ifdef MSC01E_INT_BASE
168         if (cpu_has_veic) {
169                 set_vi_handler(MSC01E_INT_PERFCTR, mips_perf_dispatch);
170                 cp0_perfcount_irq = MSC01E_INT_BASE + MSC01E_INT_PERFCTR;
171         } else
172 #endif
173         if (cp0_perfcount_irq >= 0) {
174                 if (cpu_has_vint)
175                         set_vi_handler(cp0_perfcount_irq, mips_perf_dispatch);
176 #ifdef CONFIG_SMP
177                 set_irq_handler(cp0_perfcount_irq, handle_percpu_irq);
178 #endif
179         }
180 }
181
182 void __init plat_timer_setup(struct irqaction *irq)
183 {
184 #ifdef MSC01E_INT_BASE
185         if (cpu_has_veic) {
186                 set_vi_handler(MSC01E_INT_CPUCTR, mips_timer_dispatch);
187                 mips_cpu_timer_irq = MSC01E_INT_BASE + MSC01E_INT_CPUCTR;
188         }
189         else
190 #endif
191         {
192                 if (cpu_has_vint)
193                         set_vi_handler(cp0_compare_irq, mips_timer_dispatch);
194                 mips_cpu_timer_irq = MIPS_CPU_IRQ_BASE + cp0_compare_irq;
195         }
196
197 #ifdef CONFIG_MIPS_MT_SMTC
198         setup_irq_smtc(mips_cpu_timer_irq, irq, 0x100 << cp0_compare_irq);
199 #else
200         setup_irq(mips_cpu_timer_irq, irq);
201 #endif /* CONFIG_MIPS_MT_SMTC */
202 #ifdef CONFIG_SMP
203         set_irq_handler(mips_cpu_timer_irq, handle_percpu_irq);
204 #endif
205
206         plat_perf_setup();
207 }