[ARM] remove duplicate #includes
[linux-3.10.git] / arch / arm / plat-omap / pm.c
1 /*
2  * linux/arch/arm/plat-omap/pm.c
3  *
4  * OMAP Power Management Routines
5  *
6  * Original code for the SA11x0:
7  * Copyright (c) 2001 Cliff Brake <cbrake@accelent.com>
8  *
9  * Modified for the PXA250 by Nicolas Pitre:
10  * Copyright (c) 2002 Monta Vista Software, Inc.
11  *
12  * Modified for the OMAP1510 by David Singleton:
13  * Copyright (c) 2002 Monta Vista Software, Inc.
14  *
15  * Cleanup 2004 for OMAP1510/1610 by Dirk Behme <dirk.behme@de.bosch.com>
16  *
17  * This program is free software; you can redistribute it and/or modify it
18  * under the terms of the GNU General Public License as published by the
19  * Free Software Foundation; either version 2 of the License, or (at your
20  * option) any later version.
21  *
22  * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
23  * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
24  * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
25  * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
26  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
27  * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
28  * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
29  * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
30  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
31  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
32  *
33  * You should have received a copy of the GNU General Public License along
34  * with this program; if not, write to the Free Software Foundation, Inc.,
35  * 675 Mass Ave, Cambridge, MA 02139, USA.
36  */
37
38 #include <linux/pm.h>
39 #include <linux/sched.h>
40 #include <linux/proc_fs.h>
41 #include <linux/interrupt.h>
42
43 #include <asm/io.h>
44 #include <asm/irq.h>
45 #include <asm/mach/time.h>
46 #include <asm/mach/irq.h>
47
48 #include <asm/mach-types.h>
49 #include <asm/arch/irqs.h>
50 #include <asm/arch/tc.h>
51 #include <asm/arch/pm.h>
52 #include <asm/arch/mux.h>
53 #include <asm/arch/tps65010.h>
54 #include <asm/arch/dsp_common.h>
55
56 #include <asm/arch/clock.h>
57 #include <asm/arch/sram.h>
58
59 static unsigned int arm_sleep_save[ARM_SLEEP_SAVE_SIZE];
60 static unsigned short ulpd_sleep_save[ULPD_SLEEP_SAVE_SIZE];
61 static unsigned int mpui730_sleep_save[MPUI730_SLEEP_SAVE_SIZE];
62 static unsigned int mpui1510_sleep_save[MPUI1510_SLEEP_SAVE_SIZE];
63 static unsigned int mpui1610_sleep_save[MPUI1610_SLEEP_SAVE_SIZE];
64
65 static void (*omap_sram_idle)(void) = NULL;
66 static void (*omap_sram_suspend)(unsigned long r0, unsigned long r1) = NULL;
67
68 /*
69  * Let's power down on idle, but only if we are really
70  * idle, because once we start down the path of
71  * going idle we continue to do idle even if we get
72  * a clock tick interrupt . .
73  */
74 void omap_pm_idle(void)
75 {
76         unsigned int mask32 = 0;
77
78         /*
79          * If the DSP is being used let's just idle the CPU, the overhead
80          * to wake up from Big Sleep is big, milliseconds versus micro
81          * seconds for wait for interrupt.
82          */
83
84         local_irq_disable();
85         local_fiq_disable();
86         if (need_resched()) {
87                 local_fiq_enable();
88                 local_irq_enable();
89                 return;
90         }
91         mask32 = omap_readl(ARM_SYSST);
92
93         /*
94          * Prevent the ULPD from entering low power state by setting
95          * POWER_CTRL_REG:4 = 0
96          */
97         omap_writew(omap_readw(ULPD_POWER_CTRL) &
98                     ~ULPD_DEEP_SLEEP_TRANSITION_EN, ULPD_POWER_CTRL);
99
100         /*
101          * Since an interrupt may set up a timer, we don't want to
102          * reprogram the hardware timer with interrupts enabled.
103          * Re-enable interrupts only after returning from idle.
104          */
105         timer_dyn_reprogram();
106
107         if ((mask32 & DSP_IDLE) == 0) {
108                 __asm__ volatile ("mcr  p15, 0, r0, c7, c0, 4");
109         } else
110                 omap_sram_idle();
111
112         local_fiq_enable();
113         local_irq_enable();
114 }
115
116 /*
117  * Configuration of the wakeup event is board specific. For the
118  * moment we put it into this helper function. Later it may move
119  * to board specific files.
120  */
121 static void omap_pm_wakeup_setup(void)
122 {
123         u32 level1_wake = 0;
124         u32 level2_wake = OMAP_IRQ_BIT(INT_UART2);
125
126         /*
127          * Turn off all interrupts except GPIO bank 1, L1-2nd level cascade,
128          * and the L2 wakeup interrupts: keypad and UART2. Note that the
129          * drivers must still separately call omap_set_gpio_wakeup() to
130          * wake up to a GPIO interrupt.
131          */
132         if (cpu_is_omap730())
133                 level1_wake = OMAP_IRQ_BIT(INT_730_GPIO_BANK1) |
134                         OMAP_IRQ_BIT(INT_730_IH2_IRQ);
135         else if (cpu_is_omap1510())
136                 level1_wake = OMAP_IRQ_BIT(INT_GPIO_BANK1) |
137                         OMAP_IRQ_BIT(INT_1510_IH2_IRQ);
138         else if (cpu_is_omap16xx())
139                 level1_wake = OMAP_IRQ_BIT(INT_GPIO_BANK1) |
140                         OMAP_IRQ_BIT(INT_1610_IH2_IRQ);
141
142         omap_writel(~level1_wake, OMAP_IH1_MIR);
143
144         if (cpu_is_omap730()) {
145                 omap_writel(~level2_wake, OMAP_IH2_0_MIR);
146                 omap_writel(~(OMAP_IRQ_BIT(INT_730_WAKE_UP_REQ) | OMAP_IRQ_BIT(INT_730_MPUIO_KEYPAD)), OMAP_IH2_1_MIR);
147         } else if (cpu_is_omap1510()) {
148                 level2_wake |= OMAP_IRQ_BIT(INT_KEYBOARD);
149                 omap_writel(~level2_wake,  OMAP_IH2_MIR);
150         } else if (cpu_is_omap16xx()) {
151                 level2_wake |= OMAP_IRQ_BIT(INT_KEYBOARD);
152                 omap_writel(~level2_wake, OMAP_IH2_0_MIR);
153
154                 /* INT_1610_WAKE_UP_REQ is needed for GPIO wakeup... */
155                 omap_writel(~OMAP_IRQ_BIT(INT_1610_WAKE_UP_REQ), OMAP_IH2_1_MIR);
156                 omap_writel(~0x0, OMAP_IH2_2_MIR);
157                 omap_writel(~0x0, OMAP_IH2_3_MIR);
158         }
159
160         /*  New IRQ agreement, recalculate in cascade order */
161         omap_writel(1, OMAP_IH2_CONTROL);
162         omap_writel(1, OMAP_IH1_CONTROL);
163 }
164
165 void omap_pm_suspend(void)
166 {
167         unsigned long arg0 = 0, arg1 = 0;
168
169         printk("PM: OMAP%x is trying to enter deep sleep...\n", system_rev);
170
171         omap_serial_wake_trigger(1);
172
173         if (machine_is_omap_osk()) {
174                 /* Stop LED1 (D9) blink */
175                 tps65010_set_led(LED1, OFF);
176         }
177
178         omap_writew(0xffff, ULPD_SOFT_DISABLE_REQ_REG);
179
180         /*
181          * Step 1: turn off interrupts (FIXME: NOTE: already disabled)
182          */
183
184         local_irq_disable();
185         local_fiq_disable();
186
187         /*
188          * Step 2: save registers
189          *
190          * The omap is a strange/beautiful device. The caches, memory
191          * and register state are preserved across power saves.
192          * We have to save and restore very little register state to
193          * idle the omap.
194          *
195          * Save interrupt, MPUI, ARM and UPLD control registers.
196          */
197
198         if (cpu_is_omap730()) {
199                 MPUI730_SAVE(OMAP_IH1_MIR);
200                 MPUI730_SAVE(OMAP_IH2_0_MIR);
201                 MPUI730_SAVE(OMAP_IH2_1_MIR);
202                 MPUI730_SAVE(MPUI_CTRL);
203                 MPUI730_SAVE(MPUI_DSP_BOOT_CONFIG);
204                 MPUI730_SAVE(MPUI_DSP_API_CONFIG);
205                 MPUI730_SAVE(EMIFS_CONFIG);
206                 MPUI730_SAVE(EMIFF_SDRAM_CONFIG);
207
208         } else if (cpu_is_omap1510()) {
209                 MPUI1510_SAVE(OMAP_IH1_MIR);
210                 MPUI1510_SAVE(OMAP_IH2_MIR);
211                 MPUI1510_SAVE(MPUI_CTRL);
212                 MPUI1510_SAVE(MPUI_DSP_BOOT_CONFIG);
213                 MPUI1510_SAVE(MPUI_DSP_API_CONFIG);
214                 MPUI1510_SAVE(EMIFS_CONFIG);
215                 MPUI1510_SAVE(EMIFF_SDRAM_CONFIG);
216         } else if (cpu_is_omap16xx()) {
217                 MPUI1610_SAVE(OMAP_IH1_MIR);
218                 MPUI1610_SAVE(OMAP_IH2_0_MIR);
219                 MPUI1610_SAVE(OMAP_IH2_1_MIR);
220                 MPUI1610_SAVE(OMAP_IH2_2_MIR);
221                 MPUI1610_SAVE(OMAP_IH2_3_MIR);
222                 MPUI1610_SAVE(MPUI_CTRL);
223                 MPUI1610_SAVE(MPUI_DSP_BOOT_CONFIG);
224                 MPUI1610_SAVE(MPUI_DSP_API_CONFIG);
225                 MPUI1610_SAVE(EMIFS_CONFIG);
226                 MPUI1610_SAVE(EMIFF_SDRAM_CONFIG);
227         }
228
229         ARM_SAVE(ARM_CKCTL);
230         ARM_SAVE(ARM_IDLECT1);
231         ARM_SAVE(ARM_IDLECT2);
232         if (!(cpu_is_omap1510()))
233                 ARM_SAVE(ARM_IDLECT3);
234         ARM_SAVE(ARM_EWUPCT);
235         ARM_SAVE(ARM_RSTCT1);
236         ARM_SAVE(ARM_RSTCT2);
237         ARM_SAVE(ARM_SYSST);
238         ULPD_SAVE(ULPD_CLOCK_CTRL);
239         ULPD_SAVE(ULPD_STATUS_REQ);
240
241         /* (Step 3 removed - we now allow deep sleep by default) */
242
243         /*
244          * Step 4: OMAP DSP Shutdown
245          */
246
247
248         /*
249          * Step 5: Wakeup Event Setup
250          */
251
252         omap_pm_wakeup_setup();
253
254         /*
255          * Step 6: ARM and Traffic controller shutdown
256          */
257
258         /* disable ARM watchdog */
259         omap_writel(0x00F5, OMAP_WDT_TIMER_MODE);
260         omap_writel(0x00A0, OMAP_WDT_TIMER_MODE);
261
262         /*
263          * Step 6b: ARM and Traffic controller shutdown
264          *
265          * Step 6 continues here. Prepare jump to power management
266          * assembly code in internal SRAM.
267          *
268          * Since the omap_cpu_suspend routine has been copied to
269          * SRAM, we'll do an indirect procedure call to it and pass the
270          * contents of arm_idlect1 and arm_idlect2 so it can restore
271          * them when it wakes up and it will return.
272          */
273
274         arg0 = arm_sleep_save[ARM_SLEEP_SAVE_ARM_IDLECT1];
275         arg1 = arm_sleep_save[ARM_SLEEP_SAVE_ARM_IDLECT2];
276
277         /*
278          * Step 6c: ARM and Traffic controller shutdown
279          *
280          * Jump to assembly code. The processor will stay there
281          * until wake up.
282          */
283         omap_sram_suspend(arg0, arg1);
284
285         /*
286          * If we are here, processor is woken up!
287          */
288
289         /*
290          * Restore ARM state, except ARM_IDLECT1/2 which omap_cpu_suspend did
291          */
292
293         if (!(cpu_is_omap1510()))
294                 ARM_RESTORE(ARM_IDLECT3);
295         ARM_RESTORE(ARM_CKCTL);
296         ARM_RESTORE(ARM_EWUPCT);
297         ARM_RESTORE(ARM_RSTCT1);
298         ARM_RESTORE(ARM_RSTCT2);
299         ARM_RESTORE(ARM_SYSST);
300         ULPD_RESTORE(ULPD_CLOCK_CTRL);
301         ULPD_RESTORE(ULPD_STATUS_REQ);
302
303         if (cpu_is_omap730()) {
304                 MPUI730_RESTORE(EMIFS_CONFIG);
305                 MPUI730_RESTORE(EMIFF_SDRAM_CONFIG);
306                 MPUI730_RESTORE(OMAP_IH1_MIR);
307                 MPUI730_RESTORE(OMAP_IH2_0_MIR);
308                 MPUI730_RESTORE(OMAP_IH2_1_MIR);
309         } else if (cpu_is_omap1510()) {
310                 MPUI1510_RESTORE(MPUI_CTRL);
311                 MPUI1510_RESTORE(MPUI_DSP_BOOT_CONFIG);
312                 MPUI1510_RESTORE(MPUI_DSP_API_CONFIG);
313                 MPUI1510_RESTORE(EMIFS_CONFIG);
314                 MPUI1510_RESTORE(EMIFF_SDRAM_CONFIG);
315                 MPUI1510_RESTORE(OMAP_IH1_MIR);
316                 MPUI1510_RESTORE(OMAP_IH2_MIR);
317         } else if (cpu_is_omap16xx()) {
318                 MPUI1610_RESTORE(MPUI_CTRL);
319                 MPUI1610_RESTORE(MPUI_DSP_BOOT_CONFIG);
320                 MPUI1610_RESTORE(MPUI_DSP_API_CONFIG);
321                 MPUI1610_RESTORE(EMIFS_CONFIG);
322                 MPUI1610_RESTORE(EMIFF_SDRAM_CONFIG);
323
324                 MPUI1610_RESTORE(OMAP_IH1_MIR);
325                 MPUI1610_RESTORE(OMAP_IH2_0_MIR);
326                 MPUI1610_RESTORE(OMAP_IH2_1_MIR);
327                 MPUI1610_RESTORE(OMAP_IH2_2_MIR);
328                 MPUI1610_RESTORE(OMAP_IH2_3_MIR);
329         }
330
331         omap_writew(0, ULPD_SOFT_DISABLE_REQ_REG);
332
333         /*
334          * Reenable interrupts
335          */
336
337         local_irq_enable();
338         local_fiq_enable();
339
340         omap_serial_wake_trigger(0);
341
342         printk("PM: OMAP%x is re-starting from deep sleep...\n", system_rev);
343
344         if (machine_is_omap_osk()) {
345                 /* Let LED1 (D9) blink again */
346                 tps65010_set_led(LED1, BLINK);
347         }
348 }
349
350 #if defined(DEBUG) && defined(CONFIG_PROC_FS)
351 static int g_read_completed;
352
353 /*
354  * Read system PM registers for debugging
355  */
356 static int omap_pm_read_proc(
357         char *page_buffer,
358         char **my_first_byte,
359         off_t virtual_start,
360         int length,
361         int *eof,
362         void *data)
363 {
364         int my_buffer_offset = 0;
365         char * const my_base = page_buffer;
366
367         ARM_SAVE(ARM_CKCTL);
368         ARM_SAVE(ARM_IDLECT1);
369         ARM_SAVE(ARM_IDLECT2);
370         if (!(cpu_is_omap1510()))
371                 ARM_SAVE(ARM_IDLECT3);
372         ARM_SAVE(ARM_EWUPCT);
373         ARM_SAVE(ARM_RSTCT1);
374         ARM_SAVE(ARM_RSTCT2);
375         ARM_SAVE(ARM_SYSST);
376
377         ULPD_SAVE(ULPD_IT_STATUS);
378         ULPD_SAVE(ULPD_CLOCK_CTRL);
379         ULPD_SAVE(ULPD_SOFT_REQ);
380         ULPD_SAVE(ULPD_STATUS_REQ);
381         ULPD_SAVE(ULPD_DPLL_CTRL);
382         ULPD_SAVE(ULPD_POWER_CTRL);
383
384         if (cpu_is_omap730()) {
385                 MPUI730_SAVE(MPUI_CTRL);
386                 MPUI730_SAVE(MPUI_DSP_STATUS);
387                 MPUI730_SAVE(MPUI_DSP_BOOT_CONFIG);
388                 MPUI730_SAVE(MPUI_DSP_API_CONFIG);
389                 MPUI730_SAVE(EMIFF_SDRAM_CONFIG);
390                 MPUI730_SAVE(EMIFS_CONFIG);
391         } else if (cpu_is_omap1510()) {
392                 MPUI1510_SAVE(MPUI_CTRL);
393                 MPUI1510_SAVE(MPUI_DSP_STATUS);
394                 MPUI1510_SAVE(MPUI_DSP_BOOT_CONFIG);
395                 MPUI1510_SAVE(MPUI_DSP_API_CONFIG);
396                 MPUI1510_SAVE(EMIFF_SDRAM_CONFIG);
397                 MPUI1510_SAVE(EMIFS_CONFIG);
398         } else if (cpu_is_omap16xx()) {
399                 MPUI1610_SAVE(MPUI_CTRL);
400                 MPUI1610_SAVE(MPUI_DSP_STATUS);
401                 MPUI1610_SAVE(MPUI_DSP_BOOT_CONFIG);
402                 MPUI1610_SAVE(MPUI_DSP_API_CONFIG);
403                 MPUI1610_SAVE(EMIFF_SDRAM_CONFIG);
404                 MPUI1610_SAVE(EMIFS_CONFIG);
405         }
406
407         if (virtual_start == 0) {
408                 g_read_completed = 0;
409
410                 my_buffer_offset += sprintf(my_base + my_buffer_offset,
411                    "ARM_CKCTL_REG:            0x%-8x     \n"
412                    "ARM_IDLECT1_REG:          0x%-8x     \n"
413                    "ARM_IDLECT2_REG:          0x%-8x     \n"
414                    "ARM_IDLECT3_REG:          0x%-8x     \n"
415                    "ARM_EWUPCT_REG:           0x%-8x     \n"
416                    "ARM_RSTCT1_REG:           0x%-8x     \n"
417                    "ARM_RSTCT2_REG:           0x%-8x     \n"
418                    "ARM_SYSST_REG:            0x%-8x     \n"
419                    "ULPD_IT_STATUS_REG:       0x%-4x     \n"
420                    "ULPD_CLOCK_CTRL_REG:      0x%-4x     \n"
421                    "ULPD_SOFT_REQ_REG:        0x%-4x     \n"
422                    "ULPD_DPLL_CTRL_REG:       0x%-4x     \n"
423                    "ULPD_STATUS_REQ_REG:      0x%-4x     \n"
424                    "ULPD_POWER_CTRL_REG:      0x%-4x     \n",
425                    ARM_SHOW(ARM_CKCTL),
426                    ARM_SHOW(ARM_IDLECT1),
427                    ARM_SHOW(ARM_IDLECT2),
428                    ARM_SHOW(ARM_IDLECT3),
429                    ARM_SHOW(ARM_EWUPCT),
430                    ARM_SHOW(ARM_RSTCT1),
431                    ARM_SHOW(ARM_RSTCT2),
432                    ARM_SHOW(ARM_SYSST),
433                    ULPD_SHOW(ULPD_IT_STATUS),
434                    ULPD_SHOW(ULPD_CLOCK_CTRL),
435                    ULPD_SHOW(ULPD_SOFT_REQ),
436                    ULPD_SHOW(ULPD_DPLL_CTRL),
437                    ULPD_SHOW(ULPD_STATUS_REQ),
438                    ULPD_SHOW(ULPD_POWER_CTRL));
439
440                 if (cpu_is_omap730()) {
441                         my_buffer_offset += sprintf(my_base + my_buffer_offset,
442                            "MPUI730_CTRL_REG         0x%-8x \n"
443                            "MPUI730_DSP_STATUS_REG:      0x%-8x \n"
444                            "MPUI730_DSP_BOOT_CONFIG_REG: 0x%-8x \n"
445          "MPUI730_DSP_API_CONFIG_REG:  0x%-8x \n"
446          "MPUI730_SDRAM_CONFIG_REG:    0x%-8x \n"
447          "MPUI730_EMIFS_CONFIG_REG:    0x%-8x \n",
448          MPUI730_SHOW(MPUI_CTRL),
449          MPUI730_SHOW(MPUI_DSP_STATUS),
450          MPUI730_SHOW(MPUI_DSP_BOOT_CONFIG),
451          MPUI730_SHOW(MPUI_DSP_API_CONFIG),
452          MPUI730_SHOW(EMIFF_SDRAM_CONFIG),
453          MPUI730_SHOW(EMIFS_CONFIG));
454                 } else if (cpu_is_omap1510()) {
455                         my_buffer_offset += sprintf(my_base + my_buffer_offset,
456                            "MPUI1510_CTRL_REG             0x%-8x \n"
457                            "MPUI1510_DSP_STATUS_REG:      0x%-8x \n"
458                            "MPUI1510_DSP_BOOT_CONFIG_REG: 0x%-8x \n"
459                            "MPUI1510_DSP_API_CONFIG_REG:  0x%-8x \n"
460                            "MPUI1510_SDRAM_CONFIG_REG:    0x%-8x \n"
461                            "MPUI1510_EMIFS_CONFIG_REG:    0x%-8x \n",
462                            MPUI1510_SHOW(MPUI_CTRL),
463                            MPUI1510_SHOW(MPUI_DSP_STATUS),
464                            MPUI1510_SHOW(MPUI_DSP_BOOT_CONFIG),
465                            MPUI1510_SHOW(MPUI_DSP_API_CONFIG),
466                            MPUI1510_SHOW(EMIFF_SDRAM_CONFIG),
467                            MPUI1510_SHOW(EMIFS_CONFIG));
468                 } else if (cpu_is_omap16xx()) {
469                         my_buffer_offset += sprintf(my_base + my_buffer_offset,
470                            "MPUI1610_CTRL_REG             0x%-8x \n"
471                            "MPUI1610_DSP_STATUS_REG:      0x%-8x \n"
472                            "MPUI1610_DSP_BOOT_CONFIG_REG: 0x%-8x \n"
473                            "MPUI1610_DSP_API_CONFIG_REG:  0x%-8x \n"
474                            "MPUI1610_SDRAM_CONFIG_REG:    0x%-8x \n"
475                            "MPUI1610_EMIFS_CONFIG_REG:    0x%-8x \n",
476                            MPUI1610_SHOW(MPUI_CTRL),
477                            MPUI1610_SHOW(MPUI_DSP_STATUS),
478                            MPUI1610_SHOW(MPUI_DSP_BOOT_CONFIG),
479                            MPUI1610_SHOW(MPUI_DSP_API_CONFIG),
480                            MPUI1610_SHOW(EMIFF_SDRAM_CONFIG),
481                            MPUI1610_SHOW(EMIFS_CONFIG));
482                 }
483
484                 g_read_completed++;
485         } else if (g_read_completed >= 1) {
486                  *eof = 1;
487                  return 0;
488         }
489         g_read_completed++;
490
491         *my_first_byte = page_buffer;
492         return  my_buffer_offset;
493 }
494
495 static void omap_pm_init_proc(void)
496 {
497         struct proc_dir_entry *entry;
498
499         entry = create_proc_read_entry("driver/omap_pm",
500                                        S_IWUSR | S_IRUGO, NULL,
501            omap_pm_read_proc, NULL);
502 }
503
504 #endif /* DEBUG && CONFIG_PROC_FS */
505
506 /*
507  *      omap_pm_prepare - Do preliminary suspend work.
508  *      @state:         suspend state we're entering.
509  *
510  */
511 //#include <asm/hardware.h>
512
513 static int omap_pm_prepare(suspend_state_t state)
514 {
515         int error = 0;
516
517         switch (state)
518         {
519         case PM_SUSPEND_STANDBY:
520         case PM_SUSPEND_MEM:
521                 break;
522
523         case PM_SUSPEND_DISK:
524                 return -ENOTSUPP;
525
526         default:
527                 return -EINVAL;
528         }
529
530         return error;
531 }
532
533
534 /*
535  *      omap_pm_enter - Actually enter a sleep state.
536  *      @state:         State we're entering.
537  *
538  */
539
540 static int omap_pm_enter(suspend_state_t state)
541 {
542         switch (state)
543         {
544         case PM_SUSPEND_STANDBY:
545         case PM_SUSPEND_MEM:
546                 omap_pm_suspend();
547                 break;
548
549         case PM_SUSPEND_DISK:
550                 return -ENOTSUPP;
551
552         default:
553                 return -EINVAL;
554         }
555
556         return 0;
557 }
558
559
560 /**
561  *      omap_pm_finish - Finish up suspend sequence.
562  *      @state:         State we're coming out of.
563  *
564  *      This is called after we wake back up (or if entering the sleep state
565  *      failed).
566  */
567
568 static int omap_pm_finish(suspend_state_t state)
569 {
570         return 0;
571 }
572
573
574 static irqreturn_t  omap_wakeup_interrupt(int  irq, void *  dev,
575                                      struct pt_regs *  regs)
576 {
577         return IRQ_HANDLED;
578 }
579
580 static struct irqaction omap_wakeup_irq = {
581         .name           = "peripheral wakeup",
582         .flags          = SA_INTERRUPT,
583         .handler        = omap_wakeup_interrupt
584 };
585
586
587
588 static struct pm_ops omap_pm_ops ={
589         .pm_disk_mode = 0,
590         .prepare        = omap_pm_prepare,
591         .enter          = omap_pm_enter,
592         .finish         = omap_pm_finish,
593 };
594
595 static int __init omap_pm_init(void)
596 {
597         printk("Power Management for TI OMAP.\n");
598         /*
599          * We copy the assembler sleep/wakeup routines to SRAM.
600          * These routines need to be in SRAM as that's the only
601          * memory the MPU can see when it wakes up.
602          */
603         if (cpu_is_omap730()) {
604                 omap_sram_idle = omap_sram_push(omap730_idle_loop_suspend,
605                                                 omap730_idle_loop_suspend_sz);
606                 omap_sram_suspend = omap_sram_push(omap730_cpu_suspend,
607          omap730_cpu_suspend_sz);
608         } else if (cpu_is_omap1510()) {
609                 omap_sram_idle = omap_sram_push(omap1510_idle_loop_suspend,
610                                                 omap1510_idle_loop_suspend_sz);
611                 omap_sram_suspend = omap_sram_push(omap1510_cpu_suspend,
612                                                    omap1510_cpu_suspend_sz);
613         } else if (cpu_is_omap16xx()) {
614                 omap_sram_idle = omap_sram_push(omap1610_idle_loop_suspend,
615                                                 omap1610_idle_loop_suspend_sz);
616                 omap_sram_suspend = omap_sram_push(omap1610_cpu_suspend,
617                                                    omap1610_cpu_suspend_sz);
618         }
619
620         if (omap_sram_idle == NULL || omap_sram_suspend == NULL) {
621                 printk(KERN_ERR "PM not initialized: Missing SRAM support\n");
622                 return -ENODEV;
623         }
624
625         pm_idle = omap_pm_idle;
626
627         if (cpu_is_omap730())
628                 setup_irq(INT_730_WAKE_UP_REQ, &omap_wakeup_irq);
629         else if (cpu_is_omap16xx())
630                 setup_irq(INT_1610_WAKE_UP_REQ, &omap_wakeup_irq);
631
632 #if 0
633         /* --- BEGIN BOARD-DEPENDENT CODE --- */
634         /* Sleepx mask direction */
635         omap_writew((omap_readw(0xfffb5008) & ~2), 0xfffb5008);
636         /* Unmask sleepx signal */
637         omap_writew((omap_readw(0xfffb5004) & ~2), 0xfffb5004);
638         /* --- END BOARD-DEPENDENT CODE --- */
639 #endif
640
641         /* Program new power ramp-up time
642          * (0 for most boards since we don't lower voltage when in deep sleep)
643          */
644         omap_writew(ULPD_SETUP_ANALOG_CELL_3_VAL, ULPD_SETUP_ANALOG_CELL_3);
645
646         /* Setup ULPD POWER_CTRL_REG - enter deep sleep whenever possible */
647         omap_writew(ULPD_POWER_CTRL_REG_VAL, ULPD_POWER_CTRL);
648
649         /* Configure IDLECT3 */
650         if (cpu_is_omap730())
651                 omap_writel(OMAP730_IDLECT3_VAL, OMAP730_IDLECT3);
652         else if (cpu_is_omap16xx())
653                 omap_writel(OMAP1610_IDLECT3_VAL, OMAP1610_IDLECT3);
654
655         pm_set_ops(&omap_pm_ops);
656
657 #if defined(DEBUG) && defined(CONFIG_PROC_FS)
658         omap_pm_init_proc();
659 #endif
660
661         if (cpu_is_omap16xx()) {
662                 /* configure LOW_PWR pin */
663                 omap_cfg_reg(T20_1610_LOW_PWR);
664         }
665
666         return 0;
667 }
668 __initcall(omap_pm_init);
669