a7e9b96f258a4b34e9a209dca6b2f7ddb69e8228
[linux-3.10.git] / arch / arm / mach-pxa / mainstone.c
1 /*
2  *  linux/arch/arm/mach-pxa/mainstone.c
3  *
4  *  Support for the Intel HCDDBBVA0 Development Platform.
5  *  (go figure how they came up with such name...)
6  *
7  *  Author:     Nicolas Pitre
8  *  Created:    Nov 05, 2002
9  *  Copyright:  MontaVista Software Inc.
10  *
11  *  This program is free software; you can redistribute it and/or modify
12  *  it under the terms of the GNU General Public License version 2 as
13  *  published by the Free Software Foundation.
14  */
15
16 #include <linux/init.h>
17 #include <linux/platform_device.h>
18 #include <linux/sysdev.h>
19 #include <linux/interrupt.h>
20 #include <linux/sched.h>
21 #include <linux/bitops.h>
22 #include <linux/fb.h>
23 #include <linux/ioport.h>
24 #include <linux/mtd/mtd.h>
25 #include <linux/mtd/partitions.h>
26
27 #include <asm/types.h>
28 #include <asm/setup.h>
29 #include <asm/memory.h>
30 #include <asm/mach-types.h>
31 #include <asm/hardware.h>
32 #include <asm/irq.h>
33 #include <asm/sizes.h>
34
35 #include <asm/mach/arch.h>
36 #include <asm/mach/map.h>
37 #include <asm/mach/irq.h>
38 #include <asm/mach/flash.h>
39
40 #include <asm/arch/pxa-regs.h>
41 #include <asm/arch/mainstone.h>
42 #include <asm/arch/audio.h>
43 #include <asm/arch/pxafb.h>
44 #include <asm/arch/mmc.h>
45 #include <asm/arch/irda.h>
46 #include <asm/arch/ohci.h>
47
48 #include "generic.h"
49
50
51 static unsigned long mainstone_irq_enabled;
52
53 static void mainstone_mask_irq(unsigned int irq)
54 {
55         int mainstone_irq = (irq - MAINSTONE_IRQ(0));
56         MST_INTMSKENA = (mainstone_irq_enabled &= ~(1 << mainstone_irq));
57 }
58
59 static void mainstone_unmask_irq(unsigned int irq)
60 {
61         int mainstone_irq = (irq - MAINSTONE_IRQ(0));
62         /* the irq can be acknowledged only if deasserted, so it's done here */
63         MST_INTSETCLR &= ~(1 << mainstone_irq);
64         MST_INTMSKENA = (mainstone_irq_enabled |= (1 << mainstone_irq));
65 }
66
67 static struct irq_chip mainstone_irq_chip = {
68         .name           = "FPGA",
69         .ack            = mainstone_mask_irq,
70         .mask           = mainstone_mask_irq,
71         .unmask         = mainstone_unmask_irq,
72 };
73
74 static void mainstone_irq_handler(unsigned int irq, struct irqdesc *desc,
75                                   struct pt_regs *regs)
76 {
77         unsigned long pending = MST_INTSETCLR & mainstone_irq_enabled;
78         do {
79                 GEDR(0) = GPIO_bit(0);  /* clear useless edge notification */
80                 if (likely(pending)) {
81                         irq = MAINSTONE_IRQ(0) + __ffs(pending);
82                         desc = irq_desc + irq;
83                         desc_handle_irq(irq, desc, regs);
84                 }
85                 pending = MST_INTSETCLR & mainstone_irq_enabled;
86         } while (pending);
87 }
88
89 static void __init mainstone_init_irq(void)
90 {
91         int irq;
92
93         pxa_init_irq();
94
95         /* setup extra Mainstone irqs */
96         for(irq = MAINSTONE_IRQ(0); irq <= MAINSTONE_IRQ(15); irq++) {
97                 set_irq_chip(irq, &mainstone_irq_chip);
98                 set_irq_handler(irq, do_level_IRQ);
99                 if (irq == MAINSTONE_IRQ(10) || irq == MAINSTONE_IRQ(14))
100                         set_irq_flags(irq, IRQF_VALID | IRQF_PROBE | IRQF_NOAUTOEN);
101                 else
102                         set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
103         }
104         set_irq_flags(MAINSTONE_IRQ(8), 0);
105         set_irq_flags(MAINSTONE_IRQ(12), 0);
106
107         MST_INTMSKENA = 0;
108         MST_INTSETCLR = 0;
109
110         set_irq_chained_handler(IRQ_GPIO(0), mainstone_irq_handler);
111         set_irq_type(IRQ_GPIO(0), IRQT_FALLING);
112 }
113
114 #ifdef CONFIG_PM
115
116 static int mainstone_irq_resume(struct sys_device *dev)
117 {
118         MST_INTMSKENA = mainstone_irq_enabled;
119         return 0;
120 }
121
122 static struct sysdev_class mainstone_irq_sysclass = {
123         set_kset_name("cpld_irq"),
124         .resume = mainstone_irq_resume,
125 };
126
127 static struct sys_device mainstone_irq_device = {
128         .cls = &mainstone_irq_sysclass,
129 };
130
131 static int __init mainstone_irq_device_init(void)
132 {
133         int ret = sysdev_class_register(&mainstone_irq_sysclass);
134         if (ret == 0)
135                 ret = sysdev_register(&mainstone_irq_device);
136         return ret;
137 }
138
139 device_initcall(mainstone_irq_device_init);
140
141 #endif
142
143
144 static struct resource smc91x_resources[] = {
145         [0] = {
146                 .start  = (MST_ETH_PHYS + 0x300),
147                 .end    = (MST_ETH_PHYS + 0xfffff),
148                 .flags  = IORESOURCE_MEM,
149         },
150         [1] = {
151                 .start  = MAINSTONE_IRQ(3),
152                 .end    = MAINSTONE_IRQ(3),
153                 .flags  = IORESOURCE_IRQ,
154         }
155 };
156
157 static struct platform_device smc91x_device = {
158         .name           = "smc91x",
159         .id             = 0,
160         .num_resources  = ARRAY_SIZE(smc91x_resources),
161         .resource       = smc91x_resources,
162 };
163
164 static int mst_audio_startup(struct snd_pcm_substream *substream, void *priv)
165 {
166         if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
167                 MST_MSCWR2 &= ~MST_MSCWR2_AC97_SPKROFF;
168         return 0;
169 }
170
171 static void mst_audio_shutdown(struct snd_pcm_substream *substream, void *priv)
172 {
173         if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
174                 MST_MSCWR2 |= MST_MSCWR2_AC97_SPKROFF;
175 }
176
177 static long mst_audio_suspend_mask;
178
179 static void mst_audio_suspend(void *priv)
180 {
181         mst_audio_suspend_mask = MST_MSCWR2;
182         MST_MSCWR2 |= MST_MSCWR2_AC97_SPKROFF;
183 }
184
185 static void mst_audio_resume(void *priv)
186 {
187         MST_MSCWR2 &= mst_audio_suspend_mask | ~MST_MSCWR2_AC97_SPKROFF;
188 }
189
190 static pxa2xx_audio_ops_t mst_audio_ops = {
191         .startup        = mst_audio_startup,
192         .shutdown       = mst_audio_shutdown,
193         .suspend        = mst_audio_suspend,
194         .resume         = mst_audio_resume,
195 };
196
197 static struct platform_device mst_audio_device = {
198         .name           = "pxa2xx-ac97",
199         .id             = -1,
200         .dev            = { .platform_data = &mst_audio_ops },
201 };
202
203 static struct resource flash_resources[] = {
204         [0] = {
205                 .start  = PXA_CS0_PHYS,
206                 .end    = PXA_CS0_PHYS + SZ_64M - 1,
207                 .flags  = IORESOURCE_MEM,
208         },
209         [1] = {
210                 .start  = PXA_CS1_PHYS,
211                 .end    = PXA_CS1_PHYS + SZ_64M - 1,
212                 .flags  = IORESOURCE_MEM,
213         },
214 };
215
216 static struct mtd_partition mainstoneflash0_partitions[] = {
217         {
218                 .name =         "Bootloader",
219                 .size =         0x00040000,
220                 .offset =       0,
221                 .mask_flags =   MTD_WRITEABLE  /* force read-only */
222         },{
223                 .name =         "Kernel",
224                 .size =         0x00400000,
225                 .offset =       0x00040000,
226         },{
227                 .name =         "Filesystem",
228                 .size =         MTDPART_SIZ_FULL,
229                 .offset =       0x00440000
230         }
231 };
232
233 static struct flash_platform_data mst_flash_data[2] = {
234         {
235                 .map_name       = "cfi_probe",
236                 .parts          = mainstoneflash0_partitions,
237                 .nr_parts       = ARRAY_SIZE(mainstoneflash0_partitions),
238         }, {
239                 .map_name       = "cfi_probe",
240                 .parts          = NULL,
241                 .nr_parts       = 0,
242         }
243 };
244
245 static struct platform_device mst_flash_device[2] = {
246         {
247                 .name           = "pxa2xx-flash",
248                 .id             = 0,
249                 .dev = {
250                         .platform_data = &mst_flash_data[0],
251                 },
252                 .resource = &flash_resources[0],
253                 .num_resources = 1,
254         },
255         {
256                 .name           = "pxa2xx-flash",
257                 .id             = 1,
258                 .dev = {
259                         .platform_data = &mst_flash_data[1],
260                 },
261                 .resource = &flash_resources[1],
262                 .num_resources = 1,
263         },
264 };
265
266 static void mainstone_backlight_power(int on)
267 {
268         if (on) {
269                 pxa_gpio_mode(GPIO16_PWM0_MD);
270                 pxa_set_cken(CKEN0_PWM0, 1);
271                 PWM_CTRL0 = 0;
272                 PWM_PWDUTY0 = 0x3ff;
273                 PWM_PERVAL0 = 0x3ff;
274         } else {
275                 PWM_CTRL0 = 0;
276                 PWM_PWDUTY0 = 0x0;
277                 PWM_PERVAL0 = 0x3FF;
278                 pxa_set_cken(CKEN0_PWM0, 0);
279         }
280 }
281
282 static struct pxafb_mach_info toshiba_ltm04c380k __initdata = {
283         .pixclock               = 50000,
284         .xres                   = 640,
285         .yres                   = 480,
286         .bpp                    = 16,
287         .hsync_len              = 1,
288         .left_margin            = 0x9f,
289         .right_margin           = 1,
290         .vsync_len              = 44,
291         .upper_margin           = 0,
292         .lower_margin           = 0,
293         .sync                   = FB_SYNC_HOR_HIGH_ACT|FB_SYNC_VERT_HIGH_ACT,
294         .lccr0                  = LCCR0_Act,
295         .lccr3                  = LCCR3_PCP,
296         .pxafb_backlight_power  = mainstone_backlight_power,
297 };
298
299 static struct pxafb_mach_info toshiba_ltm035a776c __initdata = {
300         .pixclock               = 110000,
301         .xres                   = 240,
302         .yres                   = 320,
303         .bpp                    = 16,
304         .hsync_len              = 4,
305         .left_margin            = 8,
306         .right_margin           = 20,
307         .vsync_len              = 3,
308         .upper_margin           = 1,
309         .lower_margin           = 10,
310         .sync                   = FB_SYNC_HOR_HIGH_ACT|FB_SYNC_VERT_HIGH_ACT,
311         .lccr0                  = LCCR0_Act,
312         .lccr3                  = LCCR3_PCP,
313         .pxafb_backlight_power  = mainstone_backlight_power,
314 };
315
316 static int mainstone_mci_init(struct device *dev, irqreturn_t (*mstone_detect_int)(int, void *, struct pt_regs *), void *data)
317 {
318         int err;
319
320         /*
321          * setup GPIO for PXA27x MMC controller
322          */
323         pxa_gpio_mode(GPIO32_MMCCLK_MD);
324         pxa_gpio_mode(GPIO112_MMCCMD_MD);
325         pxa_gpio_mode(GPIO92_MMCDAT0_MD);
326         pxa_gpio_mode(GPIO109_MMCDAT1_MD);
327         pxa_gpio_mode(GPIO110_MMCDAT2_MD);
328         pxa_gpio_mode(GPIO111_MMCDAT3_MD);
329
330         /* make sure SD/Memory Stick multiplexer's signals
331          * are routed to MMC controller
332          */
333         MST_MSCWR1 &= ~MST_MSCWR1_MS_SEL;
334
335         err = request_irq(MAINSTONE_MMC_IRQ, mstone_detect_int, IRQF_DISABLED,
336                              "MMC card detect", data);
337         if (err) {
338                 printk(KERN_ERR "mainstone_mci_init: MMC/SD: can't request MMC card detect IRQ\n");
339                 return -1;
340         }
341
342         return 0;
343 }
344
345 static void mainstone_mci_setpower(struct device *dev, unsigned int vdd)
346 {
347         struct pxamci_platform_data* p_d = dev->platform_data;
348
349         if (( 1 << vdd) & p_d->ocr_mask) {
350                 printk(KERN_DEBUG "%s: on\n", __FUNCTION__);
351                 MST_MSCWR1 |= MST_MSCWR1_MMC_ON;
352                 MST_MSCWR1 &= ~MST_MSCWR1_MS_SEL;
353         } else {
354                 printk(KERN_DEBUG "%s: off\n", __FUNCTION__);
355                 MST_MSCWR1 &= ~MST_MSCWR1_MMC_ON;
356         }
357 }
358
359 static void mainstone_mci_exit(struct device *dev, void *data)
360 {
361         free_irq(MAINSTONE_MMC_IRQ, data);
362 }
363
364 static struct pxamci_platform_data mainstone_mci_platform_data = {
365         .ocr_mask       = MMC_VDD_32_33|MMC_VDD_33_34,
366         .init           = mainstone_mci_init,
367         .setpower       = mainstone_mci_setpower,
368         .exit           = mainstone_mci_exit,
369 };
370
371 static void mainstone_irda_transceiver_mode(struct device *dev, int mode)
372 {
373         unsigned long flags;
374
375         local_irq_save(flags);
376         if (mode & IR_SIRMODE) {
377                 MST_MSCWR1 &= ~MST_MSCWR1_IRDA_FIR;
378         } else if (mode & IR_FIRMODE) {
379                 MST_MSCWR1 |= MST_MSCWR1_IRDA_FIR;
380         }
381         if (mode & IR_OFF) {
382                 MST_MSCWR1 = (MST_MSCWR1 & ~MST_MSCWR1_IRDA_MASK) | MST_MSCWR1_IRDA_OFF;
383         } else {
384                 MST_MSCWR1 = (MST_MSCWR1 & ~MST_MSCWR1_IRDA_MASK) | MST_MSCWR1_IRDA_FULL;
385         }
386         local_irq_restore(flags);
387 }
388
389 static struct pxaficp_platform_data mainstone_ficp_platform_data = {
390         .transceiver_cap  = IR_SIRMODE | IR_FIRMODE | IR_OFF,
391         .transceiver_mode = mainstone_irda_transceiver_mode,
392 };
393
394 static struct platform_device *platform_devices[] __initdata = {
395         &smc91x_device,
396         &mst_audio_device,
397         &mst_flash_device[0],
398         &mst_flash_device[1],
399 };
400
401 static int mainstone_ohci_init(struct device *dev)
402 {
403         /* setup Port1 GPIO pin. */
404         pxa_gpio_mode( 88 | GPIO_ALT_FN_1_IN);  /* USBHPWR1 */
405         pxa_gpio_mode( 89 | GPIO_ALT_FN_2_OUT); /* USBHPEN1 */
406
407         /* Set the Power Control Polarity Low and Power Sense
408            Polarity Low to active low. */
409         UHCHR = (UHCHR | UHCHR_PCPL | UHCHR_PSPL) &
410                 ~(UHCHR_SSEP1 | UHCHR_SSEP2 | UHCHR_SSEP3 | UHCHR_SSE);
411
412         return 0;
413 }
414
415 static struct pxaohci_platform_data mainstone_ohci_platform_data = {
416         .port_mode      = PMM_PERPORT_MODE,
417         .init           = mainstone_ohci_init,
418 };
419
420 static void __init mainstone_init(void)
421 {
422         int SW7 = 0;  /* FIXME: get from SCR (Mst doc section 3.2.1.1) */
423
424         mst_flash_data[0].width = (BOOT_DEF & 1) ? 2 : 4;
425         mst_flash_data[1].width = 4;
426
427         /* Compensate for SW7 which swaps the flash banks */
428         mst_flash_data[SW7].name = "processor-flash";
429         mst_flash_data[SW7 ^ 1].name = "mainboard-flash";
430
431         printk(KERN_NOTICE "Mainstone configured to boot from %s\n",
432                mst_flash_data[0].name);
433
434         /* system bus arbiter setting
435          * - Core_Park
436          * - LCD_wt:DMA_wt:CORE_Wt = 2:3:4
437          */
438         ARB_CNTRL = ARB_CORE_PARK | 0x234;
439
440         /*
441          * On Mainstone, we route AC97_SYSCLK via GPIO45 to
442          * the audio daughter card
443          */
444         pxa_gpio_mode(GPIO45_SYSCLK_AC97_MD);
445
446         platform_add_devices(platform_devices, ARRAY_SIZE(platform_devices));
447
448         /* reading Mainstone's "Virtual Configuration Register"
449            might be handy to select LCD type here */
450         if (0)
451                 set_pxa_fb_info(&toshiba_ltm04c380k);
452         else
453                 set_pxa_fb_info(&toshiba_ltm035a776c);
454
455         pxa_set_mci_info(&mainstone_mci_platform_data);
456         pxa_set_ficp_info(&mainstone_ficp_platform_data);
457         pxa_set_ohci_info(&mainstone_ohci_platform_data);
458 }
459
460
461 static struct map_desc mainstone_io_desc[] __initdata = {
462         {       /* CPLD */
463                 .virtual        =  MST_FPGA_VIRT,
464                 .pfn            = __phys_to_pfn(MST_FPGA_PHYS),
465                 .length         = 0x00100000,
466                 .type           = MT_DEVICE
467         }
468 };
469
470 static void __init mainstone_map_io(void)
471 {
472         pxa_map_io();
473         iotable_init(mainstone_io_desc, ARRAY_SIZE(mainstone_io_desc));
474
475         /* initialize sleep mode regs (wake-up sources, etc) */
476         PGSR0 = 0x00008800;
477         PGSR1 = 0x00000002;
478         PGSR2 = 0x0001FC00;
479         PGSR3 = 0x00001F81;
480         PWER  = 0xC0000002;
481         PRER  = 0x00000002;
482         PFER  = 0x00000002;
483         /*      for use I SRAM as framebuffer.  */
484         PSLR |= 0xF04;
485         PCFR = 0x66;
486         /*      For Keypad wakeup.      */
487         KPC &=~KPC_ASACT;
488         KPC |=KPC_AS;
489         PKWR  = 0x000FD000;
490         /*      Need read PKWR back after set it.       */
491         PKWR;
492 }
493
494 MACHINE_START(MAINSTONE, "Intel HCDDBBVA0 Development Platform (aka Mainstone)")
495         /* Maintainer: MontaVista Software Inc. */
496         .phys_io        = 0x40000000,
497         .boot_params    = 0xa0000100,   /* BLOB boot parameter setting */
498         .io_pg_offst    = (io_p2v(0x40000000) >> 18) & 0xfffc,
499         .map_io         = mainstone_map_io,
500         .init_irq       = mainstone_init_irq,
501         .timer          = &pxa_timer,
502         .init_machine   = mainstone_init,
503 MACHINE_END