[ARM] 3848/1: pxafb: Add option of fixing video modes and spitz QVGA mode support
[linux-3.10.git] / arch / arm / mach-pxa / lpd270.c
1 /*
2  * linux/arch/arm/mach-pxa/lpd270.c
3  *
4  * Support for the LogicPD PXA270 Card Engine.
5  * Derived from the mainstone code, which carries these notices:
6  *
7  * Author:      Nicolas Pitre
8  * Created:     Nov 05, 2002
9  * Copyright:   MontaVista Software Inc.
10  *
11  * This program is free software; you can redistribute it and/or modify
12  * it under the terms of the GNU General Public License version 2 as
13  * published by the Free Software Foundation.
14  */
15
16 #include <linux/init.h>
17 #include <linux/platform_device.h>
18 #include <linux/sysdev.h>
19 #include <linux/interrupt.h>
20 #include <linux/sched.h>
21 #include <linux/bitops.h>
22 #include <linux/fb.h>
23 #include <linux/ioport.h>
24 #include <linux/mtd/mtd.h>
25 #include <linux/mtd/partitions.h>
26
27 #include <asm/types.h>
28 #include <asm/setup.h>
29 #include <asm/memory.h>
30 #include <asm/mach-types.h>
31 #include <asm/hardware.h>
32 #include <asm/irq.h>
33 #include <asm/sizes.h>
34
35 #include <asm/mach/arch.h>
36 #include <asm/mach/map.h>
37 #include <asm/mach/irq.h>
38 #include <asm/mach/flash.h>
39
40 #include <asm/arch/pxa-regs.h>
41 #include <asm/arch/lpd270.h>
42 #include <asm/arch/audio.h>
43 #include <asm/arch/pxafb.h>
44 #include <asm/arch/mmc.h>
45 #include <asm/arch/irda.h>
46 #include <asm/arch/ohci.h>
47
48 #include "generic.h"
49
50
51 static unsigned int lpd270_irq_enabled;
52
53 static void lpd270_mask_irq(unsigned int irq)
54 {
55         int lpd270_irq = irq - LPD270_IRQ(0);
56
57         __raw_writew(~(1 << lpd270_irq), LPD270_INT_STATUS);
58
59         lpd270_irq_enabled &= ~(1 << lpd270_irq);
60         __raw_writew(lpd270_irq_enabled, LPD270_INT_MASK);
61 }
62
63 static void lpd270_unmask_irq(unsigned int irq)
64 {
65         int lpd270_irq = irq - LPD270_IRQ(0);
66
67         lpd270_irq_enabled |= 1 << lpd270_irq;
68         __raw_writew(lpd270_irq_enabled, LPD270_INT_MASK);
69 }
70
71 static struct irq_chip lpd270_irq_chip = {
72         .name           = "CPLD",
73         .ack            = lpd270_mask_irq,
74         .mask           = lpd270_mask_irq,
75         .unmask         = lpd270_unmask_irq,
76 };
77
78 static void lpd270_irq_handler(unsigned int irq, struct irqdesc *desc,
79                                   struct pt_regs *regs)
80 {
81         unsigned long pending;
82
83         pending = __raw_readw(LPD270_INT_STATUS) & lpd270_irq_enabled;
84         do {
85                 GEDR(0) = GPIO_bit(0);  /* clear useless edge notification */
86                 if (likely(pending)) {
87                         irq = LPD270_IRQ(0) + __ffs(pending);
88                         desc = irq_desc + irq;
89                         desc_handle_irq(irq, desc, regs);
90
91                         pending = __raw_readw(LPD270_INT_STATUS) &
92                                                 lpd270_irq_enabled;
93                 }
94         } while (pending);
95 }
96
97 static void __init lpd270_init_irq(void)
98 {
99         int irq;
100
101         pxa_init_irq();
102
103         __raw_writew(0, LPD270_INT_MASK);
104         __raw_writew(0, LPD270_INT_STATUS);
105
106         /* setup extra LogicPD PXA270 irqs */
107         for (irq = LPD270_IRQ(2); irq <= LPD270_IRQ(4); irq++) {
108                 set_irq_chip(irq, &lpd270_irq_chip);
109                 set_irq_handler(irq, do_level_IRQ);
110                 set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
111         }
112         set_irq_chained_handler(IRQ_GPIO(0), lpd270_irq_handler);
113         set_irq_type(IRQ_GPIO(0), IRQT_FALLING);
114 }
115
116
117 #ifdef CONFIG_PM
118 static int lpd270_irq_resume(struct sys_device *dev)
119 {
120         __raw_writew(lpd270_irq_enabled, LPD270_INT_MASK);
121         return 0;
122 }
123
124 static struct sysdev_class lpd270_irq_sysclass = {
125         set_kset_name("cpld_irq"),
126         .resume = lpd270_irq_resume,
127 };
128
129 static struct sys_device lpd270_irq_device = {
130         .cls = &lpd270_irq_sysclass,
131 };
132
133 static int __init lpd270_irq_device_init(void)
134 {
135         int ret = sysdev_class_register(&lpd270_irq_sysclass);
136         if (ret == 0)
137                 ret = sysdev_register(&lpd270_irq_device);
138         return ret;
139 }
140
141 device_initcall(lpd270_irq_device_init);
142 #endif
143
144
145 static struct resource smc91x_resources[] = {
146         [0] = {
147                 .start  = LPD270_ETH_PHYS,
148                 .end    = (LPD270_ETH_PHYS + 0xfffff),
149                 .flags  = IORESOURCE_MEM,
150         },
151         [1] = {
152                 .start  = LPD270_ETHERNET_IRQ,
153                 .end    = LPD270_ETHERNET_IRQ,
154                 .flags  = IORESOURCE_IRQ,
155         },
156 };
157
158 static struct platform_device smc91x_device = {
159         .name           = "smc91x",
160         .id             = 0,
161         .num_resources  = ARRAY_SIZE(smc91x_resources),
162         .resource       = smc91x_resources,
163 };
164
165 static struct platform_device lpd270_audio_device = {
166         .name           = "pxa2xx-ac97",
167         .id             = -1,
168 };
169
170 static struct resource lpd270_flash_resources[] = {
171         [0] = {
172                 .start  = PXA_CS0_PHYS,
173                 .end    = PXA_CS0_PHYS + SZ_64M - 1,
174                 .flags  = IORESOURCE_MEM,
175         },
176         [1] = {
177                 .start  = PXA_CS1_PHYS,
178                 .end    = PXA_CS1_PHYS + SZ_64M - 1,
179                 .flags  = IORESOURCE_MEM,
180         },
181 };
182
183 static struct mtd_partition lpd270_flash0_partitions[] = {
184         {
185                 .name =         "Bootloader",
186                 .size =         0x00040000,
187                 .offset =       0,
188                 .mask_flags =   MTD_WRITEABLE  /* force read-only */
189         }, {
190                 .name =         "Kernel",
191                 .size =         0x00400000,
192                 .offset =       0x00040000,
193         }, {
194                 .name =         "Filesystem",
195                 .size =         MTDPART_SIZ_FULL,
196                 .offset =       0x00440000
197         },
198 };
199
200 static struct flash_platform_data lpd270_flash_data[2] = {
201         {
202                 .name           = "processor-flash",
203                 .map_name       = "cfi_probe",
204                 .parts          = lpd270_flash0_partitions,
205                 .nr_parts       = ARRAY_SIZE(lpd270_flash0_partitions),
206         }, {
207                 .name           = "mainboard-flash",
208                 .map_name       = "cfi_probe",
209                 .parts          = NULL,
210                 .nr_parts       = 0,
211         }
212 };
213
214 static struct platform_device lpd270_flash_device[2] = {
215         {
216                 .name           = "pxa2xx-flash",
217                 .id             = 0,
218                 .dev = {
219                         .platform_data  = &lpd270_flash_data[0],
220                 },
221                 .resource       = &lpd270_flash_resources[0],
222                 .num_resources  = 1,
223         }, {
224                 .name           = "pxa2xx-flash",
225                 .id             = 1,
226                 .dev = {
227                         .platform_data  = &lpd270_flash_data[1],
228                 },
229                 .resource       = &lpd270_flash_resources[1],
230                 .num_resources  = 1,
231         },
232 };
233
234 static void lpd270_backlight_power(int on)
235 {
236         if (on) {
237                 pxa_gpio_mode(GPIO16_PWM0_MD);
238                 pxa_set_cken(CKEN0_PWM0, 1);
239                 PWM_CTRL0 = 0;
240                 PWM_PWDUTY0 = 0x3ff;
241                 PWM_PERVAL0 = 0x3ff;
242         } else {
243                 PWM_CTRL0 = 0;
244                 PWM_PWDUTY0 = 0x0;
245                 PWM_PERVAL0 = 0x3FF;
246                 pxa_set_cken(CKEN0_PWM0, 0);
247         }
248 }
249
250 /* 5.7" TFT QVGA (LoLo display number 1) */
251 static struct pxafb_mode_info sharp_lq057q3dc02_mode = {
252         .pixclock               = 150000,
253         .xres                   = 320,
254         .yres                   = 240,
255         .bpp                    = 16,
256         .hsync_len              = 0x14,
257         .left_margin            = 0x28,
258         .right_margin           = 0x0a,
259         .vsync_len              = 0x02,
260         .upper_margin           = 0x08,
261         .lower_margin           = 0x14,
262         .sync                   = FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
263 };
264
265 static struct pxafb_mach_info sharp_lq057q3dc02 = {
266         .modes                  = &sharp_lq057q3dc02_mode,
267         .num_modes              = 1,
268         .lccr0                  = 0x07800080,
269         .lccr3                  = 0x00400000,
270         .pxafb_backlight_power  = lpd270_backlight_power,
271 };
272
273 /* 12.1" TFT SVGA (LoLo display number 2) */
274 static struct pxafb_mode_info sharp_lq121s1dg31_mode = {
275         .pixclock               = 50000,
276         .xres                   = 800,
277         .yres                   = 600,
278         .bpp                    = 16,
279         .hsync_len              = 0x05,
280         .left_margin            = 0x52,
281         .right_margin           = 0x05,
282         .vsync_len              = 0x04,
283         .upper_margin           = 0x14,
284         .lower_margin           = 0x0a,
285         .sync                   = FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
286 };
287
288 static struct pxafb_mach_info sharp_lq121s1dg31 = {
289         .modes                  = &sharp_lq121s1dg31_mode,
290         .num_modes              = 1,
291         .lccr0                  = 0x07800080,
292         .lccr3                  = 0x00400000,
293         .pxafb_backlight_power  = lpd270_backlight_power,
294 };
295
296 /* 3.6" TFT QVGA (LoLo display number 3) */
297 static struct pxafb_mode_info sharp_lq036q1da01_mode = {
298         .pixclock               = 150000,
299         .xres                   = 320,
300         .yres                   = 240,
301         .bpp                    = 16,
302         .hsync_len              = 0x0e,
303         .left_margin            = 0x04,
304         .right_margin           = 0x0a,
305         .vsync_len              = 0x03,
306         .upper_margin           = 0x03,
307         .lower_margin           = 0x03,
308         .sync                   = FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
309 };
310
311 static struct pxafb_mach_info sharp_lq036q1da01 = {
312         .modes                  = &sharp_lq036q1da01_mode,
313         .num_modes              = 1,
314         .lccr0                  = 0x07800080,
315         .lccr3                  = 0x00400000,
316         .pxafb_backlight_power  = lpd270_backlight_power,
317 };
318
319 /* 6.4" TFT VGA (LoLo display number 5) */
320 static struct pxafb_mode_info sharp_lq64d343_mode = {
321         .pixclock               = 25000,
322         .xres                   = 640,
323         .yres                   = 480,
324         .bpp                    = 16,
325         .hsync_len              = 0x31,
326         .left_margin            = 0x89,
327         .right_margin           = 0x19,
328         .vsync_len              = 0x12,
329         .upper_margin           = 0x22,
330         .lower_margin           = 0x00,
331         .sync                   = FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
332 };
333
334 static struct pxafb_mach_info sharp_lq64d343 = {
335         .modes                  = &sharp_lq64d343_mode,
336         .num_modes              = 1,
337         .lccr0                  = 0x07800080,
338         .lccr3                  = 0x00400000,
339         .pxafb_backlight_power  = lpd270_backlight_power,
340 };
341
342 /* 10.4" TFT VGA (LoLo display number 7) */
343 static struct pxafb_mode_info sharp_lq10d368_mode = {
344         .pixclock               = 25000,
345         .xres                   = 640,
346         .yres                   = 480,
347         .bpp                    = 16,
348         .hsync_len              = 0x31,
349         .left_margin            = 0x89,
350         .right_margin           = 0x19,
351         .vsync_len              = 0x12,
352         .upper_margin           = 0x22,
353         .lower_margin           = 0x00,
354         .sync                   = FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
355 };
356
357 static struct pxafb_mach_info sharp_lq10d368 = {
358         .modes                  = &sharp_lq10d368_mode,
359         .num_modes              = 1,
360         .lccr0                  = 0x07800080,
361         .lccr3                  = 0x00400000,
362         .pxafb_backlight_power  = lpd270_backlight_power,
363 };
364
365 /* 3.5" TFT QVGA (LoLo display number 8) */
366 static struct pxafb_mode_info sharp_lq035q7db02_20_mode = {
367         .pixclock               = 150000,
368         .xres                   = 240,
369         .yres                   = 320,
370         .bpp                    = 16,
371         .hsync_len              = 0x0e,
372         .left_margin            = 0x0a,
373         .right_margin           = 0x0a,
374         .vsync_len              = 0x03,
375         .upper_margin           = 0x05,
376         .lower_margin           = 0x14,
377         .sync                   = FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
378 };
379
380 static struct pxafb_mach_info sharp_lq035q7db02_20 = {
381         .modes                  = &sharp_lq035q7db02_20_mode,
382         .num_modes              = 1,
383         .lccr0                  = 0x07800080,
384         .lccr3                  = 0x00400000,
385         .pxafb_backlight_power  = lpd270_backlight_power,
386 };
387
388 static struct pxafb_mach_info *lpd270_lcd_to_use;
389
390 static int __init lpd270_set_lcd(char *str)
391 {
392         if (!strnicmp(str, "lq057q3dc02", 11)) {
393                 lpd270_lcd_to_use = &sharp_lq057q3dc02;
394         } else if (!strnicmp(str, "lq121s1dg31", 11)) {
395                 lpd270_lcd_to_use = &sharp_lq121s1dg31;
396         } else if (!strnicmp(str, "lq036q1da01", 11)) {
397                 lpd270_lcd_to_use = &sharp_lq036q1da01;
398         } else if (!strnicmp(str, "lq64d343", 8)) {
399                 lpd270_lcd_to_use = &sharp_lq64d343;
400         } else if (!strnicmp(str, "lq10d368", 8)) {
401                 lpd270_lcd_to_use = &sharp_lq10d368;
402         } else if (!strnicmp(str, "lq035q7db02-20", 14)) {
403                 lpd270_lcd_to_use = &sharp_lq035q7db02_20;
404         } else {
405                 printk(KERN_INFO "lpd270: unknown lcd panel [%s]\n", str);
406         }
407
408         return 1;
409 }
410
411 __setup("lcd=", lpd270_set_lcd);
412
413 static struct platform_device *platform_devices[] __initdata = {
414         &smc91x_device,
415         &lpd270_audio_device,
416         &lpd270_flash_device[0],
417         &lpd270_flash_device[1],
418 };
419
420 static int lpd270_ohci_init(struct device *dev)
421 {
422         /* setup Port1 GPIO pin. */
423         pxa_gpio_mode(88 | GPIO_ALT_FN_1_IN);   /* USBHPWR1 */
424         pxa_gpio_mode(89 | GPIO_ALT_FN_2_OUT);  /* USBHPEN1 */
425
426         /* Set the Power Control Polarity Low and Power Sense
427            Polarity Low to active low. */
428         UHCHR = (UHCHR | UHCHR_PCPL | UHCHR_PSPL) &
429                 ~(UHCHR_SSEP1 | UHCHR_SSEP2 | UHCHR_SSEP3 | UHCHR_SSE);
430
431         return 0;
432 }
433
434 static struct pxaohci_platform_data lpd270_ohci_platform_data = {
435         .port_mode      = PMM_PERPORT_MODE,
436         .init           = lpd270_ohci_init,
437 };
438
439 static void __init lpd270_init(void)
440 {
441         lpd270_flash_data[0].width = (BOOT_DEF & 1) ? 2 : 4;
442         lpd270_flash_data[1].width = 4;
443
444         /*
445          * System bus arbiter setting:
446          * - Core_Park
447          * - LCD_wt:DMA_wt:CORE_Wt = 2:3:4
448          */
449         ARB_CNTRL = ARB_CORE_PARK | 0x234;
450
451         /*
452          * On LogicPD PXA270, we route AC97_SYSCLK via GPIO45.
453          */
454         pxa_gpio_mode(GPIO45_SYSCLK_AC97_MD);
455
456         platform_add_devices(platform_devices, ARRAY_SIZE(platform_devices));
457
458         if (lpd270_lcd_to_use != NULL)
459                 set_pxa_fb_info(lpd270_lcd_to_use);
460
461         pxa_set_ohci_info(&lpd270_ohci_platform_data);
462 }
463
464
465 static struct map_desc lpd270_io_desc[] __initdata = {
466         {
467                 .virtual        = LPD270_CPLD_VIRT,
468                 .pfn            = __phys_to_pfn(LPD270_CPLD_PHYS),
469                 .length         = LPD270_CPLD_SIZE,
470                 .type           = MT_DEVICE,
471         },
472 };
473
474 static void __init lpd270_map_io(void)
475 {
476         pxa_map_io();
477         iotable_init(lpd270_io_desc, ARRAY_SIZE(lpd270_io_desc));
478
479         /* initialize sleep mode regs (wake-up sources, etc) */
480         PGSR0 = 0x00008800;
481         PGSR1 = 0x00000002;
482         PGSR2 = 0x0001FC00;
483         PGSR3 = 0x00001F81;
484         PWER  = 0xC0000002;
485         PRER  = 0x00000002;
486         PFER  = 0x00000002;
487
488         /* for use I SRAM as framebuffer.  */
489         PSLR |= 0x00000F04;
490         PCFR  = 0x00000066;
491 }
492
493 MACHINE_START(LOGICPD_PXA270, "LogicPD PXA270 Card Engine")
494         /* Maintainer: Peter Barada */
495         .phys_io        = 0x40000000,
496         .io_pg_offst    = (io_p2v(0x40000000) >> 18) & 0xfffc,
497         .boot_params    = 0xa0000100,
498         .map_io         = lpd270_map_io,
499         .init_irq       = lpd270_init_irq,
500         .timer          = &pxa_timer,
501         .init_machine   = lpd270_init,
502 MACHINE_END