e702e0cb899e251c40f77de2eeef64f1de1d6ced
[linux-3.10.git] / arch / arm / mach-omap1 / serial.c
1 /*
2  * linux/arch/arm/mach-omap1/id.c
3  *
4  * OMAP1 CPU identification code
5  *
6  * This program is free software; you can redistribute it and/or modify
7  * it under the terms of the GNU General Public License version 2 as
8  * published by the Free Software Foundation.
9  */
10
11 #include <linux/config.h>
12 #include <linux/module.h>
13 #include <linux/kernel.h>
14 #include <linux/init.h>
15 #include <linux/delay.h>
16 #include <linux/serial.h>
17 #include <linux/tty.h>
18 #include <linux/serial_8250.h>
19 #include <linux/serial_reg.h>
20
21 #include <asm/io.h>
22 #include <asm/mach-types.h>
23 #include <asm/hardware/clock.h>
24
25 #include <asm/arch/board.h>
26 #include <asm/arch/mux.h>
27 #include <asm/arch/gpio.h>
28 #include <asm/arch/fpga.h>
29 #ifdef CONFIG_PM
30 #include <asm/arch/pm.h>
31 #endif
32
33 static struct clk * uart1_ck = NULL;
34 static struct clk * uart2_ck = NULL;
35 static struct clk * uart3_ck = NULL;
36
37 static inline unsigned int omap_serial_in(struct plat_serial8250_port *up,
38                                           int offset)
39 {
40         offset <<= up->regshift;
41         return (unsigned int)__raw_readb(up->membase + offset);
42 }
43
44 static inline void omap_serial_outp(struct plat_serial8250_port *p, int offset,
45                                     int value)
46 {
47         offset <<= p->regshift;
48         __raw_writeb(value, p->membase + offset);
49 }
50
51 /*
52  * Internal UARTs need to be initialized for the 8250 autoconfig to work
53  * properly. Note that the TX watermark initialization may not be needed
54  * once the 8250.c watermark handling code is merged.
55  */
56 static void __init omap_serial_reset(struct plat_serial8250_port *p)
57 {
58         omap_serial_outp(p, UART_OMAP_MDR1, 0x07);      /* disable UART */
59         omap_serial_outp(p, UART_OMAP_SCR, 0x08);       /* TX watermark */
60         omap_serial_outp(p, UART_OMAP_MDR1, 0x00);      /* enable UART */
61
62         if (!cpu_is_omap1510()) {
63                 omap_serial_outp(p, UART_OMAP_SYSC, 0x01);
64                 while (!(omap_serial_in(p, UART_OMAP_SYSC) & 0x01));
65         }
66 }
67
68 static struct plat_serial8250_port serial_platform_data[] = {
69         {
70                 .membase        = (char*)IO_ADDRESS(OMAP_UART1_BASE),
71                 .mapbase        = (unsigned long)OMAP_UART1_BASE,
72                 .irq            = INT_UART1,
73                 .flags          = UPF_BOOT_AUTOCONF,
74                 .iotype         = UPIO_MEM,
75                 .regshift       = 2,
76                 .uartclk        = OMAP16XX_BASE_BAUD * 16,
77         },
78         {
79                 .membase        = (char*)IO_ADDRESS(OMAP_UART2_BASE),
80                 .mapbase        = (unsigned long)OMAP_UART2_BASE,
81                 .irq            = INT_UART2,
82                 .flags          = UPF_BOOT_AUTOCONF,
83                 .iotype         = UPIO_MEM,
84                 .regshift       = 2,
85                 .uartclk        = OMAP16XX_BASE_BAUD * 16,
86         },
87         {
88                 .membase        = (char*)IO_ADDRESS(OMAP_UART3_BASE),
89                 .mapbase        = (unsigned long)OMAP_UART3_BASE,
90                 .irq            = INT_UART3,
91                 .flags          = UPF_BOOT_AUTOCONF,
92                 .iotype         = UPIO_MEM,
93                 .regshift       = 2,
94                 .uartclk        = OMAP16XX_BASE_BAUD * 16,
95         },
96         { },
97 };
98
99 static struct platform_device serial_device = {
100         .name                   = "serial8250",
101         .id                     = 0,
102         .dev                    = {
103                 .platform_data  = serial_platform_data,
104         },
105 };
106
107 /*
108  * Note that on Innovator-1510 UART2 pins conflict with USB2.
109  * By default UART2 does not work on Innovator-1510 if you have
110  * USB OHCI enabled. To use UART2, you must disable USB2 first.
111  */
112 void __init omap_serial_init(int ports[OMAP_MAX_NR_PORTS])
113 {
114         int i;
115
116         if (cpu_is_omap730()) {
117                 serial_platform_data[0].regshift = 0;
118                 serial_platform_data[1].regshift = 0;
119                 serial_platform_data[0].irq = INT_730_UART_MODEM_1;
120                 serial_platform_data[1].irq = INT_730_UART_MODEM_IRDA_2;
121         }
122
123         if (cpu_is_omap1510()) {
124                 serial_platform_data[0].uartclk = OMAP1510_BASE_BAUD * 16;
125                 serial_platform_data[1].uartclk = OMAP1510_BASE_BAUD * 16;
126                 serial_platform_data[2].uartclk = OMAP1510_BASE_BAUD * 16;
127         }
128
129         for (i = 0; i < OMAP_MAX_NR_PORTS; i++) {
130                 unsigned char reg;
131
132                 if (ports[i] == 0) {
133                         serial_platform_data[i].membase = NULL;
134                         serial_platform_data[i].mapbase = 0;
135                         continue;
136                 }
137
138                 switch (i) {
139                 case 0:
140                         uart1_ck = clk_get(NULL, "uart1_ck");
141                         if (IS_ERR(uart1_ck))
142                                 printk("Could not get uart1_ck\n");
143                         else {
144                                 clk_use(uart1_ck);
145                                 if (cpu_is_omap1510())
146                                         clk_set_rate(uart1_ck, 12000000);
147                         }
148                         if (cpu_is_omap1510()) {
149                                 omap_cfg_reg(UART1_TX);
150                                 omap_cfg_reg(UART1_RTS);
151                                 if (machine_is_omap_innovator()) {
152                                         reg = fpga_read(OMAP1510_FPGA_POWER);
153                                         reg |= OMAP1510_FPGA_PCR_COM1_EN;
154                                         fpga_write(reg, OMAP1510_FPGA_POWER);
155                                         udelay(10);
156                                 }
157                         }
158                         break;
159                 case 1:
160                         uart2_ck = clk_get(NULL, "uart2_ck");
161                         if (IS_ERR(uart2_ck))
162                                 printk("Could not get uart2_ck\n");
163                         else {
164                                 clk_use(uart2_ck);
165                                 if (cpu_is_omap1510())
166                                         clk_set_rate(uart2_ck, 12000000);
167                                 else
168                                         clk_set_rate(uart2_ck, 48000000);
169                         }
170                         if (cpu_is_omap1510()) {
171                                 omap_cfg_reg(UART2_TX);
172                                 omap_cfg_reg(UART2_RTS);
173                                 if (machine_is_omap_innovator()) {
174                                         reg = fpga_read(OMAP1510_FPGA_POWER);
175                                         reg |= OMAP1510_FPGA_PCR_COM2_EN;
176                                         fpga_write(reg, OMAP1510_FPGA_POWER);
177                                         udelay(10);
178                                 }
179                         }
180                         break;
181                 case 2:
182                         uart3_ck = clk_get(NULL, "uart3_ck");
183                         if (IS_ERR(uart3_ck))
184                                 printk("Could not get uart3_ck\n");
185                         else {
186                                 clk_use(uart3_ck);
187                                 if (cpu_is_omap1510())
188                                         clk_set_rate(uart3_ck, 12000000);
189                         }
190                         if (cpu_is_omap1510()) {
191                                 omap_cfg_reg(UART3_TX);
192                                 omap_cfg_reg(UART3_RX);
193                         }
194                         break;
195                 }
196                 omap_serial_reset(&serial_platform_data[i]);
197         }
198 }
199
200 #ifdef CONFIG_OMAP_SERIAL_WAKE
201
202 static irqreturn_t omap_serial_wake_interrupt(int irq, void *dev_id,
203                                               struct pt_regs *regs)
204 {
205         /* Need to do something with serial port right after wake-up? */
206         return IRQ_HANDLED;
207 }
208
209 /*
210  * Reroutes serial RX lines to GPIO lines for the duration of
211  * sleep to allow waking up the device from serial port even
212  * in deep sleep.
213  */
214 void omap_serial_wake_trigger(int enable)
215 {
216         if (!cpu_is_omap16xx())
217                 return;
218
219         if (uart1_ck != NULL) {
220                 if (enable)
221                         omap_cfg_reg(V14_16XX_GPIO37);
222                 else
223                         omap_cfg_reg(V14_16XX_UART1_RX);
224         }
225         if (uart2_ck != NULL) {
226                 if (enable)
227                         omap_cfg_reg(R9_16XX_GPIO18);
228                 else
229                         omap_cfg_reg(R9_16XX_UART2_RX);
230         }
231         if (uart3_ck != NULL) {
232                 if (enable)
233                         omap_cfg_reg(L14_16XX_GPIO49);
234                 else
235                         omap_cfg_reg(L14_16XX_UART3_RX);
236         }
237 }
238
239 static void __init omap_serial_set_port_wakeup(int gpio_nr)
240 {
241         int ret;
242
243         ret = omap_request_gpio(gpio_nr);
244         if (ret < 0) {
245                 printk(KERN_ERR "Could not request UART wake GPIO: %i\n",
246                        gpio_nr);
247                 return;
248         }
249         omap_set_gpio_direction(gpio_nr, 1);
250         set_irq_type(OMAP_GPIO_IRQ(gpio_nr), IRQT_RISING);
251         ret = request_irq(OMAP_GPIO_IRQ(gpio_nr), &omap_serial_wake_interrupt,
252                           0, "serial wakeup", NULL);
253         if (ret) {
254                 omap_free_gpio(gpio_nr);
255                 printk(KERN_ERR "No interrupt for UART wake GPIO: %i\n",
256                        gpio_nr);
257                 return;
258         }
259         enable_irq_wake(OMAP_GPIO_IRQ(gpio_nr));
260 }
261
262 static int __init omap_serial_wakeup_init(void)
263 {
264         if (!cpu_is_omap16xx())
265                 return 0;
266
267         if (uart1_ck != NULL)
268                 omap_serial_set_port_wakeup(37);
269         if (uart2_ck != NULL)
270                 omap_serial_set_port_wakeup(18);
271         if (uart3_ck != NULL)
272                 omap_serial_set_port_wakeup(49);
273
274         return 0;
275 }
276 late_initcall(omap_serial_wakeup_init);
277
278 #endif  /* CONFIG_OMAP_SERIAL_WAKE */
279
280 static int __init omap_init(void)
281 {
282         return platform_device_register(&serial_device);
283 }
284 arch_initcall(omap_init);