]> nv-tegra.nvidia Code Review - linux-2.6.git/commitdiff
[CPUFREQ] Fix up merge conflicts with recent ACPI changes.
authorDave Jones <davej@redhat.com>
Sun, 11 Feb 2007 01:36:29 +0000 (20:36 -0500)
committerDave Jones <davej@redhat.com>
Sun, 11 Feb 2007 01:36:29 +0000 (20:36 -0500)
Signed-off-by: Dave Jones <davej@redhat.com>
1  2 
arch/i386/kernel/cpu/cpufreq/longhaul.c

index 8f40cb47720e390a1a83836ad72e4e6d042508cb,a3db9332d652eccbc9c3745b55aaf309c4eebbe7..fa5cac255c16e32f0e2e19562b92ef8874fa740b
@@@ -177,34 -170,16 +177,34 @@@ static void do_powersaver(int cx_addres
        longhaul.bits.RevisionKey = longhaul.bits.RevisionID;
        longhaul.bits.SoftBusRatio = clock_ratio_index & 0xf;
        longhaul.bits.SoftBusRatio4 = (clock_ratio_index & 0x10) >> 4;
 -      longhaul.bits.EnableSoftBusRatio = 1;
 -
 -      if (can_scale_voltage) {
 +      /* Setup new voltage */
 +      if (can_scale_voltage)
                longhaul.bits.SoftVID = f_msr_table[clock_ratio_index].vrm;
 +      /* Sync to timer tick */
 +      safe_halt();
 +      /* Raise voltage if necessary */
 +      if (can_scale_voltage && longhaul_pos < dest_pos) {
                longhaul.bits.EnableSoftVID = 1;
-                       t = inl(acpi_fadt.xpm_tmr_blk.address);
 +              wrmsrl(MSR_VIA_LONGHAUL, longhaul.val);
 +              /* Change voltage */
 +              if (!cx_address) {
 +                      ACPI_FLUSH_CPU_CACHE();
 +                      halt();
 +              } else {
 +                      ACPI_FLUSH_CPU_CACHE();
 +                      /* Invoke C3 */
 +                      inb(cx_address);
 +                      /* Dummy op - must do something useless after P_LVL3
 +                       * read */
++                      t = inl(acpi_gbl_FADT.xpm_timer_block.address);
 +              }
 +              longhaul.bits.EnableSoftVID = 0;
 +              wrmsrl(MSR_VIA_LONGHAUL, longhaul.val);
 +              longhaul_pos = dest_pos;
        }
  
 -      /* Sync to timer tick */
 -      safe_halt();
        /* Change frequency on next halt or sleep */
 +      longhaul.bits.EnableSoftBusRatio = 1;
        wrmsrl(MSR_VIA_LONGHAUL, longhaul.val);
        if (!cx_address) {
                ACPI_FLUSH_CPU_CACHE();
                /* Invoke C3 */
                inb(cx_address);
                /* Dummy op - must do something useless after P_LVL3 read */
-               t = inl(acpi_fadt.xpm_tmr_blk.address);
+               t = inl(acpi_gbl_FADT.xpm_timer_block.address);
        }
        /* Disable bus ratio bit */
 -      local_irq_disable();
 -      longhaul.bits.RevisionKey = longhaul.bits.RevisionID;
        longhaul.bits.EnableSoftBusRatio = 0;
 -      longhaul.bits.EnableSoftBSEL = 0;
 -      longhaul.bits.EnableSoftVID = 0;
        wrmsrl(MSR_VIA_LONGHAUL, longhaul.val);
-                       t = inl(acpi_fadt.xpm_tmr_blk.address);
 +
 +      /* Reduce voltage if necessary */
 +      if (can_scale_voltage && longhaul_pos > dest_pos) {
 +              longhaul.bits.EnableSoftVID = 1;
 +              wrmsrl(MSR_VIA_LONGHAUL, longhaul.val);
 +              /* Change voltage */
 +              if (!cx_address) {
 +                      ACPI_FLUSH_CPU_CACHE();
 +                      halt();
 +              } else {
 +                      ACPI_FLUSH_CPU_CACHE();
 +                      /* Invoke C3 */
 +                      inb(cx_address);
 +                      /* Dummy op - must do something useless after P_LVL3
 +                       * read */
++                      t = inl(acpi_gbl_FADT.xpm_timer_block.address);
 +              }
 +              longhaul.bits.EnableSoftVID = 0;
 +              wrmsrl(MSR_VIA_LONGHAUL, longhaul.val);
 +              longhaul_pos = dest_pos;
 +      }
  }
  
  /**
@@@ -505,32 -496,6 +502,33 @@@ static void __init longhaul_setup_volta
                minvid.mV/1000, minvid.mV%1000,
                numvscales);
  
 +      /* Calculate max frequency at min voltage */
 +      j = longhaul.bits.MinMHzBR;
 +      if (longhaul.bits.MinMHzBR4)
 +              j += 16;
 +      min_vid_speed = eblcr_table[j];
 +      if (min_vid_speed == -1)
 +              return;
 +      switch (longhaul.bits.MinMHzFSB) {
 +      case 0:
 +              min_vid_speed *= 13333;
 +              break;
 +      case 1:
 +              min_vid_speed *= 10000;
 +              break;
 +      case 3:
 +              min_vid_speed *= 6666;
 +              break;
 +      default:
 +              return;
 +              break;
 +      }
 +      if (min_vid_speed >= highest_speed)
 +              return;
 +      /* Calculate kHz for one voltage step */
 +      kHz_step = (highest_speed - min_vid_speed) / numvscales;
 +
++
        j = 0;
        while (longhaul_table[j].frequency != CPUFREQ_TABLE_END) {
                speed = longhaul_table[j].frequency;