Merge branch 'master' into upstream
authorJeff Garzik <jeff@garzik.org>
Sat, 20 May 2006 04:03:38 +0000 (00:03 -0400)
committerJeff Garzik <jeff@garzik.org>
Sat, 20 May 2006 04:03:38 +0000 (00:03 -0400)
57 files changed:
Documentation/networking/README.ipw2200
MAINTAINERS
drivers/net/Kconfig
drivers/net/Makefile
drivers/net/au1000_eth.c
drivers/net/cassini.c
drivers/net/e1000/Makefile
drivers/net/e1000/e1000.h
drivers/net/e1000/e1000_ethtool.c
drivers/net/e1000/e1000_hw.c
drivers/net/e1000/e1000_hw.h
drivers/net/e1000/e1000_main.c
drivers/net/e1000/e1000_osdep.h
drivers/net/e1000/e1000_param.c
drivers/net/s2io-regs.h
drivers/net/s2io.c
drivers/net/s2io.h
drivers/net/sis900.c
drivers/net/sis900.h
drivers/net/smc911x.c [new file with mode: 0644]
drivers/net/smc911x.h [new file with mode: 0644]
drivers/net/smc91x.h
drivers/net/wan/pci200syn.c
drivers/net/wireless/Kconfig
drivers/net/wireless/airo.c
drivers/net/wireless/bcm43xx/bcm43xx.h
drivers/net/wireless/bcm43xx/bcm43xx_debugfs.c
drivers/net/wireless/bcm43xx/bcm43xx_main.c
drivers/net/wireless/hermes.c
drivers/net/wireless/hermes.h
drivers/net/wireless/ipw2200.c
drivers/net/wireless/ipw2200.h
drivers/net/wireless/orinoco.c
drivers/net/wireless/orinoco.h
drivers/net/wireless/orinoco_cs.c
drivers/net/wireless/orinoco_nortel.c
drivers/net/wireless/orinoco_pci.c
drivers/net/wireless/orinoco_pci.h [new file with mode: 0644]
drivers/net/wireless/orinoco_plx.c
drivers/net/wireless/orinoco_tmd.c
drivers/net/wireless/spectrum_cs.c
drivers/s390/net/Makefile
drivers/s390/net/ctcmain.c
drivers/s390/net/ctcmain.h
drivers/s390/net/ctctty.c [deleted file]
drivers/s390/net/ctctty.h [deleted file]
include/linux/pci_ids.h
include/net/ieee80211.h
include/net/ieee80211softmac_wx.h
net/ieee80211/ieee80211_crypt_tkip.c
net/ieee80211/ieee80211_rx.c
net/ieee80211/ieee80211_tx.c
net/ieee80211/ieee80211_wx.c
net/ieee80211/softmac/ieee80211softmac_assoc.c
net/ieee80211/softmac/ieee80211softmac_event.c
net/ieee80211/softmac/ieee80211softmac_priv.h
net/ieee80211/softmac/ieee80211softmac_wx.c

index acb30c5dcff333e11f9f9fd72957b71b3a9af02c..4f2a40f1dbc629837463a96695759e3848f41c68 100644 (file)
@@ -14,8 +14,8 @@ Copyright (C) 2004-2006, Intel Corporation
 
 README.ipw2200
 
-Version: 1.0.8
-Date   : October 20, 2005
+Version: 1.1.2
+Date   : March 30, 2006
 
 
 Index
@@ -103,7 +103,7 @@ file.
 
 1.1. Overview of Features
 -----------------------------------------------
-The current release (1.0.8) supports the following features:
+The current release (1.1.2) supports the following features:
 
 + BSS mode (Infrastructure, Managed)
 + IBSS mode (Ad-Hoc)
@@ -247,8 +247,8 @@ and can set the contents via echo.  For example:
 % cat /sys/bus/pci/drivers/ipw2200/debug_level
 
 Will report the current debug level of the driver's logging subsystem 
-(only available if CONFIG_IPW_DEBUG was configured when the driver was 
-built).
+(only available if CONFIG_IPW2200_DEBUG was configured when the driver
+was built).
 
 You can set the debug level via:
 
index 753584cf4e7e30a50224a8e908dc6fa695e2336f..69398f0bfc27c2d5d456da87d3f4abf109768056 100644 (file)
@@ -1404,6 +1404,8 @@ P:        Jesse Brandeburg
 M:     jesse.brandeburg@intel.com
 P:     Jeff Kirsher
 M:     jeffrey.t.kirsher@intel.com
+P:     Auke Kok
+M:     auke-jan.h.kok@intel.com
 W:     http://sourceforge.net/projects/e1000/
 S:     Supported
 
@@ -1416,6 +1418,8 @@ P:        Jesse Brandeburg
 M:     jesse.brandeburg@intel.com
 P:     Jeff Kirsher
 M:     jeffrey.t.kirsher@intel.com
+P:     Auke Kok
+M:     auke-jan.h.kok@intel.com
 W:     http://sourceforge.net/projects/e1000/
 S:     Supported
 
@@ -1428,6 +1432,8 @@ P:        John Ronciak
 M:     john.ronciak@intel.com
 P:     Jesse Brandeburg
 M:     jesse.brandeburg@intel.com
+P:     Auke Kok
+M:     auke-jan.h.kok@intel.com
 W:     http://sourceforge.net/projects/e1000/
 S:     Supported
 
index bdaaad8f2123d5410c1985ceb526e200bb1958e6..68bc073b8b31f9e65cc300482cecb8db2f27a16a 100644 (file)
@@ -865,6 +865,22 @@ config DM9000
          <file:Documentation/networking/net-modules.txt>.  The module will be
          called dm9000.
 
+config SMC911X
+       tristate "SMSC LAN911[5678] support"
+       select CRC32
+       select MII
+       depends on NET_ETHERNET
+       help
+         This is a driver for SMSC's LAN911x series of Ethernet chipsets
+         including the new LAN9115, LAN9116, LAN9117, and LAN9118.
+         Say Y if you want it compiled into the kernel, 
+         and read the Ethernet-HOWTO, available from
+         <http://www.linuxdoc.org/docs.html#howto>.
+
+         This driver is also available as a module. The module will be 
+         called smc911x.  If you want to compile it as a module, say M 
+         here and read <file:Documentation/modules.txt>
+
 config NET_VENDOR_RACAL
        bool "Racal-Interlan (Micom) NI cards"
        depends on NET_ETHERNET && ISA
index b90468aea077aee9a2b5ee95f10acd7869fd72aa..b01cc9a3cb10db0b012843b5a06f38f099aaef13 100644 (file)
@@ -193,6 +193,7 @@ obj-$(CONFIG_AMD8111_ETH) += amd8111e.o
 obj-$(CONFIG_IBMVETH) += ibmveth.o
 obj-$(CONFIG_S2IO) += s2io.o
 obj-$(CONFIG_SMC91X) += smc91x.o
+obj-$(CONFIG_SMC911X) += smc911x.o
 obj-$(CONFIG_DM9000) += dm9000.o
 obj-$(CONFIG_FEC_8XX) += fec_8xx/
 
index 14dbad14afb64da8be9d94f57d74be1579d2f1d7..e1fe960d71b371a520f7a0c9869ee67d25bed17c 100644 (file)
@@ -2,7 +2,7 @@
  *
  * Alchemy Au1x00 ethernet driver
  *
- * Copyright 2001,2002,2003 MontaVista Software Inc.
+ * Copyright 2001-2003, 2006 MontaVista Software Inc.
  * Copyright 2002 TimeSys Corp.
  * Added ethtool/mii-tool support,
  * Copyright 2004 Matt Porter <mporter@kernel.crashing.org>
@@ -68,7 +68,7 @@ static int au1000_debug = 5;
 static int au1000_debug = 3;
 #endif
 
-#define DRV_NAME       "au1000eth"
+#define DRV_NAME       "au1000_eth"
 #define DRV_VERSION    "1.5"
 #define DRV_AUTHOR     "Pete Popov <ppopov@embeddedalley.com>"
 #define DRV_DESC       "Au1xxx on-chip Ethernet driver"
@@ -80,7 +80,7 @@ MODULE_LICENSE("GPL");
 // prototypes
 static void hard_stop(struct net_device *);
 static void enable_rx_tx(struct net_device *dev);
-static struct net_device * au1000_probe(u32 ioaddr, int irq, int port_num);
+static struct net_device * au1000_probe(int port_num);
 static int au1000_init(struct net_device *);
 static int au1000_open(struct net_device *);
 static int au1000_close(struct net_device *);
@@ -1160,12 +1160,27 @@ setup_hw_rings(struct au1000_private *aup, u32 rx_base, u32 tx_base)
 }
 
 static struct {
-       int port;
        u32 base_addr;
        u32 macen_addr;
        int irq;
        struct net_device *dev;
-} iflist[2];
+} iflist[2] = {
+#ifdef CONFIG_SOC_AU1000
+       {AU1000_ETH0_BASE, AU1000_MAC0_ENABLE, AU1000_MAC0_DMA_INT},
+       {AU1000_ETH1_BASE, AU1000_MAC1_ENABLE, AU1000_MAC1_DMA_INT}
+#endif
+#ifdef CONFIG_SOC_AU1100
+       {AU1100_ETH0_BASE, AU1100_MAC0_ENABLE, AU1100_MAC0_DMA_INT}
+#endif
+#ifdef CONFIG_SOC_AU1500
+       {AU1500_ETH0_BASE, AU1500_MAC0_ENABLE, AU1500_MAC0_DMA_INT},
+       {AU1500_ETH1_BASE, AU1500_MAC1_ENABLE, AU1500_MAC1_DMA_INT}
+#endif
+#ifdef CONFIG_SOC_AU1550
+       {AU1550_ETH0_BASE, AU1550_MAC0_ENABLE, AU1550_MAC0_DMA_INT},
+       {AU1550_ETH1_BASE, AU1550_MAC1_ENABLE, AU1550_MAC1_DMA_INT}
+#endif
+};
 
 static int num_ifs;
 
@@ -1176,58 +1191,14 @@ static int num_ifs;
  */
 static int __init au1000_init_module(void)
 {
-       struct cpuinfo_mips *c = &current_cpu_data;
        int ni = (int)((au_readl(SYS_PINFUNC) & (u32)(SYS_PF_NI2)) >> 4);
        struct net_device *dev;
        int i, found_one = 0;
 
-       switch (c->cputype) {
-#ifdef CONFIG_SOC_AU1000
-       case CPU_AU1000:
-               num_ifs = 2 - ni;
-               iflist[0].base_addr = AU1000_ETH0_BASE;
-               iflist[1].base_addr = AU1000_ETH1_BASE;
-               iflist[0].macen_addr = AU1000_MAC0_ENABLE;
-               iflist[1].macen_addr = AU1000_MAC1_ENABLE;
-               iflist[0].irq = AU1000_MAC0_DMA_INT;
-               iflist[1].irq = AU1000_MAC1_DMA_INT;
-               break;
-#endif
-#ifdef CONFIG_SOC_AU1100
-       case CPU_AU1100:
-               num_ifs = 1 - ni;
-               iflist[0].base_addr = AU1100_ETH0_BASE;
-               iflist[0].macen_addr = AU1100_MAC0_ENABLE;
-               iflist[0].irq = AU1100_MAC0_DMA_INT;
-               break;
-#endif
-#ifdef CONFIG_SOC_AU1500
-       case CPU_AU1500:
-               num_ifs = 2 - ni;
-               iflist[0].base_addr = AU1500_ETH0_BASE;
-               iflist[1].base_addr = AU1500_ETH1_BASE;
-               iflist[0].macen_addr = AU1500_MAC0_ENABLE;
-               iflist[1].macen_addr = AU1500_MAC1_ENABLE;
-               iflist[0].irq = AU1500_MAC0_DMA_INT;
-               iflist[1].irq = AU1500_MAC1_DMA_INT;
-               break;
-#endif
-#ifdef CONFIG_SOC_AU1550
-       case CPU_AU1550:
-               num_ifs = 2 - ni;
-               iflist[0].base_addr = AU1550_ETH0_BASE;
-               iflist[1].base_addr = AU1550_ETH1_BASE;
-               iflist[0].macen_addr = AU1550_MAC0_ENABLE;
-               iflist[1].macen_addr = AU1550_MAC1_ENABLE;
-               iflist[0].irq = AU1550_MAC0_DMA_INT;
-               iflist[1].irq = AU1550_MAC1_DMA_INT;
-               break;
-#endif
-       default:
-               num_ifs = 0;
-       }
+       num_ifs = NUM_ETH_INTERFACES - ni;
+
        for(i = 0; i < num_ifs; i++) {
-               dev = au1000_probe(iflist[i].base_addr, iflist[i].irq, i);
+               dev = au1000_probe(i);
                iflist[i].dev = dev;
                if (dev)
                        found_one++;
@@ -1436,8 +1407,7 @@ static struct ethtool_ops au1000_ethtool_ops = {
        .get_link = au1000_get_link
 };
 
-static struct net_device *
-au1000_probe(u32 ioaddr, int irq, int port_num)
+static struct net_device * au1000_probe(int port_num)
 {
        static unsigned version_printed = 0;
        struct au1000_private *aup = NULL;
@@ -1445,94 +1415,95 @@ au1000_probe(u32 ioaddr, int irq, int port_num)
        db_dest_t *pDB, *pDBfree;
        char *pmac, *argptr;
        char ethaddr[6];
-       int i, err;
+       int irq, i, err;
+       u32 base, macen;
+
+       if (port_num >= NUM_ETH_INTERFACES)
+               return NULL;
 
-       if (!request_mem_region(CPHYSADDR(ioaddr), MAC_IOSIZE, "Au1x00 ENET"))
+       base  = CPHYSADDR(iflist[port_num].base_addr );
+       macen = CPHYSADDR(iflist[port_num].macen_addr);
+       irq = iflist[port_num].irq;
+
+       if (!request_mem_region( base, MAC_IOSIZE, "Au1x00 ENET") ||
+           !request_mem_region(macen, 4, "Au1x00 ENET"))
                return NULL;
 
-       if (version_printed++ == 0) 
+       if (version_printed++ == 0)
                printk("%s version %s %s\n", DRV_NAME, DRV_VERSION, DRV_AUTHOR);
 
        dev = alloc_etherdev(sizeof(struct au1000_private));
        if (!dev) {
-               printk (KERN_ERR "au1000 eth: alloc_etherdev failed\n");  
+               printk(KERN_ERR "%s: alloc_etherdev failed\n", DRV_NAME);
                return NULL;
        }
 
-       if ((err = register_netdev(dev))) {
-               printk(KERN_ERR "Au1x_eth Cannot register net device err %d\n",
-                               err);
+       if ((err = register_netdev(dev)) != 0) {
+               printk(KERN_ERR "%s: Cannot register net device, error %d\n",
+                               DRV_NAME, err);
                free_netdev(dev);
                return NULL;
        }
 
-       printk("%s: Au1x Ethernet found at 0x%x, irq %d\n", 
-                       dev->name, ioaddr, irq);
+       printk("%s: Au1xx0 Ethernet found at 0x%x, irq %d\n",
+               dev->name, base, irq);
 
        aup = dev->priv;
 
        /* Allocate the data buffers */
        /* Snooping works fine with eth on all au1xxx */
-       aup->vaddr = (u32)dma_alloc_noncoherent(NULL,
-                       MAX_BUF_SIZE * (NUM_TX_BUFFS+NUM_RX_BUFFS),
-                       &aup->dma_addr,
-                       0);
+       aup->vaddr = (u32)dma_alloc_noncoherent(NULL, MAX_BUF_SIZE *
+                                               (NUM_TX_BUFFS + NUM_RX_BUFFS),
+                                               &aup->dma_addr, 0);
        if (!aup->vaddr) {
                free_netdev(dev);
-               release_mem_region(CPHYSADDR(ioaddr), MAC_IOSIZE);
+               release_mem_region( base, MAC_IOSIZE);
+               release_mem_region(macen, 4);
                return NULL;
        }
 
        /* aup->mac is the base address of the MAC's registers */
-       aup->mac = (volatile mac_reg_t *)((unsigned long)ioaddr);
+       aup->mac = (volatile mac_reg_t *)iflist[port_num].base_addr;
+
        /* Setup some variables for quick register address access */
-       if (ioaddr == iflist[0].base_addr)
-       {
-               /* check env variables first */
-               if (!get_ethernet_addr(ethaddr)) { 
+       aup->enable = (volatile u32 *)iflist[port_num].macen_addr;
+       aup->mac_id = port_num;
+       au_macs[port_num] = aup;
+
+       if (port_num == 0) {
+               /* Check the environment variables first */
+               if (get_ethernet_addr(ethaddr) == 0)
                        memcpy(au1000_mac_addr, ethaddr, sizeof(au1000_mac_addr));
-               else {
+               else {
                        /* Check command line */
                        argptr = prom_getcmdline();
-                       if ((pmac = strstr(argptr, "ethaddr=")) == NULL) {
-                               printk(KERN_INFO "%s: No mac address found\n", 
-                                               dev->name);
-                               /* use the hard coded mac addresses */
-                       else {
+                       if ((pmac = strstr(argptr, "ethaddr=")) == NULL)
+                               printk(KERN_INFO "%s: No MAC address found\n",
+                                                dev->name);
+                               /* Use the hard coded MAC addresses */
+                       else {
                                str2eaddr(ethaddr, pmac + strlen("ethaddr="));
                                memcpy(au1000_mac_addr, ethaddr, 
-                                               sizeof(au1000_mac_addr));
+                                      sizeof(au1000_mac_addr));
                        }
                }
-                       aup->enable = (volatile u32 *) 
-                               ((unsigned long)iflist[0].macen_addr);
-               memcpy(dev->dev_addr, au1000_mac_addr, sizeof(au1000_mac_addr));
+
                setup_hw_rings(aup, MAC0_RX_DMA_ADDR, MAC0_TX_DMA_ADDR);
-               aup->mac_id = 0;
-               au_macs[0] = aup;
-       }
-               else
-       if (ioaddr == iflist[1].base_addr)
-       {
-                       aup->enable = (volatile u32 *) 
-                               ((unsigned long)iflist[1].macen_addr);
-               memcpy(dev->dev_addr, au1000_mac_addr, sizeof(au1000_mac_addr));
-               dev->dev_addr[4] += 0x10;
+       } else if (port_num == 1)
                setup_hw_rings(aup, MAC1_RX_DMA_ADDR, MAC1_TX_DMA_ADDR);
-               aup->mac_id = 1;
-               au_macs[1] = aup;
-       }
-       else
-       {
-               printk(KERN_ERR "%s: bad ioaddr\n", dev->name);
-       }
 
-       /* bring the device out of reset, otherwise probing the mii
-        * will hang */
+       /*
+        * Assign to the Ethernet ports two consecutive MAC addresses
+        * to match those that are printed on their stickers
+        */
+       memcpy(dev->dev_addr, au1000_mac_addr, sizeof(au1000_mac_addr));
+       dev->dev_addr[5] += port_num;
+
+       /* Bring the device out of reset, otherwise probing the MII will hang */
        *aup->enable = MAC_EN_CLOCK_ENABLE;
        au_sync_delay(2);
-       *aup->enable = MAC_EN_RESET0 | MAC_EN_RESET1 | 
-               MAC_EN_RESET2 | MAC_EN_CLOCK_ENABLE;
+       *aup->enable = MAC_EN_RESET0 | MAC_EN_RESET1 | MAC_EN_RESET2 |
+                      MAC_EN_CLOCK_ENABLE;
        au_sync_delay(2);
 
        aup->mii = kmalloc(sizeof(struct mii_phy), GFP_KERNEL);
@@ -1581,7 +1552,7 @@ au1000_probe(u32 ioaddr, int irq, int port_num)
        }
 
        spin_lock_init(&aup->lock);
-       dev->base_addr = ioaddr;
+       dev->base_addr = base;
        dev->irq = irq;
        dev->open = au1000_open;
        dev->hard_start_xmit = au1000_tx;
@@ -1615,13 +1586,12 @@ err_out:
                if (aup->tx_db_inuse[i])
                        ReleaseDB(aup, aup->tx_db_inuse[i]);
        }
-       dma_free_noncoherent(NULL,
-                       MAX_BUF_SIZE * (NUM_TX_BUFFS+NUM_RX_BUFFS),
-                       (void *)aup->vaddr,
-                       aup->dma_addr);
+       dma_free_noncoherent(NULL, MAX_BUF_SIZE * (NUM_TX_BUFFS + NUM_RX_BUFFS),
+                            (void *)aup->vaddr, aup->dma_addr);
        unregister_netdev(dev);
        free_netdev(dev);
-       release_mem_region(CPHYSADDR(ioaddr), MAC_IOSIZE);
+       release_mem_region( base, MAC_IOSIZE);
+       release_mem_region(macen, 4);
        return NULL;
 }
 
@@ -1806,20 +1776,18 @@ static void __exit au1000_cleanup_module(void)
                        aup = (struct au1000_private *) dev->priv;
                        unregister_netdev(dev);
                        kfree(aup->mii);
-                       for (j = 0; j < NUM_RX_DMA; j++) {
+                       for (j = 0; j < NUM_RX_DMA; j++)
                                if (aup->rx_db_inuse[j])
                                        ReleaseDB(aup, aup->rx_db_inuse[j]);
-                       }
-                       for (j = 0; j < NUM_TX_DMA; j++) {
+                       for (j = 0; j < NUM_TX_DMA; j++)
                                if (aup->tx_db_inuse[j])
                                        ReleaseDB(aup, aup->tx_db_inuse[j]);
-                       }
-                       dma_free_noncoherent(NULL,
-                                       MAX_BUF_SIZE * (NUM_TX_BUFFS+NUM_RX_BUFFS),
-                                       (void *)aup->vaddr,
-                                       aup->dma_addr);
+                       dma_free_noncoherent(NULL, MAX_BUF_SIZE *
+                                            (NUM_TX_BUFFS + NUM_RX_BUFFS),
+                                            (void *)aup->vaddr, aup->dma_addr);
+                       release_mem_region(dev->base_addr, MAC_IOSIZE);
+                       release_mem_region(CPHYSADDR(iflist[i].macen_addr), 4);
                        free_netdev(dev);
-                       release_mem_region(CPHYSADDR(iflist[i].base_addr), MAC_IOSIZE);
                }
        }
 }
index ac48f7543500b7c53d5099383fa26c83c247a45e..39f36aa05aa8b005bf4b2b2638ef7f1a47810f6e 100644 (file)
@@ -4877,7 +4877,7 @@ static int __devinit cas_init_one(struct pci_dev *pdev,
                                  const struct pci_device_id *ent)
 {
        static int cas_version_printed = 0;
-       unsigned long casreg_base, casreg_len;
+       unsigned long casreg_len;
        struct net_device *dev;
        struct cas *cp;
        int i, err, pci_using_dac;
@@ -4972,7 +4972,6 @@ static int __devinit cas_init_one(struct pci_dev *pdev,
                pci_using_dac = 0;
        }
 
-       casreg_base = pci_resource_start(pdev, 0);
        casreg_len = pci_resource_len(pdev, 0);
 
        cp = netdev_priv(dev);
@@ -5024,7 +5023,7 @@ static int __devinit cas_init_one(struct pci_dev *pdev,
        cp->timer_ticks = 0;
 
        /* give us access to cassini registers */
-       cp->regs = ioremap(casreg_base, casreg_len);
+       cp->regs = pci_iomap(pdev, 0, casreg_len);
        if (cp->regs == 0UL) {
                printk(KERN_ERR PFX "Cannot map device registers, "
                       "aborting.\n");
@@ -5123,7 +5122,7 @@ err_out_iounmap:
                cas_shutdown(cp);
        mutex_unlock(&cp->pm_mutex);
 
-       iounmap(cp->regs);
+       pci_iounmap(pdev, cp->regs);
 
 
 err_out_free_res:
@@ -5171,7 +5170,7 @@ static void __devexit cas_remove_one(struct pci_dev *pdev)
 #endif
        pci_free_consistent(pdev, sizeof(struct cas_init_block),
                            cp->init_block, cp->block_dvma);
-       iounmap(cp->regs);
+       pci_iounmap(pdev, cp->regs);
        free_netdev(dev);
        pci_release_regions(pdev);
        pci_disable_device(pdev);
index ca9f89552da37507bab48b49e304145597ff1cf9..92823ac89d4263f955c1a592a806b1ab75c82cad 100644 (file)
@@ -22,6 +22,7 @@
 # 
 # Contact Information:
 # Linux NICS <linux.nics@intel.com>
+# e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
 # Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
 #
 ################################################################################
index 281de41d030a9991b590314f89b53e25ef07540e..2bc34fbfa69c0ee93b7b17f277c6fd14e67d4712 100644 (file)
@@ -1,7 +1,7 @@
 /*******************************************************************************
 
   
-  Copyright(c) 1999 - 2005 Intel Corporation. All rights reserved.
+  Copyright(c) 1999 - 2006 Intel Corporation. All rights reserved.
   
   This program is free software; you can redistribute it and/or modify it 
   under the terms of the GNU General Public License as published by the Free 
@@ -22,6 +22,7 @@
   
   Contact Information:
   Linux NICS <linux.nics@intel.com>
+  e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
   Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
 
 *******************************************************************************/
@@ -114,6 +115,8 @@ struct e1000_adapter;
 /* Supported Rx Buffer Sizes */
 #define E1000_RXBUFFER_128   128    /* Used for packet split */
 #define E1000_RXBUFFER_256   256    /* Used for packet split */
+#define E1000_RXBUFFER_512   512
+#define E1000_RXBUFFER_1024  1024
 #define E1000_RXBUFFER_2048  2048
 #define E1000_RXBUFFER_4096  4096
 #define E1000_RXBUFFER_8192  8192
@@ -334,7 +337,6 @@ struct e1000_adapter {
        boolean_t have_msi;
 #endif
        /* to not mess up cache alignment, always add to the bottom */
-       boolean_t txb2b;
 #ifdef NETIF_F_TSO
        boolean_t tso_force;
 #endif
index ecccca35c6f4db1ba739224a6cdc978f7a2c82ad..e48dc578fde29c2b2079c98be28b6dacbd3cd26f 100644 (file)
@@ -1,7 +1,7 @@
 /*******************************************************************************
 
   
-  Copyright(c) 1999 - 2005 Intel Corporation. All rights reserved.
+  Copyright(c) 1999 - 2006 Intel Corporation. All rights reserved.
   
   This program is free software; you can redistribute it and/or modify it 
   under the terms of the GNU General Public License as published by the Free 
@@ -22,6 +22,7 @@
   
   Contact Information:
   Linux NICS <linux.nics@intel.com>
+  e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
   Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
 
 *******************************************************************************/
index 523c2c9fc0ac6e315ded95e4c8cc23dec2364ddf..4c796e54b8401874f6e59463497e3cef949eeb71 100644 (file)
@@ -1,7 +1,7 @@
 /*******************************************************************************
 
   
-  Copyright(c) 1999 - 2005 Intel Corporation. All rights reserved.
+  Copyright(c) 1999 - 2006 Intel Corporation. All rights reserved.
   
   This program is free software; you can redistribute it and/or modify it 
   under the terms of the GNU General Public License as published by the Free 
@@ -22,6 +22,7 @@
   
   Contact Information:
   Linux NICS <linux.nics@intel.com>
+  e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
   Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
 
 *******************************************************************************/
index 150e45e30f87a7f85e53d67909cd35618e57b1f8..03d07ebde4f7c7c1efe675882461b0d33d458462 100644 (file)
@@ -1,7 +1,7 @@
 /*******************************************************************************
 
   
-  Copyright(c) 1999 - 2005 Intel Corporation. All rights reserved.
+  Copyright(c) 1999 - 2006 Intel Corporation. All rights reserved.
   
   This program is free software; you can redistribute it and/or modify it 
   under the terms of the GNU General Public License as published by the Free 
@@ -22,6 +22,7 @@
   
   Contact Information:
   Linux NICS <linux.nics@intel.com>
+  e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
   Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
 
 *******************************************************************************/
index c99e87838f92913ce277c9a2494955551cb79f04..fb8cef6191422868eba824a51b8768676b475b48 100644 (file)
@@ -1,7 +1,7 @@
 /*******************************************************************************
 
   
-  Copyright(c) 1999 - 2005 Intel Corporation. All rights reserved.
+  Copyright(c) 1999 - 2006 Intel Corporation. All rights reserved.
   
   This program is free software; you can redistribute it and/or modify it 
   under the terms of the GNU General Public License as published by the Free 
@@ -22,6 +22,7 @@
   
   Contact Information:
   Linux NICS <linux.nics@intel.com>
+  e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
   Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
 
 *******************************************************************************/
@@ -74,9 +75,9 @@ static char e1000_driver_string[] = "Intel(R) PRO/1000 Network Driver";
 #else
 #define DRIVERNAPI "-NAPI"
 #endif
-#define DRV_VERSION "7.0.33-k2"DRIVERNAPI
+#define DRV_VERSION "7.0.38-k2"DRIVERNAPI
 char e1000_driver_version[] = DRV_VERSION;
-static char e1000_copyright[] = "Copyright (c) 1999-2005 Intel Corporation.";
+static char e1000_copyright[] = "Copyright (c) 1999-2006 Intel Corporation.";
 
 /* e1000_pci_tbl - PCI Device ID Table
  *
@@ -208,8 +209,8 @@ static void e1000_leave_82542_rst(struct e1000_adapter *adapter);
 static void e1000_tx_timeout(struct net_device *dev);
 static void e1000_reset_task(struct net_device *dev);
 static void e1000_smartspeed(struct e1000_adapter *adapter);
-static inline int e1000_82547_fifo_workaround(struct e1000_adapter *adapter,
-                                             struct sk_buff *skb);
+static int e1000_82547_fifo_workaround(struct e1000_adapter *adapter,
+                                       struct sk_buff *skb);
 
 static void e1000_vlan_rx_register(struct net_device *netdev, struct vlan_group *grp);
 static void e1000_vlan_rx_add_vid(struct net_device *netdev, uint16_t vid);
@@ -291,7 +292,7 @@ module_exit(e1000_exit_module);
  * @adapter: board private structure
  **/
 
-static inline void
+static void
 e1000_irq_disable(struct e1000_adapter *adapter)
 {
        atomic_inc(&adapter->irq_sem);
@@ -305,7 +306,7 @@ e1000_irq_disable(struct e1000_adapter *adapter)
  * @adapter: board private structure
  **/
 
-static inline void
+static void
 e1000_irq_enable(struct e1000_adapter *adapter)
 {
        if (likely(atomic_dec_and_test(&adapter->irq_sem))) {
@@ -349,7 +350,7 @@ e1000_update_mng_vlan(struct e1000_adapter *adapter)
  * 
  **/
 
-static inline void 
+static void
 e1000_release_hw_control(struct e1000_adapter *adapter)
 {
        uint32_t ctrl_ext;
@@ -359,6 +360,7 @@ e1000_release_hw_control(struct e1000_adapter *adapter)
        switch (adapter->hw.mac_type) {
        case e1000_82571:
        case e1000_82572:
+       case e1000_80003es2lan:
                ctrl_ext = E1000_READ_REG(&adapter->hw, CTRL_EXT);
                E1000_WRITE_REG(&adapter->hw, CTRL_EXT,
                                ctrl_ext & ~E1000_CTRL_EXT_DRV_LOAD);
@@ -383,7 +385,7 @@ e1000_release_hw_control(struct e1000_adapter *adapter)
  * 
  **/
 
-static inline void 
+static void
 e1000_get_hw_control(struct e1000_adapter *adapter)
 {
        uint32_t ctrl_ext;
@@ -392,6 +394,7 @@ e1000_get_hw_control(struct e1000_adapter *adapter)
        switch (adapter->hw.mac_type) {
        case e1000_82571:
        case e1000_82572:
+       case e1000_80003es2lan:
                ctrl_ext = E1000_READ_REG(&adapter->hw, CTRL_EXT);
                E1000_WRITE_REG(&adapter->hw, CTRL_EXT,
                                ctrl_ext | E1000_CTRL_EXT_DRV_LOAD);
@@ -419,7 +422,7 @@ e1000_up(struct e1000_adapter *adapter)
                uint16_t mii_reg;
                e1000_read_phy_reg(&adapter->hw, PHY_CTRL, &mii_reg);
                if (mii_reg & MII_CR_POWER_DOWN)
-                       e1000_phy_reset(&adapter->hw);
+                       e1000_phy_hw_reset(&adapter->hw);
        }
 
        e1000_set_multi(netdev);
@@ -970,8 +973,8 @@ e1000_sw_init(struct e1000_adapter *adapter)
 
        pci_read_config_word(pdev, PCI_COMMAND, &hw->pci_cmd_word);
 
-       adapter->rx_buffer_len = E1000_RXBUFFER_2048;
-       adapter->rx_ps_bsize0 = E1000_RXBUFFER_256;
+       adapter->rx_buffer_len = MAXIMUM_ETHERNET_FRAME_SIZE;
+       adapter->rx_ps_bsize0 = E1000_RXBUFFER_128;
        hw->max_frame_size = netdev->mtu +
                             ENET_HEADER_SIZE + ETHERNET_FCS_SIZE;
        hw->min_frame_size = MINIMUM_ETHERNET_FRAME_SIZE;
@@ -1179,7 +1182,7 @@ e1000_close(struct net_device *netdev)
  * @start: address of beginning of memory
  * @len: length of memory
  **/
-static inline boolean_t
+static boolean_t
 e1000_check_64k_bound(struct e1000_adapter *adapter,
                      void *start, unsigned long len)
 {
@@ -1597,14 +1600,21 @@ e1000_setup_rctl(struct e1000_adapter *adapter)
                rctl |= E1000_RCTL_LPE;
 
        /* Setup buffer sizes */
-       if (adapter->hw.mac_type >= e1000_82571) {
-               /* We can now specify buffers in 1K increments.
-                * BSIZE and BSEX are ignored in this case. */
-               rctl |= adapter->rx_buffer_len << 0x11;
-       } else {
-               rctl &= ~E1000_RCTL_SZ_4096;
-               rctl |= E1000_RCTL_BSEX; 
-               switch (adapter->rx_buffer_len) {
+       rctl &= ~E1000_RCTL_SZ_4096;
+       rctl |= E1000_RCTL_BSEX;
+       switch (adapter->rx_buffer_len) {
+               case E1000_RXBUFFER_256:
+                       rctl |= E1000_RCTL_SZ_256;
+                       rctl &= ~E1000_RCTL_BSEX;
+                       break;
+               case E1000_RXBUFFER_512:
+                       rctl |= E1000_RCTL_SZ_512;
+                       rctl &= ~E1000_RCTL_BSEX;
+                       break;
+               case E1000_RXBUFFER_1024:
+                       rctl |= E1000_RCTL_SZ_1024;
+                       rctl &= ~E1000_RCTL_BSEX;
+                       break;
                case E1000_RXBUFFER_2048:
                default:
                        rctl |= E1000_RCTL_SZ_2048;
@@ -1619,7 +1629,6 @@ e1000_setup_rctl(struct e1000_adapter *adapter)
                case E1000_RXBUFFER_16384:
                        rctl |= E1000_RCTL_SZ_16384;
                        break;
-               }
        }
 
 #ifndef CONFIG_E1000_DISABLE_PACKET_SPLIT
@@ -1713,7 +1722,7 @@ e1000_configure_rx(struct e1000_adapter *adapter)
        if (hw->mac_type >= e1000_82571) {
                ctrl_ext = E1000_READ_REG(hw, CTRL_EXT);
                /* Reset delay timers after every interrupt */
-               ctrl_ext |= E1000_CTRL_EXT_CANC;
+               ctrl_ext |= E1000_CTRL_EXT_INT_TIMER_CLR;
 #ifdef CONFIG_E1000_NAPI
                /* Auto-Mask interrupts upon ICR read. */
                ctrl_ext |= E1000_CTRL_EXT_IAME;
@@ -1805,7 +1814,7 @@ e1000_free_all_tx_resources(struct e1000_adapter *adapter)
                e1000_free_tx_resources(adapter, &adapter->tx_ring[i]);
 }
 
-static inline void
+static void
 e1000_unmap_and_free_tx_resource(struct e1000_adapter *adapter,
                        struct e1000_buffer *buffer_info)
 {
@@ -2245,6 +2254,7 @@ e1000_watchdog_task(struct e1000_adapter *adapter)
 
        if (link) {
                if (!netif_carrier_ok(netdev)) {
+                       boolean_t txb2b = 1;
                        e1000_get_speed_and_duplex(&adapter->hw,
                                                   &adapter->link_speed,
                                                   &adapter->link_duplex);
@@ -2258,23 +2268,22 @@ e1000_watchdog_task(struct e1000_adapter *adapter)
                         * and adjust the timeout factor */
                        netdev->tx_queue_len = adapter->tx_queue_len;
                        adapter->tx_timeout_factor = 1;
-                       adapter->txb2b = 1;
                        switch (adapter->link_speed) {
                        case SPEED_10:
-                               adapter->txb2b = 0;
+                               txb2b = 0;
                                netdev->tx_queue_len = 10;
                                adapter->tx_timeout_factor = 8;
                                break;
                        case SPEED_100:
-                               adapter->txb2b = 0;
+                               txb2b = 0;
                                netdev->tx_queue_len = 100;
                                /* maybe add some timeout factor ? */
                                break;
                        }
 
-                       if ((adapter->hw.mac_type == e1000_82571 || 
+                       if ((adapter->hw.mac_type == e1000_82571 ||
                             adapter->hw.mac_type == e1000_82572) &&
-                           adapter->txb2b == 0) {
+                           txb2b == 0) {
 #define SPEED_MODE_BIT (1 << 21)
                                uint32_t tarc0;
                                tarc0 = E1000_READ_REG(&adapter->hw, TARC0);
@@ -2398,7 +2407,7 @@ e1000_watchdog_task(struct e1000_adapter *adapter)
 #define E1000_TX_FLAGS_VLAN_MASK       0xffff0000
 #define E1000_TX_FLAGS_VLAN_SHIFT      16
 
-static inline int
+static int
 e1000_tso(struct e1000_adapter *adapter, struct e1000_tx_ring *tx_ring,
           struct sk_buff *skb)
 {
@@ -2478,7 +2487,7 @@ e1000_tso(struct e1000_adapter *adapter, struct e1000_tx_ring *tx_ring,
        return FALSE;
 }
 
-static inline boolean_t
+static boolean_t
 e1000_tx_csum(struct e1000_adapter *adapter, struct e1000_tx_ring *tx_ring,
               struct sk_buff *skb)
 {
@@ -2514,7 +2523,7 @@ e1000_tx_csum(struct e1000_adapter *adapter, struct e1000_tx_ring *tx_ring,
 #define E1000_MAX_TXD_PWR      12
 #define E1000_MAX_DATA_PER_TXD (1<<E1000_MAX_TXD_PWR)
 
-static inline int
+static int
 e1000_tx_map(struct e1000_adapter *adapter, struct e1000_tx_ring *tx_ring,
              struct sk_buff *skb, unsigned int first, unsigned int max_per_txd,
              unsigned int nr_frags, unsigned int mss)
@@ -2623,7 +2632,7 @@ e1000_tx_map(struct e1000_adapter *adapter, struct e1000_tx_ring *tx_ring,
        return count;
 }
 
-static inline void
+static void
 e1000_tx_queue(struct e1000_adapter *adapter, struct e1000_tx_ring *tx_ring,
                int tx_flags, int count)
 {
@@ -2687,7 +2696,7 @@ e1000_tx_queue(struct e1000_adapter *adapter, struct e1000_tx_ring *tx_ring,
 #define E1000_FIFO_HDR                 0x10
 #define E1000_82547_PAD_LEN            0x3E0
 
-static inline int
+static int
 e1000_82547_fifo_workaround(struct e1000_adapter *adapter, struct sk_buff *skb)
 {
        uint32_t fifo_space = adapter->tx_fifo_size - adapter->tx_fifo_head;
@@ -2714,7 +2723,7 @@ no_fifo_stall_required:
 }
 
 #define MINIMUM_DHCP_PACKET_SIZE 282
-static inline int
+static int
 e1000_transfer_dhcp_info(struct e1000_adapter *adapter, struct sk_buff *skb)
 {
        struct e1000_hw *hw =  &adapter->hw;
@@ -2980,8 +2989,7 @@ e1000_change_mtu(struct net_device *netdev, int new_mtu)
 
        /* Adapter-specific max frame size limits. */
        switch (adapter->hw.mac_type) {
-       case e1000_82542_rev2_0:
-       case e1000_82542_rev2_1:
+       case e1000_undefined ... e1000_82542_rev2_1:
                if (max_frame > MAXIMUM_ETHERNET_FRAME_SIZE) {
                        DPRINTK(PROBE, ERR, "Jumbo Frames not supported.\n");
                        return -EINVAL;
@@ -3015,27 +3023,32 @@ e1000_change_mtu(struct net_device *netdev, int new_mtu)
                break;
        }
 
-
-       if (adapter->hw.mac_type > e1000_82547_rev_2) {
-               adapter->rx_buffer_len = max_frame;
-               E1000_ROUNDUP(adapter->rx_buffer_len, 1024);
-       } else {
-               if(unlikely((adapter->hw.mac_type < e1000_82543) &&
-                  (max_frame > MAXIMUM_ETHERNET_FRAME_SIZE))) {
-                       DPRINTK(PROBE, ERR, "Jumbo Frames not supported "
-                                           "on 82542\n");
-                       return -EINVAL;
-               } else {
-                       if(max_frame <= E1000_RXBUFFER_2048)
-                               adapter->rx_buffer_len = E1000_RXBUFFER_2048;
-                       else if(max_frame <= E1000_RXBUFFER_4096)
-                               adapter->rx_buffer_len = E1000_RXBUFFER_4096;
-                       else if(max_frame <= E1000_RXBUFFER_8192)
-                               adapter->rx_buffer_len = E1000_RXBUFFER_8192;
-                       else if(max_frame <= E1000_RXBUFFER_16384)
-                               adapter->rx_buffer_len = E1000_RXBUFFER_16384;
-               }
-       }
+       /* NOTE: dev_alloc_skb reserves 16 bytes, and typically NET_IP_ALIGN
+        * means we reserve 2 more, this pushes us to allocate from the next
+        * larger slab size
+        * i.e. RXBUFFER_2048 --> size-4096 slab */
+
+       if (max_frame <= E1000_RXBUFFER_256)
+               adapter->rx_buffer_len = E1000_RXBUFFER_256;
+       else if (max_frame <= E1000_RXBUFFER_512)
+               adapter->rx_buffer_len = E1000_RXBUFFER_512;
+       else if (max_frame <= E1000_RXBUFFER_1024)
+               adapter->rx_buffer_len = E1000_RXBUFFER_1024;
+       else if (max_frame <= E1000_RXBUFFER_2048)
+               adapter->rx_buffer_len = E1000_RXBUFFER_2048;
+       else if (max_frame <= E1000_RXBUFFER_4096)
+               adapter->rx_buffer_len = E1000_RXBUFFER_4096;
+       else if (max_frame <= E1000_RXBUFFER_8192)
+               adapter->rx_buffer_len = E1000_RXBUFFER_8192;
+       else if (max_frame <= E1000_RXBUFFER_16384)
+               adapter->rx_buffer_len = E1000_RXBUFFER_16384;
+
+       /* adjust allocation if LPE protects us, and we aren't using SBP */
+#define MAXIMUM_ETHERNET_VLAN_SIZE 1522
+       if (!adapter->hw.tbi_compatibility_on &&
+           ((max_frame == MAXIMUM_ETHERNET_FRAME_SIZE) ||
+            (max_frame == MAXIMUM_ETHERNET_VLAN_SIZE)))
+               adapter->rx_buffer_len = MAXIMUM_ETHERNET_VLAN_SIZE;
 
        netdev->mtu = new_mtu;
 
@@ -3163,7 +3176,6 @@ e1000_update_stats(struct e1000_adapter *adapter)
                adapter->stats.crcerrs + adapter->stats.algnerrc +
                adapter->stats.ruc + adapter->stats.roc +
                adapter->stats.cexterr;
-       adapter->net_stats.rx_dropped = 0;
        adapter->net_stats.rx_length_errors = adapter->stats.ruc +
                                              adapter->stats.roc;
        adapter->net_stats.rx_crc_errors = adapter->stats.crcerrs;
@@ -3389,13 +3401,15 @@ e1000_clean_tx_irq(struct e1000_adapter *adapter,
 
        tx_ring->next_to_clean = i;
 
-       spin_lock(&tx_ring->tx_lock);
-
+#define TX_WAKE_THRESHOLD 32
        if (unlikely(cleaned && netif_queue_stopped(netdev) &&
-                   netif_carrier_ok(netdev)))
-               netif_wake_queue(netdev);
-
-       spin_unlock(&tx_ring->tx_lock);
+                    netif_carrier_ok(netdev))) {
+               spin_lock(&tx_ring->tx_lock);
+               if (netif_queue_stopped(netdev) &&
+                   (E1000_DESC_UNUSED(tx_ring) >= TX_WAKE_THRESHOLD))
+                       netif_wake_queue(netdev);
+               spin_unlock(&tx_ring->tx_lock);
+       }
 
        if (adapter->detect_tx_hung) {
                /* Detect a transmit hang in hardware, this serializes the
@@ -3443,7 +3457,7 @@ e1000_clean_tx_irq(struct e1000_adapter *adapter,
  * @sk_buff:     socket buffer with received data
  **/
 
-static inline void
+static void
 e1000_rx_checksum(struct e1000_adapter *adapter,
                  uint32_t status_err, uint32_t csum,
                  struct sk_buff *skb)
@@ -3567,7 +3581,8 @@ e1000_clean_rx_irq(struct e1000_adapter *adapter,
                                                       flags);
                                length--;
                        } else {
-                               dev_kfree_skb_irq(skb);
+                               /* recycle */
+                               buffer_info->skb = skb;
                                goto next_desc;
                        }
                }
@@ -3675,6 +3690,7 @@ e1000_clean_rx_irq_ps(struct e1000_adapter *adapter,
        i = rx_ring->next_to_clean;
        rx_desc = E1000_RX_DESC_PS(*rx_ring, i);
        staterr = le32_to_cpu(rx_desc->wb.middle.status_error);
+       buffer_info = &rx_ring->buffer_info[i];
 
        while (staterr & E1000_RXD_STAT_DD) {
                buffer_info = &rx_ring->buffer_info[i];
@@ -3735,7 +3751,7 @@ e1000_clean_rx_irq_ps(struct e1000_adapter *adapter,
 
                /* page alloc/put takes too long and effects small packet
                 * throughput, so unsplit small packets and save the alloc/put*/
-               if (l1 && ((length + l1) < E1000_CB_LENGTH)) {
+               if (l1 && ((length + l1) <= adapter->rx_ps_bsize0)) {
                        u8 *vaddr;
                        /* there is no documentation about how to call 
                         * kmap_atomic, so we can't hold the mapping
@@ -4157,7 +4173,7 @@ e1000_mii_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
                        spin_unlock_irqrestore(&adapter->stats_lock, flags);
                        return -EIO;
                }
-               if (adapter->hw.phy_type == e1000_media_type_copper) {
+               if (adapter->hw.media_type == e1000_media_type_copper) {
                        switch (data->reg_num) {
                        case PHY_CTRL:
                                if (mii_reg & MII_CR_POWER_DOWN)
@@ -4516,21 +4532,13 @@ e1000_suspend(struct pci_dev *pdev, pm_message_t state)
 
                E1000_WRITE_REG(&adapter->hw, WUC, E1000_WUC_PME_EN);
                E1000_WRITE_REG(&adapter->hw, WUFC, wufc);
-               retval = pci_enable_wake(pdev, PCI_D3hot, 1);
-               if (retval)
-                       DPRINTK(PROBE, ERR, "Error enabling D3 wake\n");
-               retval = pci_enable_wake(pdev, PCI_D3cold, 1);
-               if (retval)
-                       DPRINTK(PROBE, ERR, "Error enabling D3 cold wake\n");
+               pci_enable_wake(pdev, PCI_D3hot, 1);
+               pci_enable_wake(pdev, PCI_D3cold, 1);
        } else {
                E1000_WRITE_REG(&adapter->hw, WUC, 0);
                E1000_WRITE_REG(&adapter->hw, WUFC, 0);
-               retval = pci_enable_wake(pdev, PCI_D3hot, 0);
-               if (retval)
-                       DPRINTK(PROBE, ERR, "Error enabling D3 wake\n");
-               retval = pci_enable_wake(pdev, PCI_D3cold, 0);
-               if (retval)
-                       DPRINTK(PROBE, ERR, "Error enabling D3 cold wake\n");
+               pci_enable_wake(pdev, PCI_D3hot, 0);
+               pci_enable_wake(pdev, PCI_D3cold, 0);
        }
 
        if (adapter->hw.mac_type >= e1000_82540 &&
@@ -4539,13 +4547,8 @@ e1000_suspend(struct pci_dev *pdev, pm_message_t state)
                if (manc & E1000_MANC_SMBUS_EN) {
                        manc |= E1000_MANC_ARP_EN;
                        E1000_WRITE_REG(&adapter->hw, MANC, manc);
-                       retval = pci_enable_wake(pdev, PCI_D3hot, 1);
-                       if (retval)
-                               DPRINTK(PROBE, ERR, "Error enabling D3 wake\n");
-                       retval = pci_enable_wake(pdev, PCI_D3cold, 1);
-                       if (retval)
-                               DPRINTK(PROBE, ERR,
-                                       "Error enabling D3 cold wake\n");
+                       pci_enable_wake(pdev, PCI_D3hot, 1);
+                       pci_enable_wake(pdev, PCI_D3cold, 1);
                }
        }
 
@@ -4555,9 +4558,7 @@ e1000_suspend(struct pci_dev *pdev, pm_message_t state)
 
        pci_disable_device(pdev);
 
-       retval = pci_set_power_state(pdev, pci_choose_state(pdev, state));
-       if (retval)
-               DPRINTK(PROBE, ERR, "Error in setting power state\n");
+       pci_set_power_state(pdev, pci_choose_state(pdev, state));
 
        return 0;
 }
@@ -4568,22 +4569,15 @@ e1000_resume(struct pci_dev *pdev)
 {
        struct net_device *netdev = pci_get_drvdata(pdev);
        struct e1000_adapter *adapter = netdev_priv(netdev);
-       int retval;
        uint32_t manc, ret_val;
 
-       retval = pci_set_power_state(pdev, PCI_D0);
-       if (retval)
-               DPRINTK(PROBE, ERR, "Error in setting power state\n");
+       pci_set_power_state(pdev, PCI_D0);
        e1000_pci_restore_state(adapter);
        ret_val = pci_enable_device(pdev);
        pci_set_master(pdev);
 
-       retval = pci_enable_wake(pdev, PCI_D3hot, 0);
-       if (retval)
-               DPRINTK(PROBE, ERR, "Error enabling D3 wake\n");
-       retval = pci_enable_wake(pdev, PCI_D3cold, 0);
-       if (retval)
-               DPRINTK(PROBE, ERR, "Error enabling D3 cold wake\n");
+       pci_enable_wake(pdev, PCI_D3hot, 0);
+       pci_enable_wake(pdev, PCI_D3cold, 0);
 
        e1000_reset(adapter);
        E1000_WRITE_REG(&adapter->hw, WUS, ~0);
index 9790db974dc1dcc3ff8f3dfc953727d07c8e14a2..048d052be29d6a6d9a27856e2e3b7af3c142c95a 100644 (file)
@@ -1,7 +1,7 @@
 /*******************************************************************************
 
   
-  Copyright(c) 1999 - 2005 Intel Corporation. All rights reserved.
+  Copyright(c) 1999 - 2006 Intel Corporation. All rights reserved.
   
   This program is free software; you can redistribute it and/or modify it 
   under the terms of the GNU General Public License as published by the Free 
@@ -22,6 +22,7 @@
   
   Contact Information:
   Linux NICS <linux.nics@intel.com>
+  e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
   Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
 
 *******************************************************************************/
index e0a4d37d1b85db46779a14caeac22dd588b19b43..e55f8969a0fb0ca85f46f43ad2f9708e5bf55622 100644 (file)
@@ -1,7 +1,7 @@
 /*******************************************************************************
 
   
-  Copyright(c) 1999 - 2005 Intel Corporation. All rights reserved.
+  Copyright(c) 1999 - 2006 Intel Corporation. All rights reserved.
   
   This program is free software; you can redistribute it and/or modify it 
   under the terms of the GNU General Public License as published by the Free 
@@ -22,6 +22,7 @@
   
   Contact Information:
   Linux NICS <linux.nics@intel.com>
+  e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
   Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
 
 *******************************************************************************/
index 00179bc3437fccea29fa780d9df5da4233d1f886..0ef525899566ed2f24bf934dcbacab16870c0778 100644 (file)
@@ -167,6 +167,7 @@ typedef struct _XENA_dev_config {
        u8 unused4[0x08];
 
        u64 gpio_int_reg;
+#define GPIO_INT_REG_DP_ERR_INT                BIT(0)
 #define GPIO_INT_REG_LINK_DOWN                 BIT(1)
 #define GPIO_INT_REG_LINK_UP                   BIT(2)
        u64 gpio_int_mask;
@@ -187,7 +188,7 @@ typedef struct _XENA_dev_config {
 /* PIC Control registers */
        u64 pic_control;
 #define PIC_CNTL_RX_ALARM_MAP_1                BIT(0)
-#define PIC_CNTL_SHARED_SPLITS(n)              vBIT(n,11,4)
+#define PIC_CNTL_SHARED_SPLITS(n)              vBIT(n,11,5)
 
        u64 swapper_ctrl;
 #define SWAPPER_CTRL_PIF_R_FE                  BIT(0)
@@ -267,6 +268,21 @@ typedef struct _XENA_dev_config {
 
        /* General Configuration */
        u64 mdio_control;
+#define MDIO_MMD_INDX_ADDR(val)                vBIT(val, 0, 16)
+#define MDIO_MMD_DEV_ADDR(val)         vBIT(val, 19, 5)
+#define MDIO_MMD_PMA_DEV_ADDR          0x1
+#define MDIO_MMD_PMD_DEV_ADDR          0x1
+#define MDIO_MMD_WIS_DEV_ADDR          0x2
+#define MDIO_MMD_PCS_DEV_ADDR          0x3
+#define MDIO_MMD_PHYXS_DEV_ADDR                0x4
+#define MDIO_MMS_PRT_ADDR(val)         vBIT(val, 27, 5)
+#define MDIO_CTRL_START_TRANS(val)     vBIT(val, 56, 4)
+#define MDIO_OP(val)                   vBIT(val, 60, 2)
+#define MDIO_OP_ADDR_TRANS             0x0
+#define MDIO_OP_WRITE_TRANS            0x1
+#define MDIO_OP_READ_POST_INC_TRANS    0x2
+#define MDIO_OP_READ_TRANS             0x3
+#define MDIO_MDIO_DATA(val)            vBIT(val, 32, 16)
 
        u64 dtx_control;
 
@@ -284,9 +300,13 @@ typedef struct _XENA_dev_config {
        u64 gpio_control;
 #define GPIO_CTRL_GPIO_0               BIT(8)
        u64 misc_control;
+#define EXT_REQ_EN                     BIT(1)
 #define MISC_LINK_STABILITY_PRD(val)   vBIT(val,29,3)
 
-       u8 unused7_1[0x240 - 0x208];
+       u8 unused7_1[0x230 - 0x208];
+
+       u64 pic_control2;
+       u64 ini_dperr_ctrl;
 
        u64 wreq_split_mask;
 #define        WREQ_SPLIT_MASK_SET_MASK(val)   vBIT(val, 52, 12)
@@ -493,6 +513,7 @@ typedef struct _XENA_dev_config {
 #define PRC_CTRL_NO_SNOOP_DESC                 BIT(22)
 #define PRC_CTRL_NO_SNOOP_BUFF                 BIT(23)
 #define PRC_CTRL_BIMODAL_INTERRUPT             BIT(37)
+#define PRC_CTRL_GROUP_READS                   BIT(38)
 #define PRC_CTRL_RXD_BACKOFF_INTERVAL(val)     vBIT(val,40,24)
 
        u64 prc_alarm_action;
@@ -541,7 +562,12 @@ typedef struct _XENA_dev_config {
 #define RX_PA_CFG_IGNORE_LLC_CTRL          BIT(3)
 #define RX_PA_CFG_IGNORE_L2_ERR            BIT(6)
 
-       u8 unused12[0x700 - 0x1D8];
+       u64 unused_11_1;
+
+       u64 ring_bump_counter1;
+       u64 ring_bump_counter2;
+
+       u8 unused12[0x700 - 0x1F0];
 
        u64 rxdma_debug_ctrl;
 
index 79208f434ac17773123c9cb92364131687c3fc64..4e999818140330b11ad690a66658cb1079db216d 100644 (file)
  *
  * The module loadable parameters that are supported by the driver and a brief
  * explaination of all the variables.
+ *
  * rx_ring_num : This can be used to program the number of receive rings used
  * in the driver.
- * rx_ring_sz: This defines the number of descriptors each ring can have. This
- * is also an array of size 8.
+ * rx_ring_sz: This defines the number of receive blocks each ring can have.
+ *     This is also an array of size 8.
  * rx_ring_mode: This defines the operation mode of all 8 rings. The valid
  *             values are 1, 2 and 3.
  * tx_fifo_num: This defines the number of Tx FIFOs thats used int the driver.
  * tx_fifo_len: This too is an array of 8. Each element defines the number of
  * Tx descriptors that can be associated with each corresponding FIFO.
+ * intr_type: This defines the type of interrupt. The values can be 0(INTA),
+ *     1(MSI), 2(MSI_X). Default value is '0(INTA)'
+ * lro: Specifies whether to enable Large Receive Offload (LRO) or not.
+ *     Possible values '1' for enable '0' for disable. Default is '0'
+ * lro_max_pkts: This parameter defines maximum number of packets can be
+ *     aggregated as a single large packet
  ************************************************************************/
 
 #include <linux/config.h>
@@ -70,7 +77,7 @@
 #include "s2io.h"
 #include "s2io-regs.h"
 
-#define DRV_VERSION "2.0.11.2"
+#define DRV_VERSION "2.0.14.2"
 
 /* S2io Driver name & version. */
 static char s2io_driver_name[] = "Neterion";
@@ -106,18 +113,14 @@ static inline int RXD_IS_UP2DT(RxD_t *rxdp)
 #define LOW    2
 static inline int rx_buffer_level(nic_t * sp, int rxb_size, int ring)
 {
-       int level = 0;
        mac_info_t *mac_control;
 
        mac_control = &sp->mac_control;
-       if ((mac_control->rings[ring].pkt_cnt - rxb_size) > 16) {
-               level = LOW;
-               if (rxb_size <= rxd_count[sp->rxd_mode]) {
-                       level = PANIC;
-               }
-       }
-
-       return level;
+       if (rxb_size <= rxd_count[sp->rxd_mode])
+               return PANIC;
+       else if ((mac_control->rings[ring].pkt_cnt - rxb_size) > 16)
+               return  LOW;
+       return 0;
 }
 
 /* Ethtool related variables and Macros. */
@@ -136,7 +139,11 @@ static char ethtool_stats_keys[][ETH_GSTRING_LEN] = {
        {"tmac_mcst_frms"},
        {"tmac_bcst_frms"},
        {"tmac_pause_ctrl_frms"},
+       {"tmac_ttl_octets"},
+       {"tmac_ucst_frms"},
+       {"tmac_nucst_frms"},
        {"tmac_any_err_frms"},
+       {"tmac_ttl_less_fb_octets"},
        {"tmac_vld_ip_octets"},
        {"tmac_vld_ip"},
        {"tmac_drop_ip"},
@@ -151,13 +158,27 @@ static char ethtool_stats_keys[][ETH_GSTRING_LEN] = {
        {"rmac_vld_mcst_frms"},
        {"rmac_vld_bcst_frms"},
        {"rmac_in_rng_len_err_frms"},
+       {"rmac_out_rng_len_err_frms"},
        {"rmac_long_frms"},
        {"rmac_pause_ctrl_frms"},
+       {"rmac_unsup_ctrl_frms"},
+       {"rmac_ttl_octets"},
+       {"rmac_accepted_ucst_frms"},
+       {"rmac_accepted_nucst_frms"},
        {"rmac_discarded_frms"},
+       {"rmac_drop_events"},
+       {"rmac_ttl_less_fb_octets"},
+       {"rmac_ttl_frms"},
        {"rmac_usized_frms"},
        {"rmac_osized_frms"},
        {"rmac_frag_frms"},
        {"rmac_jabber_frms"},
+       {"rmac_ttl_64_frms"},
+       {"rmac_ttl_65_127_frms"},
+       {"rmac_ttl_128_255_frms"},
+       {"rmac_ttl_256_511_frms"},
+       {"rmac_ttl_512_1023_frms"},
+       {"rmac_ttl_1024_1518_frms"},
        {"rmac_ip"},
        {"rmac_ip_octets"},
        {"rmac_hdr_err_ip"},
@@ -166,12 +187,82 @@ static char ethtool_stats_keys[][ETH_GSTRING_LEN] = {
        {"rmac_tcp"},
        {"rmac_udp"},
        {"rmac_err_drp_udp"},
+       {"rmac_xgmii_err_sym"},
+       {"rmac_frms_q0"},
+       {"rmac_frms_q1"},
+       {"rmac_frms_q2"},
+       {"rmac_frms_q3"},
+       {"rmac_frms_q4"},
+       {"rmac_frms_q5"},
+       {"rmac_frms_q6"},
+       {"rmac_frms_q7"},
+       {"rmac_full_q0"},
+       {"rmac_full_q1"},
+       {"rmac_full_q2"},
+       {"rmac_full_q3"},
+       {"rmac_full_q4"},
+       {"rmac_full_q5"},
+       {"rmac_full_q6"},
+       {"rmac_full_q7"},
        {"rmac_pause_cnt"},
+       {"rmac_xgmii_data_err_cnt"},
+       {"rmac_xgmii_ctrl_err_cnt"},
        {"rmac_accepted_ip"},
        {"rmac_err_tcp"},
+       {"rd_req_cnt"},
+       {"new_rd_req_cnt"},
+       {"new_rd_req_rtry_cnt"},
+       {"rd_rtry_cnt"},
+       {"wr_rtry_rd_ack_cnt"},
+       {"wr_req_cnt"},
+       {"new_wr_req_cnt"},
+       {"new_wr_req_rtry_cnt"},
+       {"wr_rtry_cnt"},
+       {"wr_disc_cnt"},
+       {"rd_rtry_wr_ack_cnt"},
+       {"txp_wr_cnt"},
+       {"txd_rd_cnt"},
+       {"txd_wr_cnt"},
+       {"rxd_rd_cnt"},
+       {"rxd_wr_cnt"},
+       {"txf_rd_cnt"},
+       {"rxf_wr_cnt"},
+       {"rmac_ttl_1519_4095_frms"},
+       {"rmac_ttl_4096_8191_frms"},
+       {"rmac_ttl_8192_max_frms"},
+       {"rmac_ttl_gt_max_frms"},
+       {"rmac_osized_alt_frms"},
+       {"rmac_jabber_alt_frms"},
+       {"rmac_gt_max_alt_frms"},
+       {"rmac_vlan_frms"},
+       {"rmac_len_discard"},
+       {"rmac_fcs_discard"},
+       {"rmac_pf_discard"},
+       {"rmac_da_discard"},
+       {"rmac_red_discard"},
+       {"rmac_rts_discard"},
+       {"rmac_ingm_full_discard"},
+       {"link_fault_cnt"},
        {"\n DRIVER STATISTICS"},
        {"single_bit_ecc_errs"},
        {"double_bit_ecc_errs"},
+       {"parity_err_cnt"},
+       {"serious_err_cnt"},
+       {"soft_reset_cnt"},
+       {"fifo_full_cnt"},
+       {"ring_full_cnt"},
+       ("alarm_transceiver_temp_high"),
+       ("alarm_transceiver_temp_low"),
+       ("alarm_laser_bias_current_high"),
+       ("alarm_laser_bias_current_low"),
+       ("alarm_laser_output_power_high"),
+       ("alarm_laser_output_power_low"),
+       ("warn_transceiver_temp_high"),
+       ("warn_transceiver_temp_low"),
+       ("warn_laser_bias_current_high"),
+       ("warn_laser_bias_current_low"),
+       ("warn_laser_output_power_high"),
+       ("warn_laser_output_power_low"),
        ("lro_aggregated_pkts"),
        ("lro_flush_both_count"),
        ("lro_out_of_sequence_pkts"),
@@ -220,9 +311,7 @@ static void s2io_vlan_rx_kill_vid(struct net_device *dev, unsigned long vid)
  * the XAUI.
  */
 
-#define SWITCH_SIGN    0xA5A5A5A5A5A5A5A5ULL
 #define        END_SIGN        0x0
-
 static const u64 herc_act_dtx_cfg[] = {
        /* Set address */
        0x8000051536750000ULL, 0x80000515367500E0ULL,
@@ -244,37 +333,19 @@ static const u64 herc_act_dtx_cfg[] = {
        END_SIGN
 };
 
-static const u64 xena_mdio_cfg[] = {
-       /* Reset PMA PLL */
-       0xC001010000000000ULL, 0xC0010100000000E0ULL,
-       0xC0010100008000E4ULL,
-       /* Remove Reset from PMA PLL */
-       0xC001010000000000ULL, 0xC0010100000000E0ULL,
-       0xC0010100000000E4ULL,
-       END_SIGN
-};
-
 static const u64 xena_dtx_cfg[] = {
+       /* Set address */
        0x8000051500000000ULL, 0x80000515000000E0ULL,
-       0x80000515D93500E4ULL, 0x8001051500000000ULL,
-       0x80010515000000E0ULL, 0x80010515001E00E4ULL,
-       0x8002051500000000ULL, 0x80020515000000E0ULL,
-       0x80020515F21000E4ULL,
-       /* Set PADLOOPBACKN */
-       0x8002051500000000ULL, 0x80020515000000E0ULL,
-       0x80020515B20000E4ULL, 0x8003051500000000ULL,
-       0x80030515000000E0ULL, 0x80030515B20000E4ULL,
-       0x8004051500000000ULL, 0x80040515000000E0ULL,
-       0x80040515B20000E4ULL, 0x8005051500000000ULL,
-       0x80050515000000E0ULL, 0x80050515B20000E4ULL,
-       SWITCH_SIGN,
-       /* Remove PADLOOPBACKN */
+       /* Write data */
+       0x80000515D9350004ULL, 0x80000515D93500E4ULL,
+       /* Set address */
+       0x8001051500000000ULL, 0x80010515000000E0ULL,
+       /* Write data */
+       0x80010515001E0004ULL, 0x80010515001E00E4ULL,
+       /* Set address */
        0x8002051500000000ULL, 0x80020515000000E0ULL,
-       0x80020515F20000E4ULL, 0x8003051500000000ULL,
-       0x80030515000000E0ULL, 0x80030515F20000E4ULL,
-       0x8004051500000000ULL, 0x80040515000000E0ULL,
-       0x80040515F20000E4ULL, 0x8005051500000000ULL,
-       0x80050515000000E0ULL, 0x80050515F20000E4ULL,
+       /* Write data */
+       0x80020515F2100004ULL, 0x80020515F21000E4ULL,
        END_SIGN
 };
 
@@ -303,15 +374,15 @@ static const u64 fix_mac[] = {
 /* Module Loadable parameters. */
 static unsigned int tx_fifo_num = 1;
 static unsigned int tx_fifo_len[MAX_TX_FIFOS] =
-    {[0 ...(MAX_TX_FIFOS - 1)] = 0 };
+    {DEFAULT_FIFO_0_LEN, [1 ...(MAX_TX_FIFOS - 1)] = DEFAULT_FIFO_1_7_LEN};
 static unsigned int rx_ring_num = 1;
 static unsigned int rx_ring_sz[MAX_RX_RINGS] =
-    {[0 ...(MAX_RX_RINGS - 1)] = };
+    {[0 ...(MAX_RX_RINGS - 1)] = SMALL_BLK_CNT};
 static unsigned int rts_frm_len[MAX_RX_RINGS] =
     {[0 ...(MAX_RX_RINGS - 1)] = 0 };
 static unsigned int rx_ring_mode = 1;
 static unsigned int use_continuous_tx_intrs = 1;
-static unsigned int rmac_pause_time = 65535;
+static unsigned int rmac_pause_time = 0x100;
 static unsigned int mc_pause_threshold_q0q3 = 187;
 static unsigned int mc_pause_threshold_q4q7 = 187;
 static unsigned int shared_splits;
@@ -549,11 +620,6 @@ static int init_shared_mem(struct s2io_nic *nic)
                                        rx_blocks->block_dma_addr +
                                        (rxd_size[nic->rxd_mode] * l);
                        }
-
-                       mac_control->rings[i].rx_blocks[j].block_virt_addr =
-                               tmp_v_addr;
-                       mac_control->rings[i].rx_blocks[j].block_dma_addr =
-                               tmp_p_addr;
                }
                /* Interlinking all Rx Blocks */
                for (j = 0; j < blk_cnt; j++) {
@@ -772,7 +838,21 @@ static int s2io_verify_pci_mode(nic_t *nic)
        return mode;
 }
 
+#define NEC_VENID   0x1033
+#define NEC_DEVID   0x0125
+static int s2io_on_nec_bridge(struct pci_dev *s2io_pdev)
+{
+       struct pci_dev *tdev = NULL;
+       while ((tdev = pci_find_device(PCI_ANY_ID, PCI_ANY_ID, tdev)) != NULL) {
+               if ((tdev->vendor == NEC_VENID) && (tdev->device == NEC_DEVID)){
+                       if (tdev->bus == s2io_pdev->bus->parent)
+                               return 1;
+               }
+       }
+       return 0;
+}
 
+int bus_speed[8] = {33, 133, 133, 200, 266, 133, 200, 266};
 /**
  * s2io_print_pci_mode -
  */
@@ -789,6 +869,14 @@ static int s2io_print_pci_mode(nic_t *nic)
        if ( val64 & PCI_MODE_UNKNOWN_MODE)
                return -1;      /* Unknown PCI mode */
 
+       config->bus_speed = bus_speed[mode];
+
+       if (s2io_on_nec_bridge(nic->pdev)) {
+               DBG_PRINT(ERR_DBG, "%s: Device is on PCI-E bus\n",
+                                                       nic->dev->name);
+               return mode;
+       }
+
        if (val64 & PCI_MODE_32_BITS) {
                DBG_PRINT(ERR_DBG, "%s: Device is on 32 bit ", nic->dev->name);
        } else {
@@ -798,35 +886,27 @@ static int s2io_print_pci_mode(nic_t *nic)
        switch(mode) {
                case PCI_MODE_PCI_33:
                        DBG_PRINT(ERR_DBG, "33MHz PCI bus\n");
-                       config->bus_speed = 33;
                        break;
                case PCI_MODE_PCI_66:
                        DBG_PRINT(ERR_DBG, "66MHz PCI bus\n");
-                       config->bus_speed = 133;
                        break;
                case PCI_MODE_PCIX_M1_66:
                        DBG_PRINT(ERR_DBG, "66MHz PCIX(M1) bus\n");
-                       config->bus_speed = 133; /* Herc doubles the clock rate */
                        break;
                case PCI_MODE_PCIX_M1_100:
                        DBG_PRINT(ERR_DBG, "100MHz PCIX(M1) bus\n");
-                       config->bus_speed = 200;
                        break;
                case PCI_MODE_PCIX_M1_133:
                        DBG_PRINT(ERR_DBG, "133MHz PCIX(M1) bus\n");
-                       config->bus_speed = 266;
                        break;
                case PCI_MODE_PCIX_M2_66:
                        DBG_PRINT(ERR_DBG, "133MHz PCIX(M2) bus\n");
-                       config->bus_speed = 133;
                        break;
                case PCI_MODE_PCIX_M2_100:
                        DBG_PRINT(ERR_DBG, "200MHz PCIX(M2) bus\n");
-                       config->bus_speed = 200;
                        break;
                case PCI_MODE_PCIX_M2_133:
                        DBG_PRINT(ERR_DBG, "266MHz PCIX(M2) bus\n");
-                       config->bus_speed = 266;
                        break;
                default:
                        return -1;      /* Unsupported bus speed */
@@ -854,7 +934,7 @@ static int init_nic(struct s2io_nic *nic)
        int i, j;
        mac_info_t *mac_control;
        struct config_param *config;
-       int mdio_cnt = 0, dtx_cnt = 0;
+       int dtx_cnt = 0;
        unsigned long long mem_share;
        int mem_size;
 
@@ -901,20 +981,6 @@ static int init_nic(struct s2io_nic *nic)
        val64 = dev->mtu;
        writeq(vBIT(val64, 2, 14), &bar0->rmac_max_pyld_len);
 
-       /*
-        * Configuring the XAUI Interface of Xena.
-        * ***************************************
-        * To Configure the Xena's XAUI, one has to write a series
-        * of 64 bit values into two registers in a particular
-        * sequence. Hence a macro 'SWITCH_SIGN' has been defined
-        * which will be defined in the array of configuration values
-        * (xena_dtx_cfg & xena_mdio_cfg) at appropriate places
-        * to switch writing from one regsiter to another. We continue
-        * writing these values until we encounter the 'END_SIGN' macro.
-        * For example, After making a series of 21 writes into
-        * dtx_control register the 'SWITCH_SIGN' appears and hence we
-        * start writing into mdio_control until we encounter END_SIGN.
-        */
        if (nic->device_type & XFRAME_II_DEVICE) {
                while (herc_act_dtx_cfg[dtx_cnt] != END_SIGN) {
                        SPECIAL_REG_WRITE(herc_act_dtx_cfg[dtx_cnt],
@@ -924,35 +990,11 @@ static int init_nic(struct s2io_nic *nic)
                        dtx_cnt++;
                }
        } else {
-               while (1) {
-                     dtx_cfg:
-                       while (xena_dtx_cfg[dtx_cnt] != END_SIGN) {
-                               if (xena_dtx_cfg[dtx_cnt] == SWITCH_SIGN) {
-                                       dtx_cnt++;
-                                       goto mdio_cfg;
-                               }
-                               SPECIAL_REG_WRITE(xena_dtx_cfg[dtx_cnt],
-                                                 &bar0->dtx_control, UF);
-                               val64 = readq(&bar0->dtx_control);
-                               dtx_cnt++;
-                       }
-                     mdio_cfg:
-                       while (xena_mdio_cfg[mdio_cnt] != END_SIGN) {
-                               if (xena_mdio_cfg[mdio_cnt] == SWITCH_SIGN) {
-                                       mdio_cnt++;
-                                       goto dtx_cfg;
-                               }
-                               SPECIAL_REG_WRITE(xena_mdio_cfg[mdio_cnt],
-                                                 &bar0->mdio_control, UF);
-                               val64 = readq(&bar0->mdio_control);
-                               mdio_cnt++;
-                       }
-                       if ((xena_dtx_cfg[dtx_cnt] == END_SIGN) &&
-                           (xena_mdio_cfg[mdio_cnt] == END_SIGN)) {
-                               break;
-                       } else {
-                               goto dtx_cfg;
-                       }
+               while (xena_dtx_cfg[dtx_cnt] != END_SIGN) {
+                       SPECIAL_REG_WRITE(xena_dtx_cfg[dtx_cnt],
+                                         &bar0->dtx_control, UF);
+                       val64 = readq(&bar0->dtx_control);
+                       dtx_cnt++;
                }
        }
 
@@ -994,11 +1036,6 @@ static int init_nic(struct s2io_nic *nic)
                }
        }
 
-       /* Enable Tx FIFO partition 0. */
-       val64 = readq(&bar0->tx_fifo_partition_0);
-       val64 |= BIT(0);        /* To enable the FIFO partition. */
-       writeq(val64, &bar0->tx_fifo_partition_0);
-
        /*
         * Disable 4 PCCs for Xena1, 2 and 3 as per H/W bug
         * SXE-008 TRANSMIT DMA ARBITRATION ISSUE.
@@ -1177,6 +1214,11 @@ static int init_nic(struct s2io_nic *nic)
                break;
        }
 
+       /* Enable Tx FIFO partition 0. */
+       val64 = readq(&bar0->tx_fifo_partition_0);
+       val64 |= (TX_FIFO_PARTITION_EN);
+       writeq(val64, &bar0->tx_fifo_partition_0);
+
        /* Filling the Rx round robin registers as per the
         * number of Rings and steering based on QoS.
          */
@@ -1545,19 +1587,26 @@ static int init_nic(struct s2io_nic *nic)
        val64 |= PIC_CNTL_SHARED_SPLITS(shared_splits);
        writeq(val64, &bar0->pic_control);
 
+       if (nic->config.bus_speed == 266) {
+               writeq(TXREQTO_VAL(0x7f) | TXREQTO_EN, &bar0->txreqtimeout);
+               writeq(0x0, &bar0->read_retry_delay);
+               writeq(0x0, &bar0->write_retry_delay);
+       }
+
        /*
         * Programming the Herc to split every write transaction
         * that does not start on an ADB to reduce disconnects.
         */
        if (nic->device_type == XFRAME_II_DEVICE) {
-               val64 = WREQ_SPLIT_MASK_SET_MASK(255);
-               writeq(val64, &bar0->wreq_split_mask);
-       }
-
-       /* Setting Link stability period to 64 ms */ 
-       if (nic->device_type == XFRAME_II_DEVICE) {
-               val64 = MISC_LINK_STABILITY_PRD(3);
+               val64 = EXT_REQ_EN | MISC_LINK_STABILITY_PRD(3);
                writeq(val64, &bar0->misc_control);
+               val64 = readq(&bar0->pic_control2);
+               val64 &= ~(BIT(13)|BIT(14)|BIT(15));
+               writeq(val64, &bar0->pic_control2);
+       }
+       if (strstr(nic->product_name, "CX4")) {
+               val64 = TMAC_AVG_IPG(0x17);
+               writeq(val64, &bar0->tmac_avg_ipg);
        }
 
        return SUCCESS;
@@ -1948,6 +1997,10 @@ static int start_nic(struct s2io_nic *nic)
                        val64 |= PRC_CTRL_RC_ENABLED;
                else
                        val64 |= PRC_CTRL_RC_ENABLED | PRC_CTRL_RING_MODE_3;
+               if (nic->device_type == XFRAME_II_DEVICE)
+                       val64 |= PRC_CTRL_GROUP_READS;
+               val64 &= ~PRC_CTRL_RXD_BACKOFF_INTERVAL(0xFFFFFF);
+               val64 |= PRC_CTRL_RXD_BACKOFF_INTERVAL(0x1000);
                writeq(val64, &bar0->prc_ctrl_n[i]);
        }
 
@@ -2018,6 +2071,13 @@ static int start_nic(struct s2io_nic *nic)
        val64 |= ADAPTER_EOI_TX_ON;
        writeq(val64, &bar0->adapter_control);
 
+       if (s2io_link_fault_indication(nic) == MAC_RMAC_ERR_TIMER) {
+               /*
+                * Dont see link state interrupts initally on some switches,
+                * so directly scheduling the link state task here.
+                */
+               schedule_work(&nic->set_link_task);
+       }
        /* SXE-002: Initialize link and activity LED */
        subid = nic->pdev->subsystem_device;
        if (((subid & 0xFF) >= 0x07) &&
@@ -2029,12 +2089,6 @@ static int start_nic(struct s2io_nic *nic)
                writeq(val64, (void __iomem *)bar0 + 0x2700);
        }
 
-       /*
-        * Don't see link state interrupts on certain switches, so
-        * directly scheduling a link state task from here.
-        */
-       schedule_work(&nic->set_link_task);
-
        return SUCCESS;
 }
 /**
@@ -2134,7 +2188,7 @@ static void stop_nic(struct s2io_nic *nic)
 {
        XENA_dev_config_t __iomem *bar0 = nic->bar0;
        register u64 val64 = 0;
-       u16 interruptible, i;
+       u16 interruptible;
        mac_info_t *mac_control;
        struct config_param *config;
 
@@ -2147,12 +2201,10 @@ static void stop_nic(struct s2io_nic *nic)
        interruptible |= TX_MAC_INTR | RX_MAC_INTR;
        en_dis_able_nic_intrs(nic, interruptible, DISABLE_INTRS);
 
-       /*  Disable PRCs */
-       for (i = 0; i < config->rx_ring_num; i++) {
-               val64 = readq(&bar0->prc_ctrl_n[i]);
-               val64 &= ~((u64) PRC_CTRL_RC_ENABLED);
-               writeq(val64, &bar0->prc_ctrl_n[i]);
-       }
+       /* Clearing Adapter_En bit of ADAPTER_CONTROL Register */
+       val64 = readq(&bar0->adapter_control);
+       val64 &= ~(ADAPTER_CNTL_EN);
+       writeq(val64, &bar0->adapter_control);
 }
 
 static int fill_rxd_3buf(nic_t *nic, RxD_t *rxdp, struct sk_buff *skb)
@@ -2231,13 +2283,12 @@ static int fill_rx_buffers(struct s2io_nic *nic, int ring_no)
        alloc_cnt = mac_control->rings[ring_no].pkt_cnt -
            atomic_read(&nic->rx_bufs_left[ring_no]);
 
+       block_no1 = mac_control->rings[ring_no].rx_curr_get_info.block_index;
+       off1 = mac_control->rings[ring_no].rx_curr_get_info.offset;
        while (alloc_tab < alloc_cnt) {
                block_no = mac_control->rings[ring_no].rx_curr_put_info.
                    block_index;
-               block_no1 = mac_control->rings[ring_no].rx_curr_get_info.
-                   block_index;
                off = mac_control->rings[ring_no].rx_curr_put_info.offset;
-               off1 = mac_control->rings[ring_no].rx_curr_get_info.offset;
 
                rxdp = mac_control->rings[ring_no].
                                rx_blocks[block_no].rxds[off].virt_addr;
@@ -2307,9 +2358,9 @@ static int fill_rx_buffers(struct s2io_nic *nic, int ring_no)
                        memset(rxdp, 0, sizeof(RxD1_t));
                        skb_reserve(skb, NET_IP_ALIGN);
                        ((RxD1_t*)rxdp)->Buffer0_ptr = pci_map_single
-                           (nic->pdev, skb->data, size, PCI_DMA_FROMDEVICE);
-                       rxdp->Control_2 &= (~MASK_BUFFER0_SIZE_1);
-                       rxdp->Control_2 |= SET_BUFFER0_SIZE_1(size);
+                           (nic->pdev, skb->data, size - NET_IP_ALIGN,
+                               PCI_DMA_FROMDEVICE);
+                       rxdp->Control_2 = SET_BUFFER0_SIZE_1(size - NET_IP_ALIGN);
 
                } else if (nic->rxd_mode >= RXD_MODE_3A) {
                        /*
@@ -2516,7 +2567,7 @@ static int s2io_poll(struct net_device *dev, int *budget)
        mac_info_t *mac_control;
        struct config_param *config;
        XENA_dev_config_t __iomem *bar0 = nic->bar0;
-       u64 val64;
+       u64 val64 = 0xFFFFFFFFFFFFFFFFULL;
        int i;
 
        atomic_inc(&nic->isr_cnt);
@@ -2528,8 +2579,8 @@ static int s2io_poll(struct net_device *dev, int *budget)
                nic->pkts_to_process = dev->quota;
        org_pkts_to_process = nic->pkts_to_process;
 
-       val64 = readq(&bar0->rx_traffic_int);
        writeq(val64, &bar0->rx_traffic_int);
+       val64 = readl(&bar0->rx_traffic_int);
 
        for (i = 0; i < config->rx_ring_num; i++) {
                rx_intr_handler(&mac_control->rings[i]);
@@ -2554,7 +2605,8 @@ static int s2io_poll(struct net_device *dev, int *budget)
                }
        }
        /* Re enable the Rx interrupts. */
-       en_dis_able_nic_intrs(nic, RX_TRAFFIC_INTR, ENABLE_INTRS);
+       writeq(0x0, &bar0->rx_traffic_mask);
+       val64 = readl(&bar0->rx_traffic_mask);
        atomic_dec(&nic->isr_cnt);
        return 0;
 
@@ -2666,6 +2718,7 @@ static void rx_intr_handler(ring_info_t *ring_data)
                                         ((RxD3_t*)rxdp)->Buffer2_ptr,
                                         dev->mtu, PCI_DMA_FROMDEVICE);
                }
+               prefetch(skb->data);
                rx_osm_handler(ring_data, rxdp);
                get_info.offset++;
                ring_data->rx_curr_get_info.offset = get_info.offset;
@@ -2737,6 +2790,10 @@ static void tx_intr_handler(fifo_info_t *fifo_data)
                if (txdlp->Control_1 & TXD_T_CODE) {
                        unsigned long long err;
                        err = txdlp->Control_1 & TXD_T_CODE;
+                       if (err & 0x1) {
+                               nic->mac_control.stats_info->sw_stat.
+                                               parity_err_cnt++;
+                       }
                        if ((err >> 48) == 0xA) {
                                DBG_PRINT(TX_DBG, "TxD returned due \
 to loss of link\n");
@@ -2760,7 +2817,8 @@ to loss of link\n");
                dev_kfree_skb_irq(skb);
 
                get_info.offset++;
-               get_info.offset %= get_info.fifo_len + 1;
+               if (get_info.offset == get_info.fifo_len + 1)
+                       get_info.offset = 0;
                txdlp = (TxD_t *) fifo_data->list_info
                    [get_info.offset].list_virt_addr;
                fifo_data->tx_curr_get_info.offset =
@@ -2773,6 +2831,256 @@ to loss of link\n");
        spin_unlock(&nic->tx_lock);
 }
 
+/**
+ *  s2io_mdio_write - Function to write in to MDIO registers
+ *  @mmd_type : MMD type value (PMA/PMD/WIS/PCS/PHYXS)
+ *  @addr     : address value
+ *  @value    : data value
+ *  @dev      : pointer to net_device structure
+ *  Description:
+ *  This function is used to write values to the MDIO registers
+ *  NONE
+ */
+static void s2io_mdio_write(u32 mmd_type, u64 addr, u16 value, struct net_device *dev)
+{
+       u64 val64 = 0x0;
+       nic_t *sp = dev->priv;
+       XENA_dev_config_t *bar0 = (XENA_dev_config_t *)sp->bar0;
+
+       //address transaction
+       val64 = val64 | MDIO_MMD_INDX_ADDR(addr)
+                       | MDIO_MMD_DEV_ADDR(mmd_type)
+                       | MDIO_MMS_PRT_ADDR(0x0);
+       writeq(val64, &bar0->mdio_control);
+       val64 = val64 | MDIO_CTRL_START_TRANS(0xE);
+       writeq(val64, &bar0->mdio_control);
+       udelay(100);
+
+       //Data transaction
+       val64 = 0x0;
+       val64 = val64 | MDIO_MMD_INDX_ADDR(addr)
+                       | MDIO_MMD_DEV_ADDR(mmd_type)
+                       | MDIO_MMS_PRT_ADDR(0x0)
+                       | MDIO_MDIO_DATA(value)
+                       | MDIO_OP(MDIO_OP_WRITE_TRANS);
+       writeq(val64, &bar0->mdio_control);
+       val64 = val64 | MDIO_CTRL_START_TRANS(0xE);
+       writeq(val64, &bar0->mdio_control);
+       udelay(100);
+
+       val64 = 0x0;
+       val64 = val64 | MDIO_MMD_INDX_ADDR(addr)
+       | MDIO_MMD_DEV_ADDR(mmd_type)
+       | MDIO_MMS_PRT_ADDR(0x0)
+       | MDIO_OP(MDIO_OP_READ_TRANS);
+       writeq(val64, &bar0->mdio_control);
+       val64 = val64 | MDIO_CTRL_START_TRANS(0xE);
+       writeq(val64, &bar0->mdio_control);
+       udelay(100);
+
+}
+
+/**
+ *  s2io_mdio_read - Function to write in to MDIO registers
+ *  @mmd_type : MMD type value (PMA/PMD/WIS/PCS/PHYXS)
+ *  @addr     : address value
+ *  @dev      : pointer to net_device structure
+ *  Description:
+ *  This function is used to read values to the MDIO registers
+ *  NONE
+ */
+static u64 s2io_mdio_read(u32 mmd_type, u64 addr, struct net_device *dev)
+{
+       u64 val64 = 0x0;
+       u64 rval64 = 0x0;
+       nic_t *sp = dev->priv;
+       XENA_dev_config_t *bar0 = (XENA_dev_config_t *)sp->bar0;
+
+       /* address transaction */
+       val64 = val64 | MDIO_MMD_INDX_ADDR(addr)
+                       | MDIO_MMD_DEV_ADDR(mmd_type)
+                       | MDIO_MMS_PRT_ADDR(0x0);
+       writeq(val64, &bar0->mdio_control);
+       val64 = val64 | MDIO_CTRL_START_TRANS(0xE);
+       writeq(val64, &bar0->mdio_control);
+       udelay(100);
+
+       /* Data transaction */
+       val64 = 0x0;
+       val64 = val64 | MDIO_MMD_INDX_ADDR(addr)
+                       | MDIO_MMD_DEV_ADDR(mmd_type)
+                       | MDIO_MMS_PRT_ADDR(0x0)
+                       | MDIO_OP(MDIO_OP_READ_TRANS);
+       writeq(val64, &bar0->mdio_control);
+       val64 = val64 | MDIO_CTRL_START_TRANS(0xE);
+       writeq(val64, &bar0->mdio_control);
+       udelay(100);
+
+       /* Read the value from regs */
+       rval64 = readq(&bar0->mdio_control);
+       rval64 = rval64 & 0xFFFF0000;
+       rval64 = rval64 >> 16;
+       return rval64;
+}
+/**
+ *  s2io_chk_xpak_counter - Function to check the status of the xpak counters
+ *  @counter      : couter value to be updated
+ *  @flag         : flag to indicate the status
+ *  @type         : counter type
+ *  Description:
+ *  This function is to check the status of the xpak counters value
+ *  NONE
+ */
+
+static void s2io_chk_xpak_counter(u64 *counter, u64 * regs_stat, u32 index, u16 flag, u16 type)
+{
+       u64 mask = 0x3;
+       u64 val64;
+       int i;
+       for(i = 0; i <index; i++)
+               mask = mask << 0x2;
+
+       if(flag > 0)
+       {
+               *counter = *counter + 1;
+               val64 = *regs_stat & mask;
+               val64 = val64 >> (index * 0x2);
+               val64 = val64 + 1;
+               if(val64 == 3)
+               {
+                       switch(type)
+                       {
+                       case 1:
+                               DBG_PRINT(ERR_DBG, "Take Xframe NIC out of "
+                                         "service. Excessive temperatures may "
+                                         "result in premature transceiver "
+                                         "failure \n");
+                       break;
+                       case 2:
+                               DBG_PRINT(ERR_DBG, "Take Xframe NIC out of "
+                                         "service Excessive bias currents may "
+                                         "indicate imminent laser diode "
+                                         "failure \n");
+                       break;
+                       case 3:
+                               DBG_PRINT(ERR_DBG, "Take Xframe NIC out of "
+                                         "service Excessive laser output "
+                                         "power may saturate far-end "
+                                         "receiver\n");
+                       break;
+                       default:
+                               DBG_PRINT(ERR_DBG, "Incorrect XPAK Alarm "
+                                         "type \n");
+                       }
+                       val64 = 0x0;
+               }
+               val64 = val64 << (index * 0x2);
+               *regs_stat = (*regs_stat & (~mask)) | (val64);
+
+       } else {
+               *regs_stat = *regs_stat & (~mask);
+       }
+}
+
+/**
+ *  s2io_updt_xpak_counter - Function to update the xpak counters
+ *  @dev         : pointer to net_device struct
+ *  Description:
+ *  This function is to upate the status of the xpak counters value
+ *  NONE
+ */
+static void s2io_updt_xpak_counter(struct net_device *dev)
+{
+       u16 flag  = 0x0;
+       u16 type  = 0x0;
+       u16 val16 = 0x0;
+       u64 val64 = 0x0;
+       u64 addr  = 0x0;
+
+       nic_t *sp = dev->priv;
+       StatInfo_t *stat_info = sp->mac_control.stats_info;
+
+       /* Check the communication with the MDIO slave */
+       addr = 0x0000;
+       val64 = 0x0;
+       val64 = s2io_mdio_read(MDIO_MMD_PMA_DEV_ADDR, addr, dev);
+       if((val64 == 0xFFFF) || (val64 == 0x0000))
+       {
+               DBG_PRINT(ERR_DBG, "ERR: MDIO slave access failed - "
+                         "Returned %llx\n", (unsigned long long)val64);
+               return;
+       }
+
+       /* Check for the expecte value of 2040 at PMA address 0x0000 */
+       if(val64 != 0x2040)
+       {
+               DBG_PRINT(ERR_DBG, "Incorrect value at PMA address 0x0000 - ");
+               DBG_PRINT(ERR_DBG, "Returned: %llx- Expected: 0x2040\n",
+                         (unsigned long long)val64);
+               return;
+       }
+
+       /* Loading the DOM register to MDIO register */
+       addr = 0xA100;
+       s2io_mdio_write(MDIO_MMD_PMA_DEV_ADDR, addr, val16, dev);
+       val64 = s2io_mdio_read(MDIO_MMD_PMA_DEV_ADDR, addr, dev);
+
+       /* Reading the Alarm flags */
+       addr = 0xA070;
+       val64 = 0x0;
+       val64 = s2io_mdio_read(MDIO_MMD_PMA_DEV_ADDR, addr, dev);
+
+       flag = CHECKBIT(val64, 0x7);
+       type = 1;
+       s2io_chk_xpak_counter(&stat_info->xpak_stat.alarm_transceiver_temp_high,
+                               &stat_info->xpak_stat.xpak_regs_stat,
+                               0x0, flag, type);
+
+       if(CHECKBIT(val64, 0x6))
+               stat_info->xpak_stat.alarm_transceiver_temp_low++;
+
+       flag = CHECKBIT(val64, 0x3);
+       type = 2;
+       s2io_chk_xpak_counter(&stat_info->xpak_stat.alarm_laser_bias_current_high,
+                               &stat_info->xpak_stat.xpak_regs_stat,
+                               0x2, flag, type);
+
+       if(CHECKBIT(val64, 0x2))
+               stat_info->xpak_stat.alarm_laser_bias_current_low++;
+
+       flag = CHECKBIT(val64, 0x1);
+       type = 3;
+       s2io_chk_xpak_counter(&stat_info->xpak_stat.alarm_laser_output_power_high,
+                               &stat_info->xpak_stat.xpak_regs_stat,
+                               0x4, flag, type);
+
+       if(CHECKBIT(val64, 0x0))
+               stat_info->xpak_stat.alarm_laser_output_power_low++;
+
+       /* Reading the Warning flags */
+       addr = 0xA074;
+       val64 = 0x0;
+       val64 = s2io_mdio_read(MDIO_MMD_PMA_DEV_ADDR, addr, dev);
+
+       if(CHECKBIT(val64, 0x7))
+               stat_info->xpak_stat.warn_transceiver_temp_high++;
+
+       if(CHECKBIT(val64, 0x6))
+               stat_info->xpak_stat.warn_transceiver_temp_low++;
+
+       if(CHECKBIT(val64, 0x3))
+               stat_info->xpak_stat.warn_laser_bias_current_high++;
+
+       if(CHECKBIT(val64, 0x2))
+               stat_info->xpak_stat.warn_laser_bias_current_low++;
+
+       if(CHECKBIT(val64, 0x1))
+               stat_info->xpak_stat.warn_laser_output_power_high++;
+
+       if(CHECKBIT(val64, 0x0))
+               stat_info->xpak_stat.warn_laser_output_power_low++;
+}
+
 /**
  *  alarm_intr_handler - Alarm Interrrupt handler
  *  @nic: device private variable
@@ -2790,6 +3098,18 @@ static void alarm_intr_handler(struct s2io_nic *nic)
        struct net_device *dev = (struct net_device *) nic->dev;
        XENA_dev_config_t __iomem *bar0 = nic->bar0;
        register u64 val64 = 0, err_reg = 0;
+       u64 cnt;
+       int i;
+       nic->mac_control.stats_info->sw_stat.ring_full_cnt = 0;
+       /* Handling the XPAK counters update */
+       if(nic->mac_control.stats_info->xpak_stat.xpak_timer_count < 72000) {
+               /* waiting for an hour */
+               nic->mac_control.stats_info->xpak_stat.xpak_timer_count++;
+       } else {
+               s2io_updt_xpak_counter(dev);
+               /* reset the count to zero */
+               nic->mac_control.stats_info->xpak_stat.xpak_timer_count = 0;
+       }
 
        /* Handling link status change error Intr */
        if (s2io_link_fault_indication(nic) == MAC_RMAC_ERR_TIMER) {
@@ -2816,6 +3136,8 @@ static void alarm_intr_handler(struct s2io_nic *nic)
                                             MC_ERR_REG_MIRI_ECC_DB_ERR_1)) {
                                        netif_stop_queue(dev);
                                        schedule_work(&nic->rst_timer_task);
+                                       nic->mac_control.stats_info->sw_stat.
+                                                       soft_reset_cnt++;
                                }
                        }
                } else {
@@ -2827,11 +3149,13 @@ static void alarm_intr_handler(struct s2io_nic *nic)
        /* In case of a serious error, the device will be Reset. */
        val64 = readq(&bar0->serr_source);
        if (val64 & SERR_SOURCE_ANY) {
+               nic->mac_control.stats_info->sw_stat.serious_err_cnt++;
                DBG_PRINT(ERR_DBG, "%s: Device indicates ", dev->name);
                DBG_PRINT(ERR_DBG, "serious error %llx!!\n", 
                          (unsigned long long)val64);
                netif_stop_queue(dev);
                schedule_work(&nic->rst_timer_task);
+               nic->mac_control.stats_info->sw_stat.soft_reset_cnt++;
        }
 
        /*
@@ -2849,6 +3173,35 @@ static void alarm_intr_handler(struct s2io_nic *nic)
                ac = readq(&bar0->adapter_control);
                schedule_work(&nic->set_link_task);
        }
+       /* Check for data parity error */
+       val64 = readq(&bar0->pic_int_status);
+       if (val64 & PIC_INT_GPIO) {
+               val64 = readq(&bar0->gpio_int_reg);
+               if (val64 & GPIO_INT_REG_DP_ERR_INT) {
+                       nic->mac_control.stats_info->sw_stat.parity_err_cnt++;
+                       schedule_work(&nic->rst_timer_task);
+                       nic->mac_control.stats_info->sw_stat.soft_reset_cnt++;
+               }
+       }
+
+       /* Check for ring full counter */
+       if (nic->device_type & XFRAME_II_DEVICE) {
+               val64 = readq(&bar0->ring_bump_counter1);
+               for (i=0; i<4; i++) {
+                       cnt = ( val64 & vBIT(0xFFFF,(i*16),16));
+                       cnt >>= 64 - ((i+1)*16);
+                       nic->mac_control.stats_info->sw_stat.ring_full_cnt
+                               += cnt;
+               }
+
+               val64 = readq(&bar0->ring_bump_counter2);
+               for (i=0; i<4; i++) {
+                       cnt = ( val64 & vBIT(0xFFFF,(i*16),16));
+                       cnt >>= 64 - ((i+1)*16);
+                       nic->mac_control.stats_info->sw_stat.ring_full_cnt
+                               += cnt;
+               }
+       }
 
        /* Other type of interrupts are not being handled now,  TODO */
 }
@@ -2864,23 +3217,26 @@ static void alarm_intr_handler(struct s2io_nic *nic)
  *   SUCCESS on success and FAILURE on failure.
  */
 
-static int wait_for_cmd_complete(nic_t * sp)
+static int wait_for_cmd_complete(void *addr, u64 busy_bit)
 {
-       XENA_dev_config_t __iomem *bar0 = sp->bar0;
        int ret = FAILURE, cnt = 0;
        u64 val64;
 
        while (TRUE) {
-               val64 = readq(&bar0->rmac_addr_cmd_mem);
-               if (!(val64 & RMAC_ADDR_CMD_MEM_STROBE_CMD_EXECUTING)) {
+               val64 = readq(addr);
+               if (!(val64 & busy_bit)) {
                        ret = SUCCESS;
                        break;
                }
-               msleep(50);
+
+               if(in_interrupt())
+                       mdelay(50);
+               else
+                       msleep(50);
+
                if (cnt++ > 10)
                        break;
        }
-
        return ret;
 }
 
@@ -2919,6 +3275,9 @@ static void s2io_reset(nic_t * sp)
         * PCI write to sw_reset register is done by this time.
         */
        msleep(250);
+       if (strstr(sp->product_name, "CX4")) {
+               msleep(750);
+       }
 
        /* Restore the PCI state saved during initialization. */
        pci_restore_state(sp->pdev);
@@ -3137,7 +3496,7 @@ static void restore_xmsi_data(nic_t *nic)
        u64 val64;
        int i;
 
-       for (i=0; i< MAX_REQUESTED_MSI_X; i++) {
+       for (i=0; i< nic->avail_msix_vectors; i++) {
                writeq(nic->msix_info[i].addr, &bar0->xmsi_address);
                writeq(nic->msix_info[i].data, &bar0->xmsi_data);
                val64 = (BIT(7) | BIT(15) | vBIT(i, 26, 6));
@@ -3156,7 +3515,7 @@ static void store_xmsi_data(nic_t *nic)
        int i;
 
        /* Store and display */
-       for (i=0; i< MAX_REQUESTED_MSI_X; i++) {
+       for (i=0; i< nic->avail_msix_vectors; i++) {
                val64 = (BIT(15) | vBIT(i, 26, 6));
                writeq(val64, &bar0->xmsi_access);
                if (wait_for_msix_trans(nic, i)) {
@@ -3284,15 +3643,24 @@ static int s2io_enable_msi_x(nic_t *nic)
                writeq(tx_mat, &bar0->tx_mat0_n[7]);
        }
 
+       nic->avail_msix_vectors = 0;
        ret = pci_enable_msix(nic->pdev, nic->entries, MAX_REQUESTED_MSI_X);
+       /* We fail init if error or we get less vectors than min required */
+       if (ret >= (nic->config.tx_fifo_num + nic->config.rx_ring_num + 1)) {
+               nic->avail_msix_vectors = ret;
+               ret = pci_enable_msix(nic->pdev, nic->entries, ret);
+       }
        if (ret) {
                DBG_PRINT(ERR_DBG, "%s: Enabling MSIX failed\n", nic->dev->name);
                kfree(nic->entries);
                kfree(nic->s2io_entries);
                nic->entries = NULL;
                nic->s2io_entries = NULL;
+               nic->avail_msix_vectors = 0;
                return -ENOMEM;
        }
+       if (!nic->avail_msix_vectors)
+               nic->avail_msix_vectors = MAX_REQUESTED_MSI_X;
 
        /*
         * To enable MSI-X, MSI also needs to be enabled, due to a bug
@@ -3325,8 +3693,6 @@ static int s2io_open(struct net_device *dev)
 {
        nic_t *sp = dev->priv;
        int err = 0;
-       int i;
-       u16 msi_control; /* Temp variable */
 
        /*
         * Make sure you have link off by default every time
@@ -3336,11 +3702,14 @@ static int s2io_open(struct net_device *dev)
        sp->last_link_state = 0;
 
        /* Initialize H/W and enable interrupts */
-       if (s2io_card_up(sp)) {
+       err = s2io_card_up(sp);
+       if (err) {
                DBG_PRINT(ERR_DBG, "%s: H/W initialization failed\n",
                          dev->name);
-               err = -ENODEV;
-               goto hw_init_failed;
+               if (err == -ENODEV)
+                       goto hw_init_failed;
+               else
+                       goto hw_enable_failed;
        }
 
        /* Store the values of the MSIX table in the nic_t structure */
@@ -3357,6 +3726,8 @@ failed\n", dev->name);
                }
        }
        if (sp->intr_type == MSI_X) {
+               int i;
+
                for (i=1; (sp->s2io_entries[i].in_use == MSIX_FLG); i++) {
                        if (sp->s2io_entries[i].type == MSIX_FIFO_TYPE) {
                                sprintf(sp->desc1, "%s:MSI-X-%d-TX",
@@ -3409,24 +3780,26 @@ setting_mac_address_failed:
 isr_registration_failed:
        del_timer_sync(&sp->alarm_timer);
        if (sp->intr_type == MSI_X) {
-               if (sp->device_type == XFRAME_II_DEVICE) {
-                       for (i=1; (sp->s2io_entries[i].in_use == 
-                               MSIX_REGISTERED_SUCCESS); i++) {
-                               int vector = sp->entries[i].vector;
-                               void *arg = sp->s2io_entries[i].arg;
+               int i;
+               u16 msi_control; /* Temp variable */
 
-                               free_irq(vector, arg);
-                       }
-                       pci_disable_msix(sp->pdev);
+               for (i=1; (sp->s2io_entries[i].in_use == 
+                               MSIX_REGISTERED_SUCCESS); i++) {
+                       int vector = sp->entries[i].vector;
+                       void *arg = sp->s2io_entries[i].arg;
 
-                       /* Temp */
-                       pci_read_config_word(sp->pdev, 0x42, &msi_control);
-                       msi_control &= 0xFFFE; /* Disable MSI */
-                       pci_write_config_word(sp->pdev, 0x42, msi_control);
+                       free_irq(vector, arg);
                }
+               pci_disable_msix(sp->pdev);
+
+               /* Temp */
+               pci_read_config_word(sp->pdev, 0x42, &msi_control);
+               msi_control &= 0xFFFE; /* Disable MSI */
+               pci_write_config_word(sp->pdev, 0x42, msi_control);
        }
        else if (sp->intr_type == MSI)
                pci_disable_msi(sp->pdev);
+hw_enable_failed:
        s2io_reset(sp);
 hw_init_failed:
        if (sp->intr_type == MSI_X) {
@@ -3454,35 +3827,12 @@ hw_init_failed:
 static int s2io_close(struct net_device *dev)
 {
        nic_t *sp = dev->priv;
-       int i;
-       u16 msi_control;
 
        flush_scheduled_work();
        netif_stop_queue(dev);
        /* Reset card, kill tasklet and free Tx and Rx buffers. */
-       s2io_card_down(sp);
-
-       if (sp->intr_type == MSI_X) {
-               if (sp->device_type == XFRAME_II_DEVICE) {
-                       for (i=1; (sp->s2io_entries[i].in_use == 
-                                       MSIX_REGISTERED_SUCCESS); i++) {
-                               int vector = sp->entries[i].vector;
-                               void *arg = sp->s2io_entries[i].arg;
+       s2io_card_down(sp, 1);
 
-                               free_irq(vector, arg);
-                       }
-                       pci_read_config_word(sp->pdev, 0x42, &msi_control);
-                       msi_control &= 0xFFFE; /* Disable MSI */
-                       pci_write_config_word(sp->pdev, 0x42, msi_control);
-
-                       pci_disable_msix(sp->pdev);
-               }
-       }
-       else {
-               free_irq(sp->pdev->irq, dev);
-               if (sp->intr_type == MSI)
-                       pci_disable_msi(sp->pdev);
-       }       
        sp->device_close_flag = TRUE;   /* Device is shut down. */
        return 0;
 }
@@ -3545,7 +3895,8 @@ static int s2io_xmit(struct sk_buff *skb, struct net_device *dev)
 
        queue_len = mac_control->fifos[queue].tx_curr_put_info.fifo_len + 1;
        /* Avoid "put" pointer going beyond "get" pointer */
-       if (txdp->Host_Control || (((put_off + 1) % queue_len) == get_off)) {
+       if (txdp->Host_Control ||
+                  ((put_off+1) == queue_len ? 0 : (put_off+1)) == get_off) {
                DBG_PRINT(TX_DBG, "Error in xmit, No free TXDs.\n");
                netif_stop_queue(dev);
                dev_kfree_skb(skb);
@@ -3655,11 +4006,13 @@ static int s2io_xmit(struct sk_buff *skb, struct net_device *dev)
        mmiowb();
 
        put_off++;
-       put_off %= mac_control->fifos[queue].tx_curr_put_info.fifo_len + 1;
+       if (put_off == mac_control->fifos[queue].tx_curr_put_info.fifo_len + 1)
+               put_off = 0;
        mac_control->fifos[queue].tx_curr_put_info.offset = put_off;
 
        /* Avoid "put" pointer going beyond "get" pointer */
-       if (((put_off + 1) % queue_len) == get_off) {
+       if (((put_off+1) == queue_len ? 0 : (put_off+1)) == get_off) {
+               sp->mac_control.stats_info->sw_stat.fifo_full_cnt++;
                DBG_PRINT(TX_DBG,
                          "No free TxDs for xmit, Put: 0x%x Get:0x%x\n",
                          put_off, get_off);
@@ -3795,7 +4148,6 @@ s2io_msix_fifo_handle(int irq, void *dev_id, struct pt_regs *regs)
        atomic_dec(&sp->isr_cnt);
        return IRQ_HANDLED;
 }
-
 static void s2io_txpic_intr_handle(nic_t *sp)
 {
        XENA_dev_config_t __iomem *bar0 = sp->bar0;
@@ -3806,41 +4158,56 @@ static void s2io_txpic_intr_handle(nic_t *sp)
                val64 = readq(&bar0->gpio_int_reg);
                if ((val64 & GPIO_INT_REG_LINK_DOWN) &&
                    (val64 & GPIO_INT_REG_LINK_UP)) {
+                       /*
+                        * This is unstable state so clear both up/down
+                        * interrupt and adapter to re-evaluate the link state.
+                        */
                        val64 |=  GPIO_INT_REG_LINK_DOWN;
                        val64 |= GPIO_INT_REG_LINK_UP;
                        writeq(val64, &bar0->gpio_int_reg);
-                       goto masking;
-               }
-
-               if (((sp->last_link_state == LINK_UP) &&
-                       (val64 & GPIO_INT_REG_LINK_DOWN)) ||
-               ((sp->last_link_state == LINK_DOWN) &&
-               (val64 & GPIO_INT_REG_LINK_UP))) {
                        val64 = readq(&bar0->gpio_int_mask);
-                       val64 |=  GPIO_INT_MASK_LINK_DOWN;
-                       val64 |= GPIO_INT_MASK_LINK_UP;
+                       val64 &= ~(GPIO_INT_MASK_LINK_UP |
+                                  GPIO_INT_MASK_LINK_DOWN);
                        writeq(val64, &bar0->gpio_int_mask);
-                       s2io_set_link((unsigned long)sp);
                }
-masking:
-               if (sp->last_link_state == LINK_UP) {
-                       /*enable down interrupt */
-                       val64 = readq(&bar0->gpio_int_mask);
-                       /* unmasks link down intr */
-                       val64 &=  ~GPIO_INT_MASK_LINK_DOWN;
-                       /* masks link up intr */
-                       val64 |= GPIO_INT_MASK_LINK_UP;
-                       writeq(val64, &bar0->gpio_int_mask);
-               } else {
-                       /*enable UP Interrupt */
-                       val64 = readq(&bar0->gpio_int_mask);
-                       /* unmasks link up interrupt */
-                       val64 &= ~GPIO_INT_MASK_LINK_UP;
-                       /* masks link down interrupt */
-                       val64 |=  GPIO_INT_MASK_LINK_DOWN;
-                       writeq(val64, &bar0->gpio_int_mask);
+               else if (val64 & GPIO_INT_REG_LINK_UP) {
+                       val64 = readq(&bar0->adapter_status);
+                       if (verify_xena_quiescence(sp, val64,
+                                                  sp->device_enabled_once)) {
+                               /* Enable Adapter */
+                               val64 = readq(&bar0->adapter_control);
+                               val64 |= ADAPTER_CNTL_EN;
+                               writeq(val64, &bar0->adapter_control);
+                               val64 |= ADAPTER_LED_ON;
+                               writeq(val64, &bar0->adapter_control);
+                               if (!sp->device_enabled_once)
+                                       sp->device_enabled_once = 1;
+
+                               s2io_link(sp, LINK_UP);
+                               /*
+                                * unmask link down interrupt and mask link-up
+                                * intr
+                                */
+                               val64 = readq(&bar0->gpio_int_mask);
+                               val64 &= ~GPIO_INT_MASK_LINK_DOWN;
+                               val64 |= GPIO_INT_MASK_LINK_UP;
+                               writeq(val64, &bar0->gpio_int_mask);
+
+                       }
+               }else if (val64 & GPIO_INT_REG_LINK_DOWN) {
+                       val64 = readq(&bar0->adapter_status);
+                       if (verify_xena_quiescence(sp, val64,
+                                                  sp->device_enabled_once)) {
+                               s2io_link(sp, LINK_DOWN);
+                               /* Link is down so unmaks link up interrupt */
+                               val64 = readq(&bar0->gpio_int_mask);
+                               val64 &= ~GPIO_INT_MASK_LINK_UP;
+                               val64 |= GPIO_INT_MASK_LINK_DOWN;
+                               writeq(val64, &bar0->gpio_int_mask);
+                       }
                }
        }
+       val64 = readq(&bar0->gpio_int_mask);
 }
 
 /**
@@ -3863,7 +4230,7 @@ static irqreturn_t s2io_isr(int irq, void *dev_id, struct pt_regs *regs)
        nic_t *sp = dev->priv;
        XENA_dev_config_t __iomem *bar0 = sp->bar0;
        int i;
-       u64 reason = 0, val64;
+       u64 reason = 0, val64, org_mask;
        mac_info_t *mac_control;
        struct config_param *config;
 
@@ -3887,43 +4254,41 @@ static irqreturn_t s2io_isr(int irq, void *dev_id, struct pt_regs *regs)
                return IRQ_NONE;
        }
 
+       val64 = 0xFFFFFFFFFFFFFFFFULL;
+       /* Store current mask before masking all interrupts */
+       org_mask = readq(&bar0->general_int_mask);
+       writeq(val64, &bar0->general_int_mask);
+
 #ifdef CONFIG_S2IO_NAPI
        if (reason & GEN_INTR_RXTRAFFIC) {
                if (netif_rx_schedule_prep(dev)) {
-                       en_dis_able_nic_intrs(sp, RX_TRAFFIC_INTR,
-                                             DISABLE_INTRS);
+                       writeq(val64, &bar0->rx_traffic_mask);
                        __netif_rx_schedule(dev);
                }
        }
 #else
-       /* If Intr is because of Rx Traffic */
-       if (reason & GEN_INTR_RXTRAFFIC) {
-               /*
-                * rx_traffic_int reg is an R1 register, writing all 1's
-                * will ensure that the actual interrupt causing bit get's
-                * cleared and hence a read can be avoided.
-                */
-               val64 = 0xFFFFFFFFFFFFFFFFULL;
-               writeq(val64, &bar0->rx_traffic_int);
-               for (i = 0; i < config->rx_ring_num; i++) {
-                       rx_intr_handler(&mac_control->rings[i]);
-               }
+       /*
+        * Rx handler is called by default, without checking for the
+        * cause of interrupt.
+        * rx_traffic_int reg is an R1 register, writing all 1's
+        * will ensure that the actual interrupt causing bit get's
+        * cleared and hence a read can be avoided.
+        */
+       writeq(val64, &bar0->rx_traffic_int);
+       for (i = 0; i < config->rx_ring_num; i++) {
+               rx_intr_handler(&mac_control->rings[i]);
        }
 #endif
 
-       /* If Intr is because of Tx Traffic */
-       if (reason & GEN_INTR_TXTRAFFIC) {
-               /*
-                * tx_traffic_int reg is an R1 register, writing all 1's
-                * will ensure that the actual interrupt causing bit get's
-                * cleared and hence a read can be avoided.
-                */
-               val64 = 0xFFFFFFFFFFFFFFFFULL;
-               writeq(val64, &bar0->tx_traffic_int);
+       /*
+        * tx_traffic_int reg is an R1 register, writing all 1's
+        * will ensure that the actual interrupt causing bit get's
+        * cleared and hence a read can be avoided.
+        */
+       writeq(val64, &bar0->tx_traffic_int);
 
-               for (i = 0; i < config->tx_fifo_num; i++)
-                       tx_intr_handler(&mac_control->fifos[i]);
-       }
+       for (i = 0; i < config->tx_fifo_num; i++)
+               tx_intr_handler(&mac_control->fifos[i]);
 
        if (reason & GEN_INTR_TXPIC)
                s2io_txpic_intr_handle(sp);
@@ -3949,6 +4314,7 @@ static irqreturn_t s2io_isr(int irq, void *dev_id, struct pt_regs *regs)
                                        DBG_PRINT(ERR_DBG, " in ISR!!\n");
                                        clear_bit(0, (&sp->tasklet_status));
                                        atomic_dec(&sp->isr_cnt);
+                                       writeq(org_mask, &bar0->general_int_mask);
                                        return IRQ_HANDLED;
                                }
                                clear_bit(0, (&sp->tasklet_status));
@@ -3964,7 +4330,7 @@ static irqreturn_t s2io_isr(int irq, void *dev_id, struct pt_regs *regs)
                }
        }
 #endif
-
+       writeq(org_mask, &bar0->general_int_mask);
        atomic_dec(&sp->isr_cnt);
        return IRQ_HANDLED;
 }
@@ -4067,7 +4433,8 @@ static void s2io_set_multicast(struct net_device *dev)
                    RMAC_ADDR_CMD_MEM_OFFSET(MAC_MC_ALL_MC_ADDR_OFFSET);
                writeq(val64, &bar0->rmac_addr_cmd_mem);
                /* Wait till command completes */
-               wait_for_cmd_complete(sp);
+               wait_for_cmd_complete(&bar0->rmac_addr_cmd_mem,
+                                     RMAC_ADDR_CMD_MEM_STROBE_CMD_EXECUTING);
 
                sp->m_cast_flg = 1;
                sp->all_multi_pos = MAC_MC_ALL_MC_ADDR_OFFSET;
@@ -4082,7 +4449,8 @@ static void s2io_set_multicast(struct net_device *dev)
                    RMAC_ADDR_CMD_MEM_OFFSET(sp->all_multi_pos);
                writeq(val64, &bar0->rmac_addr_cmd_mem);
                /* Wait till command completes */
-               wait_for_cmd_complete(sp);
+               wait_for_cmd_complete(&bar0->rmac_addr_cmd_mem,
+                                     RMAC_ADDR_CMD_MEM_STROBE_CMD_EXECUTING);
 
                sp->m_cast_flg = 0;
                sp->all_multi_pos = 0;
@@ -4147,7 +4515,8 @@ static void s2io_set_multicast(struct net_device *dev)
                        writeq(val64, &bar0->rmac_addr_cmd_mem);
 
                        /* Wait for command completes */
-                       if (wait_for_cmd_complete(sp)) {
+                       if (wait_for_cmd_complete(&bar0->rmac_addr_cmd_mem,
+                                     RMAC_ADDR_CMD_MEM_STROBE_CMD_EXECUTING)) {
                                DBG_PRINT(ERR_DBG, "%s: Adding ",
                                          dev->name);
                                DBG_PRINT(ERR_DBG, "Multicasts failed\n");
@@ -4177,7 +4546,8 @@ static void s2io_set_multicast(struct net_device *dev)
                        writeq(val64, &bar0->rmac_addr_cmd_mem);
 
                        /* Wait for command completes */
-                       if (wait_for_cmd_complete(sp)) {
+                       if (wait_for_cmd_complete(&bar0->rmac_addr_cmd_mem,
+                                     RMAC_ADDR_CMD_MEM_STROBE_CMD_EXECUTING)) {
                                DBG_PRINT(ERR_DBG, "%s: Adding ",
                                          dev->name);
                                DBG_PRINT(ERR_DBG, "Multicasts failed\n");
@@ -4222,7 +4592,8 @@ static int s2io_set_mac_addr(struct net_device *dev, u8 * addr)
            RMAC_ADDR_CMD_MEM_OFFSET(0);
        writeq(val64, &bar0->rmac_addr_cmd_mem);
        /* Wait till command completes */
-       if (wait_for_cmd_complete(sp)) {
+       if (wait_for_cmd_complete(&bar0->rmac_addr_cmd_mem,
+                     RMAC_ADDR_CMD_MEM_STROBE_CMD_EXECUTING)) {
                DBG_PRINT(ERR_DBG, "%s: set_mac_addr failed\n", dev->name);
                return FAILURE;
        }
@@ -4619,6 +4990,44 @@ static int write_eeprom(nic_t * sp, int off, u64 data, int cnt)
        }
        return ret;
 }
+static void s2io_vpd_read(nic_t *nic)
+{
+       u8 vpd_data[256],data;
+       int i=0, cnt, fail = 0;
+       int vpd_addr = 0x80;
+
+       if (nic->device_type == XFRAME_II_DEVICE) {
+               strcpy(nic->product_name, "Xframe II 10GbE network adapter");
+               vpd_addr = 0x80;
+       }
+       else {
+               strcpy(nic->product_name, "Xframe I 10GbE network adapter");
+               vpd_addr = 0x50;
+       }
+
+       for (i = 0; i < 256; i +=4 ) {
+               pci_write_config_byte(nic->pdev, (vpd_addr + 2), i);
+               pci_read_config_byte(nic->pdev,  (vpd_addr + 2), &data);
+               pci_write_config_byte(nic->pdev, (vpd_addr + 3), 0);
+               for (cnt = 0; cnt <5; cnt++) {
+                       msleep(2);
+                       pci_read_config_byte(nic->pdev, (vpd_addr + 3), &data);
+                       if (data == 0x80)
+                               break;
+               }
+               if (cnt >= 5) {
+                       DBG_PRINT(ERR_DBG, "Read of VPD data failed\n");
+                       fail = 1;
+                       break;
+               }
+               pci_read_config_dword(nic->pdev,  (vpd_addr + 4),
+                                     (u32 *)&vpd_data[i]);
+       }
+       if ((!fail) && (vpd_data[1] < VPD_PRODUCT_NAME_LEN)) {
+               memset(nic->product_name, 0, vpd_data[1]);
+               memcpy(nic->product_name, &vpd_data[3], vpd_data[1]);
+       }
+}
 
 /**
  *  s2io_ethtool_geeprom  - reads the value stored in the Eeprom.
@@ -4931,8 +5340,10 @@ static int s2io_link_test(nic_t * sp, uint64_t * data)
        u64 val64;
 
        val64 = readq(&bar0->adapter_status);
-       if (val64 & ADAPTER_STATUS_RMAC_LOCAL_FAULT)
+       if(!(LINK_IS_UP(val64)))
                *data = 1;
+       else
+               *data = 0;
 
        return 0;
 }
@@ -5112,7 +5523,6 @@ static void s2io_get_ethtool_stats(struct net_device *dev,
        int i = 0;
        nic_t *sp = dev->priv;
        StatInfo_t *stat_info = sp->mac_control.stats_info;
-       u64 tmp;
 
        s2io_updt_stats(sp);
        tmp_stats[i++] =
@@ -5129,9 +5539,19 @@ static void s2io_get_ethtool_stats(struct net_device *dev,
                (u64)le32_to_cpu(stat_info->tmac_bcst_frms_oflow) << 32 |
                le32_to_cpu(stat_info->tmac_bcst_frms);
        tmp_stats[i++] = le64_to_cpu(stat_info->tmac_pause_ctrl_frms);
+        tmp_stats[i++] =
+                (u64)le32_to_cpu(stat_info->tmac_ttl_octets_oflow) << 32 |
+                le32_to_cpu(stat_info->tmac_ttl_octets);
+       tmp_stats[i++] =
+                (u64)le32_to_cpu(stat_info->tmac_ucst_frms_oflow) << 32 |
+                le32_to_cpu(stat_info->tmac_ucst_frms);
+       tmp_stats[i++] =
+                (u64)le32_to_cpu(stat_info->tmac_nucst_frms_oflow) << 32 |
+                le32_to_cpu(stat_info->tmac_nucst_frms);
        tmp_stats[i++] =
                (u64)le32_to_cpu(stat_info->tmac_any_err_frms_oflow) << 32 |
                le32_to_cpu(stat_info->tmac_any_err_frms);
+        tmp_stats[i++] = le64_to_cpu(stat_info->tmac_ttl_less_fb_octets);
        tmp_stats[i++] = le64_to_cpu(stat_info->tmac_vld_ip_octets);
        tmp_stats[i++] =
                (u64)le32_to_cpu(stat_info->tmac_vld_ip_oflow) << 32 |
@@ -5163,11 +5583,27 @@ static void s2io_get_ethtool_stats(struct net_device *dev,
                (u64)le32_to_cpu(stat_info->rmac_vld_bcst_frms_oflow) << 32 |
                le32_to_cpu(stat_info->rmac_vld_bcst_frms);
        tmp_stats[i++] = le32_to_cpu(stat_info->rmac_in_rng_len_err_frms);
+       tmp_stats[i++] = le32_to_cpu(stat_info->rmac_out_rng_len_err_frms);
        tmp_stats[i++] = le64_to_cpu(stat_info->rmac_long_frms);
        tmp_stats[i++] = le64_to_cpu(stat_info->rmac_pause_ctrl_frms);
+       tmp_stats[i++] = le64_to_cpu(stat_info->rmac_unsup_ctrl_frms);
+        tmp_stats[i++] =
+                (u64)le32_to_cpu(stat_info->rmac_ttl_octets_oflow) << 32 |
+               le32_to_cpu(stat_info->rmac_ttl_octets);
+        tmp_stats[i++] =
+                (u64)le32_to_cpu(stat_info->rmac_accepted_ucst_frms_oflow)
+               << 32 | le32_to_cpu(stat_info->rmac_accepted_ucst_frms);
+       tmp_stats[i++] =
+                (u64)le32_to_cpu(stat_info->rmac_accepted_nucst_frms_oflow)
+                 << 32 | le32_to_cpu(stat_info->rmac_accepted_nucst_frms);
        tmp_stats[i++] =
                (u64)le32_to_cpu(stat_info->rmac_discarded_frms_oflow) << 32 |
                le32_to_cpu(stat_info->rmac_discarded_frms);
+        tmp_stats[i++] =
+                (u64)le32_to_cpu(stat_info->rmac_drop_events_oflow)
+                 << 32 | le32_to_cpu(stat_info->rmac_drop_events);
+        tmp_stats[i++] = le64_to_cpu(stat_info->rmac_ttl_less_fb_octets);
+        tmp_stats[i++] = le64_to_cpu(stat_info->rmac_ttl_frms);
        tmp_stats[i++] =
                (u64)le32_to_cpu(stat_info->rmac_usized_frms_oflow) << 32 |
                le32_to_cpu(stat_info->rmac_usized_frms);
@@ -5180,40 +5616,129 @@ static void s2io_get_ethtool_stats(struct net_device *dev,
        tmp_stats[i++] =
                (u64)le32_to_cpu(stat_info->rmac_jabber_frms_oflow) << 32 |
                le32_to_cpu(stat_info->rmac_jabber_frms);
-       tmp_stats[i++] = (u64)le32_to_cpu(stat_info->rmac_ip_oflow) << 32 |
+       tmp_stats[i++] = le64_to_cpu(stat_info->rmac_ttl_64_frms);
+        tmp_stats[i++] = le64_to_cpu(stat_info->rmac_ttl_65_127_frms);
+        tmp_stats[i++] = le64_to_cpu(stat_info->rmac_ttl_128_255_frms);
+        tmp_stats[i++] = le64_to_cpu(stat_info->rmac_ttl_256_511_frms);
+        tmp_stats[i++] = le64_to_cpu(stat_info->rmac_ttl_512_1023_frms);
+        tmp_stats[i++] = le64_to_cpu(stat_info->rmac_ttl_1024_1518_frms);
+       tmp_stats[i++] =
+               (u64)le32_to_cpu(stat_info->rmac_ip_oflow) << 32 |
                le32_to_cpu(stat_info->rmac_ip);
        tmp_stats[i++] = le64_to_cpu(stat_info->rmac_ip_octets);
        tmp_stats[i++] = le32_to_cpu(stat_info->rmac_hdr_err_ip);
-       tmp_stats[i++] = (u64)le32_to_cpu(stat_info->rmac_drop_ip_oflow) << 32 |
+       tmp_stats[i++] =
+               (u64)le32_to_cpu(stat_info->rmac_drop_ip_oflow) << 32 |
                le32_to_cpu(stat_info->rmac_drop_ip);
-       tmp_stats[i++] = (u64)le32_to_cpu(stat_info->rmac_icmp_oflow) << 32 |
+       tmp_stats[i++] =
+               (u64)le32_to_cpu(stat_info->rmac_icmp_oflow) << 32 |
                le32_to_cpu(stat_info->rmac_icmp);
        tmp_stats[i++] = le64_to_cpu(stat_info->rmac_tcp);
-       tmp_stats[i++] = (u64)le32_to_cpu(stat_info->rmac_udp_oflow) << 32 |
+       tmp_stats[i++] =
+               (u64)le32_to_cpu(stat_info->rmac_udp_oflow) << 32 |
                le32_to_cpu(stat_info->rmac_udp);
        tmp_stats[i++] =
                (u64)le32_to_cpu(stat_info->rmac_err_drp_udp_oflow) << 32 |
                le32_to_cpu(stat_info->rmac_err_drp_udp);
+       tmp_stats[i++] = le64_to_cpu(stat_info->rmac_xgmii_err_sym);
+        tmp_stats[i++] = le64_to_cpu(stat_info->rmac_frms_q0);
+        tmp_stats[i++] = le64_to_cpu(stat_info->rmac_frms_q1);
+        tmp_stats[i++] = le64_to_cpu(stat_info->rmac_frms_q2);
+        tmp_stats[i++] = le64_to_cpu(stat_info->rmac_frms_q3);
+        tmp_stats[i++] = le64_to_cpu(stat_info->rmac_frms_q4);
+        tmp_stats[i++] = le64_to_cpu(stat_info->rmac_frms_q5);
+        tmp_stats[i++] = le64_to_cpu(stat_info->rmac_frms_q6);
+        tmp_stats[i++] = le64_to_cpu(stat_info->rmac_frms_q7);
+        tmp_stats[i++] = le16_to_cpu(stat_info->rmac_full_q0);
+        tmp_stats[i++] = le16_to_cpu(stat_info->rmac_full_q1);
+        tmp_stats[i++] = le16_to_cpu(stat_info->rmac_full_q2);
+        tmp_stats[i++] = le16_to_cpu(stat_info->rmac_full_q3);
+        tmp_stats[i++] = le16_to_cpu(stat_info->rmac_full_q4);
+        tmp_stats[i++] = le16_to_cpu(stat_info->rmac_full_q5);
+        tmp_stats[i++] = le16_to_cpu(stat_info->rmac_full_q6);
+        tmp_stats[i++] = le16_to_cpu(stat_info->rmac_full_q7);
        tmp_stats[i++] =
                (u64)le32_to_cpu(stat_info->rmac_pause_cnt_oflow) << 32 |
                le32_to_cpu(stat_info->rmac_pause_cnt);
+       tmp_stats[i++] = le64_to_cpu(stat_info->rmac_xgmii_data_err_cnt);
+        tmp_stats[i++] = le64_to_cpu(stat_info->rmac_xgmii_ctrl_err_cnt);
        tmp_stats[i++] =
                (u64)le32_to_cpu(stat_info->rmac_accepted_ip_oflow) << 32 |
                le32_to_cpu(stat_info->rmac_accepted_ip);
        tmp_stats[i++] = le32_to_cpu(stat_info->rmac_err_tcp);
+       tmp_stats[i++] = le32_to_cpu(stat_info->rd_req_cnt);
+       tmp_stats[i++] = le32_to_cpu(stat_info->new_rd_req_cnt);
+       tmp_stats[i++] = le32_to_cpu(stat_info->new_rd_req_rtry_cnt);
+       tmp_stats[i++] = le32_to_cpu(stat_info->rd_rtry_cnt);
+       tmp_stats[i++] = le32_to_cpu(stat_info->wr_rtry_rd_ack_cnt);
+       tmp_stats[i++] = le32_to_cpu(stat_info->wr_req_cnt);
+       tmp_stats[i++] = le32_to_cpu(stat_info->new_wr_req_cnt);
+       tmp_stats[i++] = le32_to_cpu(stat_info->new_wr_req_rtry_cnt);
+       tmp_stats[i++] = le32_to_cpu(stat_info->wr_rtry_cnt);
+       tmp_stats[i++] = le32_to_cpu(stat_info->wr_disc_cnt);
+       tmp_stats[i++] = le32_to_cpu(stat_info->rd_rtry_wr_ack_cnt);
+       tmp_stats[i++] = le32_to_cpu(stat_info->txp_wr_cnt);
+       tmp_stats[i++] = le32_to_cpu(stat_info->txd_rd_cnt);
+       tmp_stats[i++] = le32_to_cpu(stat_info->txd_wr_cnt);
+       tmp_stats[i++] = le32_to_cpu(stat_info->rxd_rd_cnt);
+       tmp_stats[i++] = le32_to_cpu(stat_info->rxd_wr_cnt);
+       tmp_stats[i++] = le32_to_cpu(stat_info->txf_rd_cnt);
+       tmp_stats[i++] = le32_to_cpu(stat_info->rxf_wr_cnt);
+       tmp_stats[i++] = le64_to_cpu(stat_info->rmac_ttl_1519_4095_frms);
+        tmp_stats[i++] = le64_to_cpu(stat_info->rmac_ttl_4096_8191_frms);
+        tmp_stats[i++] = le64_to_cpu(stat_info->rmac_ttl_8192_max_frms);
+        tmp_stats[i++] = le64_to_cpu(stat_info->rmac_ttl_gt_max_frms);
+        tmp_stats[i++] = le64_to_cpu(stat_info->rmac_osized_alt_frms);
+        tmp_stats[i++] = le64_to_cpu(stat_info->rmac_jabber_alt_frms);
+        tmp_stats[i++] = le64_to_cpu(stat_info->rmac_gt_max_alt_frms);
+        tmp_stats[i++] = le64_to_cpu(stat_info->rmac_vlan_frms);
+        tmp_stats[i++] = le32_to_cpu(stat_info->rmac_len_discard);
+        tmp_stats[i++] = le32_to_cpu(stat_info->rmac_fcs_discard);
+        tmp_stats[i++] = le32_to_cpu(stat_info->rmac_pf_discard);
+        tmp_stats[i++] = le32_to_cpu(stat_info->rmac_da_discard);
+        tmp_stats[i++] = le32_to_cpu(stat_info->rmac_red_discard);
+        tmp_stats[i++] = le32_to_cpu(stat_info->rmac_rts_discard);
+        tmp_stats[i++] = le32_to_cpu(stat_info->rmac_ingm_full_discard);
+        tmp_stats[i++] = le32_to_cpu(stat_info->link_fault_cnt);
        tmp_stats[i++] = 0;
        tmp_stats[i++] = stat_info->sw_stat.single_ecc_errs;
        tmp_stats[i++] = stat_info->sw_stat.double_ecc_errs;
+       tmp_stats[i++] = stat_info->sw_stat.parity_err_cnt;
+       tmp_stats[i++] = stat_info->sw_stat.serious_err_cnt;
+       tmp_stats[i++] = stat_info->sw_stat.soft_reset_cnt;
+       tmp_stats[i++] = stat_info->sw_stat.fifo_full_cnt;
+       tmp_stats[i++] = stat_info->sw_stat.ring_full_cnt;
+       tmp_stats[i++] = stat_info->xpak_stat.alarm_transceiver_temp_high;
+       tmp_stats[i++] = stat_info->xpak_stat.alarm_transceiver_temp_low;
+       tmp_stats[i++] = stat_info->xpak_stat.alarm_laser_bias_current_high;
+       tmp_stats[i++] = stat_info->xpak_stat.alarm_laser_bias_current_low;
+       tmp_stats[i++] = stat_info->xpak_stat.alarm_laser_output_power_high;
+       tmp_stats[i++] = stat_info->xpak_stat.alarm_laser_output_power_low;
+       tmp_stats[i++] = stat_info->xpak_stat.warn_transceiver_temp_high;
+       tmp_stats[i++] = stat_info->xpak_stat.warn_transceiver_temp_low;
+       tmp_stats[i++] = stat_info->xpak_stat.warn_laser_bias_current_high;
+       tmp_stats[i++] = stat_info->xpak_stat.warn_laser_bias_current_low;
+       tmp_stats[i++] = stat_info->xpak_stat.warn_laser_output_power_high;
+       tmp_stats[i++] = stat_info->xpak_stat.warn_laser_output_power_low;
        tmp_stats[i++] = stat_info->sw_stat.clubbed_frms_cnt;
        tmp_stats[i++] = stat_info->sw_stat.sending_both;
        tmp_stats[i++] = stat_info->sw_stat.outof_sequence_pkts;
        tmp_stats[i++] = stat_info->sw_stat.flush_max_pkts;
-       tmp = 0;
        if (stat_info->sw_stat.num_aggregations) {
-               tmp = stat_info->sw_stat.sum_avg_pkts_aggregated;
-               do_div(tmp, stat_info->sw_stat.num_aggregations);
+               u64 tmp = stat_info->sw_stat.sum_avg_pkts_aggregated;
+               int count = 0;
+               /* 
+                * Since 64-bit divide does not work on all platforms,
+                * do repeated subtraction.
+                */
+               while (tmp >= stat_info->sw_stat.num_aggregations) {
+                       tmp -= stat_info->sw_stat.num_aggregations;
+                       count++;
+               }
+               tmp_stats[i++] = count;
        }
-       tmp_stats[i++] = tmp;
+       else
+               tmp_stats[i++] = 0;
 }
 
 static int s2io_ethtool_get_regs_len(struct net_device *dev)
@@ -5351,7 +5876,7 @@ static int s2io_change_mtu(struct net_device *dev, int new_mtu)
 
        dev->mtu = new_mtu;
        if (netif_running(dev)) {
-               s2io_card_down(sp);
+               s2io_card_down(sp, 0);
                netif_stop_queue(dev);
                if (s2io_card_up(sp)) {
                        DBG_PRINT(ERR_DBG, "%s: Device bring up failed\n",
@@ -5489,12 +6014,172 @@ static void s2io_set_link(unsigned long data)
        clear_bit(0, &(nic->link_state));
 }
 
-static void s2io_card_down(nic_t * sp)
+static int set_rxd_buffer_pointer(nic_t *sp, RxD_t *rxdp, buffAdd_t *ba,
+                          struct sk_buff **skb, u64 *temp0, u64 *temp1,
+                          u64 *temp2, int size)
+{
+       struct net_device *dev = sp->dev;
+       struct sk_buff *frag_list;
+
+       if ((sp->rxd_mode == RXD_MODE_1) && (rxdp->Host_Control == 0)) {
+               /* allocate skb */
+               if (*skb) {
+                       DBG_PRINT(INFO_DBG, "SKB is not NULL\n");
+                       /*
+                        * As Rx frame are not going to be processed,
+                        * using same mapped address for the Rxd
+                        * buffer pointer
+                        */
+                       ((RxD1_t*)rxdp)->Buffer0_ptr = *temp0;
+               } else {
+                       *skb = dev_alloc_skb(size);
+                       if (!(*skb)) {
+                               DBG_PRINT(ERR_DBG, "%s: Out of ", dev->name);
+                               DBG_PRINT(ERR_DBG, "memory to allocate SKBs\n");
+                               return -ENOMEM ;
+                       }
+                       /* storing the mapped addr in a temp variable
+                        * such it will be used for next rxd whose
+                        * Host Control is NULL
+                        */
+                       ((RxD1_t*)rxdp)->Buffer0_ptr = *temp0 =
+                               pci_map_single( sp->pdev, (*skb)->data,
+                                       size - NET_IP_ALIGN,
+                                       PCI_DMA_FROMDEVICE);
+                       rxdp->Host_Control = (unsigned long) (*skb);
+               }
+       } else if ((sp->rxd_mode == RXD_MODE_3B) && (rxdp->Host_Control == 0)) {
+               /* Two buffer Mode */
+               if (*skb) {
+                       ((RxD3_t*)rxdp)->Buffer2_ptr = *temp2;
+                       ((RxD3_t*)rxdp)->Buffer0_ptr = *temp0;
+                       ((RxD3_t*)rxdp)->Buffer1_ptr = *temp1;
+               } else {
+                       *skb = dev_alloc_skb(size);
+                       ((RxD3_t*)rxdp)->Buffer2_ptr = *temp2 =
+                               pci_map_single(sp->pdev, (*skb)->data,
+                                              dev->mtu + 4,
+                                              PCI_DMA_FROMDEVICE);
+                       ((RxD3_t*)rxdp)->Buffer0_ptr = *temp0 =
+                               pci_map_single( sp->pdev, ba->ba_0, BUF0_LEN,
+                                               PCI_DMA_FROMDEVICE);
+                       rxdp->Host_Control = (unsigned long) (*skb);
+
+                       /* Buffer-1 will be dummy buffer not used */
+                       ((RxD3_t*)rxdp)->Buffer1_ptr = *temp1 =
+                               pci_map_single(sp->pdev, ba->ba_1, BUF1_LEN,
+                                              PCI_DMA_FROMDEVICE);
+               }
+       } else if ((rxdp->Host_Control == 0)) {
+               /* Three buffer mode */
+               if (*skb) {
+                       ((RxD3_t*)rxdp)->Buffer0_ptr = *temp0;
+                       ((RxD3_t*)rxdp)->Buffer1_ptr = *temp1;
+                       ((RxD3_t*)rxdp)->Buffer2_ptr = *temp2;
+               } else {
+                       *skb = dev_alloc_skb(size);
+
+                       ((RxD3_t*)rxdp)->Buffer0_ptr = *temp0 =
+                               pci_map_single(sp->pdev, ba->ba_0, BUF0_LEN,
+                                              PCI_DMA_FROMDEVICE);
+                       /* Buffer-1 receives L3/L4 headers */
+                       ((RxD3_t*)rxdp)->Buffer1_ptr = *temp1 =
+                               pci_map_single( sp->pdev, (*skb)->data,
+                                               l3l4hdr_size + 4,
+                                               PCI_DMA_FROMDEVICE);
+                       /*
+                        * skb_shinfo(skb)->frag_list will have L4
+                        * data payload
+                        */
+                       skb_shinfo(*skb)->frag_list = dev_alloc_skb(dev->mtu +
+                                                                  ALIGN_SIZE);
+                       if (skb_shinfo(*skb)->frag_list == NULL) {
+                               DBG_PRINT(ERR_DBG, "%s: dev_alloc_skb \
+                                         failed\n ", dev->name);
+                               return -ENOMEM ;
+                       }
+                       frag_list = skb_shinfo(*skb)->frag_list;
+                       frag_list->next = NULL;
+                       /*
+                        * Buffer-2 receives L4 data payload
+                        */
+                       ((RxD3_t*)rxdp)->Buffer2_ptr = *temp2 =
+                               pci_map_single( sp->pdev, frag_list->data,
+                                               dev->mtu, PCI_DMA_FROMDEVICE);
+               }
+       }
+       return 0;
+}
+static void set_rxd_buffer_size(nic_t *sp, RxD_t *rxdp, int size)
+{
+       struct net_device *dev = sp->dev;
+       if (sp->rxd_mode == RXD_MODE_1) {
+               rxdp->Control_2 = SET_BUFFER0_SIZE_1( size - NET_IP_ALIGN);
+       } else if (sp->rxd_mode == RXD_MODE_3B) {
+               rxdp->Control_2 = SET_BUFFER0_SIZE_3(BUF0_LEN);
+               rxdp->Control_2 |= SET_BUFFER1_SIZE_3(1);
+               rxdp->Control_2 |= SET_BUFFER2_SIZE_3( dev->mtu + 4);
+       } else {
+               rxdp->Control_2 = SET_BUFFER0_SIZE_3(BUF0_LEN);
+               rxdp->Control_2 |= SET_BUFFER1_SIZE_3(l3l4hdr_size + 4);
+               rxdp->Control_2 |= SET_BUFFER2_SIZE_3(dev->mtu);
+       }
+}
+
+static  int rxd_owner_bit_reset(nic_t *sp)
+{
+       int i, j, k, blk_cnt = 0, size;
+       mac_info_t * mac_control = &sp->mac_control;
+       struct config_param *config = &sp->config;
+       struct net_device *dev = sp->dev;
+       RxD_t *rxdp = NULL;
+       struct sk_buff *skb = NULL;
+       buffAdd_t *ba = NULL;
+       u64 temp0_64 = 0, temp1_64 = 0, temp2_64 = 0;
+
+       /* Calculate the size based on ring mode */
+       size = dev->mtu + HEADER_ETHERNET_II_802_3_SIZE +
+               HEADER_802_2_SIZE + HEADER_SNAP_SIZE;
+       if (sp->rxd_mode == RXD_MODE_1)
+               size += NET_IP_ALIGN;
+       else if (sp->rxd_mode == RXD_MODE_3B)
+               size = dev->mtu + ALIGN_SIZE + BUF0_LEN + 4;
+       else
+               size = l3l4hdr_size + ALIGN_SIZE + BUF0_LEN + 4;
+
+       for (i = 0; i < config->rx_ring_num; i++) {
+               blk_cnt = config->rx_cfg[i].num_rxd /
+                       (rxd_count[sp->rxd_mode] +1);
+
+               for (j = 0; j < blk_cnt; j++) {
+                       for (k = 0; k < rxd_count[sp->rxd_mode]; k++) {
+                               rxdp = mac_control->rings[i].
+                                       rx_blocks[j].rxds[k].virt_addr;
+                               if(sp->rxd_mode >= RXD_MODE_3A)
+                                       ba = &mac_control->rings[i].ba[j][k];
+                               set_rxd_buffer_pointer(sp, rxdp, ba,
+                                                      &skb,(u64 *)&temp0_64,
+                                                      (u64 *)&temp1_64,
+                                                      (u64 *)&temp2_64, size);
+
+                               set_rxd_buffer_size(sp, rxdp, size);
+                               wmb();
+                               /* flip the Ownership bit to Hardware */
+                               rxdp->Control_1 |= RXD_OWN_XENA;
+                       }
+               }
+       }
+       return 0;
+
+}
+
+static void s2io_card_down(nic_t * sp, int flag)
 {
        int cnt = 0;
        XENA_dev_config_t __iomem *bar0 = sp->bar0;
        unsigned long flags;
        register u64 val64 = 0;
+       struct net_device *dev = sp->dev;
 
        del_timer_sync(&sp->alarm_timer);
        /* If s2io_set_link task is executing, wait till it completes. */
@@ -5505,12 +6190,51 @@ static void s2io_card_down(nic_t * sp)
 
        /* disable Tx and Rx traffic on the NIC */
        stop_nic(sp);
+       if (flag) {
+               if (sp->intr_type == MSI_X) {
+                       int i;
+                       u16 msi_control;
+
+                       for (i=1; (sp->s2io_entries[i].in_use ==
+                               MSIX_REGISTERED_SUCCESS); i++) {
+                               int vector = sp->entries[i].vector;
+                               void *arg = sp->s2io_entries[i].arg;
+
+                               free_irq(vector, arg);
+                       }
+                       pci_read_config_word(sp->pdev, 0x42, &msi_control);
+                       msi_control &= 0xFFFE; /* Disable MSI */
+                       pci_write_config_word(sp->pdev, 0x42, msi_control);
+                       pci_disable_msix(sp->pdev);
+               } else {
+                       free_irq(sp->pdev->irq, dev);
+                       if (sp->intr_type == MSI)
+                               pci_disable_msi(sp->pdev);
+               }
+       }
+       /* Waiting till all Interrupt handlers are complete */
+       cnt = 0;
+       do {
+               msleep(10);
+               if (!atomic_read(&sp->isr_cnt))
+                       break;
+               cnt++;
+       } while(cnt < 5);
 
        /* Kill tasklet. */
        tasklet_kill(&sp->task);
 
        /* Check if the device is Quiescent and then Reset the NIC */
        do {
+               /* As per the HW requirement we need to replenish the
+                * receive buffer to avoid the ring bump. Since there is
+                * no intention of processing the Rx frame at this pointwe are
+                * just settting the ownership bit of rxd in Each Rx
+                * ring to HW and set the appropriate buffer size
+                * based on the ring mode
+                */
+               rxd_owner_bit_reset(sp);
+
                val64 = readq(&bar0->adapter_status);
                if (verify_xena_quiescence(sp, val64, sp->device_enabled_once)) {
                        break;
@@ -5528,15 +6252,6 @@ static void s2io_card_down(nic_t * sp)
        } while (1);
        s2io_reset(sp);
 
-       /* Waiting till all Interrupt handlers are complete */
-       cnt = 0;
-       do {
-               msleep(10);
-               if (!atomic_read(&sp->isr_cnt))
-                       break;
-               cnt++;
-       } while(cnt < 5);
-
        spin_lock_irqsave(&sp->tx_lock, flags);
        /* Free all Tx buffers */
        free_tx_buffers(sp);
@@ -5637,7 +6352,7 @@ static void s2io_restart_nic(unsigned long data)
        struct net_device *dev = (struct net_device *) data;
        nic_t *sp = dev->priv;
 
-       s2io_card_down(sp);
+       s2io_card_down(sp, 0);
        if (s2io_card_up(sp)) {
                DBG_PRINT(ERR_DBG, "%s: Device bring up failed\n",
                          dev->name);
@@ -5667,6 +6382,7 @@ static void s2io_tx_watchdog(struct net_device *dev)
 
        if (netif_carrier_ok(dev)) {
                schedule_work(&sp->rst_timer_task);
+               sp->mac_control.stats_info->sw_stat.soft_reset_cnt++;
        }
 }
 
@@ -5695,18 +6411,33 @@ static int rx_osm_handler(ring_info_t *ring_data, RxD_t * rxdp)
                ((unsigned long) rxdp->Host_Control);
        int ring_no = ring_data->ring_no;
        u16 l3_csum, l4_csum;
+       unsigned long long err = rxdp->Control_1 & RXD_T_CODE;
        lro_t *lro;
 
        skb->dev = dev;
-       if (rxdp->Control_1 & RXD_T_CODE) {
-               unsigned long long err = rxdp->Control_1 & RXD_T_CODE;
-               DBG_PRINT(ERR_DBG, "%s: Rx error Value: 0x%llx\n",
-                         dev->name, err);
-               dev_kfree_skb(skb);
-               sp->stats.rx_crc_errors++;
-               atomic_dec(&sp->rx_bufs_left[ring_no]);
-               rxdp->Host_Control = 0;
-               return 0;
+
+       if (err) {
+               /* Check for parity error */
+               if (err & 0x1) {
+                       sp->mac_control.stats_info->sw_stat.parity_err_cnt++;
+               }
+
+               /*
+               * Drop the packet if bad transfer code. Exception being
+               * 0x5, which could be due to unsupported IPv6 extension header.
+               * In this case, we let stack handle the packet.
+               * Note that in this case, since checksum will be incorrect,
+               * stack will validate the same.
+               */
+               if (err && ((err >> 48) != 0x5)) {
+                       DBG_PRINT(ERR_DBG, "%s: Rx error Value: 0x%llx\n",
+                               dev->name, err);
+                       sp->stats.rx_crc_errors++;
+                       dev_kfree_skb(skb);
+                       atomic_dec(&sp->rx_bufs_left[ring_no]);
+                       rxdp->Host_Control = 0;
+                       return 0;
+               }
        }
 
        /* Updating statistics */
@@ -5792,6 +6523,9 @@ static int rx_osm_handler(ring_info_t *ring_data, RxD_t * rxdp)
                                                clear_lro_session(lro);
                                                goto send_up;
                                        case 0: /* sessions exceeded */
+                                       case -1: /* non-TCP or not
+                                                 * L2 aggregatable
+                                                 */
                                        case 5: /*
                                                 * First pkt in session not
                                                 * L3/L4 aggregatable
@@ -5918,13 +6652,6 @@ static void s2io_init_pci(nic_t * sp)
        pci_write_config_word(sp->pdev, PCI_COMMAND,
                              (pci_cmd | PCI_COMMAND_PARITY));
        pci_read_config_word(sp->pdev, PCI_COMMAND, &pci_cmd);
-
-       /* Forcibly disabling relaxed ordering capability of the card. */
-       pcix_cmd &= 0xfffd;
-       pci_write_config_word(sp->pdev, PCIX_COMMAND_REGISTER,
-                             pcix_cmd);
-       pci_read_config_word(sp->pdev, PCIX_COMMAND_REGISTER,
-                            &(pcix_cmd));
 }
 
 MODULE_AUTHOR("Raghavendra Koushik <raghavendra.koushik@neterion.com>");
@@ -5954,6 +6681,55 @@ module_param(intr_type, int, 0);
 module_param(lro, int, 0);
 module_param(lro_max_pkts, int, 0);
 
+static int s2io_verify_parm(struct pci_dev *pdev, u8 *dev_intr_type)
+{
+       if ( tx_fifo_num > 8) {
+               DBG_PRINT(ERR_DBG, "s2io: Requested number of Tx fifos not "
+                        "supported\n");
+               DBG_PRINT(ERR_DBG, "s2io: Default to 8 Tx fifos\n");
+               tx_fifo_num = 8;
+       }
+       if ( rx_ring_num > 8) {
+               DBG_PRINT(ERR_DBG, "s2io: Requested number of Rx rings not "
+                        "supported\n");
+               DBG_PRINT(ERR_DBG, "s2io: Default to 8 Rx rings\n");
+               rx_ring_num = 8;
+       }
+#ifdef CONFIG_S2IO_NAPI
+       if (*dev_intr_type != INTA) {
+               DBG_PRINT(ERR_DBG, "s2io: NAPI cannot be enabled when "
+                         "MSI/MSI-X is enabled. Defaulting to INTA\n");
+               *dev_intr_type = INTA;
+       }
+#endif
+#ifndef CONFIG_PCI_MSI
+       if (*dev_intr_type != INTA) {
+               DBG_PRINT(ERR_DBG, "s2io: This kernel does not support"
+                         "MSI/MSI-X. Defaulting to INTA\n");
+               *dev_intr_type = INTA;
+       }
+#else
+       if (*dev_intr_type > MSI_X) {
+               DBG_PRINT(ERR_DBG, "s2io: Wrong intr_type requested. "
+                         "Defaulting to INTA\n");
+               *dev_intr_type = INTA;
+       }
+#endif
+       if ((*dev_intr_type == MSI_X) &&
+                       ((pdev->device != PCI_DEVICE_ID_HERC_WIN) &&
+                       (pdev->device != PCI_DEVICE_ID_HERC_UNI))) {
+               DBG_PRINT(ERR_DBG, "s2io: Xframe I does not support MSI_X. " 
+                                       "Defaulting to INTA\n");
+               *dev_intr_type = INTA;
+       }
+       if (rx_ring_mode > 3) {
+               DBG_PRINT(ERR_DBG, "s2io: Requested ring mode not supported\n");
+               DBG_PRINT(ERR_DBG, "s2io: Defaulting to 3-buffer mode\n");
+               rx_ring_mode = 3;
+       }
+       return SUCCESS;
+}
+
 /**
  *  s2io_init_nic - Initialization of the adapter .
  *  @pdev : structure containing the PCI related information of the device.
@@ -5984,15 +6760,8 @@ s2io_init_nic(struct pci_dev *pdev, const struct pci_device_id *pre)
        int mode;
        u8 dev_intr_type = intr_type;
 
-#ifdef CONFIG_S2IO_NAPI
-       if (dev_intr_type != INTA) {
-               DBG_PRINT(ERR_DBG, "NAPI cannot be enabled when MSI/MSI-X \
-is enabled. Defaulting to INTA\n");
-               dev_intr_type = INTA;
-       }
-       else
-               DBG_PRINT(ERR_DBG, "NAPI support has been enabled\n");
-#endif
+       if ((ret = s2io_verify_parm(pdev, &dev_intr_type)))
+               return ret;
 
        if ((ret = pci_enable_device(pdev))) {
                DBG_PRINT(ERR_DBG,
@@ -6017,14 +6786,6 @@ is enabled. Defaulting to INTA\n");
                pci_disable_device(pdev);
                return -ENOMEM;
        }
-
-       if ((dev_intr_type == MSI_X) && 
-                       ((pdev->device != PCI_DEVICE_ID_HERC_WIN) &&
-                       (pdev->device != PCI_DEVICE_ID_HERC_UNI))) {
-               DBG_PRINT(ERR_DBG, "Xframe I does not support MSI_X. \
-Defaulting to INTA\n");
-               dev_intr_type = INTA;
-       }
        if (dev_intr_type != MSI_X) {
                if (pci_request_regions(pdev, s2io_driver_name)) {
                        DBG_PRINT(ERR_DBG, "Request Regions failed\n"),
@@ -6100,8 +6861,6 @@ Defaulting to INTA\n");
        config = &sp->config;
 
        /* Tx side parameters. */
-       if (tx_fifo_len[0] == 0)
-               tx_fifo_len[0] = DEFAULT_FIFO_LEN; /* Default value. */
        config->tx_fifo_num = tx_fifo_num;
        for (i = 0; i < MAX_TX_FIFOS; i++) {
                config->tx_cfg[i].fifo_len = tx_fifo_len[i];
@@ -6125,8 +6884,6 @@ Defaulting to INTA\n");
        config->max_txds = MAX_SKB_FRAGS + 2;
 
        /* Rx side parameters. */
-       if (rx_ring_sz[0] == 0)
-               rx_ring_sz[0] = SMALL_BLK_CNT; /* Default value. */
        config->rx_ring_num = rx_ring_num;
        for (i = 0; i < MAX_RX_RINGS; i++) {
                config->rx_cfg[i].num_rxd = rx_ring_sz[i] *
@@ -6267,8 +7024,8 @@ Defaulting to INTA\n");
        val64 = RMAC_ADDR_CMD_MEM_RD | RMAC_ADDR_CMD_MEM_STROBE_NEW_CMD |
            RMAC_ADDR_CMD_MEM_OFFSET(0 + MAC_MAC_ADDR_START_OFFSET);
        writeq(val64, &bar0->rmac_addr_cmd_mem);
-       wait_for_cmd_complete(sp);
-
+       wait_for_cmd_complete(&bar0->rmac_addr_cmd_mem,
+                     RMAC_ADDR_CMD_MEM_STROBE_CMD_EXECUTING);
        tmp64 = readq(&bar0->rmac_addr_data0_mem);
        mac_down = (u32) tmp64;
        mac_up = (u32) (tmp64 >> 32);
@@ -6322,82 +7079,63 @@ Defaulting to INTA\n");
                ret = -ENODEV;
                goto register_failed;
        }
-
-       if (sp->device_type & XFRAME_II_DEVICE) {
-               DBG_PRINT(ERR_DBG, "%s: Neterion Xframe II 10GbE adapter ",
-                         dev->name);
-               DBG_PRINT(ERR_DBG, "(rev %d), Version %s",
+       s2io_vpd_read(sp);
+       DBG_PRINT(ERR_DBG, "%s: Neterion %s",dev->name, sp->product_name);
+       DBG_PRINT(ERR_DBG, "(rev %d), Driver version %s\n",
                                get_xena_rev_id(sp->pdev),
                                s2io_driver_version);
-               switch(sp->intr_type) {
-                       case INTA:
-                               DBG_PRINT(ERR_DBG, ", Intr type INTA");
-                               break;
-                       case MSI:
-                               DBG_PRINT(ERR_DBG, ", Intr type MSI");
-                               break;
-                       case MSI_X:
-                               DBG_PRINT(ERR_DBG, ", Intr type MSI-X");
-                               break;
-               }
-
-               DBG_PRINT(ERR_DBG, "\nCopyright(c) 2002-2005 Neterion Inc.\n");
-               DBG_PRINT(ERR_DBG, "MAC ADDR: %02x:%02x:%02x:%02x:%02x:%02x\n",
+       DBG_PRINT(ERR_DBG, "Copyright(c) 2002-2005 Neterion Inc.\n");
+       DBG_PRINT(ERR_DBG, "%s: MAC ADDR: "
+                         "%02x:%02x:%02x:%02x:%02x:%02x\n", dev->name,
                          sp->def_mac_addr[0].mac_addr[0],
                          sp->def_mac_addr[0].mac_addr[1],
                          sp->def_mac_addr[0].mac_addr[2],
                          sp->def_mac_addr[0].mac_addr[3],
                          sp->def_mac_addr[0].mac_addr[4],
                          sp->def_mac_addr[0].mac_addr[5]);
+       if (sp->device_type & XFRAME_II_DEVICE) {
                mode = s2io_print_pci_mode(sp);
                if (mode < 0) {
-                       DBG_PRINT(ERR_DBG, " Unsupported PCI bus mode ");
+                       DBG_PRINT(ERR_DBG, " Unsupported PCI bus mode\n");
                        ret = -EBADSLT;
+                       unregister_netdev(dev);
                        goto set_swap_failed;
                }
-       } else {
-               DBG_PRINT(ERR_DBG, "%s: Neterion Xframe I 10GbE adapter ",
-                         dev->name);
-               DBG_PRINT(ERR_DBG, "(rev %d), Version %s",
-                                       get_xena_rev_id(sp->pdev),
-                                       s2io_driver_version);
-               switch(sp->intr_type) {
-                       case INTA:
-                               DBG_PRINT(ERR_DBG, ", Intr type INTA");
-                               break;
-                       case MSI:
-                               DBG_PRINT(ERR_DBG, ", Intr type MSI");
-                               break;
-                       case MSI_X:
-                               DBG_PRINT(ERR_DBG, ", Intr type MSI-X");
-                               break;
-               }
-               DBG_PRINT(ERR_DBG, "\nCopyright(c) 2002-2005 Neterion Inc.\n");
-               DBG_PRINT(ERR_DBG, "MAC ADDR: %02x:%02x:%02x:%02x:%02x:%02x\n",
-                         sp->def_mac_addr[0].mac_addr[0],
-                         sp->def_mac_addr[0].mac_addr[1],
-                         sp->def_mac_addr[0].mac_addr[2],
-                         sp->def_mac_addr[0].mac_addr[3],
-                         sp->def_mac_addr[0].mac_addr[4],
-                         sp->def_mac_addr[0].mac_addr[5]);
        }
-       if (sp->rxd_mode == RXD_MODE_3B)
-               DBG_PRINT(ERR_DBG, "%s: 2-Buffer mode support has been "
-                         "enabled\n",dev->name);
-       if (sp->rxd_mode == RXD_MODE_3A)
-               DBG_PRINT(ERR_DBG, "%s: 3-Buffer mode support has been "
-                         "enabled\n",dev->name);
-
+       switch(sp->rxd_mode) {
+               case RXD_MODE_1:
+                   DBG_PRINT(ERR_DBG, "%s: 1-Buffer receive mode enabled\n",
+                                               dev->name);
+                   break;
+               case RXD_MODE_3B:
+                   DBG_PRINT(ERR_DBG, "%s: 2-Buffer receive mode enabled\n",
+                                               dev->name);
+                   break;
+               case RXD_MODE_3A:
+                   DBG_PRINT(ERR_DBG, "%s: 3-Buffer receive mode enabled\n",
+                                               dev->name);
+                   break;
+       }
+#ifdef CONFIG_S2IO_NAPI
+       DBG_PRINT(ERR_DBG, "%s: NAPI enabled\n", dev->name);
+#endif
+       switch(sp->intr_type) {
+               case INTA:
+                   DBG_PRINT(ERR_DBG, "%s: Interrupt type INTA\n", dev->name);
+                   break;
+               case MSI:
+                   DBG_PRINT(ERR_DBG, "%s: Interrupt type MSI\n", dev->name);
+                   break;
+               case MSI_X:
+                   DBG_PRINT(ERR_DBG, "%s: Interrupt type MSI-X\n", dev->name);
+                   break;
+       }
        if (sp->lro)
                DBG_PRINT(ERR_DBG, "%s: Large receive offload enabled\n",
-                       dev->name);
+                         dev->name);
 
        /* Initialize device name */
-       strcpy(sp->name, dev->name);
-       if (sp->device_type & XFRAME_II_DEVICE)
-               strcat(sp->name, ": Neterion Xframe II 10GbE adapter");
-       else
-               strcat(sp->name, ": Neterion Xframe I 10GbE adapter");
+       sprintf(sp->name, "%s Neterion %s", dev->name, sp->product_name);
 
        /* Initialize bimodal Interrupts */
        sp->config.bimodal = bimodal;
index 0a0b5b29d81ead016ac0828966ad2fd6f05a1ca2..3203732a668d81357353dd0e1c19511dadeef02c 100644 (file)
@@ -31,6 +31,8 @@
 #define SUCCESS 0
 #define FAILURE -1
 
+#define CHECKBIT(value, nbit) (value & (1 << nbit))
+
 /* Maximum time to flicker LED when asked to identify NIC using ethtool */
 #define MAX_FLICKER_TIME       60000 /* 60 Secs */
 
@@ -78,6 +80,11 @@ static int debug_level = ERR_DBG;
 typedef struct {
        unsigned long long single_ecc_errs;
        unsigned long long double_ecc_errs;
+       unsigned long long parity_err_cnt;
+       unsigned long long serious_err_cnt;
+       unsigned long long soft_reset_cnt;
+       unsigned long long fifo_full_cnt;
+       unsigned long long ring_full_cnt;
        /* LRO statistics */
        unsigned long long clubbed_frms_cnt;
        unsigned long long sending_both;
@@ -87,6 +94,25 @@ typedef struct {
        unsigned long long num_aggregations;
 } swStat_t;
 
+/* Xpak releated alarm and warnings */
+typedef struct {
+       u64 alarm_transceiver_temp_high;
+       u64 alarm_transceiver_temp_low;
+       u64 alarm_laser_bias_current_high;
+       u64 alarm_laser_bias_current_low;
+       u64 alarm_laser_output_power_high;
+       u64 alarm_laser_output_power_low;
+       u64 warn_transceiver_temp_high;
+       u64 warn_transceiver_temp_low;
+       u64 warn_laser_bias_current_high;
+       u64 warn_laser_bias_current_low;
+       u64 warn_laser_output_power_high;
+       u64 warn_laser_output_power_low;
+       u64 xpak_regs_stat;
+       u32 xpak_timer_count;
+} xpakStat_t;
+
+
 /* The statistics block of Xena */
 typedef struct stat_block {
 /* Tx MAC statistics counters. */
@@ -263,7 +289,9 @@ typedef struct stat_block {
        u32 rmac_accepted_ip_oflow;
        u32 reserved_14;
        u32 link_fault_cnt;
+       u8  buffer[20];
        swStat_t sw_stat;
+       xpakStat_t xpak_stat;
 } StatInfo_t;
 
 /*
@@ -659,7 +687,8 @@ typedef struct {
 } usr_addr_t;
 
 /* Default Tunable parameters of the NIC. */
-#define DEFAULT_FIFO_LEN 4096
+#define DEFAULT_FIFO_0_LEN 4096
+#define DEFAULT_FIFO_1_7_LEN 512
 #define SMALL_BLK_CNT  30
 #define LARGE_BLK_CNT  100
 
@@ -732,7 +761,7 @@ struct s2io_nic {
        int device_close_flag;
        int device_enabled_once;
 
-       char name[50];
+       char name[60];
        struct tasklet_struct task;
        volatile unsigned long tasklet_status;
 
@@ -803,6 +832,8 @@ struct s2io_nic {
        char desc1[35];
        char desc2[35];
 
+       int avail_msix_vectors; /* No. of MSI-X vectors granted by system */
+
        struct msix_info_st msix_info[0x3f];
 
 #define XFRAME_I_DEVICE                1
@@ -824,6 +855,8 @@ struct s2io_nic {
        spinlock_t      rx_lock;
        atomic_t        isr_cnt;
        u64 *ufo_in_band_v;
+#define VPD_PRODUCT_NAME_LEN 50
+       u8  product_name[VPD_PRODUCT_NAME_LEN];
 };
 
 #define RESET_ERROR 1;
@@ -848,28 +881,32 @@ static inline void writeq(u64 val, void __iomem *addr)
        writel((u32) (val), addr);
        writel((u32) (val >> 32), (addr + 4));
 }
+#endif
 
-/* In 32 bit modes, some registers have to be written in a
- * particular order to expect correct hardware operation. The
- * macro SPECIAL_REG_WRITE is used to perform such ordered
- * writes. Defines UF (Upper First) and LF (Lower First) will
- * be used to specify the required write order.
+/* 
+ * Some registers have to be written in a particular order to 
+ * expect correct hardware operation. The macro SPECIAL_REG_WRITE 
+ * is used to perform such ordered writes. Defines UF (Upper First) 
+ * and LF (Lower First) will be used to specify the required write order.
  */
 #define UF     1
 #define LF     2
 static inline void SPECIAL_REG_WRITE(u64 val, void __iomem *addr, int order)
 {
+       u32 ret;
+
        if (order == LF) {
                writel((u32) (val), addr);
+               ret = readl(addr);
                writel((u32) (val >> 32), (addr + 4));
+               ret = readl(addr + 4);
        } else {
                writel((u32) (val >> 32), (addr + 4));
+               ret = readl(addr + 4);
                writel((u32) (val), addr);
+               ret = readl(addr);
        }
 }
-#else
-#define SPECIAL_REG_WRITE(val, addr, dummy) writeq(val, addr)
-#endif
 
 /*  Interrupt related values of Xena */
 
@@ -965,7 +1002,7 @@ static int verify_xena_quiescence(nic_t *sp, u64 val64, int flag);
 static struct ethtool_ops netdev_ethtool_ops;
 static void s2io_set_link(unsigned long data);
 static int s2io_set_swapper(nic_t * sp);
-static void s2io_card_down(nic_t *nic);
+static void s2io_card_down(nic_t *nic, int flag);
 static int s2io_card_up(nic_t *nic);
 static int get_xena_rev_id(struct pci_dev *pdev);
 static void restore_xmsi_data(nic_t *nic);
index f5a3bf4d959a458f1fd1930be72d29c6f186a0d9..d058741722091c3555f1b3cf0f399c0a67b83a6e 100644 (file)
@@ -1,6 +1,6 @@
 /* sis900.c: A SiS 900/7016 PCI Fast Ethernet driver for Linux.
    Copyright 1999 Silicon Integrated System Corporation 
-   Revision:   1.08.09 Sep. 19 2005
+   Revision:   1.08.10 Apr. 2 2006
    
    Modified from the driver which is originally written by Donald Becker.
    
    SiS 7014 Single Chip 100BASE-TX/10BASE-T Physical Layer Solution,
    preliminary Rev. 1.0 Jan. 18, 1998
 
+   Rev 1.08.10 Apr.  2 2006 Daniele Venzano add vlan (jumbo packets) support
    Rev 1.08.09 Sep. 19 2005 Daniele Venzano add Wake on LAN support
    Rev 1.08.08 Jan. 22 2005 Daniele Venzano use netif_msg for debugging messages
-   Rev 1.08.07 Nov.  2 2003 Daniele Venzano <webvenza@libero.it> add suspend/resume support
+   Rev 1.08.07 Nov.  2 2003 Daniele Venzano <venza@brownhat.org> add suspend/resume support
    Rev 1.08.06 Sep. 24 2002 Mufasa Yang bug fix for Tx timeout & add SiS963 support
    Rev 1.08.05 Jun.  6 2002 Mufasa Yang bug fix for read_eeprom & Tx descriptor over-boundary
    Rev 1.08.04 Apr. 25 2002 Mufasa Yang <mufasa@sis.com.tw> added SiS962 support
@@ -77,7 +78,7 @@
 #include "sis900.h"
 
 #define SIS900_MODULE_NAME "sis900"
-#define SIS900_DRV_VERSION "v1.08.09 Sep. 19 2005"
+#define SIS900_DRV_VERSION "v1.08.10 Apr. 2 2006"
 
 static char version[] __devinitdata =
 KERN_INFO "sis900.c: " SIS900_DRV_VERSION "\n";
@@ -1402,6 +1403,11 @@ static void sis900_set_mode (long ioaddr, int speed, int duplex)
                rx_flags |= RxATX;
        }
 
+#if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
+       /* Can accept Jumbo packet */
+       rx_flags |= RxAJAB;
+#endif
+
        outl (tx_flags, ioaddr + txcfg);
        outl (rx_flags, ioaddr + rxcfg);
 }
@@ -1714,18 +1720,26 @@ static int sis900_rx(struct net_device *net_dev)
 
        while (rx_status & OWN) {
                unsigned int rx_size;
+               unsigned int data_size;
 
                if (--rx_work_limit < 0)
                        break;
 
-               rx_size = (rx_status & DSIZE) - CRC_SIZE;
+               data_size = rx_status & DSIZE;
+               rx_size = data_size - CRC_SIZE;
+
+#if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
+               /* ``TOOLONG'' flag means jumbo packet recived. */
+               if ((rx_status & TOOLONG) && data_size <= MAX_FRAME_SIZE)
+                       rx_status &= (~ ((unsigned int)TOOLONG));
+#endif
 
                if (rx_status & (ABORT|OVERRUN|TOOLONG|RUNT|RXISERR|CRCERR|FAERR)) {
                        /* corrupted packet received */
                        if (netif_msg_rx_err(sis_priv))
                                printk(KERN_DEBUG "%s: Corrupted packet "
-                                      "received, buffer status = 0x%8.8x.\n",
-                                      net_dev->name, rx_status);
+                                      "received, buffer status = 0x%8.8x/%d.\n",
+                                      net_dev->name, rx_status, data_size);
                        sis_priv->stats.rx_errors++;
                        if (rx_status & OVERRUN)
                                sis_priv->stats.rx_over_errors++;
index 50323941e3c0dea55d8c7357a63bc35631cae6db..4834e3a156948bc001c68ddf01735351edb6330c 100644 (file)
@@ -310,8 +310,14 @@ enum sis630_revision_id {
 #define CRC_SIZE                4
 #define MAC_HEADER_SIZE         14
 
-#define TX_BUF_SIZE     1536
-#define RX_BUF_SIZE     1536
+#if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
+#define MAX_FRAME_SIZE  (1518 + 4)
+#else
+#define MAX_FRAME_SIZE  1518
+#endif /* CONFIG_VLAN_802_1Q */
+
+#define TX_BUF_SIZE     (MAX_FRAME_SIZE+18)
+#define RX_BUF_SIZE     (MAX_FRAME_SIZE+18)
 
 #define NUM_TX_DESC     16             /* Number of Tx descriptor registers. */
 #define NUM_RX_DESC     16             /* Number of Rx descriptor registers. */
diff --git a/drivers/net/smc911x.c b/drivers/net/smc911x.c
new file mode 100644 (file)
index 0000000..bdd8702
--- /dev/null
@@ -0,0 +1,2307 @@
+/*
+ * smc911x.c
+ * This is a driver for SMSC's LAN911{5,6,7,8} single-chip Ethernet devices.
+ *
+ * Copyright (C) 2005 Sensoria Corp
+ *        Derived from the unified SMC91x driver by Nicolas Pitre
+ *        and the smsc911x.c reference driver by SMSC
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ *
+ * Arguments:
+ *      watchdog  = TX watchdog timeout
+ *      tx_fifo_kb = Size of TX FIFO in KB
+ *
+ * History:
+ *       04/16/05      Dustin McIntire          Initial version
+ */
+static const char version[] =
+        "smc911x.c: v1.0 04-16-2005 by Dustin McIntire <dustin@sensoria.com>\n";
+
+/* Debugging options */
+#define ENABLE_SMC_DEBUG_RX            0
+#define ENABLE_SMC_DEBUG_TX            0
+#define ENABLE_SMC_DEBUG_DMA           0
+#define ENABLE_SMC_DEBUG_PKTS          0
+#define ENABLE_SMC_DEBUG_MISC          0
+#define ENABLE_SMC_DEBUG_FUNC          0
+
+#define SMC_DEBUG_RX           ((ENABLE_SMC_DEBUG_RX   ? 1 : 0) << 0)
+#define SMC_DEBUG_TX           ((ENABLE_SMC_DEBUG_TX   ? 1 : 0) << 1)
+#define SMC_DEBUG_DMA          ((ENABLE_SMC_DEBUG_DMA  ? 1 : 0) << 2)
+#define SMC_DEBUG_PKTS         ((ENABLE_SMC_DEBUG_PKTS ? 1 : 0) << 3)
+#define SMC_DEBUG_MISC         ((ENABLE_SMC_DEBUG_MISC ? 1 : 0) << 4)
+#define SMC_DEBUG_FUNC         ((ENABLE_SMC_DEBUG_FUNC ? 1 : 0) << 5)
+
+#ifndef SMC_DEBUG
+#define SMC_DEBUG       ( SMC_DEBUG_RX   | \
+                          SMC_DEBUG_TX   | \
+                          SMC_DEBUG_DMA  | \
+                          SMC_DEBUG_PKTS | \
+                          SMC_DEBUG_MISC | \
+                          SMC_DEBUG_FUNC   \
+                        )
+#endif
+
+
+#include <linux/config.h>
+#include <linux/init.h>
+#include <linux/module.h>
+#include <linux/kernel.h>
+#include <linux/sched.h>
+#include <linux/slab.h>
+#include <linux/delay.h>
+#include <linux/interrupt.h>
+#include <linux/errno.h>
+#include <linux/ioport.h>
+#include <linux/crc32.h>
+#include <linux/device.h>
+#include <linux/platform_device.h>
+#include <linux/spinlock.h>
+#include <linux/ethtool.h>
+#include <linux/mii.h>
+#include <linux/workqueue.h>
+
+#include <linux/netdevice.h>
+#include <linux/etherdevice.h>
+#include <linux/skbuff.h>
+
+#include <asm/io.h>
+#include <asm/irq.h>
+
+#include "smc911x.h"
+
+/*
+ * Transmit timeout, default 5 seconds.
+ */
+static int watchdog = 5000;
+module_param(watchdog, int, 0400);
+MODULE_PARM_DESC(watchdog, "transmit timeout in milliseconds");
+
+static int tx_fifo_kb=8;
+module_param(tx_fifo_kb, int, 0400);
+MODULE_PARM_DESC(tx_fifo_kb,"transmit FIFO size in KB (1<x<15)(default=8)");
+
+MODULE_LICENSE("GPL");
+
+/*
+ * The internal workings of the driver.  If you are changing anything
+ * here with the SMC stuff, you should have the datasheet and know
+ * what you are doing.
+ */
+#define CARDNAME "smc911x"
+
+/*
+ * Use power-down feature of the chip
+ */
+#define POWER_DOWN              1
+
+
+/* store this information for the driver.. */
+struct smc911x_local {
+       /*
+        * If I have to wait until the DMA is finished and ready to reload a
+        * packet, I will store the skbuff here. Then, the DMA will send it
+        * out and free it.
+        */
+       struct sk_buff *pending_tx_skb;
+
+       /*
+        * these are things that the kernel wants me to keep, so users
+        * can find out semi-useless statistics of how well the card is
+        * performing
+        */
+       struct net_device_stats stats;
+
+       /* version/revision of the SMC911x chip */
+       u16 version;
+       u16 revision;
+
+       /* FIFO sizes */
+       int tx_fifo_kb;
+       int tx_fifo_size;
+       int rx_fifo_size;
+       int afc_cfg;
+
+       /* Contains the current active receive/phy mode */
+       int ctl_rfduplx;
+       int ctl_rspeed;
+
+       u32 msg_enable;
+       u32 phy_type;
+       struct mii_if_info mii;
+
+       /* work queue */
+       struct work_struct phy_configure;
+       int work_pending;
+
+       int tx_throttle;
+       spinlock_t lock;
+
+#ifdef SMC_USE_DMA
+       /* DMA needs the physical address of the chip */
+       u_long physaddr;
+       int rxdma;
+       int txdma;
+       int rxdma_active;
+       int txdma_active;
+       struct sk_buff *current_rx_skb;
+       struct sk_buff *current_tx_skb;
+       struct device *dev;
+#endif
+};
+
+#if SMC_DEBUG > 0
+#define DBG(n, args...)                                 \
+       do {                                     \
+               if (SMC_DEBUG & (n))             \
+                       printk(args);            \
+       } while (0)
+
+#define PRINTK(args...)   printk(args)
+#else
+#define DBG(n, args...)   do { } while (0)
+#define PRINTK(args...)   printk(KERN_DEBUG args)
+#endif
+
+#if SMC_DEBUG_PKTS > 0
+static void PRINT_PKT(u_char *buf, int length)
+{
+       int i;
+       int remainder;
+       int lines;
+
+       lines = length / 16;
+       remainder = length % 16;
+
+       for (i = 0; i < lines ; i ++) {
+               int cur;
+               for (cur = 0; cur < 8; cur++) {
+                       u_char a, b;
+                       a = *buf++;
+                       b = *buf++;
+                       printk("%02x%02x ", a, b);
+               }
+               printk("\n");
+       }
+       for (i = 0; i < remainder/2 ; i++) {
+               u_char a, b;
+               a = *buf++;
+               b = *buf++;
+               printk("%02x%02x ", a, b);
+       }
+       printk("\n");
+}
+#else
+#define PRINT_PKT(x...)  do { } while (0)
+#endif
+
+
+/* this enables an interrupt in the interrupt mask register */
+#define SMC_ENABLE_INT(x) do {                         \
+       unsigned int  __mask;                           \
+       unsigned long __flags;                          \
+       spin_lock_irqsave(&lp->lock, __flags);          \
+       __mask = SMC_GET_INT_EN();                      \
+       __mask |= (x);                                  \
+       SMC_SET_INT_EN(__mask);                         \
+       spin_unlock_irqrestore(&lp->lock, __flags);     \
+} while (0)
+
+/* this disables an interrupt from the interrupt mask register */
+#define SMC_DISABLE_INT(x) do {                                \
+       unsigned int  __mask;                           \
+       unsigned long __flags;                          \
+       spin_lock_irqsave(&lp->lock, __flags);          \
+       __mask = SMC_GET_INT_EN();                      \
+       __mask &= ~(x);                                 \
+       SMC_SET_INT_EN(__mask);                         \
+       spin_unlock_irqrestore(&lp->lock, __flags);     \
+} while (0)
+
+/*
+ * this does a soft reset on the device
+ */
+static void smc911x_reset(struct net_device *dev)
+{
+       unsigned long ioaddr = dev->base_addr;
+       struct smc911x_local *lp = netdev_priv(dev);
+       unsigned int reg, timeout=0, resets=1;
+       unsigned long flags;
+
+       DBG(SMC_DEBUG_FUNC, "%s: --> %s\n", dev->name, __FUNCTION__);
+
+       /*       Take out of PM setting first */
+       if ((SMC_GET_PMT_CTRL() & PMT_CTRL_READY_) == 0) {
+               /* Write to the bytetest will take out of powerdown */
+               SMC_SET_BYTE_TEST(0);
+               timeout=10;
+               do {
+                       udelay(10);
+                       reg = SMC_GET_PMT_CTRL() & PMT_CTRL_READY_;
+               } while ( timeout-- && !reg);
+               if (timeout == 0) {
+                       PRINTK("%s: smc911x_reset timeout waiting for PM restore\n", dev->name);
+                       return;
+               }
+       }
+
+       /* Disable all interrupts */
+       spin_lock_irqsave(&lp->lock, flags);
+       SMC_SET_INT_EN(0);
+       spin_unlock_irqrestore(&lp->lock, flags);
+
+       while (resets--) {
+               SMC_SET_HW_CFG(HW_CFG_SRST_);
+               timeout=10;
+               do {
+                       udelay(10);
+                       reg = SMC_GET_HW_CFG();
+                       /* If chip indicates reset timeout then try again */
+                       if (reg & HW_CFG_SRST_TO_) {
+                               PRINTK("%s: chip reset timeout, retrying...\n", dev->name);
+                               resets++;
+                               break;
+                       }
+               } while ( timeout-- && (reg & HW_CFG_SRST_));
+       }
+       if (timeout == 0) {
+               PRINTK("%s: smc911x_reset timeout waiting for reset\n", dev->name);
+               return;
+       }
+
+       /* make sure EEPROM has finished loading before setting GPIO_CFG */
+       timeout=1000;
+       while ( timeout-- && (SMC_GET_E2P_CMD() & E2P_CMD_EPC_BUSY_)) {
+               udelay(10);
+       }
+       if (timeout == 0){
+               PRINTK("%s: smc911x_reset timeout waiting for EEPROM busy\n", dev->name);
+               return;
+       }
+
+       /* Initialize interrupts */
+       SMC_SET_INT_EN(0);
+       SMC_ACK_INT(-1);
+
+       /* Reset the FIFO level and flow control settings */
+       SMC_SET_HW_CFG((lp->tx_fifo_kb & 0xF) << 16);
+//TODO: Figure out what appropriate pause time is
+       SMC_SET_FLOW(FLOW_FCPT_ | FLOW_FCEN_);
+       SMC_SET_AFC_CFG(lp->afc_cfg);
+
+
+       /* Set to LED outputs */
+       SMC_SET_GPIO_CFG(0x70070000);
+
+       /*
+        * Deassert IRQ for 1*10us for edge type interrupts
+        * and drive IRQ pin push-pull
+        */
+       SMC_SET_IRQ_CFG( (1 << 24) | INT_CFG_IRQ_EN_ | INT_CFG_IRQ_TYPE_ );
+
+       /* clear anything saved */
+       if (lp->pending_tx_skb != NULL) {
+               dev_kfree_skb (lp->pending_tx_skb);
+               lp->pending_tx_skb = NULL;
+               lp->stats.tx_errors++;
+               lp->stats.tx_aborted_errors++;
+       }
+}
+
+/*
+ * Enable Interrupts, Receive, and Transmit
+ */
+static void smc911x_enable(struct net_device *dev)
+{
+       unsigned long ioaddr = dev->base_addr;
+       struct smc911x_local *lp = netdev_priv(dev);
+       unsigned mask, cfg, cr;
+       unsigned long flags;
+
+       DBG(SMC_DEBUG_FUNC, "%s: --> %s\n", dev->name, __FUNCTION__);
+
+       SMC_SET_MAC_ADDR(dev->dev_addr);
+
+       /* Enable TX */
+       cfg = SMC_GET_HW_CFG();
+       cfg &= HW_CFG_TX_FIF_SZ_ | 0xFFF;
+       cfg |= HW_CFG_SF_;
+       SMC_SET_HW_CFG(cfg);
+       SMC_SET_FIFO_TDA(0xFF);
+       /* Update TX stats on every 64 packets received or every 1 sec */
+       SMC_SET_FIFO_TSL(64);
+       SMC_SET_GPT_CFG(GPT_CFG_TIMER_EN_ | 10000);
+
+       spin_lock_irqsave(&lp->lock, flags);
+       SMC_GET_MAC_CR(cr);
+       cr |= MAC_CR_TXEN_ | MAC_CR_HBDIS_;
+       SMC_SET_MAC_CR(cr);
+       SMC_SET_TX_CFG(TX_CFG_TX_ON_);
+       spin_unlock_irqrestore(&lp->lock, flags);
+
+       /* Add 2 byte padding to start of packets */
+       SMC_SET_RX_CFG((2<<8) & RX_CFG_RXDOFF_);
+
+       /* Turn on receiver and enable RX */
+       if (cr & MAC_CR_RXEN_)
+               DBG(SMC_DEBUG_RX, "%s: Receiver already enabled\n", dev->name);
+
+       spin_lock_irqsave(&lp->lock, flags);
+       SMC_SET_MAC_CR( cr | MAC_CR_RXEN_ );
+       spin_unlock_irqrestore(&lp->lock, flags);
+
+       /* Interrupt on every received packet */
+       SMC_SET_FIFO_RSA(0x01);
+       SMC_SET_FIFO_RSL(0x00);
+
+       /* now, enable interrupts */
+       mask = INT_EN_TDFA_EN_ | INT_EN_TSFL_EN_ | INT_EN_RSFL_EN_ |
+               INT_EN_GPT_INT_EN_ | INT_EN_RXDFH_INT_EN_ | INT_EN_RXE_EN_ |
+               INT_EN_PHY_INT_EN_;
+       if (IS_REV_A(lp->revision))
+               mask|=INT_EN_RDFL_EN_;
+       else {
+               mask|=INT_EN_RDFO_EN_;
+       }
+       SMC_ENABLE_INT(mask);
+}
+
+/*
+ * this puts the device in an inactive state
+ */
+static void smc911x_shutdown(struct net_device *dev)
+{
+       unsigned long ioaddr = dev->base_addr;
+       struct smc911x_local *lp = netdev_priv(dev);
+       unsigned cr;
+       unsigned long flags;
+
+       DBG(SMC_DEBUG_FUNC, "%s: --> %s\n", CARDNAME, __FUNCTION__);
+
+       /* Disable IRQ's */
+       SMC_SET_INT_EN(0);
+
+       /* Turn of Rx and TX */
+       spin_lock_irqsave(&lp->lock, flags);
+       SMC_GET_MAC_CR(cr);
+       cr &= ~(MAC_CR_TXEN_ | MAC_CR_RXEN_ | MAC_CR_HBDIS_);
+       SMC_SET_MAC_CR(cr);
+       SMC_SET_TX_CFG(TX_CFG_STOP_TX_);
+       spin_unlock_irqrestore(&lp->lock, flags);
+}
+
+static inline void smc911x_drop_pkt(struct net_device *dev)
+{
+       unsigned long ioaddr = dev->base_addr;
+       unsigned int fifo_count, timeout, reg;
+
+       DBG(SMC_DEBUG_FUNC | SMC_DEBUG_RX, "%s: --> %s\n", CARDNAME, __FUNCTION__);
+       fifo_count = SMC_GET_RX_FIFO_INF() & 0xFFFF;
+       if (fifo_count <= 4) {
+               /* Manually dump the packet data */
+               while (fifo_count--)
+                       SMC_GET_RX_FIFO();
+       } else   {
+               /* Fast forward through the bad packet */
+               SMC_SET_RX_DP_CTRL(RX_DP_CTRL_FFWD_BUSY_);
+               timeout=50;
+               do {
+                       udelay(10);
+                       reg = SMC_GET_RX_DP_CTRL() & RX_DP_CTRL_FFWD_BUSY_;
+               } while ( timeout-- && reg);
+               if (timeout == 0) {
+                       PRINTK("%s: timeout waiting for RX fast forward\n", dev->name);
+               }
+       }
+}
+
+/*
+ * This is the procedure to handle the receipt of a packet.
+ * It should be called after checking for packet presence in
+ * the RX status FIFO.  It must be called with the spin lock
+ * already held.
+ */
+static inline void      smc911x_rcv(struct net_device *dev)
+{
+       struct smc911x_local *lp = netdev_priv(dev);
+       unsigned long ioaddr = dev->base_addr;
+       unsigned int pkt_len, status;
+       struct sk_buff *skb;
+       unsigned char *data;
+
+       DBG(SMC_DEBUG_FUNC | SMC_DEBUG_RX, "%s: --> %s\n",
+               dev->name, __FUNCTION__);
+       status = SMC_GET_RX_STS_FIFO();
+       DBG(SMC_DEBUG_RX, "%s: Rx pkt len %d status 0x%08x \n",
+               dev->name, (status & 0x3fff0000) >> 16, status & 0xc000ffff);
+       pkt_len = (status & RX_STS_PKT_LEN_) >> 16;
+       if (status & RX_STS_ES_) {
+               /* Deal with a bad packet */
+               lp->stats.rx_errors++;
+               if (status & RX_STS_CRC_ERR_)
+                       lp->stats.rx_crc_errors++;
+               else {
+                       if (status & RX_STS_LEN_ERR_)
+                               lp->stats.rx_length_errors++;
+                       if (status & RX_STS_MCAST_)
+                               lp->stats.multicast++;
+               }
+               /* Remove the bad packet data from the RX FIFO */
+               smc911x_drop_pkt(dev);
+       } else {
+               /* Receive a valid packet */
+               /* Alloc a buffer with extra room for DMA alignment */
+               skb=dev_alloc_skb(pkt_len+32);
+               if (unlikely(skb == NULL)) {
+                       PRINTK( "%s: Low memory, rcvd packet dropped.\n",
+                               dev->name);
+                       lp->stats.rx_dropped++;
+                       smc911x_drop_pkt(dev);
+                       return;
+               }
+               /* Align IP header to 32 bits
+                * Note that the device is configured to add a 2
+                * byte padding to the packet start, so we really
+                * want to write to the orignal data pointer */
+               data = skb->data;
+               skb_reserve(skb, 2);
+               skb_put(skb,pkt_len-4);
+#ifdef SMC_USE_DMA
+               {
+               unsigned int fifo;
+               /* Lower the FIFO threshold if possible */
+               fifo = SMC_GET_FIFO_INT();
+               if (fifo & 0xFF) fifo--;
+               DBG(SMC_DEBUG_RX, "%s: Setting RX stat FIFO threshold to %d\n",
+                       dev->name, fifo & 0xff);
+               SMC_SET_FIFO_INT(fifo);
+               /* Setup RX DMA */
+               SMC_SET_RX_CFG(RX_CFG_RX_END_ALGN16_ | ((2<<8) & RX_CFG_RXDOFF_));
+               lp->rxdma_active = 1;
+               lp->current_rx_skb = skb;
+               SMC_PULL_DATA(data, (pkt_len+2+15) & ~15);
+               /* Packet processing deferred to DMA RX interrupt */
+               }
+#else
+               SMC_SET_RX_CFG(RX_CFG_RX_END_ALGN4_ | ((2<<8) & RX_CFG_RXDOFF_));
+               SMC_PULL_DATA(data, pkt_len+2+3);
+
+               DBG(SMC_DEBUG_PKTS, "%s: Received packet\n", dev->name,);
+               PRINT_PKT(data, ((pkt_len - 4) <= 64) ? pkt_len - 4 : 64);
+               dev->last_rx = jiffies;
+               skb->dev = dev;
+               skb->protocol = eth_type_trans(skb, dev);
+               netif_rx(skb);
+               lp->stats.rx_packets++;
+               lp->stats.rx_bytes += pkt_len-4;
+#endif
+       }
+}
+
+/*
+ * This is called to actually send a packet to the chip.
+ */
+static void smc911x_hardware_send_pkt(struct net_device *dev)
+{
+       struct smc911x_local *lp = netdev_priv(dev);
+       unsigned long ioaddr = dev->base_addr;
+       struct sk_buff *skb;
+       unsigned int cmdA, cmdB, len;
+       unsigned char *buf;
+       unsigned long flags;
+
+       DBG(SMC_DEBUG_FUNC | SMC_DEBUG_TX, "%s: --> %s\n", dev->name, __FUNCTION__);
+       BUG_ON(lp->pending_tx_skb == NULL);
+
+       skb = lp->pending_tx_skb;
+       lp->pending_tx_skb = NULL;
+
+       /* cmdA {25:24] data alignment [20:16] start offset [10:0] buffer length */
+       /* cmdB {31:16] pkt tag [10:0] length */
+#ifdef SMC_USE_DMA
+       /* 16 byte buffer alignment mode */
+       buf = (char*)((u32)(skb->data) & ~0xF);
+       len = (skb->len + 0xF + ((u32)skb->data & 0xF)) & ~0xF;
+       cmdA = (1<<24) | (((u32)skb->data & 0xF)<<16) |
+                       TX_CMD_A_INT_FIRST_SEG_ | TX_CMD_A_INT_LAST_SEG_ |
+                       skb->len;
+#else
+       buf = (char*)((u32)skb->data & ~0x3);
+       len = (skb->len + 3 + ((u32)skb->data & 3)) & ~0x3;
+       cmdA = (((u32)skb->data & 0x3) << 16) |
+                       TX_CMD_A_INT_FIRST_SEG_ | TX_CMD_A_INT_LAST_SEG_ |
+                       skb->len;
+#endif
+       /* tag is packet length so we can use this in stats update later */
+       cmdB = (skb->len  << 16) | (skb->len & 0x7FF);
+
+       DBG(SMC_DEBUG_TX, "%s: TX PKT LENGTH 0x%04x (%d) BUF 0x%p CMDA 0x%08x CMDB 0x%08x\n",
+                dev->name, len, len, buf, cmdA, cmdB);
+       SMC_SET_TX_FIFO(cmdA);
+       SMC_SET_TX_FIFO(cmdB);
+
+       DBG(SMC_DEBUG_PKTS, "%s: Transmitted packet\n", dev->name);
+       PRINT_PKT(buf, len <= 64 ? len : 64);
+
+       /* Send pkt via PIO or DMA */
+#ifdef SMC_USE_DMA
+       lp->current_tx_skb = skb;
+       SMC_PUSH_DATA(buf, len);
+       /* DMA complete IRQ will free buffer and set jiffies */
+#else
+       SMC_PUSH_DATA(buf, len);
+       dev->trans_start = jiffies;
+       dev_kfree_skb(skb);
+#endif
+       spin_lock_irqsave(&lp->lock, flags);
+       if (!lp->tx_throttle) {
+               netif_wake_queue(dev);
+       }
+       spin_unlock_irqrestore(&lp->lock, flags);
+       SMC_ENABLE_INT(INT_EN_TDFA_EN_ | INT_EN_TSFL_EN_);
+}
+
+/*
+ * Since I am not sure if I will have enough room in the chip's ram
+ * to store the packet, I call this routine which either sends it
+ * now, or set the card to generates an interrupt when ready
+ * for the packet.
+ */
+static int smc911x_hard_start_xmit(struct sk_buff *skb, struct net_device *dev)
+{
+       struct smc911x_local *lp = netdev_priv(dev);
+       unsigned long ioaddr = dev->base_addr;
+       unsigned int free;
+       unsigned long flags;
+
+       DBG(SMC_DEBUG_FUNC | SMC_DEBUG_TX, "%s: --> %s\n",
+               dev->name, __FUNCTION__);
+
+       BUG_ON(lp->pending_tx_skb != NULL);
+
+       free = SMC_GET_TX_FIFO_INF() & TX_FIFO_INF_TDFREE_;
+       DBG(SMC_DEBUG_TX, "%s: TX free space %d\n", dev->name, free);
+
+       /* Turn off the flow when running out of space in FIFO */
+       if (free <= SMC911X_TX_FIFO_LOW_THRESHOLD) {
+               DBG(SMC_DEBUG_TX, "%s: Disabling data flow due to low FIFO space (%d)\n",
+                       dev->name, free);
+               spin_lock_irqsave(&lp->lock, flags);
+               /* Reenable when at least 1 packet of size MTU present */
+               SMC_SET_FIFO_TDA((SMC911X_TX_FIFO_LOW_THRESHOLD)/64);
+               lp->tx_throttle = 1;
+               netif_stop_queue(dev);
+               spin_unlock_irqrestore(&lp->lock, flags);
+       }
+
+       /* Drop packets when we run out of space in TX FIFO
+        * Account for overhead required for:
+        *
+        *        Tx command words                       8 bytes
+        *        Start offset                           15 bytes
+        *        End padding                            15 bytes
+        */
+       if (unlikely(free < (skb->len + 8 + 15 + 15))) {
+               printk("%s: No Tx free space %d < %d\n",
+                       dev->name, free, skb->len);
+               lp->pending_tx_skb = NULL;
+               lp->stats.tx_errors++;
+               lp->stats.tx_dropped++;
+               dev_kfree_skb(skb);
+               return 0;
+       }
+
+#ifdef SMC_USE_DMA
+       {
+               /* If the DMA is already running then defer this packet Tx until
+                * the DMA IRQ starts it
+                */
+               spin_lock_irqsave(&lp->lock, flags);
+               if (lp->txdma_active) {
+                       DBG(SMC_DEBUG_TX | SMC_DEBUG_DMA, "%s: Tx DMA running, deferring packet\n", dev->name);
+                       lp->pending_tx_skb = skb;
+                       netif_stop_queue(dev);
+                       spin_unlock_irqrestore(&lp->lock, flags);
+                       return 0;
+               } else {
+                       DBG(SMC_DEBUG_TX | SMC_DEBUG_DMA, "%s: Activating Tx DMA\n", dev->name);
+                       lp->txdma_active = 1;
+               }
+               spin_unlock_irqrestore(&lp->lock, flags);
+       }
+#endif
+       lp->pending_tx_skb = skb;
+       smc911x_hardware_send_pkt(dev);
+
+       return 0;
+}
+
+/*
+ * This handles a TX status interrupt, which is only called when:
+ * - a TX error occurred, or
+ * - TX of a packet completed.
+ */
+static void smc911x_tx(struct net_device *dev)
+{
+       unsigned long ioaddr = dev->base_addr;
+       struct smc911x_local *lp = netdev_priv(dev);
+       unsigned int tx_status;
+
+       DBG(SMC_DEBUG_FUNC | SMC_DEBUG_TX, "%s: --> %s\n",
+               dev->name, __FUNCTION__);
+
+       /* Collect the TX status */
+       while (((SMC_GET_TX_FIFO_INF() & TX_FIFO_INF_TSUSED_) >> 16) != 0) {
+               DBG(SMC_DEBUG_TX, "%s: Tx stat FIFO used 0x%04x\n",
+                       dev->name,
+                       (SMC_GET_TX_FIFO_INF() & TX_FIFO_INF_TSUSED_) >> 16);
+               tx_status = SMC_GET_TX_STS_FIFO();
+               lp->stats.tx_packets++;
+               lp->stats.tx_bytes+=tx_status>>16;
+               DBG(SMC_DEBUG_TX, "%s: Tx FIFO tag 0x%04x status 0x%04x\n",
+                       dev->name, (tx_status & 0xffff0000) >> 16,
+                       tx_status & 0x0000ffff);
+               /* count Tx errors, but ignore lost carrier errors when in
+                * full-duplex mode */
+               if ((tx_status & TX_STS_ES_) && !(lp->ctl_rfduplx &&
+                   !(tx_status & 0x00000306))) {
+                       lp->stats.tx_errors++;
+               }
+               if (tx_status & TX_STS_MANY_COLL_) {
+                       lp->stats.collisions+=16;
+                       lp->stats.tx_aborted_errors++;
+               } else {
+                       lp->stats.collisions+=(tx_status & TX_STS_COLL_CNT_) >> 3;
+               }
+               /* carrier error only has meaning for half-duplex communication */
+               if ((tx_status & (TX_STS_LOC_ | TX_STS_NO_CARR_)) &&
+                   !lp->ctl_rfduplx) {
+                       lp->stats.tx_carrier_errors++;
+               }
+               if (tx_status & TX_STS_LATE_COLL_) {
+                       lp->stats.collisions++;
+                       lp->stats.tx_aborted_errors++;
+               }
+       }
+}
+
+
+/*---PHY CONTROL AND CONFIGURATION-----------------------------------------*/
+/*
+ * Reads a register from the MII Management serial interface
+ */
+
+static int smc911x_phy_read(struct net_device *dev, int phyaddr, int phyreg)
+{
+       unsigned long ioaddr = dev->base_addr;
+       unsigned int phydata;
+
+       SMC_GET_MII(phyreg, phyaddr, phydata);
+
+       DBG(SMC_DEBUG_MISC, "%s: phyaddr=0x%x, phyreg=0x%02x, phydata=0x%04x\n",
+               __FUNCTION__, phyaddr, phyreg, phydata);
+       return phydata;
+}
+
+
+/*
+ * Writes a register to the MII Management serial interface
+ */
+static void smc911x_phy_write(struct net_device *dev, int phyaddr, int phyreg,
+                       int phydata)
+{
+       unsigned long ioaddr = dev->base_addr;
+
+       DBG(SMC_DEBUG_MISC, "%s: phyaddr=0x%x, phyreg=0x%x, phydata=0x%x\n",
+               __FUNCTION__, phyaddr, phyreg, phydata);
+
+       SMC_SET_MII(phyreg, phyaddr, phydata);
+}
+
+/*
+ * Finds and reports the PHY address (115 and 117 have external
+ * PHY interface 118 has internal only
+ */
+static void smc911x_phy_detect(struct net_device *dev)
+{
+       unsigned long ioaddr = dev->base_addr;
+       struct smc911x_local *lp = netdev_priv(dev);
+       int phyaddr;
+       unsigned int cfg, id1, id2;
+
+       DBG(SMC_DEBUG_FUNC, "%s: --> %s\n", dev->name, __FUNCTION__);
+
+       lp->phy_type = 0;
+
+       /*
+        * Scan all 32 PHY addresses if necessary, starting at
+        * PHY#1 to PHY#31, and then PHY#0 last.
+        */
+       switch(lp->version) {
+               case 0x115:
+               case 0x117:
+                       cfg = SMC_GET_HW_CFG();
+                       if (cfg & HW_CFG_EXT_PHY_DET_) {
+                               cfg &= ~HW_CFG_PHY_CLK_SEL_;
+                               cfg |= HW_CFG_PHY_CLK_SEL_CLK_DIS_;
+                               SMC_SET_HW_CFG(cfg);
+                               udelay(10); /* Wait for clocks to stop */
+
+                               cfg |= HW_CFG_EXT_PHY_EN_;
+                               SMC_SET_HW_CFG(cfg);
+                               udelay(10); /* Wait for clocks to stop */
+
+                               cfg &= ~HW_CFG_PHY_CLK_SEL_;
+                               cfg |= HW_CFG_PHY_CLK_SEL_EXT_PHY_;
+                               SMC_SET_HW_CFG(cfg);
+                               udelay(10); /* Wait for clocks to stop */
+
+                               cfg |= HW_CFG_SMI_SEL_;
+                               SMC_SET_HW_CFG(cfg);
+
+                               for (phyaddr = 1; phyaddr < 32; ++phyaddr) {
+
+                                       /* Read the PHY identifiers */
+                                       SMC_GET_PHY_ID1(phyaddr & 31, id1);
+                                       SMC_GET_PHY_ID2(phyaddr & 31, id2);
+
+                                       /* Make sure it is a valid identifier */
+                                       if (id1 != 0x0000 && id1 != 0xffff &&
+                                           id1 != 0x8000 && id2 != 0x0000 &&
+                                           id2 != 0xffff && id2 != 0x8000) {
+                                               /* Save the PHY's address */
+                                               lp->mii.phy_id = phyaddr & 31;
+                                               lp->phy_type = id1 << 16 | id2;
+                                               break;
+                                       }
+                               }
+                       }
+               default:
+                       /* Internal media only */
+                       SMC_GET_PHY_ID1(1, id1);
+                       SMC_GET_PHY_ID2(1, id2);
+                       /* Save the PHY's address */
+                       lp->mii.phy_id = 1;
+                       lp->phy_type = id1 << 16 | id2;
+       }
+
+       DBG(SMC_DEBUG_MISC, "%s: phy_id1=0x%x, phy_id2=0x%x phyaddr=0x%d\n",
+               dev->name, id1, id2, lp->mii.phy_id);
+}
+
+/*
+ * Sets the PHY to a configuration as determined by the user.
+ * Called with spin_lock held.
+ */
+static int smc911x_phy_fixed(struct net_device *dev)
+{
+       struct smc911x_local *lp = netdev_priv(dev);
+       unsigned long ioaddr = dev->base_addr;
+       int phyaddr = lp->mii.phy_id;
+       int bmcr;
+
+       DBG(SMC_DEBUG_FUNC, "%s: --> %s\n", dev->name, __FUNCTION__);
+
+       /* Enter Link Disable state */
+       SMC_GET_PHY_BMCR(phyaddr, bmcr);
+       bmcr |= BMCR_PDOWN;
+       SMC_SET_PHY_BMCR(phyaddr, bmcr);
+
+       /*
+        * Set our fixed capabilities
+        * Disable auto-negotiation
+        */
+       bmcr &= ~BMCR_ANENABLE;
+       if (lp->ctl_rfduplx)
+               bmcr |= BMCR_FULLDPLX;
+
+       if (lp->ctl_rspeed == 100)
+               bmcr |= BMCR_SPEED100;
+
+       /* Write our capabilities to the phy control register */
+       SMC_SET_PHY_BMCR(phyaddr, bmcr);
+
+       /* Re-Configure the Receive/Phy Control register */
+       bmcr &= ~BMCR_PDOWN;
+       SMC_SET_PHY_BMCR(phyaddr, bmcr);
+
+       return 1;
+}
+
+/*
+ * smc911x_phy_reset - reset the phy
+ * @dev: net device
+ * @phy: phy address
+ *
+ * Issue a software reset for the specified PHY and
+ * wait up to 100ms for the reset to complete.  We should
+ * not access the PHY for 50ms after issuing the reset.
+ *
+ * The time to wait appears to be dependent on the PHY.
+ *
+ */
+static int smc911x_phy_reset(struct net_device *dev, int phy)
+{
+       struct smc911x_local *lp = netdev_priv(dev);
+       unsigned long ioaddr = dev->base_addr;
+       int timeout;
+       unsigned long flags;
+       unsigned int reg;
+
+       DBG(SMC_DEBUG_FUNC, "%s: --> %s()\n", dev->name, __FUNCTION__);
+
+       spin_lock_irqsave(&lp->lock, flags);
+       reg = SMC_GET_PMT_CTRL();
+       reg &= ~0xfffff030;
+       reg |= PMT_CTRL_PHY_RST_;
+       SMC_SET_PMT_CTRL(reg);
+       spin_unlock_irqrestore(&lp->lock, flags);
+       for (timeout = 2; timeout; timeout--) {
+               msleep(50);
+               spin_lock_irqsave(&lp->lock, flags);
+               reg = SMC_GET_PMT_CTRL();
+               spin_unlock_irqrestore(&lp->lock, flags);
+               if (!(reg & PMT_CTRL_PHY_RST_)) {
+                       /* extra delay required because the phy may
+                        * not be completed with its reset
+                        * when PHY_BCR_RESET_ is cleared. 256us
+                        * should suffice, but use 500us to be safe
+                        */
+                       udelay(500);
+               break;
+               }
+       }
+
+       return reg & PMT_CTRL_PHY_RST_;
+}
+
+/*
+ * smc911x_phy_powerdown - powerdown phy
+ * @dev: net device
+ * @phy: phy address
+ *
+ * Power down the specified PHY
+ */
+static void smc911x_phy_powerdown(struct net_device *dev, int phy)
+{
+       unsigned long ioaddr = dev->base_addr;
+       unsigned int bmcr;
+
+       /* Enter Link Disable state */
+       SMC_GET_PHY_BMCR(phy, bmcr);
+       bmcr |= BMCR_PDOWN;
+       SMC_SET_PHY_BMCR(phy, bmcr);
+}
+
+/*
+ * smc911x_phy_check_media - check the media status and adjust BMCR
+ * @dev: net device
+ * @init: set true for initialisation
+ *
+ * Select duplex mode depending on negotiation state.  This
+ * also updates our carrier state.
+ */
+static void smc911x_phy_check_media(struct net_device *dev, int init)
+{
+       struct smc911x_local *lp = netdev_priv(dev);
+       unsigned long ioaddr = dev->base_addr;
+       int phyaddr = lp->mii.phy_id;
+       unsigned int bmcr, cr;
+
+       DBG(SMC_DEBUG_FUNC, "%s: --> %s\n", dev->name, __FUNCTION__);
+
+       if (mii_check_media(&lp->mii, netif_msg_link(lp), init)) {
+               /* duplex state has changed */
+               SMC_GET_PHY_BMCR(phyaddr, bmcr);
+               SMC_GET_MAC_CR(cr);
+               if (lp->mii.full_duplex) {
+                       DBG(SMC_DEBUG_MISC, "%s: Configuring for full-duplex mode\n", dev->name);
+                       bmcr |= BMCR_FULLDPLX;
+                       cr |= MAC_CR_RCVOWN_;
+               } else {
+                       DBG(SMC_DEBUG_MISC, "%s: Configuring for half-duplex mode\n", dev->name);
+                       bmcr &= ~BMCR_FULLDPLX;
+                       cr &= ~MAC_CR_RCVOWN_;
+               }
+               SMC_SET_PHY_BMCR(phyaddr, bmcr);
+               SMC_SET_MAC_CR(cr);
+       }
+}
+
+/*
+ * Configures the specified PHY through the MII management interface
+ * using Autonegotiation.
+ * Calls smc911x_phy_fixed() if the user has requested a certain config.
+ * If RPC ANEG bit is set, the media selection is dependent purely on
+ * the selection by the MII (either in the MII BMCR reg or the result
+ * of autonegotiation.)  If the RPC ANEG bit is cleared, the selection
+ * is controlled by the RPC SPEED and RPC DPLX bits.
+ */
+static void smc911x_phy_configure(void *data)
+{
+       struct net_device *dev = data;
+       struct smc911x_local *lp = netdev_priv(dev);
+       unsigned long ioaddr = dev->base_addr;
+       int phyaddr = lp->mii.phy_id;
+       int my_phy_caps; /* My PHY capabilities */
+       int my_ad_caps; /* My Advertised capabilities */
+       int status;
+       unsigned long flags;
+
+       DBG(SMC_DEBUG_FUNC, "%s: --> %s()\n", dev->name, __FUNCTION__);
+
+       /*
+        * We should not be called if phy_type is zero.
+        */
+       if (lp->phy_type == 0)
+                goto smc911x_phy_configure_exit;
+
+       if (smc911x_phy_reset(dev, phyaddr)) {
+               printk("%s: PHY reset timed out\n", dev->name);
+               goto smc911x_phy_configure_exit;
+       }
+       spin_lock_irqsave(&lp->lock, flags);
+
+       /*
+        * Enable PHY Interrupts (for register 18)
+        * Interrupts listed here are enabled
+        */
+       SMC_SET_PHY_INT_MASK(phyaddr, PHY_INT_MASK_ENERGY_ON_ |
+                PHY_INT_MASK_ANEG_COMP_ | PHY_INT_MASK_REMOTE_FAULT_ |
+                PHY_INT_MASK_LINK_DOWN_);
+
+       /* If the user requested no auto neg, then go set his request */
+       if (lp->mii.force_media) {
+               smc911x_phy_fixed(dev);
+               goto smc911x_phy_configure_exit;
+       }
+
+       /* Copy our capabilities from MII_BMSR to MII_ADVERTISE */
+       SMC_GET_PHY_BMSR(phyaddr, my_phy_caps);
+       if (!(my_phy_caps & BMSR_ANEGCAPABLE)) {
+               printk(KERN_INFO "Auto negotiation NOT supported\n");
+               smc911x_phy_fixed(dev);
+               goto smc911x_phy_configure_exit;
+       }
+
+       /* CSMA capable w/ both pauses */
+       my_ad_caps = ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
+
+       if (my_phy_caps & BMSR_100BASE4)
+               my_ad_caps |= ADVERTISE_100BASE4;
+       if (my_phy_caps & BMSR_100FULL)
+               my_ad_caps |= ADVERTISE_100FULL;
+       if (my_phy_caps & BMSR_100HALF)
+               my_ad_caps |= ADVERTISE_100HALF;
+       if (my_phy_caps & BMSR_10FULL)
+               my_ad_caps |= ADVERTISE_10FULL;
+       if (my_phy_caps & BMSR_10HALF)
+               my_ad_caps |= ADVERTISE_10HALF;
+
+       /* Disable capabilities not selected by our user */
+       if (lp->ctl_rspeed != 100)
+               my_ad_caps &= ~(ADVERTISE_100BASE4|ADVERTISE_100FULL|ADVERTISE_100HALF);
+
+        if (!lp->ctl_rfduplx)
+               my_ad_caps &= ~(ADVERTISE_100FULL|ADVERTISE_10FULL);
+
+       /* Update our Auto-Neg Advertisement Register */
+       SMC_SET_PHY_MII_ADV(phyaddr, my_ad_caps);
+       lp->mii.advertising = my_ad_caps;
+
+       /*
+        * Read the register back.       Without this, it appears that when
+        * auto-negotiation is restarted, sometimes it isn't ready and
+        * the link does not come up.
+        */
+       udelay(10);
+       SMC_GET_PHY_MII_ADV(phyaddr, status);
+
+       DBG(SMC_DEBUG_MISC, "%s: phy caps=0x%04x\n", dev->name, my_phy_caps);
+       DBG(SMC_DEBUG_MISC, "%s: phy advertised caps=0x%04x\n", dev->name, my_ad_caps);
+
+       /* Restart auto-negotiation process in order to advertise my caps */
+       SMC_SET_PHY_BMCR(phyaddr, BMCR_ANENABLE | BMCR_ANRESTART);
+
+       smc911x_phy_check_media(dev, 1);
+
+smc911x_phy_configure_exit:
+       spin_unlock_irqrestore(&lp->lock, flags);
+       lp->work_pending = 0;
+}
+
+/*
+ * smc911x_phy_interrupt
+ *
+ * Purpose:  Handle interrupts relating to PHY register 18. This is
+ *      called from the "hard" interrupt handler under our private spinlock.
+ */
+static void smc911x_phy_interrupt(struct net_device *dev)
+{
+       struct smc911x_local *lp = netdev_priv(dev);
+       unsigned long ioaddr = dev->base_addr;
+       int phyaddr = lp->mii.phy_id;
+       int status;
+
+       DBG(SMC_DEBUG_FUNC, "%s: --> %s\n", dev->name, __FUNCTION__);
+
+       if (lp->phy_type == 0)
+               return;
+
+       smc911x_phy_check_media(dev, 0);
+       /* read to clear status bits */
+       SMC_GET_PHY_INT_SRC(phyaddr,status);
+       DBG(SMC_DEBUG_MISC, "%s: PHY interrupt status 0x%04x\n",
+               dev->name, status & 0xffff);
+       DBG(SMC_DEBUG_MISC, "%s: AFC_CFG 0x%08x\n",
+               dev->name, SMC_GET_AFC_CFG());
+}
+
+/*--- END PHY CONTROL AND CONFIGURATION-------------------------------------*/
+
+/*
+ * This is the main routine of the driver, to handle the device when
+ * it needs some attention.
+ */
+static irqreturn_t smc911x_interrupt(int irq, void *dev_id, struct pt_regs *regs)
+{
+       struct net_device *dev = dev_id;
+       unsigned long ioaddr = dev->base_addr;
+       struct smc911x_local *lp = netdev_priv(dev);
+       unsigned int status, mask, timeout;
+       unsigned int rx_overrun=0, cr, pkts;
+       unsigned long flags;
+
+       DBG(SMC_DEBUG_FUNC, "%s: --> %s\n", dev->name, __FUNCTION__);
+
+       spin_lock_irqsave(&lp->lock, flags);
+
+       /* Spurious interrupt check */
+       if ((SMC_GET_IRQ_CFG() & (INT_CFG_IRQ_INT_ | INT_CFG_IRQ_EN_)) !=
+               (INT_CFG_IRQ_INT_ | INT_CFG_IRQ_EN_)) {
+               return IRQ_NONE;
+       }
+
+       mask = SMC_GET_INT_EN();
+       SMC_SET_INT_EN(0);
+
+       /* set a timeout value, so I don't stay here forever */
+       timeout = 8;
+
+
+       do {
+               status = SMC_GET_INT();
+
+               DBG(SMC_DEBUG_MISC, "%s: INT 0x%08x MASK 0x%08x OUTSIDE MASK 0x%08x\n",
+                       dev->name, status, mask, status & ~mask);
+
+               status &= mask;
+               if (!status)
+                       break;
+
+               /* Handle SW interrupt condition */
+               if (status & INT_STS_SW_INT_) {
+                       SMC_ACK_INT(INT_STS_SW_INT_);
+                       mask &= ~INT_EN_SW_INT_EN_;
+               }
+               /* Handle various error conditions */
+               if (status & INT_STS_RXE_) {
+                       SMC_ACK_INT(INT_STS_RXE_);
+                       lp->stats.rx_errors++;
+               }
+               if (status & INT_STS_RXDFH_INT_) {
+                       SMC_ACK_INT(INT_STS_RXDFH_INT_);
+                       lp->stats.rx_dropped+=SMC_GET_RX_DROP();
+                }
+               /* Undocumented interrupt-what is the right thing to do here? */
+               if (status & INT_STS_RXDF_INT_) {
+                       SMC_ACK_INT(INT_STS_RXDF_INT_);
+               }
+
+               /* Rx Data FIFO exceeds set level */
+               if (status & INT_STS_RDFL_) {
+                       if (IS_REV_A(lp->revision)) {
+                               rx_overrun=1;
+                               SMC_GET_MAC_CR(cr);
+                               cr &= ~MAC_CR_RXEN_;
+                               SMC_SET_MAC_CR(cr);
+                               DBG(SMC_DEBUG_RX, "%s: RX overrun\n", dev->name);
+                               lp->stats.rx_errors++;
+                               lp->stats.rx_fifo_errors++;
+                       }
+                       SMC_ACK_INT(INT_STS_RDFL_);
+               }
+               if (status & INT_STS_RDFO_) {
+                       if (!IS_REV_A(lp->revision)) {
+                               SMC_GET_MAC_CR(cr);
+                               cr &= ~MAC_CR_RXEN_;
+                               SMC_SET_MAC_CR(cr);
+                               rx_overrun=1;
+                               DBG(SMC_DEBUG_RX, "%s: RX overrun\n", dev->name);
+                               lp->stats.rx_errors++;
+                               lp->stats.rx_fifo_errors++;
+                       }
+                       SMC_ACK_INT(INT_STS_RDFO_);
+               }
+               /* Handle receive condition */
+               if ((status & INT_STS_RSFL_) || rx_overrun) {
+                       unsigned int fifo;
+                       DBG(SMC_DEBUG_RX, "%s: RX irq\n", dev->name);
+                       fifo = SMC_GET_RX_FIFO_INF();
+                       pkts = (fifo & RX_FIFO_INF_RXSUSED_) >> 16;
+                       DBG(SMC_DEBUG_RX, "%s: Rx FIFO pkts %d, bytes %d\n",
+                               dev->name, pkts, fifo & 0xFFFF );
+                       if (pkts != 0) {
+#ifdef SMC_USE_DMA
+                               unsigned int fifo;
+                               if (lp->rxdma_active){
+                                       DBG(SMC_DEBUG_RX | SMC_DEBUG_DMA,
+                                               "%s: RX DMA active\n", dev->name);
+                                       /* The DMA is already running so up the IRQ threshold */
+                                       fifo = SMC_GET_FIFO_INT() & ~0xFF;
+                                       fifo |= pkts & 0xFF;
+                                       DBG(SMC_DEBUG_RX,
+                                               "%s: Setting RX stat FIFO threshold to %d\n",
+                                               dev->name, fifo & 0xff);
+                                       SMC_SET_FIFO_INT(fifo);
+                               } else
+#endif
+                               smc911x_rcv(dev);
+                       }
+                       SMC_ACK_INT(INT_STS_RSFL_);
+               }
+               /* Handle transmit FIFO available */
+               if (status & INT_STS_TDFA_) {
+                       DBG(SMC_DEBUG_TX, "%s: TX data FIFO space available irq\n", dev->name);
+                       SMC_SET_FIFO_TDA(0xFF);
+                       lp->tx_throttle = 0;
+#ifdef SMC_USE_DMA
+                       if (!lp->txdma_active)
+#endif
+                               netif_wake_queue(dev);
+                       SMC_ACK_INT(INT_STS_TDFA_);
+               }
+               /* Handle transmit done condition */
+#if 1
+               if (status & (INT_STS_TSFL_ | INT_STS_GPT_INT_)) {
+                       DBG(SMC_DEBUG_TX | SMC_DEBUG_MISC,
+                               "%s: Tx stat FIFO limit (%d) /GPT irq\n",
+                               dev->name, (SMC_GET_FIFO_INT() & 0x00ff0000) >> 16);
+                       smc911x_tx(dev);
+                       SMC_SET_GPT_CFG(GPT_CFG_TIMER_EN_ | 10000);
+                       SMC_ACK_INT(INT_STS_TSFL_);
+                       SMC_ACK_INT(INT_STS_TSFL_ | INT_STS_GPT_INT_);
+               }
+#else
+               if (status & INT_STS_TSFL_) {
+                       DBG(SMC_DEBUG_TX, "%s: TX status FIFO limit (%d) irq \n", dev->name, );
+                       smc911x_tx(dev);
+                       SMC_ACK_INT(INT_STS_TSFL_);
+               }
+
+               if (status & INT_STS_GPT_INT_) {
+                       DBG(SMC_DEBUG_RX, "%s: IRQ_CFG 0x%08x FIFO_INT 0x%08x RX_CFG 0x%08x\n",
+                               dev->name,
+                               SMC_GET_IRQ_CFG(),
+                               SMC_GET_FIFO_INT(),
+                               SMC_GET_RX_CFG());
+                       DBG(SMC_DEBUG_RX, "%s: Rx Stat FIFO Used 0x%02x "
+                               "Data FIFO Used 0x%04x Stat FIFO 0x%08x\n",
+                               dev->name,
+                               (SMC_GET_RX_FIFO_INF() & 0x00ff0000) >> 16,
+                               SMC_GET_RX_FIFO_INF() & 0xffff,
+                               SMC_GET_RX_STS_FIFO_PEEK());
+                       SMC_SET_GPT_CFG(GPT_CFG_TIMER_EN_ | 10000);
+                       SMC_ACK_INT(INT_STS_GPT_INT_);
+               }
+#endif
+
+               /* Handle PHY interupt condition */
+               if (status & INT_STS_PHY_INT_) {
+                       DBG(SMC_DEBUG_MISC, "%s: PHY irq\n", dev->name);
+                       smc911x_phy_interrupt(dev);
+                       SMC_ACK_INT(INT_STS_PHY_INT_);
+               }
+       } while (--timeout);
+
+       /* restore mask state */
+       SMC_SET_INT_EN(mask);
+
+       DBG(SMC_DEBUG_MISC, "%s: Interrupt done (%d loops)\n",
+               dev->name, 8-timeout);
+
+       spin_unlock_irqrestore(&lp->lock, flags);
+
+       DBG(3, "%s: Interrupt done (%d loops)\n", dev->name, 8-timeout);
+
+       return IRQ_HANDLED;
+}
+
+#ifdef SMC_USE_DMA
+static void
+smc911x_tx_dma_irq(int dma, void *data, struct pt_regs *regs)
+{
+       struct net_device *dev = (struct net_device *)data;
+       struct smc911x_local *lp = netdev_priv(dev);
+       struct sk_buff *skb = lp->current_tx_skb;
+       unsigned long flags;
+
+       DBG(SMC_DEBUG_FUNC, "%s: --> %s\n", dev->name, __FUNCTION__);
+
+       DBG(SMC_DEBUG_TX | SMC_DEBUG_DMA, "%s: TX DMA irq handler\n", dev->name);
+       /* Clear the DMA interrupt sources */
+       SMC_DMA_ACK_IRQ(dev, dma);
+       BUG_ON(skb == NULL);
+       dma_unmap_single(NULL, tx_dmabuf, tx_dmalen, DMA_TO_DEVICE);
+       dev->trans_start = jiffies;
+       dev_kfree_skb_irq(skb);
+       lp->current_tx_skb = NULL;
+       if (lp->pending_tx_skb != NULL)
+               smc911x_hardware_send_pkt(dev);
+       else {
+               DBG(SMC_DEBUG_TX | SMC_DEBUG_DMA,
+                       "%s: No pending Tx packets. DMA disabled\n", dev->name);
+               spin_lock_irqsave(&lp->lock, flags);
+               lp->txdma_active = 0;
+               if (!lp->tx_throttle) {
+                       netif_wake_queue(dev);
+               }
+               spin_unlock_irqrestore(&lp->lock, flags);
+       }
+
+       DBG(SMC_DEBUG_TX | SMC_DEBUG_DMA,
+               "%s: TX DMA irq completed\n", dev->name);
+}
+static void
+smc911x_rx_dma_irq(int dma, void *data, struct pt_regs *regs)
+{
+       struct net_device *dev = (struct net_device *)data;
+       unsigned long ioaddr = dev->base_addr;
+       struct smc911x_local *lp = netdev_priv(dev);
+       struct sk_buff *skb = lp->current_rx_skb;
+       unsigned long flags;
+       unsigned int pkts;
+
+       DBG(SMC_DEBUG_FUNC, "%s: --> %s\n", dev->name, __FUNCTION__);
+       DBG(SMC_DEBUG_RX | SMC_DEBUG_DMA, "%s: RX DMA irq handler\n", dev->name);
+       /* Clear the DMA interrupt sources */
+       SMC_DMA_ACK_IRQ(dev, dma);
+       dma_unmap_single(NULL, rx_dmabuf, rx_dmalen, DMA_FROM_DEVICE);
+       BUG_ON(skb == NULL);
+       lp->current_rx_skb = NULL;
+       PRINT_PKT(skb->data, skb->len);
+       dev->last_rx = jiffies;
+       skb->dev = dev;
+       skb->protocol = eth_type_trans(skb, dev);
+       netif_rx(skb);
+       lp->stats.rx_packets++;
+       lp->stats.rx_bytes += skb->len;
+
+       spin_lock_irqsave(&lp->lock, flags);
+       pkts = (SMC_GET_RX_FIFO_INF() & RX_FIFO_INF_RXSUSED_) >> 16;
+       if (pkts != 0) {
+               smc911x_rcv(dev);
+       }else {
+               lp->rxdma_active = 0;
+       }
+       spin_unlock_irqrestore(&lp->lock, flags);
+       DBG(SMC_DEBUG_RX | SMC_DEBUG_DMA,
+               "%s: RX DMA irq completed. DMA RX FIFO PKTS %d\n",
+               dev->name, pkts);
+}
+#endif  /* SMC_USE_DMA */
+
+#ifdef CONFIG_NET_POLL_CONTROLLER
+/*
+ * Polling receive - used by netconsole and other diagnostic tools
+ * to allow network i/o with interrupts disabled.
+ */
+static void smc911x_poll_controller(struct net_device *dev)
+{
+       disable_irq(dev->irq);
+       smc911x_interrupt(dev->irq, dev, NULL);
+       enable_irq(dev->irq);
+}
+#endif
+
+/* Our watchdog timed out. Called by the networking layer */
+static void smc911x_timeout(struct net_device *dev)
+{
+       struct smc911x_local *lp = netdev_priv(dev);
+       unsigned long ioaddr = dev->base_addr;
+       int status, mask;
+       unsigned long flags;
+
+       DBG(SMC_DEBUG_FUNC, "%s: --> %s\n", dev->name, __FUNCTION__);
+
+       spin_lock_irqsave(&lp->lock, flags);
+       status = SMC_GET_INT();
+       mask = SMC_GET_INT_EN();
+       spin_unlock_irqrestore(&lp->lock, flags);
+       DBG(SMC_DEBUG_MISC, "%s: INT 0x%02x MASK 0x%02x \n",
+               dev->name, status, mask);
+
+       /* Dump the current TX FIFO contents and restart */
+       mask = SMC_GET_TX_CFG();
+       SMC_SET_TX_CFG(mask | TX_CFG_TXS_DUMP_ | TX_CFG_TXD_DUMP_);
+       /*
+        * Reconfiguring the PHY doesn't seem like a bad idea here, but
+        * smc911x_phy_configure() calls msleep() which calls schedule_timeout()
+        * which calls schedule().       Hence we use a work queue.
+        */
+       if (lp->phy_type != 0) {
+               if (schedule_work(&lp->phy_configure)) {
+                       lp->work_pending = 1;
+               }
+       }
+
+       /* We can accept TX packets again */
+       dev->trans_start = jiffies;
+       netif_wake_queue(dev);
+}
+
+/*
+ * This routine will, depending on the values passed to it,
+ * either make it accept multicast packets, go into
+ * promiscuous mode (for TCPDUMP and cousins) or accept
+ * a select set of multicast packets
+ */
+static void smc911x_set_multicast_list(struct net_device *dev)
+{
+       struct smc911x_local *lp = netdev_priv(dev);
+       unsigned long ioaddr = dev->base_addr;
+       unsigned int multicast_table[2];
+       unsigned int mcr, update_multicast = 0;
+       unsigned long flags;
+       /* table for flipping the order of 5 bits */
+       static const unsigned char invert5[] =
+               {0x00, 0x10, 0x08, 0x18, 0x04, 0x14, 0x0C, 0x1C,
+                0x02, 0x12, 0x0A, 0x1A, 0x06, 0x16, 0x0E, 0x1E,
+                0x01, 0x11, 0x09, 0x19, 0x05, 0x15, 0x0D, 0x1D,
+                0x03, 0x13, 0x0B, 0x1B, 0x07, 0x17, 0x0F, 0x1F};
+
+
+       DBG(SMC_DEBUG_FUNC, "%s: --> %s\n", dev->name, __FUNCTION__);
+
+       spin_lock_irqsave(&lp->lock, flags);
+       SMC_GET_MAC_CR(mcr);
+       spin_unlock_irqrestore(&lp->lock, flags);
+
+       if (dev->flags & IFF_PROMISC) {
+
+               DBG(SMC_DEBUG_MISC, "%s: RCR_PRMS\n", dev->name);
+               mcr |= MAC_CR_PRMS_;
+       }
+       /*
+        * Here, I am setting this to accept all multicast packets.
+        * I don't need to zero the multicast table, because the flag is
+        * checked before the table is
+        */
+       else if (dev->flags & IFF_ALLMULTI || dev->mc_count > 16) {
+               DBG(SMC_DEBUG_MISC, "%s: RCR_ALMUL\n", dev->name);
+               mcr |= MAC_CR_MCPAS_;
+       }
+
+       /*
+        * This sets the internal hardware table to filter out unwanted
+        * multicast packets before they take up memory.
+        *
+        * The SMC chip uses a hash table where the high 6 bits of the CRC of
+        * address are the offset into the table.       If that bit is 1, then the
+        * multicast packet is accepted.  Otherwise, it's dropped silently.
+        *
+        * To use the 6 bits as an offset into the table, the high 1 bit is
+        * the number of the 32 bit register, while the low 5 bits are the bit
+        * within that register.
+        */
+       else if (dev->mc_count)  {
+               int i;
+               struct dev_mc_list *cur_addr;
+
+               /* Set the Hash perfec mode */
+               mcr |= MAC_CR_HPFILT_;
+
+               /* start with a table of all zeros: reject all */
+               memset(multicast_table, 0, sizeof(multicast_table));
+
+               cur_addr = dev->mc_list;
+               for (i = 0; i < dev->mc_count; i++, cur_addr = cur_addr->next) {
+                       int position;
+
+                       /* do we have a pointer here? */
+                       if (!cur_addr)
+                               break;
+                       /* make sure this is a multicast address -
+                               shouldn't this be a given if we have it here ? */
+                       if (!(*cur_addr->dmi_addr & 1))
+                                continue;
+
+                       /* only use the low order bits */
+                       position = crc32_le(~0, cur_addr->dmi_addr, 6) & 0x3f;
+
+                       /* do some messy swapping to put the bit in the right spot */
+                       multicast_table[invert5[position&0x1F]&0x1] |=
+                               (1<<invert5[(position>>1)&0x1F]);
+               }
+
+               /* be sure I get rid of flags I might have set */
+               mcr &= ~(MAC_CR_PRMS_ | MAC_CR_MCPAS_);
+
+               /* now, the table can be loaded into the chipset */
+               update_multicast = 1;
+       } else   {
+               DBG(SMC_DEBUG_MISC, "%s: ~(MAC_CR_PRMS_|MAC_CR_MCPAS_)\n",
+                       dev->name);
+               mcr &= ~(MAC_CR_PRMS_ | MAC_CR_MCPAS_);
+
+               /*
+                * since I'm disabling all multicast entirely, I need to
+                * clear the multicast list
+                */
+               memset(multicast_table, 0, sizeof(multicast_table));
+               update_multicast = 1;
+       }
+
+       spin_lock_irqsave(&lp->lock, flags);
+       SMC_SET_MAC_CR(mcr);
+       if (update_multicast) {
+               DBG(SMC_DEBUG_MISC,
+                       "%s: update mcast hash table 0x%08x 0x%08x\n",
+                       dev->name, multicast_table[0], multicast_table[1]);
+               SMC_SET_HASHL(multicast_table[0]);
+               SMC_SET_HASHH(multicast_table[1]);
+       }
+       spin_unlock_irqrestore(&lp->lock, flags);
+}
+
+
+/*
+ * Open and Initialize the board
+ *
+ * Set up everything, reset the card, etc..
+ */
+static int
+smc911x_open(struct net_device *dev)
+{
+       DBG(SMC_DEBUG_FUNC, "%s: --> %s\n", dev->name, __FUNCTION__);
+
+       /*
+        * Check that the address is valid.  If its not, refuse
+        * to bring the device up.       The user must specify an
+        * address using ifconfig eth0 hw ether xx:xx:xx:xx:xx:xx
+        */
+       if (!is_valid_ether_addr(dev->dev_addr)) {
+               PRINTK("%s: no valid ethernet hw addr\n", __FUNCTION__);
+               return -EINVAL;
+       }
+
+       /* reset the hardware */
+       smc911x_reset(dev);
+
+       /* Configure the PHY, initialize the link state */
+       smc911x_phy_configure(dev);
+
+       /* Turn on Tx + Rx */
+       smc911x_enable(dev);
+
+       netif_start_queue(dev);
+
+       return 0;
+}
+
+/*
+ * smc911x_close
+ *
+ * this makes the board clean up everything that it can
+ * and not talk to the outside world.   Caused by
+ * an 'ifconfig ethX down'
+ */
+static int smc911x_close(struct net_device *dev)
+{
+       struct smc911x_local *lp = netdev_priv(dev);
+
+       DBG(SMC_DEBUG_FUNC, "%s: --> %s\n", dev->name, __FUNCTION__);
+
+       netif_stop_queue(dev);
+       netif_carrier_off(dev);
+
+       /* clear everything */
+       smc911x_shutdown(dev);
+
+       if (lp->phy_type != 0) {
+               /* We need to ensure that no calls to
+                * smc911x_phy_configure are pending.
+
+                * flush_scheduled_work() cannot be called because we
+                * are running with the netlink semaphore held (from
+                * devinet_ioctl()) and the pending work queue
+                * contains linkwatch_event() (scheduled by
+                * netif_carrier_off() above). linkwatch_event() also
+                * wants the netlink semaphore.
+                */
+               while (lp->work_pending)
+                       schedule();
+               smc911x_phy_powerdown(dev, lp->mii.phy_id);
+       }
+
+       if (lp->pending_tx_skb) {
+               dev_kfree_skb(lp->pending_tx_skb);
+               lp->pending_tx_skb = NULL;
+       }
+
+       return 0;
+}
+
+/*
+ * Get the current statistics.
+ * This may be called with the card open or closed.
+ */
+static struct net_device_stats *smc911x_query_statistics(struct net_device *dev)
+{
+       struct smc911x_local *lp = netdev_priv(dev);
+       DBG(SMC_DEBUG_FUNC, "%s: --> %s\n", dev->name, __FUNCTION__);
+
+
+       return &lp->stats;
+}
+
+/*
+ * Ethtool support
+ */
+static int
+smc911x_ethtool_getsettings(struct net_device *dev, struct ethtool_cmd *cmd)
+{
+       struct smc911x_local *lp = netdev_priv(dev);
+       unsigned long ioaddr = dev->base_addr;
+       int ret, status;
+       unsigned long flags;
+
+       DBG(SMC_DEBUG_FUNC, "%s: --> %s\n", dev->name, __FUNCTION__);
+       cmd->maxtxpkt = 1;
+       cmd->maxrxpkt = 1;
+
+       if (lp->phy_type != 0) {
+               spin_lock_irqsave(&lp->lock, flags);
+               ret = mii_ethtool_gset(&lp->mii, cmd);
+               spin_unlock_irqrestore(&lp->lock, flags);
+       } else {
+               cmd->supported = SUPPORTED_10baseT_Half |
+                               SUPPORTED_10baseT_Full |
+                               SUPPORTED_TP | SUPPORTED_AUI;
+
+               if (lp->ctl_rspeed == 10)
+                       cmd->speed = SPEED_10;
+               else if (lp->ctl_rspeed == 100)
+                       cmd->speed = SPEED_100;
+
+               cmd->autoneg = AUTONEG_DISABLE;
+               if (lp->mii.phy_id==1)
+                       cmd->transceiver = XCVR_INTERNAL;
+               else
+                       cmd->transceiver = XCVR_EXTERNAL;
+               cmd->port = 0;
+               SMC_GET_PHY_SPECIAL(lp->mii.phy_id, status);
+               cmd->duplex =
+                       (status & (PHY_SPECIAL_SPD_10FULL_ | PHY_SPECIAL_SPD_100FULL_)) ?
+                               DUPLEX_FULL : DUPLEX_HALF;
+               ret = 0;
+       }
+
+       return ret;
+}
+
+static int
+smc911x_ethtool_setsettings(struct net_device *dev, struct ethtool_cmd *cmd)
+{
+       struct smc911x_local *lp = netdev_priv(dev);
+       int ret;
+       unsigned long flags;
+
+       if (lp->phy_type != 0) {
+               spin_lock_irqsave(&lp->lock, flags);
+               ret = mii_ethtool_sset(&lp->mii, cmd);
+               spin_unlock_irqrestore(&lp->lock, flags);
+       } else {
+               if (cmd->autoneg != AUTONEG_DISABLE ||
+                       cmd->speed != SPEED_10 ||
+                       (cmd->duplex != DUPLEX_HALF && cmd->duplex != DUPLEX_FULL) ||
+                       (cmd->port != PORT_TP && cmd->port != PORT_AUI))
+                       return -EINVAL;
+
+               lp->ctl_rfduplx = cmd->duplex == DUPLEX_FULL;
+
+               ret = 0;
+       }
+
+       return ret;
+}
+
+static void
+smc911x_ethtool_getdrvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
+{
+       strncpy(info->driver, CARDNAME, sizeof(info->driver));
+       strncpy(info->version, version, sizeof(info->version));
+       strncpy(info->bus_info, dev->class_dev.dev->bus_id, sizeof(info->bus_info));
+}
+
+static int smc911x_ethtool_nwayreset(struct net_device *dev)
+{
+       struct smc911x_local *lp = netdev_priv(dev);
+       int ret = -EINVAL;
+       unsigned long flags;
+
+       if (lp->phy_type != 0) {
+               spin_lock_irqsave(&lp->lock, flags);
+               ret = mii_nway_restart(&lp->mii);
+               spin_unlock_irqrestore(&lp->lock, flags);
+       }
+
+       return ret;
+}
+
+static u32 smc911x_ethtool_getmsglevel(struct net_device *dev)
+{
+       struct smc911x_local *lp = netdev_priv(dev);
+       return lp->msg_enable;
+}
+
+static void smc911x_ethtool_setmsglevel(struct net_device *dev, u32 level)
+{
+       struct smc911x_local *lp = netdev_priv(dev);
+       lp->msg_enable = level;
+}
+
+static int smc911x_ethtool_getregslen(struct net_device *dev)
+{
+       /* System regs + MAC regs + PHY regs */
+       return (((E2P_CMD - ID_REV)/4 + 1) +
+                       (WUCSR - MAC_CR)+1 + 32) * sizeof(u32);
+}
+
+static void smc911x_ethtool_getregs(struct net_device *dev,
+                                                                                struct ethtool_regs* regs, void *buf)
+{
+       unsigned long ioaddr = dev->base_addr;
+       struct smc911x_local *lp = netdev_priv(dev);
+       unsigned long flags;
+       u32 reg,i,j=0;
+       u32 *data = (u32*)buf;
+
+       regs->version = lp->version;
+       for(i=ID_REV;i<=E2P_CMD;i+=4) {
+               data[j++] = SMC_inl(ioaddr,i);
+       }
+       for(i=MAC_CR;i<=WUCSR;i++) {
+               spin_lock_irqsave(&lp->lock, flags);
+               SMC_GET_MAC_CSR(i, reg);
+               spin_unlock_irqrestore(&lp->lock, flags);
+               data[j++] = reg;
+       }
+       for(i=0;i<=31;i++) {
+               spin_lock_irqsave(&lp->lock, flags);
+               SMC_GET_MII(i, lp->mii.phy_id, reg);
+               spin_unlock_irqrestore(&lp->lock, flags);
+               data[j++] = reg & 0xFFFF;
+       }
+}
+
+static int smc911x_ethtool_wait_eeprom_ready(struct net_device *dev)
+{
+       unsigned long ioaddr = dev->base_addr;
+       unsigned int timeout;
+       int e2p_cmd;
+
+       e2p_cmd = SMC_GET_E2P_CMD();
+       for(timeout=10;(e2p_cmd & E2P_CMD_EPC_BUSY_) && timeout; timeout--) {
+               if (e2p_cmd & E2P_CMD_EPC_TIMEOUT_) {
+                       PRINTK("%s: %s timeout waiting for EEPROM to respond\n",
+                               dev->name, __FUNCTION__);
+                       return -EFAULT;
+               }
+               mdelay(1);
+               e2p_cmd = SMC_GET_E2P_CMD();
+       }
+       if (timeout == 0) {
+               PRINTK("%s: %s timeout waiting for EEPROM CMD not busy\n",
+                       dev->name, __FUNCTION__);
+               return -ETIMEDOUT;
+       }
+       return 0;
+}
+
+static inline int smc911x_ethtool_write_eeprom_cmd(struct net_device *dev,
+                                                                                                       int cmd, int addr)
+{
+       unsigned long ioaddr = dev->base_addr;
+       int ret;
+
+       if ((ret = smc911x_ethtool_wait_eeprom_ready(dev))!=0)
+               return ret;
+       SMC_SET_E2P_CMD(E2P_CMD_EPC_BUSY_ |
+               ((cmd) & (0x7<<28)) |
+               ((addr) & 0xFF));
+       return 0;
+}
+
+static inline int smc911x_ethtool_read_eeprom_byte(struct net_device *dev,
+                                                                                                       u8 *data)
+{
+       unsigned long ioaddr = dev->base_addr;
+       int ret;
+
+       if ((ret = smc911x_ethtool_wait_eeprom_ready(dev))!=0)
+               return ret;
+       *data = SMC_GET_E2P_DATA();
+       return 0;
+}
+
+static inline int smc911x_ethtool_write_eeprom_byte(struct net_device *dev,
+                                                                                                        u8 data)
+{
+       unsigned long ioaddr = dev->base_addr;
+       int ret;
+
+       if ((ret = smc911x_ethtool_wait_eeprom_ready(dev))!=0)
+               return ret;
+       SMC_SET_E2P_DATA(data);
+       return 0;
+}
+
+static int smc911x_ethtool_geteeprom(struct net_device *dev,
+                                                                         struct ethtool_eeprom *eeprom, u8 *data)
+{
+       u8 eebuf[SMC911X_EEPROM_LEN];
+       int i, ret;
+
+       for(i=0;i<SMC911X_EEPROM_LEN;i++) {
+               if ((ret=smc911x_ethtool_write_eeprom_cmd(dev, E2P_CMD_EPC_CMD_READ_, i ))!=0)
+                       return ret;
+               if ((ret=smc911x_ethtool_read_eeprom_byte(dev, &eebuf[i]))!=0)
+                       return ret;
+               }
+       memcpy(data, eebuf+eeprom->offset, eeprom->len);
+       return 0;
+}
+
+static int smc911x_ethtool_seteeprom(struct net_device *dev,
+                                                                          struct ethtool_eeprom *eeprom, u8 *data)
+{
+       int i, ret;
+
+       /* Enable erase */
+       if ((ret=smc911x_ethtool_write_eeprom_cmd(dev, E2P_CMD_EPC_CMD_EWEN_, 0 ))!=0)
+               return ret;
+       for(i=eeprom->offset;i<(eeprom->offset+eeprom->len);i++) {
+               /* erase byte */
+               if ((ret=smc911x_ethtool_write_eeprom_cmd(dev, E2P_CMD_EPC_CMD_ERASE_, i ))!=0)
+                       return ret;
+               /* write byte */
+               if ((ret=smc911x_ethtool_write_eeprom_byte(dev, *data))!=0)
+                        return ret;
+               if ((ret=smc911x_ethtool_write_eeprom_cmd(dev, E2P_CMD_EPC_CMD_WRITE_, i ))!=0)
+                       return ret;
+               }
+        return 0;
+}
+
+static int smc911x_ethtool_geteeprom_len(struct net_device *dev)
+{
+        return SMC911X_EEPROM_LEN;
+}
+
+static struct ethtool_ops smc911x_ethtool_ops = {
+       .get_settings    = smc911x_ethtool_getsettings,
+       .set_settings    = smc911x_ethtool_setsettings,
+       .get_drvinfo     = smc911x_ethtool_getdrvinfo,
+       .get_msglevel    = smc911x_ethtool_getmsglevel,
+       .set_msglevel    = smc911x_ethtool_setmsglevel,
+       .nway_reset = smc911x_ethtool_nwayreset,
+       .get_link        = ethtool_op_get_link,
+       .get_regs_len    = smc911x_ethtool_getregslen,
+       .get_regs        = smc911x_ethtool_getregs,
+       .get_eeprom_len = smc911x_ethtool_geteeprom_len,
+       .get_eeprom = smc911x_ethtool_geteeprom,
+       .set_eeprom = smc911x_ethtool_seteeprom,
+};
+
+/*
+ * smc911x_findirq
+ *
+ * This routine has a simple purpose -- make the SMC chip generate an
+ * interrupt, so an auto-detect routine can detect it, and find the IRQ,
+ */
+static int __init smc911x_findirq(unsigned long ioaddr)
+{
+       int timeout = 20;
+       unsigned long cookie;
+
+       DBG(SMC_DEBUG_FUNC, "--> %s\n", __FUNCTION__);
+
+       cookie = probe_irq_on();
+
+       /*
+        * Force a SW interrupt
+        */
+
+       SMC_SET_INT_EN(INT_EN_SW_INT_EN_);
+
+       /*
+        * Wait until positive that the interrupt has been generated
+        */
+       do {
+               int int_status;
+               udelay(10);
+               int_status = SMC_GET_INT_EN();
+               if (int_status & INT_EN_SW_INT_EN_)
+                        break;         /* got the interrupt */
+       } while (--timeout);
+
+       /*
+        * there is really nothing that I can do here if timeout fails,
+        * as autoirq_report will return a 0 anyway, which is what I
+        * want in this case.    Plus, the clean up is needed in both
+        * cases.
+        */
+
+       /* and disable all interrupts again */
+       SMC_SET_INT_EN(0);
+
+       /* and return what I found */
+       return probe_irq_off(cookie);
+}
+
+/*
+ * Function: smc911x_probe(unsigned long ioaddr)
+ *
+ * Purpose:
+ *      Tests to see if a given ioaddr points to an SMC911x chip.
+ *      Returns a 0 on success
+ *
+ * Algorithm:
+ *      (1) see if the endian word is OK
+ *      (1) see if I recognize the chip ID in the appropriate register
+ *
+ * Here I do typical initialization tasks.
+ *
+ * o  Initialize the structure if needed
+ * o  print out my vanity message if not done so already
+ * o  print out what type of hardware is detected
+ * o  print out the ethernet address
+ * o  find the IRQ
+ * o  set up my private data
+ * o  configure the dev structure with my subroutines
+ * o  actually GRAB the irq.
+ * o  GRAB the region
+ */
+static int __init smc911x_probe(struct net_device *dev, unsigned long ioaddr)
+{
+       struct smc911x_local *lp = netdev_priv(dev);
+       int i, retval;
+       unsigned int val, chip_id, revision;
+       const char *version_string;
+
+       DBG(SMC_DEBUG_FUNC, "%s: --> %s\n", dev->name, __FUNCTION__);
+
+       /* First, see if the endian word is recognized */
+       val = SMC_GET_BYTE_TEST();
+       DBG(SMC_DEBUG_MISC, "%s: endian probe returned 0x%04x\n", CARDNAME, val);
+       if (val != 0x87654321) {
+               printk(KERN_ERR "Invalid chip endian 0x08%x\n",val);
+               retval = -ENODEV;
+               goto err_out;
+       }
+
+       /*
+        * check if the revision register is something that I
+        * recognize.   These might need to be added to later,
+        * as future revisions could be added.
+        */
+       chip_id = SMC_GET_PN();
+       DBG(SMC_DEBUG_MISC, "%s: id probe returned 0x%04x\n", CARDNAME, chip_id);
+       for(i=0;chip_ids[i].id != 0; i++) {
+               if (chip_ids[i].id == chip_id) break;
+       }
+       if (!chip_ids[i].id) {
+               printk(KERN_ERR "Unknown chip ID %04x\n", chip_id);
+               retval = -ENODEV;
+               goto err_out;
+       }
+       version_string = chip_ids[i].name;
+
+       revision = SMC_GET_REV();
+       DBG(SMC_DEBUG_MISC, "%s: revision = 0x%04x\n", CARDNAME, revision);
+
+       /* At this point I'll assume that the chip is an SMC911x. */
+       DBG(SMC_DEBUG_MISC, "%s: Found a %s\n", CARDNAME, chip_ids[i].name);
+
+       /* Validate the TX FIFO size requested */
+       if ((tx_fifo_kb < 2) || (tx_fifo_kb > 14)) {
+               printk(KERN_ERR "Invalid TX FIFO size requested %d\n", tx_fifo_kb);
+               retval = -EINVAL;
+               goto err_out;
+       }
+
+       /* fill in some of the fields */
+       dev->base_addr = ioaddr;
+       lp->version = chip_ids[i].id;
+       lp->revision = revision;
+       lp->tx_fifo_kb = tx_fifo_kb;
+       /* Reverse calculate the RX FIFO size from the TX */
+       lp->tx_fifo_size=(lp->tx_fifo_kb<<10) - 512;
+       lp->rx_fifo_size= ((0x4000 - 512 - lp->tx_fifo_size) / 16) * 15;
+
+       /* Set the automatic flow control values */
+       switch(lp->tx_fifo_kb) {
+               /*
+                *       AFC_HI is about ((Rx Data Fifo Size)*2/3)/64
+                *       AFC_LO is AFC_HI/2
+                *       BACK_DUR is about 5uS*(AFC_LO) rounded down
+                */
+               case 2:/* 13440 Rx Data Fifo Size */
+                       lp->afc_cfg=0x008C46AF;break;
+               case 3:/* 12480 Rx Data Fifo Size */
+                       lp->afc_cfg=0x0082419F;break;
+               case 4:/* 11520 Rx Data Fifo Size */
+                       lp->afc_cfg=0x00783C9F;break;
+               case 5:/* 10560 Rx Data Fifo Size */
+                       lp->afc_cfg=0x006E374F;break;
+               case 6:/* 9600 Rx Data Fifo Size */
+                       lp->afc_cfg=0x0064328F;break;
+               case 7:/* 8640 Rx Data Fifo Size */
+                       lp->afc_cfg=0x005A2D7F;break;
+               case 8:/* 7680 Rx Data Fifo Size */
+                       lp->afc_cfg=0x0050287F;break;
+               case 9:/* 6720 Rx Data Fifo Size */
+                       lp->afc_cfg=0x0046236F;break;
+               case 10:/* 5760 Rx Data Fifo Size */
+                       lp->afc_cfg=0x003C1E6F;break;
+               case 11:/* 4800 Rx Data Fifo Size */
+                       lp->afc_cfg=0x0032195F;break;
+               /*
+                *       AFC_HI is ~1520 bytes less than RX Data Fifo Size
+                *       AFC_LO is AFC_HI/2
+                *       BACK_DUR is about 5uS*(AFC_LO) rounded down
+                */
+               case 12:/* 3840 Rx Data Fifo Size */
+                       lp->afc_cfg=0x0024124F;break;
+               case 13:/* 2880 Rx Data Fifo Size */
+                       lp->afc_cfg=0x0015073F;break;
+               case 14:/* 1920 Rx Data Fifo Size */
+                       lp->afc_cfg=0x0006032F;break;
+                default:
+                        PRINTK("%s: ERROR -- no AFC_CFG setting found",
+                               dev->name);
+                        break;
+       }
+
+       DBG(SMC_DEBUG_MISC | SMC_DEBUG_TX | SMC_DEBUG_RX,
+               "%s: tx_fifo %d rx_fifo %d afc_cfg 0x%08x\n", CARDNAME,
+               lp->tx_fifo_size, lp->rx_fifo_size, lp->afc_cfg);
+
+       spin_lock_init(&lp->lock);
+
+       /* Get the MAC address */
+       SMC_GET_MAC_ADDR(dev->dev_addr);
+
+       /* now, reset the chip, and put it into a known state */
+       smc911x_reset(dev);
+
+       /*
+        * If dev->irq is 0, then the device has to be banged on to see
+        * what the IRQ is.
+        *
+        * Specifying an IRQ is done with the assumption that the user knows
+        * what (s)he is doing.  No checking is done!!!!
+        */
+       if (dev->irq < 1) {
+               int trials;
+
+               trials = 3;
+               while (trials--) {
+                       dev->irq = smc911x_findirq(ioaddr);
+                       if (dev->irq)
+                               break;
+                       /* kick the card and try again */
+                       smc911x_reset(dev);
+               }
+       }
+       if (dev->irq == 0) {
+               printk("%s: Couldn't autodetect your IRQ. Use irq=xx.\n",
+                       dev->name);
+               retval = -ENODEV;
+               goto err_out;
+       }
+       dev->irq = irq_canonicalize(dev->irq);
+
+       /* Fill in the fields of the device structure with ethernet values. */
+       ether_setup(dev);
+
+       dev->open = smc911x_open;
+       dev->stop = smc911x_close;
+       dev->hard_start_xmit = smc911x_hard_start_xmit;
+       dev->tx_timeout = smc911x_timeout;
+       dev->watchdog_timeo = msecs_to_jiffies(watchdog);
+       dev->get_stats = smc911x_query_statistics;
+       dev->set_multicast_list = smc911x_set_multicast_list;
+       dev->ethtool_ops = &smc911x_ethtool_ops;
+#ifdef CONFIG_NET_POLL_CONTROLLER
+       dev->poll_controller = smc911x_poll_controller;
+#endif
+
+       INIT_WORK(&lp->phy_configure, smc911x_phy_configure, dev);
+       lp->mii.phy_id_mask = 0x1f;
+       lp->mii.reg_num_mask = 0x1f;
+       lp->mii.force_media = 0;
+       lp->mii.full_duplex = 0;
+       lp->mii.dev = dev;
+       lp->mii.mdio_read = smc911x_phy_read;
+       lp->mii.mdio_write = smc911x_phy_write;
+
+       /*
+        * Locate the phy, if any.
+        */
+       smc911x_phy_detect(dev);
+
+       /* Set default parameters */
+       lp->msg_enable = NETIF_MSG_LINK;
+       lp->ctl_rfduplx = 1;
+       lp->ctl_rspeed = 100;
+
+       /* Grab the IRQ */
+       retval = request_irq(dev->irq, &smc911x_interrupt, SA_SHIRQ, dev->name, dev);
+       if (retval)
+               goto err_out;
+
+       set_irq_type(dev->irq, IRQT_FALLING);
+
+#ifdef SMC_USE_DMA
+       lp->rxdma = SMC_DMA_REQUEST(dev, smc911x_rx_dma_irq);
+       lp->txdma = SMC_DMA_REQUEST(dev, smc911x_tx_dma_irq);
+       lp->rxdma_active = 0;
+       lp->txdma_active = 0;
+       dev->dma = lp->rxdma;
+#endif
+
+       retval = register_netdev(dev);
+       if (retval == 0) {
+               /* now, print out the card info, in a short format.. */
+               printk("%s: %s (rev %d) at %#lx IRQ %d",
+                       dev->name, version_string, lp->revision,
+                       dev->base_addr, dev->irq);
+
+#ifdef SMC_USE_DMA
+               if (lp->rxdma != -1)
+                       printk(" RXDMA %d ", lp->rxdma);
+
+               if (lp->txdma != -1)
+                       printk("TXDMA %d", lp->txdma);
+#endif
+               printk("\n");
+               if (!is_valid_ether_addr(dev->dev_addr)) {
+                       printk("%s: Invalid ethernet MAC address. Please "
+                                       "set using ifconfig\n", dev->name);
+               } else {
+                       /* Print the Ethernet address */
+                       printk("%s: Ethernet addr: ", dev->name);
+                       for (i = 0; i < 5; i++)
+                               printk("%2.2x:", dev->dev_addr[i]);
+                       printk("%2.2x\n", dev->dev_addr[5]);
+               }
+
+               if (lp->phy_type == 0) {
+                       PRINTK("%s: No PHY found\n", dev->name);
+               } else if ((lp->phy_type & ~0xff) == LAN911X_INTERNAL_PHY_ID) {
+                       PRINTK("%s: LAN911x Internal PHY\n", dev->name);
+               } else {
+                       PRINTK("%s: External PHY 0x%08x\n", dev->name, lp->phy_type);
+               }
+       }
+
+err_out:
+#ifdef SMC_USE_DMA
+       if (retval) {
+               if (lp->rxdma != -1) {
+                       SMC_DMA_FREE(dev, lp->rxdma);
+               }
+               if (lp->txdma != -1) {
+                       SMC_DMA_FREE(dev, lp->txdma);
+               }
+       }
+#endif
+       return retval;
+}
+
+/*
+ * smc911x_init(void)
+ *
+ *       Output:
+ *      0 --> there is a device
+ *      anything else, error
+ */
+static int smc911x_drv_probe(struct platform_device *pdev)
+{
+       struct net_device *ndev;
+       struct resource *res;
+       unsigned int *addr;
+       int ret;
+
+       DBG(SMC_DEBUG_FUNC, "--> %s\n",  __FUNCTION__);
+       res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+       if (!res) {
+               ret = -ENODEV;
+               goto out;
+       }
+
+       /*
+        * Request the regions.
+        */
+       if (!request_mem_region(res->start, SMC911X_IO_EXTENT, CARDNAME)) {
+                ret = -EBUSY;
+                goto out;
+       }
+
+       ndev = alloc_etherdev(sizeof(struct smc911x_local));
+       if (!ndev) {
+               printk("%s: could not allocate device.\n", CARDNAME);
+               ret = -ENOMEM;
+               goto release_1;
+       }
+       SET_MODULE_OWNER(ndev);
+       SET_NETDEV_DEV(ndev, &pdev->dev);
+
+       ndev->dma = (unsigned char)-1;
+       ndev->irq = platform_get_irq(pdev, 0);
+
+       addr = ioremap(res->start, SMC911X_IO_EXTENT);
+       if (!addr) {
+               ret = -ENOMEM;
+               goto release_both;
+       }
+
+       platform_set_drvdata(pdev, ndev);
+       ret = smc911x_probe(ndev, (unsigned long)addr);
+       if (ret != 0) {
+               platform_set_drvdata(pdev, NULL);
+               iounmap(addr);
+release_both:
+               free_netdev(ndev);
+release_1:
+               release_mem_region(res->start, SMC911X_IO_EXTENT);
+out:
+               printk("%s: not found (%d).\n", CARDNAME, ret);
+       }
+#ifdef SMC_USE_DMA
+       else {
+               struct smc911x_local *lp = netdev_priv(ndev);
+               lp->physaddr = res->start;
+               lp->dev = &pdev->dev;
+       }
+#endif
+
+       return ret;
+}
+
+static int smc911x_drv_remove(struct platform_device *pdev)
+{
+       struct net_device *ndev = platform_get_drvdata(pdev);
+       struct resource *res;
+
+       DBG(SMC_DEBUG_FUNC, "--> %s\n", __FUNCTION__);
+       platform_set_drvdata(pdev, NULL);
+
+       unregister_netdev(ndev);
+
+       free_irq(ndev->irq, ndev);
+
+#ifdef SMC_USE_DMA
+       {
+               struct smc911x_local *lp = netdev_priv(ndev);
+               if (lp->rxdma != -1) {
+                       SMC_DMA_FREE(dev, lp->rxdma);
+               }
+               if (lp->txdma != -1) {
+                       SMC_DMA_FREE(dev, lp->txdma);
+               }
+       }
+#endif
+       iounmap((void *)ndev->base_addr);
+       res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+       release_mem_region(res->start, SMC911X_IO_EXTENT);
+
+       free_netdev(ndev);
+       return 0;
+}
+
+static int smc911x_drv_suspend(struct platform_device *dev, pm_message_t state)
+{
+       struct net_device *ndev = platform_get_drvdata(dev);
+       unsigned long ioaddr = ndev->base_addr;
+
+       DBG(SMC_DEBUG_FUNC, "--> %s\n", __FUNCTION__);
+       if (ndev) {
+               if (netif_running(ndev)) {
+                       netif_device_detach(ndev);
+                       smc911x_shutdown(ndev);
+#if POWER_DOWN
+                       /* Set D2 - Energy detect only setting */
+                       SMC_SET_PMT_CTRL(2<<12);
+#endif
+               }
+       }
+       return 0;
+}
+
+static int smc911x_drv_resume(struct platform_device *dev)
+{
+       struct net_device *ndev = platform_get_drvdata(dev);
+
+       DBG(SMC_DEBUG_FUNC, "--> %s\n", __FUNCTION__);
+       if (ndev) {
+               struct smc911x_local *lp = netdev_priv(ndev);
+
+               if (netif_running(ndev)) {
+                       smc911x_reset(ndev);
+                       smc911x_enable(ndev);
+                       if (lp->phy_type != 0)
+                               smc911x_phy_configure(ndev);
+                       netif_device_attach(ndev);
+               }
+       }
+       return 0;
+}
+
+static struct platform_driver smc911x_driver = {
+       .probe           = smc911x_drv_probe,
+       .remove  = smc911x_drv_remove,
+       .suspend         = smc911x_drv_suspend,
+       .resume  = smc911x_drv_resume,
+       .driver  = {
+               .name    = CARDNAME,
+       },
+};
+
+static int __init smc911x_init(void)
+{
+       return platform_driver_register(&smc911x_driver);
+}
+
+static void __exit smc911x_cleanup(void)
+{
+       platform_driver_unregister(&smc911x_driver);
+}
+
+module_init(smc911x_init);
+module_exit(smc911x_cleanup);
diff --git a/drivers/net/smc911x.h b/drivers/net/smc911x.h
new file mode 100644 (file)
index 0000000..962a710
--- /dev/null
@@ -0,0 +1,835 @@
+/*------------------------------------------------------------------------
+ . smc911x.h - macros for SMSC's LAN911{5,6,7,8} single-chip Ethernet device.
+ .
+ . Copyright (C) 2005 Sensoria Corp.
+ . Derived from the unified SMC91x driver by Nicolas Pitre
+ .
+ . This program is free software; you can redistribute it and/or modify
+ . it under the terms of the GNU General Public License as published by
+ . the Free Software Foundation; either version 2 of the License, or
+ . (at your option) any later version.
+ .
+ . This program is distributed in the hope that it will be useful,
+ . but WITHOUT ANY WARRANTY; without even the implied warranty of
+ . MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ . GNU General Public License for more details.
+ .
+ . You should have received a copy of the GNU General Public License
+ . along with this program; if not, write to the Free Software
+ . Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ .
+ . Information contained in this file was obtained from the LAN9118
+ . manual from SMC.  To get a copy, if you really want one, you can find
+ . information under www.smsc.com.
+ .
+ . Authors
+ .      Dustin McIntire                 <dustin@sensoria.com>
+ .
+ ---------------------------------------------------------------------------*/
+#ifndef _SMC911X_H_
+#define _SMC911X_H_
+
+/*
+ * Use the DMA feature on PXA chips
+ */
+#ifdef CONFIG_ARCH_PXA
+  #define SMC_USE_PXA_DMA      1
+  #define SMC_USE_16BIT                0
+  #define SMC_USE_32BIT                1
+#endif
+
+
+/*
+ * Define the bus width specific IO macros
+ */
+
+#if    SMC_USE_16BIT
+#define SMC_inb(a, r)                   readb((a) + (r))
+#define SMC_inw(a, r)                   readw((a) + (r))
+#define SMC_inl(a, r)                   ((SMC_inw(a, r) & 0xFFFF)+(SMC_inw(a+2, r)<<16))
+#define SMC_outb(v, a, r)               writeb(v, (a) + (r))
+#define SMC_outw(v, a, r)               writew(v, (a) + (r))
+#define SMC_outl(v, a, r)                       \
+       do{                                      \
+                writel(v & 0xFFFF, (a) + (r));  \
+                writel(v >> 16, (a) + (r) + 2); \
+        } while (0)
+#define SMC_insl(a, r, p, l)    readsw((short*)((a) + (r)), p, l*2)
+#define SMC_outsl(a, r, p, l)   writesw((short*)((a) + (r)), p, l*2)
+
+#elif  SMC_USE_32BIT
+#define SMC_inb(a, r)           readb((a) + (r))
+#define SMC_inw(a, r)           readw((a) + (r))
+#define SMC_inl(a, r)           readl((a) + (r))
+#define SMC_outb(v, a, r)       writeb(v, (a) + (r))
+#define SMC_outl(v, a, r)       writel(v, (a) + (r))
+#define SMC_insl(a, r, p, l)    readsl((int*)((a) + (r)), p, l)
+#define SMC_outsl(a, r, p, l)   writesl((int*)((a) + (r)), p, l)
+
+#endif /* SMC_USE_16BIT */
+
+
+
+#if     SMC_USE_PXA_DMA
+#define SMC_USE_DMA
+
+/*
+ * Define the request and free functions
+ * These are unfortunately architecture specific as no generic allocation
+ * mechanism exits
+ */
+#define SMC_DMA_REQUEST(dev, handler) \
+        pxa_request_dma(dev->name, DMA_PRIO_LOW, handler, dev)
+
+#define SMC_DMA_FREE(dev, dma) \
+        pxa_free_dma(dma)
+
+#define SMC_DMA_ACK_IRQ(dev, dma)                                      \
+{                                                                      \
+       if (DCSR(dma) & DCSR_BUSERR) {                                  \
+               printk("%s: DMA %d bus error!\n", dev->name, dma);      \
+       }                                                               \
+       DCSR(dma) = DCSR_STARTINTR|DCSR_ENDINTR|DCSR_BUSERR;            \
+}
+
+/*
+ * Use a DMA for RX and TX packets.
+ */
+#include <linux/dma-mapping.h>
+#include <asm/dma.h>
+#include <asm/arch/pxa-regs.h>
+
+static dma_addr_t rx_dmabuf, tx_dmabuf;
+static int rx_dmalen, tx_dmalen;
+
+#ifdef SMC_insl
+#undef SMC_insl
+#define SMC_insl(a, r, p, l) \
+       smc_pxa_dma_insl(lp->dev, a, lp->physaddr, r, lp->rxdma, p, l)
+
+static inline void
+smc_pxa_dma_insl(struct device *dev, u_long ioaddr, u_long physaddr,
+               int reg, int dma, u_char *buf, int len)
+{
+       /* 64 bit alignment is required for memory to memory DMA */
+       if ((long)buf & 4) {
+               *((u32 *)buf) = SMC_inl(ioaddr, reg);
+               buf += 4;
+               len--;
+       }
+
+       len *= 4;
+       rx_dmabuf = dma_map_single(dev, buf, len, DMA_FROM_DEVICE);
+       rx_dmalen = len;
+       DCSR(dma) = DCSR_NODESC;
+       DTADR(dma) = rx_dmabuf;
+       DSADR(dma) = physaddr + reg;
+       DCMD(dma) = (DCMD_INCTRGADDR | DCMD_BURST32 |
+               DCMD_WIDTH4 | DCMD_ENDIRQEN | (DCMD_LENGTH & rx_dmalen));
+       DCSR(dma) = DCSR_NODESC | DCSR_RUN;
+}
+#endif
+
+#ifdef SMC_insw
+#undef SMC_insw
+#define SMC_insw(a, r, p, l) \
+       smc_pxa_dma_insw(lp->dev, a, lp->physaddr, r, lp->rxdma, p, l)
+
+static inline void
+smc_pxa_dma_insw(struct device *dev, u_long ioaddr, u_long physaddr,
+               int reg, int dma, u_char *buf, int len)
+{
+       /* 64 bit alignment is required for memory to memory DMA */
+       while ((long)buf & 6) {
+               *((u16 *)buf) = SMC_inw(ioaddr, reg);
+               buf += 2;
+               len--;
+       }
+
+       len *= 2;
+       rx_dmabuf = dma_map_single(dev, buf, len, DMA_FROM_DEVICE);
+       rx_dmalen = len;
+       DCSR(dma) = DCSR_NODESC;
+       DTADR(dma) = rx_dmabuf;
+       DSADR(dma) = physaddr + reg;
+       DCMD(dma) = (DCMD_INCTRGADDR | DCMD_BURST32 |
+               DCMD_WIDTH2 | DCMD_ENDIRQEN | (DCMD_LENGTH & rx_dmalen));
+       DCSR(dma) = DCSR_NODESC | DCSR_RUN;
+}
+#endif
+
+#ifdef SMC_outsl
+#undef SMC_outsl
+#define SMC_outsl(a, r, p, l) \
+        smc_pxa_dma_outsl(lp->dev, a, lp->physaddr, r, lp->txdma, p, l)
+
+static inline void
+smc_pxa_dma_outsl(struct device *dev, u_long ioaddr, u_long physaddr,
+               int reg, int dma, u_char *buf, int len)
+{
+       /* 64 bit alignment is required for memory to memory DMA */
+       if ((long)buf & 4) {
+               SMC_outl(*((u32 *)buf), ioaddr, reg);
+               buf += 4;
+               len--;
+       }
+
+       len *= 4;
+       tx_dmabuf = dma_map_single(dev, buf, len, DMA_TO_DEVICE);
+       tx_dmalen = len;
+       DCSR(dma) = DCSR_NODESC;
+       DSADR(dma) = tx_dmabuf;
+       DTADR(dma) = physaddr + reg;
+       DCMD(dma) = (DCMD_INCSRCADDR | DCMD_BURST32 |
+               DCMD_WIDTH4 | DCMD_ENDIRQEN | (DCMD_LENGTH & tx_dmalen));
+       DCSR(dma) = DCSR_NODESC | DCSR_RUN;
+}
+#endif
+
+#ifdef SMC_outsw
+#undef SMC_outsw
+#define SMC_outsw(a, r, p, l) \
+       smc_pxa_dma_outsw(lp->dev, a, lp->physaddr, r, lp->txdma, p, l)
+
+static inline void
+smc_pxa_dma_outsw(struct device *dev, u_long ioaddr, u_long physaddr,
+                 int reg, int dma, u_char *buf, int len)
+{
+       /* 64 bit alignment is required for memory to memory DMA */
+       while ((long)buf & 6) {
+               SMC_outw(*((u16 *)buf), ioaddr, reg);
+               buf += 2;
+               len--;
+       }
+
+       len *= 2;
+       tx_dmabuf = dma_map_single(dev, buf, len, DMA_TO_DEVICE);
+       tx_dmalen = len;
+       DCSR(dma) = DCSR_NODESC;
+       DSADR(dma) = tx_dmabuf;
+       DTADR(dma) = physaddr + reg;
+       DCMD(dma) = (DCMD_INCSRCADDR | DCMD_BURST32 |
+               DCMD_WIDTH2 | DCMD_ENDIRQEN | (DCMD_LENGTH & tx_dmalen));
+       DCSR(dma) = DCSR_NODESC | DCSR_RUN;
+}
+#endif
+
+#endif  /* SMC_USE_PXA_DMA */
+
+
+/* Chip Parameters and Register Definitions */
+
+#define SMC911X_TX_FIFO_LOW_THRESHOLD  (1536*2)
+
+#define SMC911X_IO_EXTENT       0x100
+
+#define SMC911X_EEPROM_LEN      7
+
+/* Below are the register offsets and bit definitions
+ * of the Lan911x memory space
+ */
+#define RX_DATA_FIFO            (0x00)
+
+#define TX_DATA_FIFO            (0x20)
+#define        TX_CMD_A_INT_ON_COMP_           (0x80000000)
+#define        TX_CMD_A_INT_BUF_END_ALGN_      (0x03000000)
+#define        TX_CMD_A_INT_4_BYTE_ALGN_       (0x00000000)
+#define        TX_CMD_A_INT_16_BYTE_ALGN_      (0x01000000)
+#define        TX_CMD_A_INT_32_BYTE_ALGN_      (0x02000000)
+#define        TX_CMD_A_INT_DATA_OFFSET_       (0x001F0000)
+#define        TX_CMD_A_INT_FIRST_SEG_         (0x00002000)
+#define        TX_CMD_A_INT_LAST_SEG_          (0x00001000)
+#define        TX_CMD_A_BUF_SIZE_              (0x000007FF)
+#define        TX_CMD_B_PKT_TAG_               (0xFFFF0000)
+#define        TX_CMD_B_ADD_CRC_DISABLE_       (0x00002000)
+#define        TX_CMD_B_DISABLE_PADDING_       (0x00001000)
+#define        TX_CMD_B_PKT_BYTE_LENGTH_       (0x000007FF)
+
+#define RX_STATUS_FIFO         (0x40)
+#define        RX_STS_PKT_LEN_                 (0x3FFF0000)
+#define        RX_STS_ES_                      (0x00008000)
+#define        RX_STS_BCST_                    (0x00002000)
+#define        RX_STS_LEN_ERR_                 (0x00001000)
+#define        RX_STS_RUNT_ERR_                (0x00000800)
+#define        RX_STS_MCAST_                   (0x00000400)
+#define        RX_STS_TOO_LONG_                (0x00000080)
+#define        RX_STS_COLL_                    (0x00000040)
+#define        RX_STS_ETH_TYPE_                (0x00000020)
+#define        RX_STS_WDOG_TMT_                (0x00000010)
+#define        RX_STS_MII_ERR_                 (0x00000008)
+#define        RX_STS_DRIBBLING_               (0x00000004)
+#define        RX_STS_CRC_ERR_                 (0x00000002)
+#define RX_STATUS_FIFO_PEEK    (0x44)
+#define TX_STATUS_FIFO         (0x48)
+#define        TX_STS_TAG_                     (0xFFFF0000)
+#define        TX_STS_ES_                      (0x00008000)
+#define        TX_STS_LOC_                     (0x00000800)
+#define        TX_STS_NO_CARR_                 (0x00000400)
+#define        TX_STS_LATE_COLL_               (0x00000200)
+#define        TX_STS_MANY_COLL_               (0x00000100)
+#define        TX_STS_COLL_CNT_                (0x00000078)
+#define        TX_STS_MANY_DEFER_              (0x00000004)
+#define        TX_STS_UNDERRUN_                (0x00000002)
+#define        TX_STS_DEFERRED_                (0x00000001)
+#define TX_STATUS_FIFO_PEEK    (0x4C)
+#define ID_REV                 (0x50)
+#define        ID_REV_CHIP_ID_                 (0xFFFF0000)  /* RO */
+#define        ID_REV_REV_ID_                  (0x0000FFFF)  /* RO */
+
+#define INT_CFG                        (0x54)
+#define        INT_CFG_INT_DEAS_               (0xFF000000)  /* R/W */
+#define        INT_CFG_INT_DEAS_CLR_           (0x00004000)
+#define        INT_CFG_INT_DEAS_STS_           (0x00002000)
+#define        INT_CFG_IRQ_INT_                (0x00001000)  /* RO */
+#define        INT_CFG_IRQ_EN_                 (0x00000100)  /* R/W */
+#define        INT_CFG_IRQ_POL_                (0x00000010)  /* R/W Not Affected by SW Reset */
+#define        INT_CFG_IRQ_TYPE_               (0x00000001)  /* R/W Not Affected by SW Reset */
+
+#define INT_STS                        (0x58)
+#define        INT_STS_SW_INT_                 (0x80000000)  /* R/WC */
+#define        INT_STS_TXSTOP_INT_             (0x02000000)  /* R/WC */
+#define        INT_STS_RXSTOP_INT_             (0x01000000)  /* R/WC */
+#define        INT_STS_RXDFH_INT_              (0x00800000)  /* R/WC */
+#define        INT_STS_RXDF_INT_               (0x00400000)  /* R/WC */
+#define        INT_STS_TX_IOC_                 (0x00200000)  /* R/WC */
+#define        INT_STS_RXD_INT_                (0x00100000)  /* R/WC */
+#define        INT_STS_GPT_INT_                (0x00080000)  /* R/WC */
+#define        INT_STS_PHY_INT_                (0x00040000)  /* RO */
+#define        INT_STS_PME_INT_                (0x00020000)  /* R/WC */
+#define        INT_STS_TXSO_                   (0x00010000)  /* R/WC */
+#define        INT_STS_RWT_                    (0x00008000)  /* R/WC */
+#define        INT_STS_RXE_                    (0x00004000)  /* R/WC */
+#define        INT_STS_TXE_                    (0x00002000)  /* R/WC */
+//#define      INT_STS_ERX_            (0x00001000)  /* R/WC */
+#define        INT_STS_TDFU_                   (0x00000800)  /* R/WC */
+#define        INT_STS_TDFO_                   (0x00000400)  /* R/WC */
+#define        INT_STS_TDFA_                   (0x00000200)  /* R/WC */
+#define        INT_STS_TSFF_                   (0x00000100)  /* R/WC */
+#define        INT_STS_TSFL_                   (0x00000080)  /* R/WC */
+//#define      INT_STS_RXDF_           (0x00000040)  /* R/WC */
+#define        INT_STS_RDFO_                   (0x00000040)  /* R/WC */
+#define        INT_STS_RDFL_                   (0x00000020)  /* R/WC */
+#define        INT_STS_RSFF_                   (0x00000010)  /* R/WC */
+#define        INT_STS_RSFL_                   (0x00000008)  /* R/WC */
+#define        INT_STS_GPIO2_INT_              (0x00000004)  /* R/WC */
+#define        INT_STS_GPIO1_INT_              (0x00000002)  /* R/WC */
+#define        INT_STS_GPIO0_INT_              (0x00000001)  /* R/WC */
+
+#define INT_EN                 (0x5C)
+#define        INT_EN_SW_INT_EN_               (0x80000000)  /* R/W */
+#define        INT_EN_TXSTOP_INT_EN_           (0x02000000)  /* R/W */
+#define        INT_EN_RXSTOP_INT_EN_           (0x01000000)  /* R/W */
+#define        INT_EN_RXDFH_INT_EN_            (0x00800000)  /* R/W */
+//#define      INT_EN_RXDF_INT_EN_             (0x00400000)  /* R/W */
+#define        INT_EN_TIOC_INT_EN_             (0x00200000)  /* R/W */
+#define        INT_EN_RXD_INT_EN_              (0x00100000)  /* R/W */
+#define        INT_EN_GPT_INT_EN_              (0x00080000)  /* R/W */
+#define        INT_EN_PHY_INT_EN_              (0x00040000)  /* R/W */
+#define        INT_EN_PME_INT_EN_              (0x00020000)  /* R/W */
+#define        INT_EN_TXSO_EN_                 (0x00010000)  /* R/W */
+#define        INT_EN_RWT_EN_                  (0x00008000)  /* R/W */
+#define        INT_EN_RXE_EN_                  (0x00004000)  /* R/W */
+#define        INT_EN_TXE_EN_                  (0x00002000)  /* R/W */
+//#define      INT_EN_ERX_EN_                  (0x00001000)  /* R/W */
+#define        INT_EN_TDFU_EN_                 (0x00000800)  /* R/W */
+#define        INT_EN_TDFO_EN_                 (0x00000400)  /* R/W */
+#define        INT_EN_TDFA_EN_                 (0x00000200)  /* R/W */
+#define        INT_EN_TSFF_EN_                 (0x00000100)  /* R/W */
+#define        INT_EN_TSFL_EN_                 (0x00000080)  /* R/W */
+//#define      INT_EN_RXDF_EN_                 (0x00000040)  /* R/W */
+#define        INT_EN_RDFO_EN_                 (0x00000040)  /* R/W */
+#define        INT_EN_RDFL_EN_                 (0x00000020)  /* R/W */
+#define        INT_EN_RSFF_EN_                 (0x00000010)  /* R/W */
+#define        INT_EN_RSFL_EN_                 (0x00000008)  /* R/W */
+#define        INT_EN_GPIO2_INT_               (0x00000004)  /* R/W */
+#define        INT_EN_GPIO1_INT_               (0x00000002)  /* R/W */
+#define        INT_EN_GPIO0_INT_               (0x00000001)  /* R/W */
+
+#define BYTE_TEST              (0x64)
+#define FIFO_INT               (0x68)
+#define        FIFO_INT_TX_AVAIL_LEVEL_        (0xFF000000)  /* R/W */
+#define        FIFO_INT_TX_STS_LEVEL_          (0x00FF0000)  /* R/W */
+#define        FIFO_INT_RX_AVAIL_LEVEL_        (0x0000FF00)  /* R/W */
+#define        FIFO_INT_RX_STS_LEVEL_          (0x000000FF)  /* R/W */
+
+#define RX_CFG                 (0x6C)
+#define        RX_CFG_RX_END_ALGN_             (0xC0000000)  /* R/W */
+#define                RX_CFG_RX_END_ALGN4_            (0x00000000)  /* R/W */
+#define                RX_CFG_RX_END_ALGN16_           (0x40000000)  /* R/W */
+#define                RX_CFG_RX_END_ALGN32_           (0x80000000)  /* R/W */
+#define        RX_CFG_RX_DMA_CNT_              (0x0FFF0000)  /* R/W */
+#define        RX_CFG_RX_DUMP_                 (0x00008000)  /* R/W */
+#define        RX_CFG_RXDOFF_                  (0x00001F00)  /* R/W */
+//#define      RX_CFG_RXBAD_                   (0x00000001)  /* R/W */
+
+#define TX_CFG                 (0x70)
+//#define      TX_CFG_TX_DMA_LVL_              (0xE0000000)     /* R/W */
+//#define      TX_CFG_TX_DMA_CNT_              (0x0FFF0000)     /* R/W Self Clearing */
+#define        TX_CFG_TXS_DUMP_                (0x00008000)  /* Self Clearing */
+#define        TX_CFG_TXD_DUMP_                (0x00004000)  /* Self Clearing */
+#define        TX_CFG_TXSAO_                   (0x00000004)  /* R/W */
+#define        TX_CFG_TX_ON_                   (0x00000002)  /* R/W */
+#define        TX_CFG_STOP_TX_                 (0x00000001)  /* Self Clearing */
+
+#define HW_CFG                 (0x74)
+#define        HW_CFG_TTM_                     (0x00200000)  /* R/W */
+#define        HW_CFG_SF_                      (0x00100000)  /* R/W */
+#define        HW_CFG_TX_FIF_SZ_               (0x000F0000)  /* R/W */
+#define        HW_CFG_TR_                      (0x00003000)  /* R/W */
+#define        HW_CFG_PHY_CLK_SEL_             (0x00000060)  /* R/W */
+#define                 HW_CFG_PHY_CLK_SEL_INT_PHY_    (0x00000000) /* R/W */
+#define                 HW_CFG_PHY_CLK_SEL_EXT_PHY_    (0x00000020) /* R/W */
+#define                 HW_CFG_PHY_CLK_SEL_CLK_DIS_    (0x00000040) /* R/W */
+#define        HW_CFG_SMI_SEL_                 (0x00000010)  /* R/W */
+#define        HW_CFG_EXT_PHY_DET_             (0x00000008)  /* RO */
+#define        HW_CFG_EXT_PHY_EN_              (0x00000004)  /* R/W */
+#define        HW_CFG_32_16_BIT_MODE_          (0x00000004)  /* RO */
+#define        HW_CFG_SRST_TO_                 (0x00000002)  /* RO */
+#define        HW_CFG_SRST_                    (0x00000001)  /* Self Clearing */
+
+#define RX_DP_CTRL             (0x78)
+#define        RX_DP_CTRL_RX_FFWD_             (0x80000000)  /* R/W */
+#define        RX_DP_CTRL_FFWD_BUSY_           (0x80000000)  /* RO */
+
+#define RX_FIFO_INF            (0x7C)
+#define         RX_FIFO_INF_RXSUSED_           (0x00FF0000)  /* RO */
+#define         RX_FIFO_INF_RXDUSED_           (0x0000FFFF)  /* RO */
+
+#define TX_FIFO_INF            (0x80)
+#define        TX_FIFO_INF_TSUSED_             (0x00FF0000)  /* RO */
+#define        TX_FIFO_INF_TDFREE_             (0x0000FFFF)  /* RO */
+
+#define PMT_CTRL               (0x84)
+#define        PMT_CTRL_PM_MODE_               (0x00003000)  /* Self Clearing */
+#define        PMT_CTRL_PHY_RST_               (0x00000400)  /* Self Clearing */
+#define        PMT_CTRL_WOL_EN_                (0x00000200)  /* R/W */
+#define        PMT_CTRL_ED_EN_                 (0x00000100)  /* R/W */
+#define        PMT_CTRL_PME_TYPE_              (0x00000040)  /* R/W Not Affected by SW Reset */
+#define        PMT_CTRL_WUPS_                  (0x00000030)  /* R/WC */
+#define                PMT_CTRL_WUPS_NOWAKE_           (0x00000000)  /* R/WC */
+#define                PMT_CTRL_WUPS_ED_               (0x00000010)  /* R/WC */
+#define                PMT_CTRL_WUPS_WOL_              (0x00000020)  /* R/WC */
+#define                PMT_CTRL_WUPS_MULTI_            (0x00000030)  /* R/WC */
+#define        PMT_CTRL_PME_IND_               (0x00000008)  /* R/W */
+#define        PMT_CTRL_PME_POL_               (0x00000004)  /* R/W */
+#define        PMT_CTRL_PME_EN_                (0x00000002)  /* R/W Not Affected by SW Reset */
+#define        PMT_CTRL_READY_                 (0x00000001)  /* RO */
+
+#define GPIO_CFG               (0x88)
+#define        GPIO_CFG_LED3_EN_               (0x40000000)  /* R/W */
+#define        GPIO_CFG_LED2_EN_               (0x20000000)  /* R/W */
+#define        GPIO_CFG_LED1_EN_               (0x10000000)  /* R/W */
+#define        GPIO_CFG_GPIO2_INT_POL_         (0x04000000)  /* R/W */
+#define        GPIO_CFG_GPIO1_INT_POL_         (0x02000000)  /* R/W */
+#define        GPIO_CFG_GPIO0_INT_POL_         (0x01000000)  /* R/W */
+#define        GPIO_CFG_EEPR_EN_               (0x00700000)  /* R/W */
+#define        GPIO_CFG_GPIOBUF2_              (0x00040000)  /* R/W */
+#define        GPIO_CFG_GPIOBUF1_              (0x00020000)  /* R/W */
+#define        GPIO_CFG_GPIOBUF0_              (0x00010000)  /* R/W */
+#define        GPIO_CFG_GPIODIR2_              (0x00000400)  /* R/W */
+#define        GPIO_CFG_GPIODIR1_              (0x00000200)  /* R/W */
+#define        GPIO_CFG_GPIODIR0_              (0x00000100)  /* R/W */
+#define        GPIO_CFG_GPIOD4_                (0x00000010)  /* R/W */
+#define        GPIO_CFG_GPIOD3_                (0x00000008)  /* R/W */
+#define        GPIO_CFG_GPIOD2_                (0x00000004)  /* R/W */
+#define        GPIO_CFG_GPIOD1_                (0x00000002)  /* R/W */
+#define        GPIO_CFG_GPIOD0_                (0x00000001)  /* R/W */
+
+#define GPT_CFG                        (0x8C)
+#define        GPT_CFG_TIMER_EN_               (0x20000000)  /* R/W */
+#define        GPT_CFG_GPT_LOAD_               (0x0000FFFF)  /* R/W */
+
+#define GPT_CNT                        (0x90)
+#define        GPT_CNT_GPT_CNT_                (0x0000FFFF)  /* RO */
+
+#define ENDIAN                 (0x98)
+#define FREE_RUN               (0x9C)
+#define RX_DROP                        (0xA0)
+#define MAC_CSR_CMD            (0xA4)
+#define         MAC_CSR_CMD_CSR_BUSY_          (0x80000000)  /* Self Clearing */
+#define         MAC_CSR_CMD_R_NOT_W_           (0x40000000)  /* R/W */
+#define         MAC_CSR_CMD_CSR_ADDR_          (0x000000FF)  /* R/W */
+
+#define MAC_CSR_DATA           (0xA8)
+#define AFC_CFG                        (0xAC)
+#define                AFC_CFG_AFC_HI_                 (0x00FF0000)  /* R/W */
+#define                AFC_CFG_AFC_LO_                 (0x0000FF00)  /* R/W */
+#define                AFC_CFG_BACK_DUR_               (0x000000F0)  /* R/W */
+#define                AFC_CFG_FCMULT_                 (0x00000008)  /* R/W */
+#define                AFC_CFG_FCBRD_                  (0x00000004)  /* R/W */
+#define                AFC_CFG_FCADD_                  (0x00000002)  /* R/W */
+#define                AFC_CFG_FCANY_                  (0x00000001)  /* R/W */
+
+#define E2P_CMD                        (0xB0)
+#define        E2P_CMD_EPC_BUSY_               (0x80000000)  /* Self Clearing */
+#define        E2P_CMD_EPC_CMD_                        (0x70000000)  /* R/W */
+#define                E2P_CMD_EPC_CMD_READ_           (0x00000000)  /* R/W */
+#define                E2P_CMD_EPC_CMD_EWDS_           (0x10000000)  /* R/W */
+#define                E2P_CMD_EPC_CMD_EWEN_           (0x20000000)  /* R/W */
+#define                E2P_CMD_EPC_CMD_WRITE_          (0x30000000)  /* R/W */
+#define                E2P_CMD_EPC_CMD_WRAL_           (0x40000000)  /* R/W */
+#define                E2P_CMD_EPC_CMD_ERASE_          (0x50000000)  /* R/W */
+#define                E2P_CMD_EPC_CMD_ERAL_           (0x60000000)  /* R/W */
+#define                E2P_CMD_EPC_CMD_RELOAD_         (0x70000000)  /* R/W */
+#define        E2P_CMD_EPC_TIMEOUT_            (0x00000200)  /* RO */
+#define        E2P_CMD_MAC_ADDR_LOADED_        (0x00000100)  /* RO */
+#define        E2P_CMD_EPC_ADDR_               (0x000000FF)  /* R/W */
+
+#define E2P_DATA               (0xB4)
+#define        E2P_DATA_EEPROM_DATA_           (0x000000FF)  /* R/W */
+/* end of LAN register offsets and bit definitions */
+
+/*
+ ****************************************************************************
+ ****************************************************************************
+ * MAC Control and Status Register (Indirect Address)
+ * Offset (through the MAC_CSR CMD and DATA port)
+ ****************************************************************************
+ ****************************************************************************
+ *
+ */
+#define MAC_CR                 (0x01)  /* R/W */
+
+/* MAC_CR - MAC Control Register */
+#define MAC_CR_RXALL_                  (0x80000000)
+// TODO: delete this bit? It is not described in the data sheet.
+#define MAC_CR_HBDIS_                  (0x10000000)
+#define MAC_CR_RCVOWN_                 (0x00800000)
+#define MAC_CR_LOOPBK_                 (0x00200000)
+#define MAC_CR_FDPX_                   (0x00100000)
+#define MAC_CR_MCPAS_                  (0x00080000)
+#define MAC_CR_PRMS_                   (0x00040000)
+#define MAC_CR_INVFILT_                        (0x00020000)
+#define MAC_CR_PASSBAD_                        (0x00010000)
+#define MAC_CR_HFILT_                  (0x00008000)
+#define MAC_CR_HPFILT_                 (0x00002000)
+#define MAC_CR_LCOLL_                  (0x00001000)
+#define MAC_CR_BCAST_                  (0x00000800)
+#define MAC_CR_DISRTY_                 (0x00000400)
+#define MAC_CR_PADSTR_                 (0x00000100)
+#define MAC_CR_BOLMT_MASK_             (0x000000C0)
+#define MAC_CR_DFCHK_                  (0x00000020)
+#define MAC_CR_TXEN_                   (0x00000008)
+#define MAC_CR_RXEN_                   (0x00000004)
+
+#define ADDRH                  (0x02)    /* R/W mask 0x0000FFFFUL */
+#define ADDRL                  (0x03)    /* R/W mask 0xFFFFFFFFUL */
+#define HASHH                  (0x04)    /* R/W */
+#define HASHL                  (0x05)    /* R/W */
+
+#define MII_ACC                        (0x06)    /* R/W */
+#define MII_ACC_PHY_ADDR_              (0x0000F800)
+#define MII_ACC_MIIRINDA_              (0x000007C0)
+#define MII_ACC_MII_WRITE_             (0x00000002)
+#define MII_ACC_MII_BUSY_              (0x00000001)
+
+#define MII_DATA               (0x07)    /* R/W mask 0x0000FFFFUL */
+
+#define FLOW                   (0x08)    /* R/W */
+#define FLOW_FCPT_                     (0xFFFF0000)
+#define FLOW_FCPASS_                   (0x00000004)
+#define FLOW_FCEN_                     (0x00000002)
+#define FLOW_FCBSY_                    (0x00000001)
+
+#define VLAN1                  (0x09)    /* R/W mask 0x0000FFFFUL */
+#define VLAN1_VTI1_                    (0x0000ffff)
+
+#define VLAN2                  (0x0A)    /* R/W mask 0x0000FFFFUL */
+#define VLAN2_VTI2_                    (0x0000ffff)
+
+#define WUFF                   (0x0B)    /* WO */
+
+#define WUCSR                  (0x0C)    /* R/W */
+#define WUCSR_GUE_                     (0x00000200)
+#define WUCSR_WUFR_                    (0x00000040)
+#define WUCSR_MPR_                     (0x00000020)
+#define WUCSR_WAKE_EN_                 (0x00000004)
+#define WUCSR_MPEN_                    (0x00000002)
+
+/*
+ ****************************************************************************
+ * Chip Specific MII Defines
+ ****************************************************************************
+ *
+ * Phy register offsets and bit definitions
+ *
+ */
+
+#define PHY_MODE_CTRL_STS      ((u32)17)       /* Mode Control/Status Register */
+//#define MODE_CTRL_STS_FASTRIP_         ((u16)0x4000)
+#define MODE_CTRL_STS_EDPWRDOWN_        ((u16)0x2000)
+//#define MODE_CTRL_STS_LOWSQEN_          ((u16)0x0800)
+//#define MODE_CTRL_STS_MDPREBP_          ((u16)0x0400)
+//#define MODE_CTRL_STS_FARLOOPBACK_  ((u16)0x0200)
+//#define MODE_CTRL_STS_FASTEST_          ((u16)0x0100)
+//#define MODE_CTRL_STS_REFCLKEN_         ((u16)0x0010)
+//#define MODE_CTRL_STS_PHYADBP_          ((u16)0x0008)
+//#define MODE_CTRL_STS_FORCE_G_LINK_ ((u16)0x0004)
+#define MODE_CTRL_STS_ENERGYON_                ((u16)0x0002)
+
+#define PHY_INT_SRC                    ((u32)29)
+#define PHY_INT_SRC_ENERGY_ON_                 ((u16)0x0080)
+#define PHY_INT_SRC_ANEG_COMP_                 ((u16)0x0040)
+#define PHY_INT_SRC_REMOTE_FAULT_              ((u16)0x0020)
+#define PHY_INT_SRC_LINK_DOWN_                 ((u16)0x0010)
+#define PHY_INT_SRC_ANEG_LP_ACK_               ((u16)0x0008)
+#define PHY_INT_SRC_PAR_DET_FAULT_             ((u16)0x0004)
+#define PHY_INT_SRC_ANEG_PGRX_                 ((u16)0x0002)
+
+#define PHY_INT_MASK                   ((u32)30)
+#define PHY_INT_MASK_ENERGY_ON_                        ((u16)0x0080)
+#define PHY_INT_MASK_ANEG_COMP_                        ((u16)0x0040)
+#define PHY_INT_MASK_REMOTE_FAULT_             ((u16)0x0020)
+#define PHY_INT_MASK_LINK_DOWN_                        ((u16)0x0010)
+#define PHY_INT_MASK_ANEG_LP_ACK_              ((u16)0x0008)
+#define PHY_INT_MASK_PAR_DET_FAULT_            ((u16)0x0004)
+#define PHY_INT_MASK_ANEG_PGRX_                        ((u16)0x0002)
+
+#define PHY_SPECIAL                    ((u32)31)
+#define PHY_SPECIAL_ANEG_DONE_                 ((u16)0x1000)
+#define PHY_SPECIAL_RES_                       ((u16)0x0040)
+#define PHY_SPECIAL_RES_MASK_                  ((u16)0x0FE1)
+#define PHY_SPECIAL_SPD_                       ((u16)0x001C)
+#define PHY_SPECIAL_SPD_10HALF_                        ((u16)0x0004)
+#define PHY_SPECIAL_SPD_10FULL_                        ((u16)0x0014)
+#define PHY_SPECIAL_SPD_100HALF_               ((u16)0x0008)
+#define PHY_SPECIAL_SPD_100FULL_               ((u16)0x0018)
+
+#define LAN911X_INTERNAL_PHY_ID                (0x0007C000)
+
+/* Chip ID values */
+#define CHIP_9115      0x115
+#define CHIP_9116      0x116
+#define CHIP_9117      0x117
+#define CHIP_9118      0x118
+
+struct chip_id {
+       u16 id;
+       char *name;
+};
+
+static const struct chip_id chip_ids[] =  {
+       { CHIP_9115, "LAN9115" },
+       { CHIP_9116, "LAN9116" },
+       { CHIP_9117, "LAN9117" },
+       { CHIP_9118, "LAN9118" },
+       { 0, NULL },
+};
+
+#define IS_REV_A(x)    ((x & 0xFFFF)==0)
+
+/*
+ * Macros to abstract register access according to the data bus
+ * capabilities.  Please use those and not the in/out primitives.
+ */
+/* FIFO read/write macros */
+#define SMC_PUSH_DATA(p, l)    SMC_outsl( ioaddr, TX_DATA_FIFO, p, (l) >> 2 )
+#define SMC_PULL_DATA(p, l)    SMC_insl ( ioaddr, RX_DATA_FIFO, p, (l) >> 2 )
+#define SMC_SET_TX_FIFO(x)     SMC_outl( x, ioaddr, TX_DATA_FIFO )
+#define SMC_GET_RX_FIFO()      SMC_inl( ioaddr, RX_DATA_FIFO )
+
+
+/* I/O mapped register read/write macros */
+#define SMC_GET_TX_STS_FIFO()          SMC_inl( ioaddr, TX_STATUS_FIFO )
+#define SMC_GET_RX_STS_FIFO()          SMC_inl( ioaddr, RX_STATUS_FIFO )
+#define SMC_GET_RX_STS_FIFO_PEEK()     SMC_inl( ioaddr, RX_STATUS_FIFO_PEEK )
+#define SMC_GET_PN()                   (SMC_inl( ioaddr, ID_REV ) >> 16)
+#define SMC_GET_REV()                  (SMC_inl( ioaddr, ID_REV ) & 0xFFFF)
+#define SMC_GET_IRQ_CFG()              SMC_inl( ioaddr, INT_CFG )
+#define SMC_SET_IRQ_CFG(x)             SMC_outl( x, ioaddr, INT_CFG )
+#define SMC_GET_INT()                  SMC_inl( ioaddr, INT_STS )
+#define SMC_ACK_INT(x)                 SMC_outl( x, ioaddr, INT_STS )
+#define SMC_GET_INT_EN()               SMC_inl( ioaddr, INT_EN )
+#define SMC_SET_INT_EN(x)              SMC_outl( x, ioaddr, INT_EN )
+#define SMC_GET_BYTE_TEST()            SMC_inl( ioaddr, BYTE_TEST )
+#define SMC_SET_BYTE_TEST(x)           SMC_outl( x, ioaddr, BYTE_TEST )
+#define SMC_GET_FIFO_INT()             SMC_inl( ioaddr, FIFO_INT )
+#define SMC_SET_FIFO_INT(x)            SMC_outl( x, ioaddr, FIFO_INT )
+#define SMC_SET_FIFO_TDA(x)                                    \
+       do {                                                    \
+               unsigned long __flags;                          \
+               int __mask;                                     \
+               local_irq_save(__flags);                        \
+               __mask = SMC_GET_FIFO_INT() & ~(0xFF<<24);      \
+               SMC_SET_FIFO_INT( __mask | (x)<<24 );           \
+               local_irq_restore(__flags);                     \
+       } while (0)
+#define SMC_SET_FIFO_TSL(x)                                    \
+       do {                                                    \
+               unsigned long __flags;                          \
+               int __mask;                                     \
+               local_irq_save(__flags);                        \
+               __mask = SMC_GET_FIFO_INT() & ~(0xFF<<16);      \
+               SMC_SET_FIFO_INT( __mask | (((x) & 0xFF)<<16)); \
+               local_irq_restore(__flags);                     \
+       } while (0)
+#define SMC_SET_FIFO_RSA(x)                                    \
+       do {                                                    \
+               unsigned long __flags;                          \
+               int __mask;                                     \
+               local_irq_save(__flags);                        \
+               __mask = SMC_GET_FIFO_INT() & ~(0xFF<<8);       \
+               SMC_SET_FIFO_INT( __mask | (((x) & 0xFF)<<8));  \
+               local_irq_restore(__flags);                     \
+       } while (0)
+#define SMC_SET_FIFO_RSL(x)                                    \
+       do {                                                    \
+               unsigned long __flags;                          \
+               int __mask;                                     \
+               local_irq_save(__flags);                        \
+               __mask = SMC_GET_FIFO_INT() & ~0xFF;            \
+               SMC_SET_FIFO_INT( __mask | ((x) & 0xFF));       \
+               local_irq_restore(__flags);                     \
+       } while (0)
+#define SMC_GET_RX_CFG()               SMC_inl( ioaddr, RX_CFG )
+#define SMC_SET_RX_CFG(x)              SMC_outl( x, ioaddr, RX_CFG )
+#define SMC_GET_TX_CFG()               SMC_inl( ioaddr, TX_CFG )
+#define SMC_SET_TX_CFG(x)              SMC_outl( x, ioaddr, TX_CFG )
+#define SMC_GET_HW_CFG()               SMC_inl( ioaddr, HW_CFG )
+#define SMC_SET_HW_CFG(x)              SMC_outl( x, ioaddr, HW_CFG )
+#define SMC_GET_RX_DP_CTRL()           SMC_inl( ioaddr, RX_DP_CTRL )
+#define SMC_SET_RX_DP_CTRL(x)          SMC_outl( x, ioaddr, RX_DP_CTRL )
+#define SMC_GET_PMT_CTRL()             SMC_inl( ioaddr, PMT_CTRL )
+#define SMC_SET_PMT_CTRL(x)            SMC_outl( x, ioaddr, PMT_CTRL )
+#define SMC_GET_GPIO_CFG()             SMC_inl( ioaddr, GPIO_CFG )
+#define SMC_SET_GPIO_CFG(x)            SMC_outl( x, ioaddr, GPIO_CFG )
+#define SMC_GET_RX_FIFO_INF()          SMC_inl(