Merge branch 'x86/amd-iommu' into x86/urgent
authorIngo Molnar <mingo@elte.hu>
Fri, 15 Aug 2008 11:57:32 +0000 (13:57 +0200)
committerIngo Molnar <mingo@elte.hu>
Fri, 15 Aug 2008 11:57:32 +0000 (13:57 +0200)
318 files changed:
Documentation/devices.txt
Documentation/ioctl-number.txt
Documentation/usb/auerswald.txt [deleted file]
Documentation/usb/power-management.txt
MAINTAINERS
arch/arm/mach-omap2/usb-tusb6010.c
arch/h8300/include/asm/Kbuild [moved from include/asm-h8300/Kbuild with 100% similarity]
arch/h8300/include/asm/a.out.h [moved from include/asm-h8300/a.out.h with 100% similarity]
arch/h8300/include/asm/atomic.h [moved from include/asm-h8300/atomic.h with 100% similarity]
arch/h8300/include/asm/auxvec.h [moved from include/asm-h8300/auxvec.h with 100% similarity]
arch/h8300/include/asm/bitops.h [moved from include/asm-h8300/bitops.h with 100% similarity]
arch/h8300/include/asm/bootinfo.h [moved from include/asm-h8300/bootinfo.h with 100% similarity]
arch/h8300/include/asm/bug.h [moved from include/asm-h8300/bug.h with 100% similarity]
arch/h8300/include/asm/bugs.h [moved from include/asm-h8300/bugs.h with 100% similarity]
arch/h8300/include/asm/byteorder.h [moved from include/asm-h8300/byteorder.h with 100% similarity]
arch/h8300/include/asm/cache.h [moved from include/asm-h8300/cache.h with 100% similarity]
arch/h8300/include/asm/cachectl.h [moved from include/asm-h8300/cachectl.h with 100% similarity]
arch/h8300/include/asm/cacheflush.h [moved from include/asm-h8300/cacheflush.h with 100% similarity]
arch/h8300/include/asm/checksum.h [moved from include/asm-h8300/checksum.h with 100% similarity]
arch/h8300/include/asm/cputime.h [moved from include/asm-h8300/cputime.h with 100% similarity]
arch/h8300/include/asm/current.h [moved from include/asm-h8300/current.h with 100% similarity]
arch/h8300/include/asm/dbg.h [moved from include/asm-h8300/dbg.h with 100% similarity]
arch/h8300/include/asm/delay.h [moved from include/asm-h8300/delay.h with 100% similarity]
arch/h8300/include/asm/device.h [moved from include/asm-h8300/device.h with 100% similarity]
arch/h8300/include/asm/div64.h [moved from include/asm-h8300/div64.h with 100% similarity]
arch/h8300/include/asm/dma.h [moved from include/asm-h8300/dma.h with 100% similarity]
arch/h8300/include/asm/elf.h [moved from include/asm-h8300/elf.h with 100% similarity]
arch/h8300/include/asm/emergency-restart.h [moved from include/asm-h8300/emergency-restart.h with 100% similarity]
arch/h8300/include/asm/errno.h [moved from include/asm-h8300/errno.h with 100% similarity]
arch/h8300/include/asm/fb.h [moved from include/asm-h8300/fb.h with 100% similarity]
arch/h8300/include/asm/fcntl.h [moved from include/asm-h8300/fcntl.h with 100% similarity]
arch/h8300/include/asm/flat.h [moved from include/asm-h8300/flat.h with 100% similarity]
arch/h8300/include/asm/fpu.h [moved from include/asm-h8300/fpu.h with 100% similarity]
arch/h8300/include/asm/futex.h [moved from include/asm-h8300/futex.h with 100% similarity]
arch/h8300/include/asm/gpio.h [moved from include/asm-h8300/gpio.h with 100% similarity]
arch/h8300/include/asm/hardirq.h [moved from include/asm-h8300/hardirq.h with 100% similarity]
arch/h8300/include/asm/hw_irq.h [moved from include/asm-h8300/hw_irq.h with 100% similarity]
arch/h8300/include/asm/io.h [moved from include/asm-h8300/io.h with 100% similarity]
arch/h8300/include/asm/ioctl.h [moved from include/asm-h8300/ioctl.h with 100% similarity]
arch/h8300/include/asm/ioctls.h [moved from include/asm-h8300/ioctls.h with 100% similarity]
arch/h8300/include/asm/ipcbuf.h [moved from include/asm-h8300/ipcbuf.h with 100% similarity]
arch/h8300/include/asm/irq.h [moved from include/asm-h8300/irq.h with 100% similarity]
arch/h8300/include/asm/irq_regs.h [moved from include/asm-h8300/irq_regs.h with 100% similarity]
arch/h8300/include/asm/kdebug.h [moved from include/asm-h8300/kdebug.h with 100% similarity]
arch/h8300/include/asm/kmap_types.h [moved from include/asm-h8300/kmap_types.h with 100% similarity]
arch/h8300/include/asm/linkage.h [moved from include/asm-h8300/linkage.h with 100% similarity]
arch/h8300/include/asm/local.h [moved from include/asm-h8300/local.h with 100% similarity]
arch/h8300/include/asm/mc146818rtc.h [moved from include/asm-h8300/mc146818rtc.h with 100% similarity]
arch/h8300/include/asm/md.h [moved from include/asm-h8300/md.h with 100% similarity]
arch/h8300/include/asm/mman.h [moved from include/asm-h8300/mman.h with 100% similarity]
arch/h8300/include/asm/mmu.h [moved from include/asm-h8300/mmu.h with 100% similarity]
arch/h8300/include/asm/mmu_context.h [moved from include/asm-h8300/mmu_context.h with 100% similarity]
arch/h8300/include/asm/module.h [moved from include/asm-h8300/module.h with 100% similarity]
arch/h8300/include/asm/msgbuf.h [moved from include/asm-h8300/msgbuf.h with 100% similarity]
arch/h8300/include/asm/mutex.h [moved from include/asm-h8300/mutex.h with 100% similarity]
arch/h8300/include/asm/page.h [moved from include/asm-h8300/page.h with 100% similarity]
arch/h8300/include/asm/page_offset.h [moved from include/asm-h8300/page_offset.h with 100% similarity]
arch/h8300/include/asm/param.h [moved from include/asm-h8300/param.h with 100% similarity]
arch/h8300/include/asm/pci.h [moved from include/asm-h8300/pci.h with 100% similarity]
arch/h8300/include/asm/percpu.h [moved from include/asm-h8300/percpu.h with 100% similarity]
arch/h8300/include/asm/pgalloc.h [moved from include/asm-h8300/pgalloc.h with 100% similarity]
arch/h8300/include/asm/pgtable.h [moved from include/asm-h8300/pgtable.h with 100% similarity]
arch/h8300/include/asm/poll.h [moved from include/asm-h8300/poll.h with 100% similarity]
arch/h8300/include/asm/posix_types.h [moved from include/asm-h8300/posix_types.h with 100% similarity]
arch/h8300/include/asm/processor.h [moved from include/asm-h8300/processor.h with 100% similarity]
arch/h8300/include/asm/ptrace.h [moved from include/asm-h8300/ptrace.h with 100% similarity]
arch/h8300/include/asm/regs267x.h [moved from include/asm-h8300/regs267x.h with 100% similarity]
arch/h8300/include/asm/regs306x.h [moved from include/asm-h8300/regs306x.h with 100% similarity]
arch/h8300/include/asm/resource.h [moved from include/asm-h8300/resource.h with 100% similarity]
arch/h8300/include/asm/scatterlist.h [moved from include/asm-h8300/scatterlist.h with 100% similarity]
arch/h8300/include/asm/sections.h [moved from include/asm-h8300/sections.h with 100% similarity]
arch/h8300/include/asm/segment.h [moved from include/asm-h8300/segment.h with 100% similarity]
arch/h8300/include/asm/sembuf.h [moved from include/asm-h8300/sembuf.h with 100% similarity]
arch/h8300/include/asm/setup.h [moved from include/asm-h8300/setup.h with 100% similarity]
arch/h8300/include/asm/sh_bios.h [moved from include/asm-h8300/sh_bios.h with 100% similarity]
arch/h8300/include/asm/shm.h [moved from include/asm-h8300/shm.h with 100% similarity]
arch/h8300/include/asm/shmbuf.h [moved from include/asm-h8300/shmbuf.h with 100% similarity]
arch/h8300/include/asm/shmparam.h [moved from include/asm-h8300/shmparam.h with 100% similarity]
arch/h8300/include/asm/sigcontext.h [moved from include/asm-h8300/sigcontext.h with 100% similarity]
arch/h8300/include/asm/siginfo.h [moved from include/asm-h8300/siginfo.h with 100% similarity]
arch/h8300/include/asm/signal.h [moved from include/asm-h8300/signal.h with 100% similarity]
arch/h8300/include/asm/smp.h [moved from include/asm-h8300/smp.h with 100% similarity]
arch/h8300/include/asm/socket.h [moved from include/asm-h8300/socket.h with 100% similarity]
arch/h8300/include/asm/sockios.h [moved from include/asm-h8300/sockios.h with 100% similarity]
arch/h8300/include/asm/spinlock.h [moved from include/asm-h8300/spinlock.h with 100% similarity]
arch/h8300/include/asm/stat.h [moved from include/asm-h8300/stat.h with 100% similarity]
arch/h8300/include/asm/statfs.h [moved from include/asm-h8300/statfs.h with 100% similarity]
arch/h8300/include/asm/string.h [moved from include/asm-h8300/string.h with 100% similarity]
arch/h8300/include/asm/system.h [moved from include/asm-h8300/system.h with 100% similarity]
arch/h8300/include/asm/target_time.h [moved from include/asm-h8300/target_time.h with 100% similarity]
arch/h8300/include/asm/termbits.h [moved from include/asm-h8300/termbits.h with 100% similarity]
arch/h8300/include/asm/termios.h [moved from include/asm-h8300/termios.h with 100% similarity]
arch/h8300/include/asm/thread_info.h [moved from include/asm-h8300/thread_info.h with 100% similarity]
arch/h8300/include/asm/timex.h [moved from include/asm-h8300/timex.h with 100% similarity]
arch/h8300/include/asm/tlb.h [moved from include/asm-h8300/tlb.h with 100% similarity]
arch/h8300/include/asm/tlbflush.h [moved from include/asm-h8300/tlbflush.h with 100% similarity]
arch/h8300/include/asm/topology.h [moved from include/asm-h8300/topology.h with 100% similarity]
arch/h8300/include/asm/traps.h [moved from include/asm-h8300/traps.h with 100% similarity]
arch/h8300/include/asm/types.h [moved from include/asm-h8300/types.h with 100% similarity]
arch/h8300/include/asm/uaccess.h [moved from include/asm-h8300/uaccess.h with 100% similarity]
arch/h8300/include/asm/ucontext.h [moved from include/asm-h8300/ucontext.h with 100% similarity]
arch/h8300/include/asm/unaligned.h [moved from include/asm-h8300/unaligned.h with 100% similarity]
arch/h8300/include/asm/unistd.h [moved from include/asm-h8300/unistd.h with 100% similarity]
arch/h8300/include/asm/user.h [moved from include/asm-h8300/user.h with 100% similarity]
arch/h8300/include/asm/virtconvert.h [moved from include/asm-h8300/virtconvert.h with 100% similarity]
arch/sparc/include/asm/irq_64.h
arch/sparc/include/asm/of_device.h
arch/sparc64/kernel/irq.c
arch/sparc64/kernel/kstack.h [new file with mode: 0644]
arch/sparc64/kernel/process.c
arch/sparc64/kernel/smp.c
arch/sparc64/kernel/stacktrace.c
arch/sparc64/kernel/traps.c
arch/sparc64/lib/mcount.S
arch/sparc64/mm/init.c
arch/sparc64/mm/ultra.S
arch/x86/kernel/amd_iommu.c
arch/x86/kernel/amd_iommu_init.c
crypto/digest.c
crypto/tcrypt.c
drivers/Makefile
drivers/char/hw_random/via-rng.c
drivers/crypto/padlock-aes.c
drivers/crypto/padlock-sha.c
drivers/crypto/talitos.c
drivers/i2c/chips/isp1301_omap.c
drivers/input/serio/i8042-sparcio.h
drivers/net/bnx2x.h
drivers/net/bnx2x_fw_defs.h
drivers/net/bnx2x_hsi.h
drivers/net/bnx2x_init.h
drivers/net/bnx2x_init_values.h
drivers/net/bnx2x_link.c
drivers/net/bnx2x_link.h
drivers/net/bnx2x_main.c
drivers/net/bnx2x_reg.h
drivers/sbus/sbus.c
drivers/serial/sunhv.c
drivers/serial/sunsab.c
drivers/serial/sunsu.c
drivers/serial/sunzilog.c
drivers/usb/Kconfig
drivers/usb/atm/cxacru.c
drivers/usb/class/cdc-acm.c
drivers/usb/class/cdc-acm.h
drivers/usb/core/driver.c
drivers/usb/core/message.c
drivers/usb/gadget/Kconfig
drivers/usb/gadget/dummy_hcd.c
drivers/usb/gadget/f_acm.c
drivers/usb/gadget/f_ecm.c
drivers/usb/gadget/f_rndis.c
drivers/usb/gadget/f_serial.c
drivers/usb/gadget/f_subset.c
drivers/usb/gadget/gadget_chips.h
drivers/usb/gadget/omap_udc.c
drivers/usb/gadget/u_serial.c
drivers/usb/gadget/u_serial.h
drivers/usb/host/isp1760-hcd.c
drivers/usb/host/isp1760-hcd.h
drivers/usb/host/ohci-hcd.c
drivers/usb/host/ohci-hub.c
drivers/usb/host/ohci-omap.c
drivers/usb/host/ohci-pci.c
drivers/usb/host/ohci-q.c
drivers/usb/host/ohci.h
drivers/usb/host/r8a66597-hcd.c
drivers/usb/misc/Kconfig
drivers/usb/misc/Makefile
drivers/usb/misc/auerswald.c [deleted file]
drivers/usb/musb/Kconfig [new file with mode: 0644]
drivers/usb/musb/Makefile [new file with mode: 0644]
drivers/usb/musb/cppi_dma.c [new file with mode: 0644]
drivers/usb/musb/cppi_dma.h [new file with mode: 0644]
drivers/usb/musb/davinci.c [new file with mode: 0644]
drivers/usb/musb/davinci.h [new file with mode: 0644]
drivers/usb/musb/musb_core.c [new file with mode: 0644]
drivers/usb/musb/musb_core.h [new file with mode: 0644]
drivers/usb/musb/musb_debug.h [new file with mode: 0644]
drivers/usb/musb/musb_dma.h [new file with mode: 0644]
drivers/usb/musb/musb_gadget.c [new file with mode: 0644]
drivers/usb/musb/musb_gadget.h [new file with mode: 0644]
drivers/usb/musb/musb_gadget_ep0.c [new file with mode: 0644]
drivers/usb/musb/musb_host.c [new file with mode: 0644]
drivers/usb/musb/musb_host.h [new file with mode: 0644]
drivers/usb/musb/musb_io.h [new file with mode: 0644]
drivers/usb/musb/musb_procfs.c [new file with mode: 0644]
drivers/usb/musb/musb_regs.h [new file with mode: 0644]
drivers/usb/musb/musb_virthub.c [new file with mode: 0644]
drivers/usb/musb/musbhsdma.c [new file with mode: 0644]
drivers/usb/musb/omap2430.c [new file with mode: 0644]
drivers/usb/musb/omap2430.h [new file with mode: 0644]
drivers/usb/musb/tusb6010.c [new file with mode: 0644]
drivers/usb/musb/tusb6010.h [new file with mode: 0644]
drivers/usb/musb/tusb6010_omap.c [new file with mode: 0644]
drivers/usb/serial/Kconfig
drivers/usb/serial/ftdi_sio.c
drivers/usb/serial/ftdi_sio.h
drivers/usb/serial/option.c
drivers/usb/serial/pl2303.c
drivers/usb/serial/pl2303.h
drivers/usb/serial/sierra.c
drivers/usb/serial/usb-serial.c
drivers/usb/storage/Kconfig
drivers/usb/storage/Makefile
drivers/usb/storage/sierra_ms.c [new file with mode: 0644]
drivers/usb/storage/sierra_ms.h [new file with mode: 0644]
drivers/usb/storage/transport.c
drivers/usb/storage/unusual_devs.h
drivers/usb/storage/usb.c
fs/dlm/config.c
fs/dlm/user.c
fs/xfs/linux-2.6/sema.h [deleted file]
fs/xfs/linux-2.6/xfs_aops.c
fs/xfs/linux-2.6/xfs_buf.c
fs/xfs/linux-2.6/xfs_buf.h
fs/xfs/linux-2.6/xfs_export.c
fs/xfs/linux-2.6/xfs_fs_subr.c
fs/xfs/linux-2.6/xfs_ioctl.c
fs/xfs/linux-2.6/xfs_iops.c
fs/xfs/linux-2.6/xfs_iops.h
fs/xfs/linux-2.6/xfs_linux.h
fs/xfs/linux-2.6/xfs_lrw.c
fs/xfs/linux-2.6/xfs_super.c
fs/xfs/linux-2.6/xfs_super.h
fs/xfs/linux-2.6/xfs_vnode.c
fs/xfs/linux-2.6/xfs_vnode.h
fs/xfs/quota/xfs_dquot.c
fs/xfs/quota/xfs_dquot.h
fs/xfs/quota/xfs_dquot_item.c
fs/xfs/quota/xfs_qm.c
fs/xfs/quota/xfs_qm.h
fs/xfs/quota/xfs_qm_bhv.c
fs/xfs/quota/xfs_qm_syscalls.c
fs/xfs/xfs_acl.c
fs/xfs/xfs_acl.h
fs/xfs/xfs_arch.h
fs/xfs/xfs_attr.c
fs/xfs/xfs_attr.h
fs/xfs/xfs_attr_leaf.c
fs/xfs/xfs_attr_leaf.h
fs/xfs/xfs_bit.c
fs/xfs/xfs_bit.h
fs/xfs/xfs_bmap.c
fs/xfs/xfs_btree.c
fs/xfs/xfs_btree.h
fs/xfs/xfs_buf_item.c
fs/xfs/xfs_dfrag.c
fs/xfs/xfs_error.c
fs/xfs/xfs_error.h
fs/xfs/xfs_filestream.c
fs/xfs/xfs_ialloc_btree.c
fs/xfs/xfs_iget.c
fs/xfs/xfs_inode.c
fs/xfs/xfs_inode.h
fs/xfs/xfs_inode_item.c
fs/xfs/xfs_itable.c
fs/xfs/xfs_log.c
fs/xfs/xfs_log.h
fs/xfs/xfs_log_priv.h
fs/xfs/xfs_log_recover.c
fs/xfs/xfs_mount.c
fs/xfs/xfs_mount.h
fs/xfs/xfs_rtalloc.c
fs/xfs/xfs_rw.c
fs/xfs/xfs_trans.c
fs/xfs/xfs_trans.h
fs/xfs/xfs_trans_buf.c
fs/xfs/xfs_trans_item.c
fs/xfs/xfs_utils.c
fs/xfs/xfs_utils.h
fs/xfs/xfs_vfsops.c
fs/xfs/xfs_vnodeops.c
include/asm-x86/amd_iommu_types.h
include/asm-x86/i387.h
include/crypto/hash.h
include/linux/completion.h
include/linux/cred.h [new file with mode: 0644]
include/linux/sched.h
include/linux/skbuff.h
include/linux/usb.h
include/linux/usb/musb.h [new file with mode: 0644]
include/linux/usb/serial.h
include/net/ip6_route.h
include/net/ip_vs.h
include/net/pkt_sched.h
net/core/gen_estimator.c
net/core/pktgen.c
net/dccp/proto.c
net/ipv4/igmp.c
net/ipv4/ipvs/ip_vs_app.c
net/ipv4/ipvs/ip_vs_conn.c
net/ipv4/ipvs/ip_vs_ctl.c
net/ipv4/ipvs/ip_vs_dh.c
net/ipv4/ipvs/ip_vs_est.c
net/ipv4/ipvs/ip_vs_lblc.c
net/ipv4/ipvs/ip_vs_lblcr.c
net/ipv4/ipvs/ip_vs_lc.c
net/ipv4/ipvs/ip_vs_nq.c
net/ipv4/ipvs/ip_vs_proto.c
net/ipv4/ipvs/ip_vs_rr.c
net/ipv4/ipvs/ip_vs_sched.c
net/ipv4/ipvs/ip_vs_sed.c
net/ipv4/ipvs/ip_vs_sh.c
net/ipv4/ipvs/ip_vs_sync.c
net/ipv4/ipvs/ip_vs_wlc.c
net/ipv4/ipvs/ip_vs_wrr.c
net/ipv4/udp.c
net/ipv6/route.c
net/ipv6/udp.c
net/rxrpc/ar-accept.c
net/sched/act_api.c
net/sched/sch_api.c
net/sched/sch_generic.c
net/sched/sch_htb.c
net/tipc/subscr.c
net/wireless/wext.c
net/xfrm/xfrm_output.c

index e6244cde26e9406527dfcaa9aae9edf9e17c6161..05c80645e4ee172fafa118eea8f8b56aec242209 100644 (file)
@@ -2560,9 +2560,6 @@ Your cooperation is appreciated.
                 96 = /dev/usb/hiddev0  1st USB HID device
                    ...
                111 = /dev/usb/hiddev15 16th USB HID device
-               112 = /dev/usb/auer0    1st auerswald ISDN device
-                   ...
-               127 = /dev/usb/auer15   16th auerswald ISDN device
                128 = /dev/usb/brlvgr0  First Braille Voyager device
                    ...
                131 = /dev/usb/brlvgr3  Fourth Braille Voyager device
index 3bb5f466a90db3e971b42fb26c60d716a30878ed..1c6b545635a27741abe8f3b5bb10490416bce0fa 100644 (file)
@@ -105,7 +105,6 @@ Code        Seq#    Include File            Comments
 'T'    all     linux/soundcard.h       conflict!
 'T'    all     asm-i386/ioctls.h       conflict!
 'U'    00-EF   linux/drivers/usb/usb.h
-'U'    F0-FF   drivers/usb/auerswald.c
 'V'    all     linux/vt.h
 'W'    00-1F   linux/watchdog.h        conflict!
 'W'    00-1F   linux/wanrouter.h       conflict!
diff --git a/Documentation/usb/auerswald.txt b/Documentation/usb/auerswald.txt
deleted file mode 100644 (file)
index 7ee4d8f..0000000
+++ /dev/null
@@ -1,30 +0,0 @@
-               Auerswald USB kernel driver
-               ===========================
-
-What is it? What can I do with it?
-==================================
-The auerswald USB kernel driver connects your linux 2.4.x
-system to the auerswald usb-enabled devices.
-
-There are two types of auerswald usb devices:
-a) small PBX systems (ISDN)
-b) COMfort system telephones (ISDN)
-
-The driver installation creates the devices
-/dev/usb/auer0..15. These devices carry a vendor-
-specific protocol. You may run all auerswald java
-software on it. The java software needs a native
-library "libAuerUsbJNINative.so" installed on
-your system. This library is available from
-auerswald and shipped as part of the java software.
-
-You may create the devices with:
-       mknod -m 666 /dev/usb/auer0 c 180 112
-       ...
-       mknod -m 666 /dev/usb/auer15 c 180 127
-
-Future plans
-============
-- Connection to ISDN4LINUX (the hisax interface)
-
-The maintainer of this driver is wolfgang@iksw-muees.de
index b2fc4d4a99177be7bd48dce560d1f28417c60aa9..9d31140e3f5bc2db17e446b426a4ecfacbbf99fc 100644 (file)
@@ -436,7 +436,12 @@ post_reset; the USB core guarantees that this is true of internal
 suspend/resume events as well.
 
 If a driver wants to block all suspend/resume calls during some
-critical section, it can simply acquire udev->pm_mutex.
+critical section, it can simply acquire udev->pm_mutex. Note that
+calls to resume may be triggered indirectly. Block IO due to memory
+allocations can make the vm subsystem resume a device. Thus while
+holding this lock you must not allocate memory with GFP_KERNEL or
+GFP_NOFS.
+
 Alternatively, if the critical section might call some of the
 usb_autopm_* routines, the driver can avoid deadlock by doing:
 
index af6aa4e4b39264313d8b2fa0dc59820877ab2600..4c5e9fe0f7db5cd80b3fe2c4a76d38a3df1d7fcc 100644 (file)
@@ -2928,6 +2928,12 @@ M:       jirislaby@gmail.com
 L:     linux-kernel@vger.kernel.org
 S:     Maintained
 
+MUSB MULTIPOINT HIGH SPEED DUAL-ROLE CONTROLLER
+P:     Felipe Balbi
+M:     felipe.balbi@nokia.com
+L:     linux-usb@vger.kernel.org
+S:     Maintained
+
 MYRICOM MYRI-10G 10GbE DRIVER (MYRI10GE)
 P:     Andrew Gallatin
 M:     gallatin@myri.com
@@ -3076,6 +3082,7 @@ M:        horms@verge.net.au
 P:     Julian Anastasov
 M:     ja@ssi.bg
 L:     netdev@vger.kernel.org
+L:     lvs-devel@vger.kernel.org
 S:     Maintained
 
 NFS, SUNRPC, AND LOCKD CLIENTS
@@ -4195,12 +4202,6 @@ M:       oliver@neukum.name
 L:     linux-usb@vger.kernel.org
 S:     Maintained
 
-USB AUERSWALD DRIVER
-P:     Wolfgang Muees
-M:     wolfgang@iksw-muees.de
-L:      linux-usb@vger.kernel.org
-S:     Maintained
-
 USB BLOCK DRIVER (UB ub)
 P:     Pete Zaitcev
 M:     zaitcev@redhat.com
index 1607c941d95fd0848d12eaf202b17a794066f25c..10ef464d6be7f3f2768a1a7d95d6adb68e88ed17 100644 (file)
@@ -317,7 +317,6 @@ tusb6010_setup_interface(struct musb_hdrc_platform_data *data,
                printk(error, 6, status);
                return -ENODEV;
        }
-       data->multipoint = 1;
        tusb_device.dev.platform_data = data;
 
        /* REVISIT let the driver know what DMA channels work */
index 3473e25231d96e3fe63a0227cf3103d409074cf4..e3dd9303643dd8f161fd5fd5234abac5a5b77a31 100644 (file)
@@ -93,4 +93,8 @@ static inline unsigned long get_softint(void)
 void __trigger_all_cpu_backtrace(void);
 #define trigger_all_cpu_backtrace() __trigger_all_cpu_backtrace()
 
+extern void *hardirq_stack[NR_CPUS];
+extern void *softirq_stack[NR_CPUS];
+#define __ARCH_HAS_DO_SOFTIRQ
+
 #endif
index e5f5aedc2293e6b857ef0f5753050aa5c733bb91..bba777a416d3bf31b7ab4b5bb5a393ea7cc2c9f7 100644 (file)
@@ -30,8 +30,7 @@ struct of_device
 extern void __iomem *of_ioremap(struct resource *res, unsigned long offset, unsigned long size, char *name);
 extern void of_iounmap(struct resource *res, void __iomem *base, unsigned long size);
 
-/* These are just here during the transition */
-#include <linux/of_device.h>
+/* This is just here during the transition */
 #include <linux/of_platform.h>
 
 #endif /* __KERNEL__ */
index ba43d85e8dded537cfeb4a23c510456e4f2c956f..9b6689d9d57097239641d51653dc921e2607b997 100644 (file)
@@ -682,10 +682,32 @@ void ack_bad_irq(unsigned int virt_irq)
               ino, virt_irq);
 }
 
+void *hardirq_stack[NR_CPUS];
+void *softirq_stack[NR_CPUS];
+
+static __attribute__((always_inline)) void *set_hardirq_stack(void)
+{
+       void *orig_sp, *sp = hardirq_stack[smp_processor_id()];
+
+       __asm__ __volatile__("mov %%sp, %0" : "=r" (orig_sp));
+       if (orig_sp < sp ||
+           orig_sp > (sp + THREAD_SIZE)) {
+               sp += THREAD_SIZE - 192 - STACK_BIAS;
+               __asm__ __volatile__("mov %0, %%sp" : : "r" (sp));
+       }
+
+       return orig_sp;
+}
+static __attribute__((always_inline)) void restore_hardirq_stack(void *orig_sp)
+{
+       __asm__ __volatile__("mov %0, %%sp" : : "r" (orig_sp));
+}
+
 void handler_irq(int irq, struct pt_regs *regs)
 {
        unsigned long pstate, bucket_pa;
        struct pt_regs *old_regs;
+       void *orig_sp;
 
        clear_softint(1 << irq);
 
@@ -703,6 +725,8 @@ void handler_irq(int irq, struct pt_regs *regs)
                               "i" (PSTATE_IE)
                             : "memory");
 
+       orig_sp = set_hardirq_stack();
+
        while (bucket_pa) {
                struct irq_desc *desc;
                unsigned long next_pa;
@@ -719,10 +743,38 @@ void handler_irq(int irq, struct pt_regs *regs)
                bucket_pa = next_pa;
        }
 
+       restore_hardirq_stack(orig_sp);
+
        irq_exit();
        set_irq_regs(old_regs);
 }
 
+void do_softirq(void)
+{
+       unsigned long flags;
+
+       if (in_interrupt())
+               return;
+
+       local_irq_save(flags);
+
+       if (local_softirq_pending()) {
+               void *orig_sp, *sp = softirq_stack[smp_processor_id()];
+
+               sp += THREAD_SIZE - 192 - STACK_BIAS;
+
+               __asm__ __volatile__("mov %%sp, %0\n\t"
+                                    "mov %1, %%sp"
+                                    : "=&r" (orig_sp)
+                                    : "r" (sp));
+               __do_softirq();
+               __asm__ __volatile__("mov %0, %%sp"
+                                    : : "r" (orig_sp));
+       }
+
+       local_irq_restore(flags);
+}
+
 #ifdef CONFIG_HOTPLUG_CPU
 void fixup_irqs(void)
 {
diff --git a/arch/sparc64/kernel/kstack.h b/arch/sparc64/kernel/kstack.h
new file mode 100644 (file)
index 0000000..4248d96
--- /dev/null
@@ -0,0 +1,60 @@
+#ifndef _KSTACK_H
+#define _KSTACK_H
+
+#include <linux/thread_info.h>
+#include <linux/sched.h>
+#include <asm/ptrace.h>
+#include <asm/irq.h>
+
+/* SP must be STACK_BIAS adjusted already.  */
+static inline bool kstack_valid(struct thread_info *tp, unsigned long sp)
+{
+       unsigned long base = (unsigned long) tp;
+
+       if (sp >= (base + sizeof(struct thread_info)) &&
+           sp <= (base + THREAD_SIZE - sizeof(struct sparc_stackf)))
+               return true;
+
+       if (hardirq_stack[tp->cpu]) {
+               base = (unsigned long) hardirq_stack[tp->cpu];
+               if (sp >= base &&
+                   sp <= (base + THREAD_SIZE - sizeof(struct sparc_stackf)))
+                       return true;
+               base = (unsigned long) softirq_stack[tp->cpu];
+               if (sp >= base &&
+                   sp <= (base + THREAD_SIZE - sizeof(struct sparc_stackf)))
+                       return true;
+       }
+       return false;
+}
+
+/* Does "regs" point to a valid pt_regs trap frame?  */
+static inline bool kstack_is_trap_frame(struct thread_info *tp, struct pt_regs *regs)
+{
+       unsigned long base = (unsigned long) tp;
+       unsigned long addr = (unsigned long) regs;
+
+       if (addr >= base &&
+           addr <= (base + THREAD_SIZE - sizeof(*regs)))
+               goto check_magic;
+
+       if (hardirq_stack[tp->cpu]) {
+               base = (unsigned long) hardirq_stack[tp->cpu];
+               if (addr >= base &&
+                   addr <= (base + THREAD_SIZE - sizeof(*regs)))
+                       goto check_magic;
+               base = (unsigned long) softirq_stack[tp->cpu];
+               if (addr >= base &&
+                   addr <= (base + THREAD_SIZE - sizeof(*regs)))
+                       goto check_magic;
+       }
+       return false;
+
+check_magic:
+       if ((regs->magic & ~0x1ff) == PT_REGS_MAGIC)
+               return true;
+       return false;
+
+}
+
+#endif /* _KSTACK_H */
index 7f5debdc5fed6ad2a4ae86b1ff78836efe8dce03..15f4178592e762d4bbff775679ae80c70e91423d 100644 (file)
@@ -52,6 +52,8 @@
 #include <asm/irq_regs.h>
 #include <asm/smp.h>
 
+#include "kstack.h"
+
 static void sparc64_yield(int cpu)
 {
        if (tlb_type != hypervisor)
@@ -235,19 +237,6 @@ void show_regs(struct pt_regs *regs)
 struct global_reg_snapshot global_reg_snapshot[NR_CPUS];
 static DEFINE_SPINLOCK(global_reg_snapshot_lock);
 
-static bool kstack_valid(struct thread_info *tp, struct reg_window *rw)
-{
-       unsigned long thread_base, fp;
-
-       thread_base = (unsigned long) tp;
-       fp = (unsigned long) rw;
-
-       if (fp < (thread_base + sizeof(struct thread_info)) ||
-           fp >= (thread_base + THREAD_SIZE))
-               return false;
-       return true;
-}
-
 static void __global_reg_self(struct thread_info *tp, struct pt_regs *regs,
                              int this_cpu)
 {
@@ -264,11 +253,11 @@ static void __global_reg_self(struct thread_info *tp, struct pt_regs *regs,
 
                rw = (struct reg_window *)
                        (regs->u_regs[UREG_FP] + STACK_BIAS);
-               if (kstack_valid(tp, rw)) {
+               if (kstack_valid(tp, (unsigned long) rw)) {
                        global_reg_snapshot[this_cpu].i7 = rw->ins[7];
                        rw = (struct reg_window *)
                                (rw->ins[6] + STACK_BIAS);
-                       if (kstack_valid(tp, rw))
+                       if (kstack_valid(tp, (unsigned long) rw))
                                global_reg_snapshot[this_cpu].rpc = rw->ins[7];
                }
        } else {
@@ -828,7 +817,7 @@ out:
 unsigned long get_wchan(struct task_struct *task)
 {
        unsigned long pc, fp, bias = 0;
-       unsigned long thread_info_base;
+       struct thread_info *tp;
        struct reg_window *rw;
         unsigned long ret = 0;
        int count = 0; 
@@ -837,14 +826,12 @@ unsigned long get_wchan(struct task_struct *task)
             task->state == TASK_RUNNING)
                goto out;
 
-       thread_info_base = (unsigned long) task_stack_page(task);
+       tp = task_thread_info(task);
        bias = STACK_BIAS;
        fp = task_thread_info(task)->ksp + bias;
 
        do {
-               /* Bogus frame pointer? */
-               if (fp < (thread_info_base + sizeof(struct thread_info)) ||
-                   fp >= (thread_info_base + THREAD_SIZE))
+               if (!kstack_valid(tp, fp))
                        break;
                rw = (struct reg_window *) fp;
                pc = rw->ins[7];
index 27b81775a4decd16c43f32df32c8347407d82bb4..743ccad61c60921b36c9bf42a556dac79ac4e23c 100644 (file)
@@ -858,9 +858,7 @@ void smp_tsb_sync(struct mm_struct *mm)
 extern unsigned long xcall_flush_tlb_mm;
 extern unsigned long xcall_flush_tlb_pending;
 extern unsigned long xcall_flush_tlb_kernel_range;
-#ifdef CONFIG_MAGIC_SYSRQ
 extern unsigned long xcall_fetch_glob_regs;
-#endif
 extern unsigned long xcall_receive_signal;
 extern unsigned long xcall_new_mmu_context_version;
 #ifdef CONFIG_KGDB
@@ -1005,12 +1003,10 @@ void kgdb_roundup_cpus(unsigned long flags)
 }
 #endif
 
-#ifdef CONFIG_MAGIC_SYSRQ
 void smp_fetch_global_regs(void)
 {
        smp_cross_call(&xcall_fetch_glob_regs, 0, 0, 0);
 }
-#endif
 
 /* We know that the window frames of the user have been flushed
  * to the stack before we get here because all callers of us
index e9d7f0660f2e044643182cb2e85f9fde7dc5006b..4e21d4a57d3b3f2ea536ed5707d61fbf6bc94181 100644 (file)
@@ -5,10 +5,12 @@
 #include <asm/ptrace.h>
 #include <asm/stacktrace.h>
 
+#include "kstack.h"
+
 void save_stack_trace(struct stack_trace *trace)
 {
-       unsigned long ksp, fp, thread_base;
        struct thread_info *tp = task_thread_info(current);
+       unsigned long ksp, fp;
 
        stack_trace_flush();
 
@@ -18,23 +20,18 @@ void save_stack_trace(struct stack_trace *trace)
        );
 
        fp = ksp + STACK_BIAS;
-       thread_base = (unsigned long) tp;
        do {
                struct sparc_stackf *sf;
                struct pt_regs *regs;
                unsigned long pc;
 
-               /* Bogus frame pointer? */
-               if (fp < (thread_base + sizeof(struct thread_info)) ||
-                   fp > (thread_base + THREAD_SIZE - sizeof(struct sparc_stackf)))
+               if (!kstack_valid(tp, fp))
                        break;
 
                sf = (struct sparc_stackf *) fp;
                regs = (struct pt_regs *) (sf + 1);
 
-               if (((unsigned long)regs <=
-                    (thread_base + THREAD_SIZE - sizeof(*regs))) &&
-                   (regs->magic & ~0x1ff) == PT_REGS_MAGIC) {
+               if (kstack_is_trap_frame(tp, regs)) {
                        if (!(regs->tstate & TSTATE_PRIV))
                                break;
                        pc = regs->tpc;
index 404e8561e2d0cec8b6d52a38be95d360624b0be7..3d924121c7960dd5b577c291a9a2dd716a272b2d 100644 (file)
@@ -39,6 +39,7 @@
 #include <asm/prom.h>
 
 #include "entry.h"
+#include "kstack.h"
 
 /* When an irrecoverable trap occurs at tl > 0, the trap entry
  * code logs the trap state registers at every level in the trap
@@ -2115,14 +2116,12 @@ void show_stack(struct task_struct *tsk, unsigned long *_ksp)
                struct pt_regs *regs;
                unsigned long pc;
 
-               /* Bogus frame pointer? */
-               if (fp < (thread_base + sizeof(struct thread_info)) ||
-                   fp >= (thread_base + THREAD_SIZE))
+               if (!kstack_valid(tp, fp))
                        break;
                sf = (struct sparc_stackf *) fp;
                regs = (struct pt_regs *) (sf + 1);
 
-               if ((regs->magic & ~0x1ff) == PT_REGS_MAGIC) {
+               if (kstack_is_trap_frame(tp, regs)) {
                        if (!(regs->tstate & TSTATE_PRIV))
                                break;
                        pc = regs->tpc;
index 7735a7a60533fa225256ad0bd2d94a00be26033a..fad90ddb3a28f1aae9a6a44e849b7393bbf87ac3 100644 (file)
@@ -48,12 +48,45 @@ mcount:
        sub             %g3, STACK_BIAS, %g3
        cmp             %sp, %g3
        bg,pt           %xcc, 1f
-        sethi          %hi(panicstring), %g3
+        nop
+       lduh            [%g6 + TI_CPU], %g1
+       sethi           %hi(hardirq_stack), %g3
+       or              %g3, %lo(hardirq_stack), %g3
+       sllx            %g1, 3, %g1
+       ldx             [%g3 + %g1], %g7
+       sub             %g7, STACK_BIAS, %g7
+       cmp             %sp, %g7
+       bleu,pt         %xcc, 2f
+        sethi          %hi(THREAD_SIZE), %g3
+       add             %g7, %g3, %g7
+       cmp             %sp, %g7
+       blu,pn          %xcc, 1f
+2:      sethi          %hi(softirq_stack), %g3
+       or              %g3, %lo(softirq_stack), %g3
+       ldx             [%g3 + %g1], %g7
+       cmp             %sp, %g7
+       bleu,pt         %xcc, 2f
+        sethi          %hi(THREAD_SIZE), %g3
+       add             %g7, %g3, %g7
+       cmp             %sp, %g7
+       blu,pn          %xcc, 1f
+        nop
+       /* If we are already on ovstack, don't hop onto it
+        * again, we are already trying to output the stack overflow
+        * message.
+        */
        sethi           %hi(ovstack), %g7               ! cant move to panic stack fast enough
         or             %g7, %lo(ovstack), %g7
-       add             %g7, OVSTACKSIZE, %g7
+       add             %g7, OVSTACKSIZE, %g3
+       sub             %g3, STACK_BIAS + 192, %g3
        sub             %g7, STACK_BIAS, %g7
-       mov             %g7, %sp
+       cmp             %sp, %g7
+       blu,pn          %xcc, 2f
+        cmp            %sp, %g3
+       bleu,pn         %xcc, 1f
+        nop
+2:     mov             %g3, %sp
+       sethi           %hi(panicstring), %g3
        call            prom_printf
         or             %g3, %lo(panicstring), %o0
        call            prom_halt
index 4e821b3ecb039faa71991809c0d4139354ee2a8d..217de3ea29e842cff4c0eff6be2b82c5a13f25fe 100644 (file)
@@ -49,6 +49,7 @@
 #include <asm/sstate.h>
 #include <asm/mdesc.h>
 #include <asm/cpudata.h>
+#include <asm/irq.h>
 
 #define MAX_PHYS_ADDRESS       (1UL << 42UL)
 #define KPTE_BITMAP_CHUNK_SZ   (256UL * 1024UL * 1024UL)
@@ -1771,6 +1772,16 @@ void __init paging_init(void)
        if (tlb_type == hypervisor)
                sun4v_mdesc_init();
 
+       /* Once the OF device tree and MDESC have been setup, we know
+        * the list of possible cpus.  Therefore we can allocate the
+        * IRQ stacks.
+        */
+       for_each_possible_cpu(i) {
+               /* XXX Use node local allocations... XXX */
+               softirq_stack[i] = __va(lmb_alloc(THREAD_SIZE, THREAD_SIZE));
+               hardirq_stack[i] = __va(lmb_alloc(THREAD_SIZE, THREAD_SIZE));
+       }
+
        /* Setup bootmem... */
        last_valid_pfn = end_pfn = bootmem_init(phys_base);
 
index ff1dc44d363e1cd1349d1b5ad7e26dda18dd394c..86773e89dc1bbf29cf71831948e6d79b5d43188b 100644 (file)
@@ -480,7 +480,6 @@ xcall_sync_tick:
        b               rtrap_xcall
         ldx            [%sp + PTREGS_OFF + PT_V9_TSTATE], %l1
 
-#ifdef CONFIG_MAGIC_SYSRQ
        .globl          xcall_fetch_glob_regs
 xcall_fetch_glob_regs:
        sethi           %hi(global_reg_snapshot), %g1
@@ -511,7 +510,6 @@ xcall_fetch_glob_regs:
        membar          #StoreStore
        stx             %g3, [%g1 + GR_SNAP_THREAD]
        retry
-#endif /* CONFIG_MAGIC_SYSRQ */
 
 #ifdef DCACHE_ALIASING_POSSIBLE
        .align          32
index 22d7d050905dd1f6b6192707b2697e38a2fd38bd..de39e1f2ede5f1c820f4abe9fa4f9ec07948419b 100644 (file)
@@ -101,16 +101,13 @@ static int iommu_queue_command(struct amd_iommu *iommu, struct iommu_cmd *cmd)
  */
 static int iommu_completion_wait(struct amd_iommu *iommu)
 {
-       int ret;
+       int ret, ready = 0;
+       unsigned status = 0;
        struct iommu_cmd cmd;
-       volatile u64 ready = 0;
-       unsigned long ready_phys = virt_to_phys(&ready);
        unsigned long i = 0;
 
        memset(&cmd, 0, sizeof(cmd));
-       cmd.data[0] = LOW_U32(ready_phys) | CMD_COMPL_WAIT_STORE_MASK;
-       cmd.data[1] = upper_32_bits(ready_phys);
-       cmd.data[2] = 1; /* value written to 'ready' */
+       cmd.data[0] = CMD_COMPL_WAIT_INT_MASK;
        CMD_SET_TYPE(&cmd, CMD_COMPL_WAIT);
 
        iommu->need_sync = 0;
@@ -122,9 +119,15 @@ static int iommu_completion_wait(struct amd_iommu *iommu)
 
        while (!ready && (i < EXIT_LOOP_COUNT)) {
                ++i;
-               cpu_relax();
+               /* wait for the bit to become one */
+               status = readl(iommu->mmio_base + MMIO_STATUS_OFFSET);
+               ready = status & MMIO_STATUS_COM_WAIT_INT_MASK;
        }
 
+       /* set bit back to zero */
+       status &= ~MMIO_STATUS_COM_WAIT_INT_MASK;
+       writel(status, iommu->mmio_base + MMIO_STATUS_OFFSET);
+
        if (unlikely((i == EXIT_LOOP_COUNT) && printk_ratelimit()))
                printk(KERN_WARNING "AMD IOMMU: Completion wait loop failed\n");
 
@@ -161,7 +164,7 @@ static int iommu_queue_inv_iommu_pages(struct amd_iommu *iommu,
        address &= PAGE_MASK;
        CMD_SET_TYPE(&cmd, CMD_INV_IOMMU_PAGES);
        cmd.data[1] |= domid;
-       cmd.data[2] = LOW_U32(address);
+       cmd.data[2] = lower_32_bits(address);
        cmd.data[3] = upper_32_bits(address);
        if (s) /* size bit - we flush more than one 4kb page */
                cmd.data[2] |= CMD_INV_IOMMU_PAGES_SIZE_MASK;
index d9a9da597e796cbcda869180879a7804888e70ea..a69cc0f5204286a9ead45b580e2f506c00a88f2a 100644 (file)
@@ -800,6 +800,21 @@ static int __init init_memory_definitions(struct acpi_table_header *table)
        return 0;
 }
 
+/*
+ * Init the device table to not allow DMA access for devices and
+ * suppress all page faults
+ */
+static void init_device_table(void)
+{
+       u16 devid;
+
+       for (devid = 0; devid <= amd_iommu_last_bdf; ++devid) {
+               set_dev_entry_bit(devid, DEV_ENTRY_VALID);
+               set_dev_entry_bit(devid, DEV_ENTRY_TRANSLATION);
+               set_dev_entry_bit(devid, DEV_ENTRY_NO_PAGE_FAULT);
+       }
+}
+
 /*
  * This function finally enables all IOMMUs found in the system after
  * they have been initialized
@@ -931,6 +946,9 @@ int __init amd_iommu_init(void)
        if (amd_iommu_pd_alloc_bitmap == NULL)
                goto free;
 
+       /* init the device table */
+       init_device_table();
+
        /*
         * let all alias entries point to itself
         */
@@ -954,15 +972,15 @@ int __init amd_iommu_init(void)
        if (acpi_table_parse("IVRS", init_memory_definitions) != 0)
                goto free;
 
-       ret = amd_iommu_init_dma_ops();
+       ret = sysdev_class_register(&amd_iommu_sysdev_class);
        if (ret)
                goto free;
 
-       ret = sysdev_class_register(&amd_iommu_sysdev_class);
+       ret = sysdev_register(&device_amd_iommu);
        if (ret)
                goto free;
 
-       ret = sysdev_register(&device_amd_iommu);
+       ret = amd_iommu_init_dma_ops();
        if (ret)
                goto free;
 
index ac0919460d143c9e45b10212899d3b2cc3ec3a25..5d3f1303da985417d0ab192c5909aadd5f60ab0b 100644 (file)
@@ -225,7 +225,7 @@ int crypto_init_digest_ops_async(struct crypto_tfm *tfm)
        struct ahash_tfm  *crt  = &tfm->crt_ahash;
        struct digest_alg *dalg = &tfm->__crt_alg->cra_digest;
 
-       if (dalg->dia_digestsize > crypto_tfm_alg_blocksize(tfm))
+       if (dalg->dia_digestsize > PAGE_SIZE / 8)
                return -EINVAL;
 
        crt->init       = digest_async_init;
index 59821a22d75238e568fc07dff1b1d6e73f804640..66368022e0bf32466fa4a4e0569e9e03303b6b12 100644 (file)
@@ -481,21 +481,31 @@ next_one:
 
                        for (k = 0, temp = 0; k < template[i].np; k++) {
                                printk(KERN_INFO "page %u\n", k);
-                               q = &axbuf[IDX[k]];
-                               hexdump(q, template[i].tap[k]);
+                               q = &xbuf[IDX[k]];
+
+                               n = template[i].tap[k];
+                               if (k == template[i].np - 1)
+                                       n += enc ? authsize : -authsize;
+                               hexdump(q, n);
                                printk(KERN_INFO "%s\n",
-                                      memcmp(q, template[i].result + temp,
-                                             template[i].tap[k] -
-                                             (k < template[i].np - 1 || enc ?
-                                              0 : authsize)) ?
+                                      memcmp(q, template[i].result + temp, n) ?
                                       "fail" : "pass");
 
-                               for (n = 0; q[template[i].tap[k] + n]; n++)
-                                       ;
+                               q += n;
+                               if (k == template[i].np - 1 && !enc) {
+                                       if (memcmp(q, template[i].input +
+                                                     temp + n, authsize))
+                                               n = authsize;
+                                       else
+                                               n = 0;
+                               } else {
+                                       for (n = 0; q[n]; n++)
+                                               ;
+                               }
                                if (n) {
                                        printk("Result buffer corruption %u "
                                               "bytes:\n", n);
-                                       hexdump(&q[template[i].tap[k]], n);
+                                       hexdump(q, n);
                                }
 
                                temp += template[i].tap[k];
index a280ab3d0833fa29e8ae031bbb53bfdba37c4191..2735bde73475c5f840c2d52266fd47e54b730bcd 100644 (file)
@@ -57,6 +57,7 @@ obj-$(CONFIG_ATA_OVER_ETH)    += block/aoe/
 obj-$(CONFIG_PARIDE)           += block/paride/
 obj-$(CONFIG_TC)               += tc/
 obj-$(CONFIG_USB)              += usb/
+obj-$(CONFIG_USB_MUSB_HDRC)    += usb/musb/
 obj-$(CONFIG_PCI)              += usb/
 obj-$(CONFIG_USB_GADGET)       += usb/gadget/
 obj-$(CONFIG_SERIO)            += input/serio/
index f7feae4ebb5e9981e7f730f637a2b1e54f5cc767..128202e18fc98780b2f576ed20e221dd75d3fe41 100644 (file)
@@ -31,6 +31,7 @@
 #include <asm/io.h>
 #include <asm/msr.h>
 #include <asm/cpufeature.h>
+#include <asm/i387.h>
 
 
 #define PFX    KBUILD_MODNAME ": "
@@ -67,16 +68,23 @@ enum {
  * Another possible performance boost may come from simply buffering
  * until we have 4 bytes, thus returning a u32 at a time,
  * instead of the current u8-at-a-time.
+ *
+ * Padlock instructions can generate a spurious DNA fault, so
+ * we have to call them in the context of irq_ts_save/restore()
  */
 
 static inline u32 xstore(u32 *addr, u32 edx_in)
 {
        u32 eax_out;
+       int ts_state;
+
+       ts_state = irq_ts_save();
 
        asm(".byte 0x0F,0xA7,0xC0 /* xstore %%edi (addr=%0) */"
                :"=m"(*addr), "=a"(eax_out)
                :"D"(addr), "d"(edx_in));
 
+       irq_ts_restore(ts_state);
        return eax_out;
 }
 
index 54a2a166e566740f1ebae141495e09013015aeea..bf2917d197a018d13f1bc48ad4c93c0b0a93ccde 100644 (file)
@@ -16,6 +16,7 @@
 #include <linux/interrupt.h>
 #include <linux/kernel.h>
 #include <asm/byteorder.h>
+#include <asm/i387.h>
 #include "padlock.h"
 
 /* Control word. */
@@ -141,6 +142,12 @@ static inline void padlock_reset_key(void)
        asm volatile ("pushfl; popfl");
 }
 
+/*
+ * While the padlock instructions don't use FP/SSE registers, they
+ * generate a spurious DNA fault when cr0.ts is '1'. These instructions
+ * should be used only inside the irq_ts_save/restore() context
+ */
+
 static inline void padlock_xcrypt(const u8 *input, u8 *output, void *key,
                                  void *control_word)
 {
@@ -205,15 +212,23 @@ static inline u8 *padlock_xcrypt_cbc(const u8 *input, u8 *output, void *key,
 static void aes_encrypt(struct crypto_tfm *tfm, u8 *out, const u8 *in)
 {
        struct aes_ctx *ctx = aes_ctx(tfm);
+       int ts_state;
        padlock_reset_key();
+
+       ts_state = irq_ts_save();
        aes_crypt(in, out, ctx->E, &ctx->cword.encrypt);
+       irq_ts_restore(ts_state);
 }
 
 static void aes_decrypt(struct crypto_tfm *tfm, u8 *out, const u8 *in)
 {
        struct aes_ctx *ctx = aes_ctx(tfm);
+       int ts_state;
        padlock_reset_key();
+
+       ts_state = irq_ts_save();
        aes_crypt(in, out, ctx->D, &ctx->cword.decrypt);
+       irq_ts_restore(ts_state);
 }
 
 static struct crypto_alg aes_alg = {
@@ -244,12 +259,14 @@ static int ecb_aes_encrypt(struct blkcipher_desc *desc,
        struct aes_ctx *ctx = blk_aes_ctx(desc->tfm);
        struct blkcipher_walk walk;
        int err;
+       int ts_state;
 
        padlock_reset_key();
 
        blkcipher_walk_init(&walk, dst, src, nbytes);
        err = blkcipher_walk_virt(desc, &walk);
 
+       ts_state = irq_ts_save();
        while ((nbytes = walk.nbytes)) {
                padlock_xcrypt_ecb(walk.src.virt.addr, walk.dst.virt.addr,
                                   ctx->E, &ctx->cword.encrypt,
@@ -257,6 +274,7 @@ static int ecb_aes_encrypt(struct blkcipher_desc *desc,
                nbytes &= AES_BLOCK_SIZE - 1;
                err = blkcipher_walk_done(desc, &walk, nbytes);
        }
+       irq_ts_restore(ts_state);
 
        return err;
 }
@@ -268,12 +286,14 @@ static int ecb_aes_decrypt(struct blkcipher_desc *desc,
        struct aes_ctx *ctx = blk_aes_ctx(desc->tfm);
        struct blkcipher_walk walk;
        int err;
+       int ts_state;
 
        padlock_reset_key();
 
        blkcipher_walk_init(&walk, dst, src, nbytes);
        err = blkcipher_walk_virt(desc, &walk);
 
+       ts_state = irq_ts_save();
        while ((nbytes = walk.nbytes)) {
                padlock_xcrypt_ecb(walk.src.virt.addr, walk.dst.virt.addr,
                                   ctx->D, &ctx->cword.decrypt,
@@ -281,7 +301,7 @@ static int ecb_aes_decrypt(struct blkcipher_desc *desc,
                nbytes &= AES_BLOCK_SIZE - 1;
                err = blkcipher_walk_done(desc, &walk, nbytes);
        }
-
+       irq_ts_restore(ts_state);
        return err;
 }
 
@@ -314,12 +334,14 @@ static int cbc_aes_encrypt(struct blkcipher_desc *desc,
        struct aes_ctx *ctx = blk_aes_ctx(desc->tfm);
        struct blkcipher_walk walk;
        int err;
+       int ts_state;
 
        padlock_reset_key();
 
        blkcipher_walk_init(&walk, dst, src, nbytes);
        err = blkcipher_walk_virt(desc, &walk);
 
+       ts_state = irq_ts_save();
        while ((nbytes = walk.nbytes)) {
                u8 *iv = padlock_xcrypt_cbc(walk.src.virt.addr,
                                            walk.dst.virt.addr, ctx->E,
@@ -329,6 +351,7 @@ static int cbc_aes_encrypt(struct blkcipher_desc *desc,
                nbytes &= AES_BLOCK_SIZE - 1;
                err = blkcipher_walk_done(desc, &walk, nbytes);
        }
+       irq_ts_restore(ts_state);
 
        return err;
 }
@@ -340,12 +363,14 @@ static int cbc_aes_decrypt(struct blkcipher_desc *desc,
        struct aes_ctx *ctx = blk_aes_ctx(desc->tfm);
        struct blkcipher_walk walk;
        int err;
+       int ts_state;
 
        padlock_reset_key();
 
        blkcipher_walk_init(&walk, dst, src, nbytes);
        err = blkcipher_walk_virt(desc, &walk);
 
+       ts_state = irq_ts_save();
        while ((nbytes = walk.nbytes)) {
                padlock_xcrypt_cbc(walk.src.virt.addr, walk.dst.virt.addr,
                                   ctx->D, walk.iv, &ctx->cword.decrypt,
@@ -354,6 +379,7 @@ static int cbc_aes_decrypt(struct blkcipher_desc *desc,
                err = blkcipher_walk_done(desc, &walk, nbytes);
        }
 
+       irq_ts_restore(ts_state);
        return err;
 }
 
index 40d5680fa0139c926ab500545736a3ac9abd0035..a7fbadebf62330864734e5302be660d2f39ab51a 100644 (file)
@@ -22,6 +22,7 @@
 #include <linux/interrupt.h>
 #include <linux/kernel.h>
 #include <linux/scatterlist.h>
+#include <asm/i387.h>
 #include "padlock.h"
 
 #define SHA1_DEFAULT_FALLBACK  "sha1-generic"
@@ -102,6 +103,7 @@ static void padlock_do_sha1(const char *in, char *out, int count)
         *     PadLock microcode needs it that big. */
        char buf[128+16];
        char *result = NEAREST_ALIGNED(buf);
+       int ts_state;
 
        ((uint32_t *)result)[0] = SHA1_H0;
        ((uint32_t *)result)[1] = SHA1_H1;
@@ -109,9 +111,12 @@ static void padlock_do_sha1(const char *in, char *out, int count)
        ((uint32_t *)result)[3] = SHA1_H3;
        ((uint32_t *)result)[4] = SHA1_H4;
  
+       /* prevent taking the spurious DNA fault with padlock. */
+       ts_state = irq_ts_save();
        asm volatile (".byte 0xf3,0x0f,0xa6,0xc8" /* rep xsha1 */
                      : "+S"(in), "+D"(result)
                      : "c"(count), "a"(0));
+       irq_ts_restore(ts_state);
 
        padlock_output_block((uint32_t *)result, (uint32_t *)out, 5);
 }
@@ -123,6 +128,7 @@ static void padlock_do_sha256(const char *in, char *out, int count)
         *     PadLock microcode needs it that big. */
        char buf[128+16];
        char *result = NEAREST_ALIGNED(buf);
+       int ts_state;
 
        ((uint32_t *)result)[0] = SHA256_H0;
        ((uint32_t *)result)[1] = SHA256_H1;
@@ -133,9 +139,12 @@ static void padlock_do_sha256(const char *in, char *out, int count)
        ((uint32_t *)result)[6] = SHA256_H6;
        ((uint32_t *)result)[7] = SHA256_H7;
 
+       /* prevent taking the spurious DNA fault with padlock. */
+       ts_state = irq_ts_save();
        asm volatile (".byte 0xf3,0x0f,0xa6,0xd0" /* rep xsha256 */
                      : "+S"(in), "+D"(result)
                      : "c"(count), "a"(0));
+       irq_ts_restore(ts_state);
 
        padlock_output_block((uint32_t *)result, (uint32_t *)out, 8);
 }
index 681c15f420834a545292b17974e523d387d2f243..ee827a7f7c6a48257e5af20219dcb256421d8994 100644 (file)
@@ -96,6 +96,9 @@ struct talitos_private {
        unsigned int exec_units;
        unsigned int desc_types;
 
+       /* SEC Compatibility info */
+       unsigned long features;
+
        /* next channel to be assigned next incoming descriptor */
        atomic_t last_chan;
 
@@ -133,6 +136,9 @@ struct talitos_private {
        struct hwrng rng;
 };
 
+/* .features flag */
+#define TALITOS_FTR_SRC_LINK_TBL_LEN_INCLUDES_EXTENT 0x00000001
+
 /*
  * map virtual single (contiguous) pointer to h/w descriptor pointer
  */
@@ -785,7 +791,7 @@ static void ipsec_esp_encrypt_done(struct device *dev,
        /* copy the generated ICV to dst */
        if (edesc->dma_len) {
                icvdata = &edesc->link_tbl[edesc->src_nents +
-                                          edesc->dst_nents + 1];
+                                          edesc->dst_nents + 2];
                sg = sg_last(areq->dst, edesc->dst_nents);
                memcpy((char *)sg_virt(sg) + sg->length - ctx->authsize,
                       icvdata, ctx->authsize);
@@ -814,7 +820,7 @@ static void ipsec_esp_decrypt_done(struct device *dev,
                /* auth check */
                if (edesc->dma_len)
                        icvdata = &edesc->link_tbl[edesc->src_nents +
-                                                  edesc->dst_nents + 1];
+                                                  edesc->dst_nents + 2];
                else
                        icvdata = &edesc->link_tbl[0];
 
@@ -921,10 +927,30 @@ static int ipsec_esp(struct ipsec_esp_edesc *edesc, struct aead_request *areq,
                sg_count = sg_to_link_tbl(areq->src, sg_count, cryptlen,
                                          &edesc->link_tbl[0]);
                if (sg_count > 1) {
+                       struct talitos_ptr *link_tbl_ptr =
+                               &edesc->link_tbl[sg_count-1];
+                       struct scatterlist *sg;
+                       struct talitos_private *priv = dev_get_drvdata(dev);
+
                        desc->ptr[4].j_extent |= DESC_PTR_LNKTBL_JUMP;
                        desc->ptr[4].ptr = cpu_to_be32(edesc->dma_link_tbl);
                        dma_sync_single_for_device(ctx->dev, edesc->dma_link_tbl,
                                                   edesc->dma_len, DMA_BIDIRECTIONAL);
+                       /* If necessary for this SEC revision,
+                        * add a link table entry for ICV.
+                        */
+                       if ((priv->features &
+                            TALITOS_FTR_SRC_LINK_TBL_LEN_INCLUDES_EXTENT) &&
+                           (edesc->desc.hdr & DESC_HDR_MODE0_ENCRYPT) == 0) {
+                               link_tbl_ptr->j_extent = 0;
+                               link_tbl_ptr++;
+                               link_tbl_ptr->j_extent = DESC_PTR_LNKTBL_RETURN;
+                               link_tbl_ptr->len = cpu_to_be16(authsize);
+                               sg = sg_last(areq->src, edesc->src_nents ? : 1);
+                               link_tbl_ptr->ptr = cpu_to_be32(
+                                               (char *)sg_dma_address(sg)
+                                               + sg->length - authsize);
+                       }
                } else {
                        /* Only one segment now, so no link tbl needed */
                        desc->ptr[4].ptr = cpu_to_be32(sg_dma_address(areq->src));
@@ -944,12 +970,11 @@ static int ipsec_esp(struct ipsec_esp_edesc *edesc, struct aead_request *areq,
                desc->ptr[5].ptr = cpu_to_be32(sg_dma_address(areq->dst));
        } else {
                struct talitos_ptr *link_tbl_ptr =
-                       &edesc->link_tbl[edesc->src_nents];
-               struct scatterlist *sg;
+                       &edesc->link_tbl[edesc->src_nents + 1];
 
                desc->ptr[5].ptr = cpu_to_be32((struct talitos_ptr *)
                                               edesc->dma_link_tbl +
-                                              edesc->src_nents);
+                                              edesc->src_nents + 1);
                if (areq->src == areq->dst) {
                        memcpy(link_tbl_ptr, &edesc->link_tbl[0],
                               edesc->src_nents * sizeof(struct talitos_ptr));
@@ -957,14 +982,10 @@ static int ipsec_esp(struct ipsec_esp_edesc *edesc, struct aead_request *areq,
                        sg_count = sg_to_link_tbl(areq->dst, sg_count, cryptlen,
                                                  link_tbl_ptr);
                }
+               /* Add an entry to the link table for ICV data */
                link_tbl_ptr += sg_count - 1;
-
-               /* handle case where sg_last contains the ICV exclusively */
-               sg = sg_last(areq->dst, edesc->dst_nents);
-               if (sg->length == ctx->authsize)
-                       link_tbl_ptr--;
-
                link_tbl_ptr->j_extent = 0;
+               sg_count++;
                link_tbl_ptr++;
                link_tbl_ptr->j_extent = DESC_PTR_LNKTBL_RETURN;
                link_tbl_ptr->len = cpu_to_be16(authsize);
@@ -973,7 +994,7 @@ static int ipsec_esp(struct ipsec_esp_edesc *edesc, struct aead_request *areq,
                link_tbl_ptr->ptr = cpu_to_be32((struct talitos_ptr *)
                                                edesc->dma_link_tbl +
                                                edesc->src_nents +
-                                               edesc->dst_nents + 1);
+                                               edesc->dst_nents + 2);
 
                desc->ptr[5].j_extent |= DESC_PTR_LNKTBL_JUMP;
                dma_sync_single_for_device(ctx->dev, edesc->dma_link_tbl,
@@ -1040,12 +1061,12 @@ static struct ipsec_esp_edesc *ipsec_esp_edesc_alloc(struct aead_request *areq,
 
        /*
         * allocate space for base edesc plus the link tables,
-        * allowing for a separate entry for the generated ICV (+ 1),
+        * allowing for two separate entries for ICV and generated ICV (+ 2),
         * and the ICV data itself
         */
        alloc_len = sizeof(struct ipsec_esp_edesc);
        if (src_nents || dst_nents) {
-               dma_len = (src_nents + dst_nents + 1) *
+               dma_len = (src_nents + dst_nents + 2) *
                                 sizeof(struct talitos_ptr) + ctx->authsize;
                alloc_len += dma_len;
        } else {
@@ -1104,7 +1125,7 @@ static int aead_authenc_decrypt(struct aead_request *req)
        /* stash incoming ICV for later cmp with ICV generated by the h/w */
        if (edesc->dma_len)
                icvdata = &edesc->link_tbl[edesc->src_nents +
-                                          edesc->dst_nents + 1];
+                                          edesc->dst_nents + 2];
        else
                icvdata = &edesc->link_tbl[0];
 
@@ -1480,6 +1501,9 @@ static int talitos_probe(struct of_device *ofdev,
                goto err_out;
        }
 
+       if (of_device_is_compatible(np, "fsl,sec3.0"))
+               priv->features |= TALITOS_FTR_SRC_LINK_TBL_LEN_INCLUDES_EXTENT;
+
        priv->head_lock = kmalloc(sizeof(spinlock_t) * priv->num_channels,
                                  GFP_KERNEL);
        priv->tail_lock = kmalloc(sizeof(spinlock_t) * priv->num_channels,
index 18355ae2155d9bf83d9276ac5204dfecf01a40b1..4655b794ebe3c7d06ad911cf898c25a5061b03d0 100644 (file)
@@ -1593,7 +1593,7 @@ fail1:
        if (machine_is_omap_h2()) {
                /* full speed signaling by default */
                isp1301_set_bits(isp, ISP1301_MODE_CONTROL_1,
-                       MC1_SPEED_REG);
+                       MC1_SPEED);
                isp1301_set_bits(isp, ISP1301_MODE_CONTROL_2,
                        MC2_SPD_SUSP_CTRL);
 
index 66bafe308b0cd053252e4f0cbf8b3644dfd7c5a5..692a79ec2a22327e98c94ef4946fe2f69b6747da 100644 (file)
@@ -1,10 +1,11 @@
 #ifndef _I8042_SPARCIO_H
 #define _I8042_SPARCIO_H
 
+#include <linux/of_device.h>
+
 #include <asm/io.h>
 #include <asm/oplib.h>
 #include <asm/prom.h>
-#include <asm/of_device.h>
 
 static int i8042_kbd_irq = -1;
 static int i8042_aux_irq = -1;
index 4bf4f7b205f24a62d3ed8fefcbc7cbdb443cc197..b468f904c7f88591cd952c983c44693412d7b239 100644 (file)
 #define DP(__mask, __fmt, __args...) do { \
        if (bp->msglevel & (__mask)) \
                printk(DP_LEVEL "[%s:%d(%s)]" __fmt, __func__, __LINE__, \
-                       bp->dev?(bp->dev->name):"?", ##__args); \
+                       bp->dev ? (bp->dev->name) : "?", ##__args); \
        } while (0)
 
 /* errors debug print */
 #define BNX2X_DBG_ERR(__fmt, __args...) do { \
        if (bp->msglevel & NETIF_MSG_PROBE) \
                printk(KERN_ERR "[%s:%d(%s)]" __fmt, __func__, __LINE__, \
-                       bp->dev?(bp->dev->name):"?", ##__args); \
+                       bp->dev ? (bp->dev->name) : "?", ##__args); \
        } while (0)
 
 /* for errors (never masked) */
 #define BNX2X_ERR(__fmt, __args...) do { \
        printk(KERN_ERR "[%s:%d(%s)]" __fmt, __func__, __LINE__, \
-               bp->dev?(bp->dev->name):"?", ##__args); \
+               bp->dev ? (bp->dev->name) : "?", ##__args); \
        } while (0)
 
 /* before we have a dev->name use dev_info() */
 #define SHMEM_RD(bp, field)            REG_RD(bp, SHMEM_ADDR(bp, field))
 #define SHMEM_WR(bp, field, val)       REG_WR(bp, SHMEM_ADDR(bp, field), val)
 
-#define NIG_WR(reg, val)       REG_WR(bp, reg, val)
-#define EMAC_WR(reg, val)      REG_WR(bp, emac_base + reg, val)
-#define BMAC_WR(reg, val)      REG_WR(bp, GRCBASE_NIG + bmac_addr + reg, val)
-
-
-#define for_each_queue(bp, var)        for (var = 0; var < bp->num_queues; var++)
-
-#define for_each_nondefault_queue(bp, var) \
-                               for (var = 1; var < bp->num_queues; var++)
-#define is_multi(bp)           (bp->num_queues > 1)
+#define EMAC_RD(bp, reg)               REG_RD(bp, emac_base + reg)
+#define EMAC_WR(bp, reg, val)          REG_WR(bp, emac_base + reg, val)
 
 
 /* fast path */
@@ -163,7 +155,7 @@ struct sw_rx_page {
 #define NUM_RX_SGE_PAGES               2
 #define RX_SGE_CNT             (BCM_PAGE_SIZE / sizeof(struct eth_rx_sge))
 #define MAX_RX_SGE_CNT                 (RX_SGE_CNT - 2)
-/* RX_SGE_CNT is promissed to be a power of 2 */
+/* RX_SGE_CNT is promised to be a power of 2 */
 #define RX_SGE_MASK                    (RX_SGE_CNT - 1)
 #define NUM_RX_SGE                     (RX_SGE_CNT * NUM_RX_SGE_PAGES)
 #define MAX_RX_SGE                     (NUM_RX_SGE - 1)
@@ -258,8 +250,7 @@ struct bnx2x_fastpath {
 
        unsigned long           tx_pkt,
                                rx_pkt,
-                               rx_calls,
-                               rx_alloc_failed;
+                               rx_calls;
        /* TPA related */
        struct sw_rx_bd         tpa_pool[ETH_MAX_AGGREGATION_QUEUES_E1H];
        u8                      tpa_state[ETH_MAX_AGGREGATION_QUEUES_E1H];
@@ -275,6 +266,15 @@ struct bnx2x_fastpath {
 
 #define bnx2x_fp(bp, nr, var)          (bp->fp[nr].var)
 
+#define BNX2X_HAS_TX_WORK(fp) \
+                       ((fp->tx_pkt_prod != le16_to_cpu(*fp->tx_cons_sb)) || \
+                        (fp->tx_pkt_prod != fp->tx_pkt_cons))
+
+#define BNX2X_HAS_RX_WORK(fp) \
+                       (fp->rx_comp_cons != le16_to_cpu(*fp->rx_cons_sb))
+
+#define BNX2X_HAS_WORK(fp)     (BNX2X_HAS_RX_WORK(fp) || BNX2X_HAS_TX_WORK(fp))
+
 
 /* MC hsi */
 #define MAX_FETCH_BD                   13      /* HW max BDs per packet */
@@ -317,7 +317,7 @@ struct bnx2x_fastpath {
 #define RCQ_BD(x)                      ((x) & MAX_RCQ_BD)
 
 
-/* This is needed for determening of last_max */
+/* This is needed for determining of last_max */
 #define SUB_S16(a, b)                  (s16)((s16)(a) - (s16)(b))
 
 #define __SGE_MASK_SET_BIT(el, bit) \
@@ -386,20 +386,28 @@ struct bnx2x_fastpath {
 #define TPA_TYPE(cqe_fp_flags)         ((cqe_fp_flags) & \
                                         (TPA_TYPE_START | TPA_TYPE_END))
 
-#define BNX2X_RX_SUM_OK(cqe) \
-                       (!(cqe->fast_path_cqe.status_flags & \
-                        (ETH_FAST_PATH_RX_CQE_IP_XSUM_NO_VALIDATION_FLG | \
-                         ETH_FAST_PATH_RX_CQE_L4_XSUM_NO_VALIDATION_FLG)))
+#define ETH_RX_ERROR_FALGS             ETH_FAST_PATH_RX_CQE_PHY_DECODE_ERR_FLG
+
+#define BNX2X_IP_CSUM_ERR(cqe) \
+                       (!((cqe)->fast_path_cqe.status_flags & \
+                          ETH_FAST_PATH_RX_CQE_IP_XSUM_NO_VALIDATION_FLG) && \
+                        ((cqe)->fast_path_cqe.type_error_flags & \
+                         ETH_FAST_PATH_RX_CQE_IP_BAD_XSUM_FLG))
+
+#define BNX2X_L4_CSUM_ERR(cqe) \
+                       (!((cqe)->fast_path_cqe.status_flags & \
+                          ETH_FAST_PATH_RX_CQE_L4_XSUM_NO_VALIDATION_FLG) && \
+                        ((cqe)->fast_path_cqe.type_error_flags & \
+                         ETH_FAST_PATH_RX_CQE_L4_BAD_XSUM_FLG))
+
+#define BNX2X_RX_CSUM_OK(cqe) \
+                       (!(BNX2X_L4_CSUM_ERR(cqe) || BNX2X_IP_CSUM_ERR(cqe)))
 
 #define BNX2X_RX_SUM_FIX(cqe) \
                        ((le16_to_cpu(cqe->fast_path_cqe.pars_flags.flags) & \
                          PARSING_FLAGS_OVER_ETHERNET_PROTOCOL) == \
                         (1 << PARSING_FLAGS_OVER_ETHERNET_PROTOCOL_SHIFT))
 
-#define ETH_RX_ERROR_FALGS     (ETH_FAST_PATH_RX_CQE_PHY_DECODE_ERR_FLG | \
-                                ETH_FAST_PATH_RX_CQE_IP_BAD_XSUM_FLG | \
-                                ETH_FAST_PATH_RX_CQE_L4_BAD_XSUM_FLG)
-
 
 #define FP_USB_FUNC_OFF                        (2 + 2*HC_USTORM_SB_NUM_INDICES)
 #define FP_CSB_FUNC_OFF                        (2 + 2*HC_CSTORM_SB_NUM_INDICES)
@@ -647,6 +655,8 @@ struct bnx2x_eth_stats {
 
        u32 brb_drop_hi;
        u32 brb_drop_lo;
+       u32 brb_truncate_hi;
+       u32 brb_truncate_lo;
 
        u32 jabber_packets_received;
 
@@ -663,6 +673,9 @@ struct bnx2x_eth_stats {
        u32 mac_discard;
 
        u32 driver_xoff;
+       u32 rx_err_discard_pkt;
+       u32 rx_skb_alloc_failed;
+       u32 hw_csum_err;
 };
 
 #define STATS_OFFSET32(stat_name) \
@@ -753,7 +766,6 @@ struct bnx2x {
        u16                     def_att_idx;
        u32                     attn_state;
        struct attn_route       attn_group[MAX_DYNAMIC_ATTN_GRPS];
-       u32                     aeu_mask;
        u32                     nig_mask;
 
        /* slow path ring */
@@ -772,7 +784,7 @@ struct bnx2x {
        u8                      stats_pending;
        u8                      set_mac_pending;
 
-       /* End of fileds used in the performance code paths */
+       /* End of fields used in the performance code paths */
 
        int                     panic;
        int                     msglevel;
@@ -794,9 +806,6 @@ struct bnx2x {
 #define BP_FUNC(bp)                    (bp->func)
 #define BP_E1HVN(bp)                   (bp->func >> 1)
 #define BP_L_ID(bp)                    (BP_E1HVN(bp) << 2)
-/* assorted E1HVN */
-#define IS_E1HMF(bp)                   (bp->e1hmf != 0)
-#define BP_MAX_QUEUES(bp)              (IS_E1HMF(bp) ? 4 : 16)
 
        int                     pm_cap;
        int                     pcie_cap;
@@ -821,6 +830,7 @@ struct bnx2x {
        u32                     mf_config;
        u16                     e1hov;
        u8                      e1hmf;
+#define IS_E1HMF(bp)                   (bp->e1hmf != 0)
 
        u8                      wol;
 
@@ -836,7 +846,6 @@ struct bnx2x {
        u16                     rx_ticks_int;
        u16                     rx_ticks;
 
-       u32                     stats_ticks;
        u32                     lin_cnt;
 
        int                     state;
@@ -852,6 +861,7 @@ struct bnx2x {
 #define BNX2X_STATE_ERROR              0xf000
 
        int                     num_queues;
+#define BP_MAX_QUEUES(bp)              (IS_E1HMF(bp) ? 4 : 16)
 
        u32                     rx_mode;
 #define BNX2X_RX_MODE_NONE             0
@@ -902,10 +912,17 @@ struct bnx2x {
 };
 
 
+#define for_each_queue(bp, var)        for (var = 0; var < bp->num_queues; var++)
+
+#define for_each_nondefault_queue(bp, var) \
+                               for (var = 1; var < bp->num_queues; var++)
+#define is_multi(bp)           (bp->num_queues > 1)
+
+
 void bnx2x_read_dmae(struct bnx2x *bp, u32 src_addr, u32 len32);
 void bnx2x_write_dmae(struct bnx2x *bp, dma_addr_t dma_addr, u32 dst_addr,
                      u32 len32);
-int bnx2x_set_gpio(struct bnx2x *bp, int gpio_num, u32 mode);
+int bnx2x_set_gpio(struct bnx2x *bp, int gpio_num, u32 mode, u8 port);
 
 static inline u32 reg_poll(struct bnx2x *bp, u32 reg, u32 expected, int ms,
                           int wait)
@@ -976,7 +993,7 @@ static inline u32 reg_poll(struct bnx2x *bp, u32 reg, u32 expected, int ms,
 #define PCICFG_LINK_SPEED_SHIFT                16
 
 
-#define BNX2X_NUM_STATS                        39
+#define BNX2X_NUM_STATS                        42
 #define BNX2X_NUM_TESTS                        8
 
 #define BNX2X_MAC_LOOPBACK             0
@@ -1007,10 +1024,10 @@ static inline u32 reg_poll(struct bnx2x *bp, u32 reg, u32 expected, int ms,
 /* resolution of the rate shaping timer - 100 usec */
 #define RS_PERIODIC_TIMEOUT_USEC       100
 /* resolution of fairness algorithm in usecs -
-   coefficient for clauclating the actuall t fair */
+   coefficient for calculating the actual t fair */
 #define T_FAIR_COEF                    10000000
 /* number of bytes in single QM arbitration cycle -
-   coeffiecnt for calculating the fairness timer */
+   coefficient for calculating the fairness timer */
 #define QM_ARB_BYTES                   40000
 #define FAIR_MEM                       2
 
index e3da7f69d27b8402916c7ba01f9e6ebd46625ea2..192fa981b9307b93f7509c370d3344fcdd4a67b2 100644 (file)
 
 
 #define CSTORM_ASSERT_LIST_INDEX_OFFSET \
-       (IS_E1H_OFFSET? 0x7000 : 0x1000)
+       (IS_E1H_OFFSET ? 0x7000 : 0x1000)
 #define CSTORM_ASSERT_LIST_OFFSET(idx) \
-       (IS_E1H_OFFSET? (0x7020 + (idx * 0x10)) : (0x1020 + (idx * 0x10)))
+       (IS_E1H_OFFSET ? (0x7020 + (idx * 0x10)) : (0x1020 + (idx * 0x10)))
 #define CSTORM_DEF_SB_HC_DISABLE_OFFSET(function, index) \
-       (IS_E1H_OFFSET? (0x8522 + ((function>>1) * 0x40) + ((function&1) \
-       * 0x100) + (index * 0x4)) : (0x1922 + (function * 0x40) + (index \
-       * 0x4)))
+       (IS_E1H_OFFSET ? (0x8522 + ((function>>1) * 0x40) + \
+       ((function&1) * 0x100) + (index * 0x4)) : (0x1922 + (function * \
+       0x40) + (index * 0x4)))
 #define CSTORM_DEF_SB_HOST_SB_ADDR_OFFSET(function) \
-       (IS_E1H_OFFSET? (0x8500 + ((function>>1) * 0x40) + ((function&1) \
-       * 0x100)) : (0x1900 + (function * 0x40)))
+       (IS_E1H_OFFSET ? (0x8500 + ((function>>1) * 0x40) + \
+       ((function&1) * 0x100)) : (0x1900 + (function * 0x40)))
 #define CSTORM_DEF_SB_HOST_STATUS_BLOCK_OFFSET(function) \
-       (IS_E1H_OFFSET? (0x8508 + ((function>>1) * 0x40) + ((function&1) \
-       * 0x100)) : (0x1908 + (function * 0x40)))
+       (IS_E1H_OFFSET ? (0x8508 + ((function>>1) * 0x40) + \
+       ((function&1) * 0x100)) : (0x1908 + (function * 0x40)))
 #define CSTORM_FUNCTION_MODE_OFFSET \
-       (IS_E1H_OFFSET? 0x11e8 : 0xffffffff)
+       (IS_E1H_OFFSET ? 0x11e8 : 0xffffffff)
 #define CSTORM_HC_BTR_OFFSET(port) \
-       (IS_E1H_OFFSET? (0x8704 + (port * 0xf0)) : (0x1984 + (port * 0xc0)))
+       (IS_E1H_OFFSET ? (0x8704 + (port * 0xf0)) : (0x1984 + (port * 0xc0)))
 #define CSTORM_SB_HC_DISABLE_OFFSET(port, cpu_id, index) \
-       (IS_E1H_OFFSET? (0x801a + (port * 0x280) + (cpu_id * 0x28) + \
+       (IS_E1H_OFFSET ? (0x801a + (port * 0x280) + (cpu_id * 0x28) + \
        (index * 0x4)) : (0x141a + (port * 0x280) + (cpu_id * 0x28) + \
        (index * 0x4)))
 #define CSTORM_SB_HC_TIMEOUT_OFFSET(port, cpu_id, index) \
-       (IS_E1H_OFFSET? (0x8018 + (port * 0x280) + (cpu_id * 0x28) + \
+       (IS_E1H_OFFSET ? (0x8018 + (port * 0x280) + (cpu_id * 0x28) + \
        (index * 0x4)) : (0x1418 + (port * 0x280) + (cpu_id * 0x28) + \
        (index * 0x4)))
 #define CSTORM_SB_HOST_SB_ADDR_OFFSET(port, cpu_id) \
-       (IS_E1H_OFFSET? (0x8000 + (port * 0x280) + (cpu_id * 0x28)) : \
+       (IS_E1H_OFFSET ? (0x8000 + (port * 0x280) + (cpu_id * 0x28)) : \
        (0x1400 + (port * 0x280) + (cpu_id * 0x28)))
 #define CSTORM_SB_HOST_STATUS_BLOCK_OFFSET(port, cpu_id) \
-       (IS_E1H_OFFSET? (0x8008 + (port * 0x280) + (cpu_id * 0x28)) : \
+       (IS_E1H_OFFSET ? (0x8008 + (port * 0x280) + (cpu_id * 0x28)) : \
        (0x1408 + (port * 0x280) + (cpu_id * 0x28)))
 #define CSTORM_STATS_FLAGS_OFFSET(function) \
-       (IS_E1H_OFFSET? (0x1108 + (function * 0x8)) : (0x5108 + \
+       (IS_E1H_OFFSET ? (0x1108 + (function * 0x8)) : (0x5108 + \
        (function * 0x8)))
 #define TSTORM_APPROXIMATE_MATCH_MULTICAST_FILTERING_OFFSET(function) \
-       (IS_E1H_OFFSET? (0x31c0 + (function * 0x20)) : 0xffffffff)
+       (IS_E1H_OFFSET ? (0x31c0 + (function * 0x20)) : 0xffffffff)
 #define TSTORM_ASSERT_LIST_INDEX_OFFSET \
-       (IS_E1H_OFFSET? 0xa000 : 0x1000)
+       (IS_E1H_OFFSET ? 0xa000 : 0x1000)
 #define TSTORM_ASSERT_LIST_OFFSET(idx) \
-       (IS_E1H_OFFSET? (0xa020 + (idx * 0x10)) : (0x1020 + (idx * 0x10)))
+       (IS_E1H_OFFSET ? (0xa020 + (idx * 0x10)) : (0x1020 + (idx * 0x10)))
 #define TSTORM_CLIENT_CONFIG_OFFSET(port, client_id) \
-       (IS_E1H_OFFSET? (0x3358 + (port * 0x3e8) + (client_id * 0x28)) : \
-       (0x9c8 + (port * 0x2f8) + (client_id * 0x28)))
+       (IS_E1H_OFFSET ? (0x3358 + (port * 0x3e8) + (client_id * 0x28)) \
+       (0x9c8 + (port * 0x2f8) + (client_id * 0x28)))
 #define TSTORM_DEF_SB_HC_DISABLE_OFFSET(function, index) \
-       (IS_E1H_OFFSET? (0xb01a + ((function>>1) * 0x28) + ((function&1) \
-       * 0xa0) + (index * 0x4)) : (0x141a + (function * 0x28) + (index * \
-       0x4)))
+       (IS_E1H_OFFSET ? (0xb01a + ((function>>1) * 0x28) + \
+       ((function&1) * 0xa0) + (index * 0x4)) : (0x141a + (function * \
+       0x28) + (index * 0x4)))
 #define TSTORM_DEF_SB_HOST_SB_ADDR_OFFSET(function) \
-       (IS_E1H_OFFSET? (0xb000 + ((function>>1) * 0x28) + ((function&1) \
-       * 0xa0)) : (0x1400 + (function * 0x28)))
+       (IS_E1H_OFFSET ? (0xb000 + ((function>>1) * 0x28) + \
+       ((function&1) * 0xa0)) : (0x1400 + (function * 0x28)))
 #define TSTORM_DEF_SB_HOST_STATUS_BLOCK_OFFSET(function) \
-       (IS_E1H_OFFSET? (0xb008 + ((function>>1) * 0x28) + ((function&1) \
-       * 0xa0)) : (0x1408 + (function * 0x28)))
+       (IS_E1H_OFFSET ? (0xb008 + ((function>>1) * 0x28) + \
+       ((function&1) * 0xa0)) : (0x1408 + (function * 0x28)))
 #define TSTORM_ETH_STATS_QUERY_ADDR_OFFSET(function) \
-       (IS_E1H_OFFSET? (0x2b80 + (function * 0x8)) : (0x4b68 + \
+       (IS_E1H_OFFSET ? (0x2b80 + (function * 0x8)) : (0x4b68 + \
        (function * 0x8)))
 #define TSTORM_FUNCTION_COMMON_CONFIG_OFFSET(function) \
-       (IS_E1H_OFFSET? (0x3000 + (function * 0x38)) : (0x1500 + \
+       (IS_E1H_OFFSET ? (0x3000 + (function * 0x38)) : (0x1500 + \
        (function * 0x38)))
 #define TSTORM_FUNCTION_MODE_OFFSET \
-       (IS_E1H_OFFSET? 0x1ad0 : 0xffffffff)
+       (IS_E1H_OFFSET ? 0x1ad0 : 0xffffffff)
 #define TSTORM_HC_BTR_OFFSET(port) \
-       (IS_E1H_OFFSET? (0xb144 + (port * 0x30)) : (0x1454 + (port * 0x18)))
+       (IS_E1H_OFFSET ? (0xb144 + (port * 0x30)) : (0x1454 + (port * 0x18)))
 #define TSTORM_INDIRECTION_TABLE_OFFSET(function) \
-       (IS_E1H_OFFSET? (0x12c8 + (function * 0x80)) : (0x22c8 + \
+       (IS_E1H_OFFSET ? (0x12c8 + (function * 0x80)) : (0x22c8 + \
        (function * 0x80)))
 #define TSTORM_INDIRECTION_TABLE_SIZE 0x80
 #define TSTORM_MAC_FILTER_CONFIG_OFFSET(function) \
-       (IS_E1H_OFFSET? (0x3008 + (function * 0x38)) : (0x1508 + \
+       (IS_E1H_OFFSET ? (0x3008 + (function * 0x38)) : (0x1508 + \
        (function * 0x38)))
+#define TSTORM_PER_COUNTER_ID_STATS_OFFSET(port, stats_counter_id) \
+       (IS_E1H_OFFSET ? (0x2010 + (port * 0x5b0) + (stats_counter_id * \
+       0x50)) : (0x4000 + (port * 0x3f0) + (stats_counter_id * 0x38)))
 #define TSTORM_RX_PRODS_OFFSET(port, client_id) \
-       (IS_E1H_OFFSET? (0x3350 + (port * 0x3e8) + (client_id * 0x28)) : \
-       (0x9c0 + (port * 0x2f8) + (client_id * 0x28)))
+       (IS_E1H_OFFSET ? (0x3350 + (port * 0x3e8) + (client_id * 0x28)) \
+       (0x9c0 + (port * 0x2f8) + (client_id * 0x28)))
 #define TSTORM_STATS_FLAGS_OFFSET(function) \
-       (IS_E1H_OFFSET? (0x2c00 + (function * 0x8)) : (0x4b88 + \
+       (IS_E1H_OFFSET ? (0x2c00 + (function * 0x8)) : (0x4b88 + \
        (function * 0x8)))
-#define TSTORM_TPA_EXIST_OFFSET (IS_E1H_OFFSET? 0x3b30 : 0x1c20)
-#define USTORM_AGG_DATA_OFFSET (IS_E1H_OFFSET? 0xa040 : 0x2c10)
-#define USTORM_AGG_DATA_SIZE (IS_E1H_OFFSET? 0x2440 : 0x1200)
+#define TSTORM_TPA_EXIST_OFFSET (IS_E1H_OFFSET ? 0x3b30 : 0x1c20)
+#define USTORM_AGG_DATA_OFFSET (IS_E1H_OFFSET ? 0xa040 : 0x2c10)
+#define USTORM_AGG_DATA_SIZE (IS_E1H_OFFSET ? 0x2440 : 0x1200)
 #define USTORM_ASSERT_LIST_INDEX_OFFSET \
-       (IS_E1H_OFFSET? 0x8000 : 0x1000)
+       (IS_E1H_OFFSET ? 0x8000 : 0x1000)
 #define USTORM_ASSERT_LIST_OFFSET(idx) \
-       (IS_E1H_OFFSET? (0x8020 + (idx * 0x10)) : (0x1020 + (idx * 0x10)))
+       (IS_E1H_OFFSET ? (0x8020 + (idx * 0x10)) : (0x1020 + (idx * 0x10)))
 #define USTORM_CQE_PAGE_BASE_OFFSET(port, clientId) \
-       (IS_E1H_OFFSET? (0x3298 + (port * 0x258) + (clientId * 0x18)) : \
+       (IS_E1H_OFFSET ? (0x3298 + (port * 0x258) + (clientId * 0x18)) : \
        (0x5450 + (port * 0x1c8) + (clientId * 0x18)))
 #define USTORM_DEF_SB_HC_DISABLE_OFFSET(function, index) \
-       (IS_E1H_OFFSET? (0x951a + ((function>>1) * 0x28) + ((function&1) \
-       * 0xa0) + (index * 0x4)) : (0x191a + (function * 0x28) + (index * \
-       0x4)))
+       (IS_E1H_OFFSET ? (0x951a + ((function>>1) * 0x28) + \
+       ((function&1) * 0xa0) + (index * 0x4)) : (0x191a + (function * \
+       0x28) + (index * 0x4)))
 #define USTORM_DEF_SB_HOST_SB_ADDR_OFFSET(function) \
-       (IS_E1H_OFFSET? (0x9500 + ((function>>1) * 0x28) + ((function&1) \
-       * 0xa0)) : (0x1900 + (function * 0x28)))
+       (IS_E1H_OFFSET ? (0x9500 + ((function>>1) * 0x28) + \
+       ((function&1) * 0xa0)) : (0x1900 + (function * 0x28)))
 #define USTORM_DEF_SB_HOST_STATUS_BLOCK_OFFSET(function) \
-       (IS_E1H_OFFSET? (0x9508 + ((function>>1) * 0x28) + ((function&1) \
-       * 0xa0)) : (0x1908 + (function * 0x28)))
+       (IS_E1H_OFFSET ? (0x9508 + ((function>>1) * 0x28) + \
+       ((function&1) * 0xa0)) : (0x1908 + (function * 0x28)))
 #define USTORM_FUNCTION_MODE_OFFSET \
-       (IS_E1H_OFFSET? 0x2448 : 0xffffffff)
+       (IS_E1H_OFFSET ? 0x2448 : 0xffffffff)
 #define USTORM_HC_BTR_OFFSET(port) \
-       (IS_E1H_OFFSET? (0x9644 + (port * 0xd0)) : (0x1954 + (port * 0xb8)))
+       (IS_E1H_OFFSET ? (0x9644 + (port * 0xd0)) : (0x1954 + (port * 0xb8)))
 #define USTORM_MAX_AGG_SIZE_OFFSET(port, clientId) \
-       (IS_E1H_OFFSET? (0x3290 + (port * 0x258) + (clientId * 0x18)) : \
+       (IS_E1H_OFFSET ? (0x3290 + (port * 0x258) + (clientId * 0x18)) : \
        (0x5448 + (port * 0x1c8) + (clientId * 0x18)))
 #define USTORM_MEM_WORKAROUND_ADDRESS_OFFSET(function) \
-       (IS_E1H_OFFSET? (0x2408 + (function * 0x8)) : (0x5408 + \
+       (IS_E1H_OFFSET ? (0x2408 + (function * 0x8)) : (0x5408 + \
        (function * 0x8)))
 #define USTORM_SB_HC_DISABLE_OFFSET(port, cpu_id, index) \
-       (IS_E1H_OFFSET? (0x901a + (port * 0x280) + (cpu_id * 0x28) + \
+       (IS_E1H_OFFSET ? (0x901a + (port * 0x280) + (cpu_id * 0x28) + \
        (index * 0x4)) : (0x141a + (port * 0x280) + (cpu_id * 0x28) + \
        (index * 0x4)))
 #define USTORM_SB_HC_TIMEOUT_OFFSET(port, cpu_id, index) \
-       (IS_E1H_OFFSET? (0x9018 + (port * 0x280) + (cpu_id * 0x28) + \
+       (IS_E1H_OFFSET ? (0x9018 + (port * 0x280) + (cpu_id * 0x28) + \
        (index * 0x4)) : (0x1418 + (port * 0x280) + (cpu_id * 0x28) + \
        (index * 0x4)))
 #define USTORM_SB_HOST_SB_ADDR_OFFSET(port, cpu_id) \
-       (IS_E1H_OFFSET? (0x9000 + (port * 0x280) + (cpu_id * 0x28)) : \
+       (IS_E1H_OFFSET ? (0x9000 + (port * 0x280) + (cpu_id * 0x28)) : \
        (0x1400 + (port * 0x280) + (cpu_id * 0x28)))
 #define USTORM_SB_HOST_STATUS_BLOCK_OFFSET(port, cpu_id) \
-       (IS_E1H_OFFSET? (0x9008 + (port * 0x280) + (cpu_id * 0x28)) : \
+       (IS_E1H_OFFSET ? (0x9008 + (port * 0x280) + (cpu_id * 0x28)) : \
        (0x1408 + (port * 0x280) + (cpu_id * 0x28)))
 #define XSTORM_ASSERT_LIST_INDEX_OFFSET \
-       (IS_E1H_OFFSET? 0x9000 : 0x1000)
+       (IS_E1H_OFFSET ? 0x9000 : 0x1000)
 #define XSTORM_ASSERT_LIST_OFFSET(idx) \
-       (IS_E1H_OFFSET? (0x9020 + (idx * 0x10)) : (0x1020 + (idx * 0x10)))
+       (IS_E1H_OFFSET ? (0x9020 + (idx * 0x10)) : (0x1020 + (idx * 0x10)))
 #define XSTORM_CMNG_PER_PORT_VARS_OFFSET(port) \
-       (IS_E1H_OFFSET? (0x24a8 + (port * 0x40)) : (0x3ba0 + (port * 0x40)))
+       (IS_E1H_OFFSET ? (0x24a8 + (port * 0x40)) : (0x3ba0 + (port * 0x40)))
 #define XSTORM_DEF_SB_HC_DISABLE_OFFSET(function, index) \
-       (IS_E1H_OFFSET? (0xa01a + ((function>>1) * 0x28) + ((function&1) \
-       * 0xa0) + (index * 0x4)) : (0x141a + (function * 0x28) + (index * \
-       0x4)))
+       (IS_E1H_OFFSET ? (0xa01a + ((function>>1) * 0x28) + \
+       ((function&1) * 0xa0) + (index * 0x4)) : (0x141a + (function * \
+       0x28) + (index * 0x4)))
 #define XSTORM_DEF_SB_HOST_SB_ADDR_OFFSET(function) \
-       (IS_E1H_OFFSET? (0xa000 + ((function>>1) * 0x28) + ((function&1) \
-       * 0xa0)) : (0x1400 + (function * 0x28)))
+       (IS_E1H_OFFSET ? (0xa000 + ((function>>1) * 0x28) + \
+       ((function&1) * 0xa0)) : (0x1400 + (function * 0x28)))
 #define XSTORM_DEF_SB_HOST_STATUS_BLOCK_OFFSET(function) \
-       (IS_E1H_OFFSET? (0xa008 + ((function>>1) * 0x28) + ((function&1) \
-       * 0xa0)) : (0x1408 + (function * 0x28)))
+       (IS_E1H_OFFSET ? (0xa008 + ((function>>1) * 0x28) + \
+       ((function&1) * 0xa0)) : (0x1408 + (function * 0x28)))
 #define XSTORM_E1HOV_OFFSET(function) \
-       (IS_E1H_OFFSET? (0x2ab8 + (function * 0x2)) : 0xffffffff)
+       (IS_E1H_OFFSET ? (0x2ab8 + (function * 0x2)) : 0xffffffff)
 #define XSTORM_ETH_STATS_QUERY_ADDR_OFFSET(function) \
-       (IS_E1H_OFFSET? (0x2418 + (function * 0x8)) : (0x3b70 + \
+       (IS_E1H_OFFSET ? (0x2418 + (function * 0x8)) : (0x3b70 + \
        (function * 0x8)))
 #define XSTORM_FAIRNESS_PER_VN_VARS_OFFSET(function) \
-       (IS_E1H_OFFSET? (0x2568 + (function * 0x70)) : (0x3c60 + \
+       (IS_E1H_OFFSET ? (0x2568 + (function * 0x70)) : (0x3c60 + \
        (function * 0x70)))
 #define XSTORM_FUNCTION_MODE_OFFSET \
-       (IS_E1H_OFFSET? 0x2ac8 : 0xffffffff)
+       (IS_E1H_OFFSET ? 0x2ac8 : 0xffffffff)
 #define XSTORM_HC_BTR_OFFSET(port) \
-       (IS_E1H_OFFSET? (0xa144 + (port * 0x30)) : (0x1454 + (port * 0x18)))
+       (IS_E1H_OFFSET ? (0xa144 + (port * 0x30)) : (0x1454 + (port * 0x18)))
+#define XSTORM_PER_COUNTER_ID_STATS_OFFSET(port, stats_counter_id) \
+       (IS_E1H_OFFSET ? (0xc000 + (port * 0x3f0) + (stats_counter_id * \
+       0x38)) : (0x3378 + (port * 0x3f0) + (stats_counter_id * 0x38)))
 #define XSTORM_RATE_SHAPING_PER_VN_VARS_OFFSET(function) \
-       (IS_E1H_OFFSET? (0x2528 + (function * 0x70)) : (0x3c20 + \
+       (IS_E1H_OFFSET ? (0x2528 + (function * 0x70)) : (0x3c20 + \
        (function * 0x70)))
 #define XSTORM_SPQ_PAGE_BASE_OFFSET(function) \
-       (IS_E1H_OFFSET? (0x2000 + (function * 0x10)) : (0x3328 + \
+       (IS_E1H_OFFSET ? (0x2000 + (function * 0x10)) : (0x3328 + \
        (function * 0x10)))
 #define XSTORM_SPQ_PROD_OFFSET(function) \
-       (IS_E1H_OFFSET? (0x2008 + (function * 0x10)) : (0x3330 + \
+       (IS_E1H_OFFSET ? (0x2008 + (function * 0x10)) : (0x3330 + \
        (function * 0x10)))
 #define XSTORM_STATS_FLAGS_OFFSET(function) \
-       (IS_E1H_OFFSET? (0x23d8 + (function * 0x8)) : (0x3b60 + \
+       (IS_E1H_OFFSET ? (0x23d8 + (function * 0x8)) : (0x3b60 + \
        (function * 0x8)))
 #define COMMON_ASM_INVALID_ASSERT_OPCODE 0x0
 
index d3e8198d7dba1dc6bfc1fd0696df3c178bc7ade9..efd764427fa12785284a924f2a8f7ca2e8dc98eb 100644 (file)
@@ -1268,7 +1268,7 @@ struct doorbell {
 
 
 /*
- * IGU driver acknowlegement register
+ * IGU driver acknowledgement register
  */
 struct igu_ack_register {
 #if defined(__BIG_ENDIAN)
@@ -1882,7 +1882,7 @@ struct timers_block_context {
 };
 
 /*
- * structure for easy accessability to assembler
+ * structure for easy accessibility to assembler
  */
 struct eth_tx_bd_flags {
        u8 as_bitfield;
@@ -2044,7 +2044,7 @@ struct eth_context {
 
 
 /*
- * ethernet doorbell
+ * Ethernet doorbell
  */
 struct eth_tx_doorbell {
 #if defined(__BIG_ENDIAN)
@@ -2256,7 +2256,7 @@ struct ramrod_data {
 };
 
 /*
- * union for ramrod data for ethernet protocol (CQE) (force size of 16 bits)
+ * union for ramrod data for Ethernet protocol (CQE) (force size of 16 bits)
  */
 union eth_ramrod_data {
        struct ramrod_data general;
@@ -2330,7 +2330,7 @@ struct spe_hdr {
 };
 
 /*
- * ethernet slow path element
+ * Ethernet slow path element
  */
 union eth_specific_data {
        u8 protocol_data[8];
@@ -2343,7 +2343,7 @@ union eth_specific_data {
 };
 
 /*
- * ethernet slow path element
+ * Ethernet slow path element
  */
 struct eth_spe {
        struct spe_hdr hdr;
@@ -2615,7 +2615,7 @@ struct tstorm_eth_rx_producers {
 
 
 /*
- * common flag to indicate existance of TPA.
+ * common flag to indicate existence of TPA.
  */
 struct tstorm_eth_tpa_exist {
 #if defined(__BIG_ENDIAN)
@@ -2765,7 +2765,7 @@ struct tstorm_common_stats {
 };
 
 /*
- * Eth statistics query sturcture for the eth_stats_quesry ramrod
+ * Eth statistics query structure for the eth_stats_query ramrod
  */
 struct eth_stats_query {
        struct xstorm_common_stats xstorm_common;
index 4c7750789b62309ca7d410c51122dbafa395d394..130927cfc75b63c79f986280029ddc4596f81c46 100644 (file)
 
 
 struct raw_op {
-       u32 op          :8;
-       u32 offset      :24;
+       u32 op:8;
+       u32 offset:24;
        u32 raw_data;
 };
 
 struct op_read {
-       u32 op          :8;
-       u32 offset      :24;
+       u32 op:8;
+       u32 offset:24;
        u32 pad;
 };
 
 struct op_write {
-       u32 op          :8;
-       u32 offset      :24;
+       u32 op:8;
+       u32 offset:24;
        u32 val;
 };
 
 struct op_string_write {
-       u32 op          :8;
-       u32 offset      :24;
+       u32 op:8;
+       u32 offset:24;
 #ifdef __LITTLE_ENDIAN
        u16 data_off;
        u16 data_len;
@@ -102,8 +102,8 @@ struct op_string_write {
 };
 
 struct op_zero {
-       u32 op          :8;
-       u32 offset      :24;
+       u32 op:8;
+       u32 offset:24;
        u32 len;
 };
 
@@ -208,7 +208,7 @@ static void bnx2x_init_wr_64(struct bnx2x *bp, u32 addr, const u32 *data,
 /*********************************************************
    There are different blobs for each PRAM section.
    In addition, each blob write operation is divided into a few operations
-   in order to decrease the amount of phys. contigious buffer needed.
+   in order to decrease the amount of phys. contiguous buffer needed.
    Thus, when we select a blob the address may be with some offset
    from the beginning of PRAM section.
    The same holds for the INT_TABLE sections.
@@ -336,7 +336,7 @@ static void bnx2x_init_block(struct bnx2x *bp, u32 op_start, u32 op_end)
                len = op->str_wr.data_len;
                data = data_base + op->str_wr.data_off;
 
-               /* carefull! it must be in order */
+               /* careful! it must be in order */
                if (unlikely(op_type > OP_WB)) {
 
                        /* If E1 only */
@@ -740,7 +740,7 @@ static u8 calc_crc8(u32 data, u8 crc)
        return crc_res;
 }
 
-/* regiesers addresses are not in order
+/* registers addresses are not in order
    so these arrays help simplify the code */
 static const int cm_start[E1H_FUNC_MAX][9] = {
        {MISC_FUNC0_START, TCM_FUNC0_START, UCM_FUNC0_START, CCM_FUNC0_START,
index 63019055e4bb56962ba5767f662136a787921c4f..9755bf6b08ddff3b4abe47fd2d573e3676912dee 100644 (file)
@@ -901,31 +901,28 @@ static const struct raw_op init_ops[] = {
        {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x3760, 0x4},
        {OP_ZR_E1, USEM_REG_FAST_MEMORY + 0x1e20, 0x42},
        {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x3738, 0x9},
-       {OP_ZR_E1, USEM_REG_FAST_MEMORY + 0x3000, 0x400},
+       {OP_ZR_E1, USEM_REG_FAST_MEMORY + 0x4b68, 0x2},
        {OP_SW_E1H, USEM_REG_FAST_MEMORY + 0x3738 + 0x24, 0x10293},
-       {OP_ZR_E1, USEM_REG_FAST_MEMORY + 0x2c00, 0x2},
+       {OP_SW_E1, USEM_REG_FAST_MEMORY + 0x4b68 + 0x8, 0x20278},
        {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x3180, 0x42},
-       {OP_SW_E1, USEM_REG_FAST_MEMORY + 0x2c00 + 0x8, 0x20278},
+       {OP_ZR_E1, USEM_REG_FAST_MEMORY + 0x4b10, 0x2},
        {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x5000, 0x400},
-       {OP_ZR_E1, USEM_REG_FAST_MEMORY + 0x4b68, 0x2},
+       {OP_SW_E1, USEM_REG_FAST_MEMORY + 0x2830, 0x2027a},
        {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x4000, 0x2},
-       {OP_SW_E1, USEM_REG_FAST_MEMORY + 0x4b68 + 0x8, 0x2027a},
        {OP_SW_E1H, USEM_REG_FAST_MEMORY + 0x4000 + 0x8, 0x20294},
-       {OP_ZR_E1, USEM_REG_FAST_MEMORY + 0x4b10, 0x2},
        {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x6b68, 0x2},
-       {OP_SW_E1, USEM_REG_FAST_MEMORY + 0x2830, 0x2027c},
        {OP_SW_E1H, USEM_REG_FAST_MEMORY + 0x6b68 + 0x8, 0x20296},
        {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x6b10, 0x2},
        {OP_SW_E1H, USEM_REG_FAST_MEMORY + 0x74c0, 0x20298},
        {OP_WR, USEM_REG_FAST_MEMORY + 0x10800, 0x1000000},
-       {OP_SW_E1, USEM_REG_FAST_MEMORY + 0x10c00, 0x10027e},
+       {OP_SW_E1, USEM_REG_FAST_MEMORY + 0x10c00, 0x10027c},
        {OP_SW_E1H, USEM_REG_FAST_MEMORY + 0x10c00, 0x10029a},
        {OP_WR, USEM_REG_FAST_MEMORY + 0x10800, 0x0},
-       {OP_SW_E1, USEM_REG_FAST_MEMORY + 0x10c40, 0x10028e},
+       {OP_SW_E1, USEM_REG_FAST_MEMORY + 0x10c40, 0x10028c},
        {OP_SW_E1H, USEM_REG_FAST_MEMORY + 0x10c40, 0x1002aa},
        {OP_ZP_E1, USEM_REG_INT_TABLE, 0xc20000},
        {OP_ZP_E1H, USEM_REG_INT_TABLE, 0xc40000},
-       {OP_WR_64_E1, USEM_REG_INT_TABLE + 0x368, 0x13029e},
+       {OP_WR_64_E1, USEM_REG_INT_TABLE + 0x368, 0x13029c},
        {OP_WR_64_E1H, USEM_REG_INT_TABLE + 0x368, 0x1302ba},
        {OP_ZP_E1, USEM_REG_PRAM, 0x311c0000},
        {OP_ZP_E1H, USEM_REG_PRAM, 0x31070000},
@@ -933,11 +930,11 @@ static const struct raw_op init_ops[] = {
        {OP_ZP_E1H, USEM_REG_PRAM + 0x8000, 0x330e0c42},
        {OP_ZP_E1, USEM_REG_PRAM + 0x10000, 0x38561919},
        {OP_ZP_E1H, USEM_REG_PRAM + 0x10000, 0x389b1906},
-       {OP_WR_64_E1, USEM_REG_PRAM + 0x17fe0, 0x500402a0},
+       {OP_WR_64_E1, USEM_REG_PRAM + 0x17fe0, 0x5004029e},
        {OP_ZP_E1H, USEM_REG_PRAM + 0x18000, 0x132272d},
        {OP_WR_64_E1H, USEM_REG_PRAM + 0x18250, 0x4fb602bc},
-#define USEM_COMMON_END         790
-#define USEM_PORT0_START        790
+#define USEM_COMMON_END         787
+#define USEM_PORT0_START        787
        {OP_ZR_E1, USEM_REG_FAST_MEMORY + 0x1400, 0xa0},
        {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x9000, 0xa0},
        {OP_ZR_E1, USEM_REG_FAST_MEMORY + 0x1900, 0xa},
@@ -950,44 +947,27 @@ static const struct raw_op init_ops[] = {
        {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x3288, 0x96},
        {OP_ZR_E1, USEM_REG_FAST_MEMORY + 0x5440, 0x72},
        {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x5000, 0x20},
-       {OP_ZR_E1, USEM_REG_FAST_MEMORY + 0x3000, 0x20},
+       {OP_ZR_E1, USEM_REG_FAST_MEMORY + 0x4b78, 0x52},
        {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x5100, 0x20},
-       {OP_ZR_E1, USEM_REG_FAST_MEMORY + 0x3100, 0x20},
+       {OP_ZR_E1, USEM_REG_FAST_MEMORY + 0x4e08, 0xc},
        {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x5200, 0x20},
-       {OP_ZR_E1, USEM_REG_FAST_MEMORY + 0x3200, 0x20},
        {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x5300, 0x20},
-       {OP_ZR_E1, USEM_REG_FAST_MEMORY + 0x3300, 0x20},
        {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x5400, 0x20},
-       {OP_ZR_E1, USEM_REG_FAST_MEMORY + 0x3400, 0x20},
        {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x5500, 0x20},
-       {OP_ZR_E1, USEM_REG_FAST_MEMORY + 0x3500, 0x20},
        {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x5600, 0x20},
-       {OP_ZR_E1, USEM_REG_FAST_MEMORY + 0x3600, 0x20},
        {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x5700, 0x20},
-       {OP_ZR_E1, USEM_REG_FAST_MEMORY + 0x3700, 0x20},
        {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x5800, 0x20},
-       {OP_ZR_E1, USEM_REG_FAST_MEMORY + 0x3800, 0x20},
        {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x5900, 0x20},
-       {OP_ZR_E1, USEM_REG_FAST_MEMORY + 0x3900, 0x20},
        {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x5a00, 0x20},
-       {OP_ZR_E1, USEM_REG_FAST_MEMORY + 0x3a00, 0x20},
        {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x5b00, 0x20},
-       {OP_ZR_E1, USEM_REG_FAST_MEMORY + 0x3b00, 0x20},
        {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x5c00, 0x20},
-       {OP_ZR_E1, USEM_REG_FAST_MEMORY + 0x3c00, 0x20},
        {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x5d00, 0x20},
-       {OP_ZR_E1, USEM_REG_FAST_MEMORY + 0x3d00, 0x20},
        {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x5e00, 0x20},
-       {OP_ZR_E1, USEM_REG_FAST_MEMORY + 0x3e00, 0x20},
        {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x5f00, 0x20},
-       {OP_ZR_E1, USEM_REG_FAST_MEMORY + 0x3f00, 0x20},
        {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x6b78, 0x52},
-       {OP_ZR_E1, USEM_REG_FAST_MEMORY + 0x2c10, 0x2},
        {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x6e08, 0xc},
-       {OP_ZR_E1, USEM_REG_FAST_MEMORY + 0x4b78, 0x52},
-       {OP_ZR_E1, USEM_REG_FAST_MEMORY + 0x4e08, 0xc},
-#define USEM_PORT0_END          838
-#define USEM_PORT1_START        838
+#define USEM_PORT0_END          818
+#define USEM_PORT1_START        818
        {OP_ZR_E1, USEM_REG_FAST_MEMORY + 0x1680, 0xa0},
        {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x9280, 0xa0},
        {OP_ZR_E1, USEM_REG_FAST_MEMORY + 0x1928, 0xa},
@@ -1000,76 +980,59 @@ static const struct raw_op init_ops[] = {
        {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x34e0, 0x96},
        {OP_ZR_E1, USEM_REG_FAST_MEMORY + 0x5608, 0x72},
        {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x5080, 0x20},
-       {OP_ZR_E1, USEM_REG_FAST_MEMORY + 0x3080, 0x20},
+       {OP_ZR_E1, USEM_REG_FAST_MEMORY + 0x4cc0, 0x52},
        {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x5180, 0x20},
-       {OP_ZR_E1, USEM_REG_FAST_MEMORY + 0x3180, 0x20},
+       {OP_ZR_E1, USEM_REG_FAST_MEMORY + 0x4e38, 0xc},
        {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x5280, 0x20},
-       {OP_ZR_E1, USEM_REG_FAST_MEMORY + 0x3280, 0x20},
        {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x5380, 0x20},
-       {OP_ZR_E1, USEM_REG_FAST_MEMORY + 0x3380, 0x20},
        {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x5480, 0x20},
-       {OP_ZR_E1, USEM_REG_FAST_MEMORY + 0x3480, 0x20},
        {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x5580, 0x20},
-       {OP_ZR_E1, USEM_REG_FAST_MEMORY + 0x3580, 0x20},
        {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x5680, 0x20},
-       {OP_ZR_E1, USEM_REG_FAST_MEMORY + 0x3680, 0x20},
        {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x5780, 0x20},
-       {OP_ZR_E1, USEM_REG_FAST_MEMORY + 0x3780, 0x20},
        {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x5880, 0x20},
-       {OP_ZR_E1, USEM_REG_FAST_MEMORY + 0x3880, 0x20},
        {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x5980, 0x20},
-       {OP_ZR_E1, USEM_REG_FAST_MEMORY + 0x3980, 0x20},
        {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x5a80, 0x20},
-       {OP_ZR_E1, USEM_REG_FAST_MEMORY + 0x3a80, 0x20},
        {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x5b80, 0x20},
-       {OP_ZR_E1, USEM_REG_FAST_MEMORY + 0x3b80, 0x20},
        {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x5c80, 0x20},
-       {OP_ZR_E1, USEM_REG_FAST_MEMORY + 0x3c80, 0x20},
        {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x5d80, 0x20},
-       {OP_ZR_E1, USEM_REG_FAST_MEMORY + 0x3d80, 0x20},
        {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x5e80, 0x20},
-       {OP_ZR_E1, USEM_REG_FAST_MEMORY + 0x3e80, 0x20},
        {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x5f80, 0x20},
-       {OP_ZR_E1, USEM_REG_FAST_MEMORY + 0x3f80, 0x20},
        {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x6cc0, 0x52},
-       {OP_ZR_E1, USEM_REG_FAST_MEMORY + 0x2c20, 0x2},
        {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x6e38, 0xc},
-       {OP_ZR_E1, USEM_REG_FAST_MEMORY + 0x4cc0, 0x52},
-       {OP_ZR_E1, USEM_REG_FAST_MEMORY + 0x4e38, 0xc},
-#define USEM_PORT1_END          886
-#define USEM_FUNC0_START        886
+#define USEM_PORT1_END          849
+#define USEM_FUNC0_START        849
        {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x3000, 0x4},
        {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x4010, 0x2},
-#define USEM_FUNC0_END          888
-#define USEM_FUNC1_START        888
+#define USEM_FUNC0_END          851
+#define USEM_FUNC1_START        851
        {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x3010, 0x4},
        {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x4020, 0x2},
-#define USEM_FUNC1_END          890
-#define USEM_FUNC2_START        890
+#define USEM_FUNC1_END          853
+#define USEM_FUNC2_START        853
        {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x3020, 0x4},
        {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x4030, 0x2},
-#define USEM_FUNC2_END          892
-#define USEM_FUNC3_START        892
+#define USEM_FUNC2_END          855
+#define USEM_FUNC3_START        855
        {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x3030, 0x4},
        {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x4040, 0x2},
-#define USEM_FUNC3_END          894
-#define USEM_FUNC4_START        894
+#define USEM_FUNC3_END          857
+#define USEM_FUNC4_START        857
        {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x3040, 0x4},
        {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x4050, 0x2},
-#define USEM_FUNC4_END          896
-#define USEM_FUNC5_START        896
+#define USEM_FUNC4_END          859
+#define USEM_FUNC5_START        859
        {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x3050, 0x4},
        {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x4060, 0x2},
-#define USEM_FUNC5_END          898
-#define USEM_FUNC6_START        898
+#define USEM_FUNC5_END          861
+#define USEM_FUNC6_START        861
        {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x3060, 0x4},
        {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x4070, 0x2},
-#define USEM_FUNC6_END          900
-#define USEM_FUNC7_START        900
+#define USEM_FUNC6_END          863
+#define USEM_FUNC7_START        863
        {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x3070, 0x4},
        {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x4080, 0x2},
-#define USEM_FUNC7_END          902
-#define CSEM_COMMON_START       902
+#define USEM_FUNC7_END          865
+#define CSEM_COMMON_START       865
        {OP_RD, CSEM_REG_MSG_NUM_FIC0, 0x0},
        {OP_RD, CSEM_REG_MSG_NUM_FIC1, 0x0},
        {OP_RD, CSEM_REG_MSG_NUM_FOC0, 0x0},
@@ -1128,29 +1091,29 @@ static const struct raw_op init_ops[] = {
        {OP_WR_E1H, CSEM_REG_FAST_MEMORY + 0x11e8, 0x0},
        {OP_ZR_E1, CSEM_REG_FAST_MEMORY + 0x25c0, 0x240},
        {OP_ZR_E1H, CSEM_REG_FAST_MEMORY + 0x3000, 0xc0},
-       {OP_SW_E1, CSEM_REG_FAST_MEMORY + 0x2ec8, 0x802a2},
+       {OP_SW_E1, CSEM_REG_FAST_MEMORY + 0x2ec8, 0x802a0},
        {OP_ZR_E1H, CSEM_REG_FAST_MEMORY + 0x4070, 0x80},
        {OP_ZR_E1H, CSEM_REG_FAST_MEMORY + 0x5280, 0x4},
        {OP_ZR_E1H, CSEM_REG_FAST_MEMORY + 0x6280, 0x240},
        {OP_SW_E1H, CSEM_REG_FAST_MEMORY + 0x6b88, 0x2002be},
        {OP_WR, CSEM_REG_FAST_MEMORY + 0x10800, 0x13fffff},
-       {OP_SW_E1, CSEM_REG_FAST_MEMORY + 0x10c00, 0x1002aa},
+       {OP_SW_E1, CSEM_REG_FAST_MEMORY + 0x10c00, 0x1002a8},
        {OP_SW_E1H, CSEM_REG_FAST_MEMORY + 0x10c00, 0x1002de},
        {OP_WR, CSEM_REG_FAST_MEMORY + 0x10800, 0x0},
-       {OP_SW_E1, CSEM_REG_FAST_MEMORY + 0x10c40, 0x1002ba},
+       {OP_SW_E1, CSEM_REG_FAST_MEMORY + 0x10c40, 0x1002b8},
        {OP_SW_E1H, CSEM_REG_FAST_MEMORY + 0x10c40, 0x1002ee},
        {OP_ZP_E1, CSEM_REG_INT_TABLE, 0x6e0000},
        {OP_ZP_E1H, CSEM_REG_INT_TABLE, 0x6f0000},
-       {OP_WR_64_E1, CSEM_REG_INT_TABLE + 0x380, 0x1002ca},
+       {OP_WR_64_E1, CSEM_REG_INT_TABLE + 0x380, 0x1002c8},
        {OP_WR_64_E1H, CSEM_REG_INT_TABLE + 0x380, 0x1002fe},
        {OP_ZP_E1, CSEM_REG_PRAM, 0x32580000},
        {OP_ZP_E1H, CSEM_REG_PRAM, 0x31fa0000},
        {OP_ZP_E1, CSEM_REG_PRAM + 0x8000, 0x18270c96},
        {OP_ZP_E1H, CSEM_REG_PRAM + 0x8000, 0x19040c7f},
-       {OP_WR_64_E1, CSEM_REG_PRAM + 0xb210, 0x682402cc},
+       {OP_WR_64_E1, CSEM_REG_PRAM + 0xb210, 0x682402ca},
        {OP_WR_64_E1H, CSEM_REG_PRAM + 0xb430, 0x67e00300},
-#define CSEM_COMMON_END         981
-#define CSEM_PORT0_START        981
+#define CSEM_COMMON_END         944
+#define CSEM_PORT0_START        944
        {OP_ZR_E1, CSEM_REG_FAST_MEMORY + 0x1400, 0xa0},
        {OP_ZR_E1H, CSEM_REG_FAST_MEMORY + 0x8000, 0xa0},
        {OP_ZR_E1, CSEM_REG_FAST_MEMORY + 0x1900, 0x10},
@@ -1163,8 +1126,8 @@ static const struct raw_op init_ops[] = {
        {OP_ZR_E1H, CSEM_REG_FAST_MEMORY + 0x6040, 0x30},
        {OP_ZR_E1, CSEM_REG_FAST_MEMORY + 0x3040, 0x6},
        {OP_ZR_E1, CSEM_REG_FAST_MEMORY + 0x2410, 0x30},
-#define CSEM_PORT0_END          993
-#define CSEM_PORT1_START        993
+#define CSEM_PORT0_END          956
+#define CSEM_PORT1_START        956
        {OP_ZR_E1, CSEM_REG_FAST_MEMORY + 0x1680, 0xa0},
        {OP_ZR_E1H, CSEM_REG_FAST_MEMORY + 0x8280, 0xa0},
        {OP_ZR_E1, CSEM_REG_FAST_MEMORY + 0x1940, 0x10},
@@ -1177,43 +1140,43 @@ static const struct raw_op init_ops[] = {
        {OP_ZR_E1H, CSEM_REG_FAST_MEMORY + 0x6100, 0x30},
        {OP_ZR_E1, CSEM_REG_FAST_MEMORY + 0x3058, 0x6},
        {OP_ZR_E1, CSEM_REG_FAST_MEMORY + 0x24d0, 0x30},
-#define CSEM_PORT1_END          1005
-#define CSEM_FUNC0_START        1005
+#define CSEM_PORT1_END          968
+#define CSEM_FUNC0_START        968
        {OP_WR_E1H, CSEM_REG_FAST_MEMORY + 0x1148, 0x0},
        {OP_ZR_E1H, CSEM_REG_FAST_MEMORY + 0x3300, 0x2},
-#define CSEM_FUNC0_END          1007
-#define CSEM_FUNC1_START        1007
+#define CSEM_FUNC0_END          970
+#define CSEM_FUNC1_START        970
        {OP_WR_E1H, CSEM_REG_FAST_MEMORY + 0x114c, 0x0},
        {OP_ZR_E1H, CSEM_REG_FAST_MEMORY + 0x3308, 0x2},
-#define CSEM_FUNC1_END          1009
-#define CSEM_FUNC2_START        1009
+#define CSEM_FUNC1_END          972
+#define CSEM_FUNC2_START        972
        {OP_WR_E1H, CSEM_REG_FAST_MEMORY + 0x1150, 0x0},
        {OP_ZR_E1H, CSEM_REG_FAST_MEMORY + 0x3310, 0x2},
-#define CSEM_FUNC2_END          1011
-#define CSEM_FUNC3_START        1011
+#define CSEM_FUNC2_END          974
+#define CSEM_FUNC3_START        974
        {OP_WR_E1H, CSEM_REG_FAST_MEMORY + 0x1154, 0x0},
        {OP_ZR_E1H, CSEM_REG_FAST_MEMORY + 0x3318, 0x2},
-#define CSEM_FUNC3_END          1013
-#define CSEM_FUNC4_START        1013
+#define CSEM_FUNC3_END          976
+#define CSEM_FUNC4_START        976
        {OP_WR_E1H, CSEM_REG_FAST_MEMORY + 0x1158, 0x0},
        {OP_ZR_E1H, CSEM_REG_FAST_MEMORY + 0x3320, 0x2},
-#define CSEM_FUNC4_END          1015
-#define CSEM_FUNC5_START        1015
+#define CSEM_FUNC4_END          978
+#define CSEM_FUNC5_START        978
        {OP_WR_E1H, CSEM_REG_FAST_MEMORY + 0x115c, 0x0},
        {OP_ZR_E1H, CSEM_REG_FAST_MEMORY + 0x3328, 0x2},
-#define CSEM_FUNC5_END          1017
-#define CSEM_FUNC6_START        1017
+#define CSEM_FUNC5_END          980
+#define CSEM_FUNC6_START        980
        {OP_WR_E1H, CSEM_REG_FAST_MEMORY + 0x1160, 0x0},
        {OP_ZR_E1H, CSEM_REG_FAST_MEMORY + 0x3330, 0x2},
-#define CSEM_FUNC6_END          1019
-#define CSEM_FUNC7_START        1019
+#define CSEM_FUNC6_END          982
+#define CSEM_FUNC7_START        982
        {OP_WR_E1H, CSEM_REG_FAST_MEMORY + 0x1164, 0x0},
        {OP_ZR_E1H, CSEM_REG_FAST_MEMORY + 0x3338, 0x2},
-#define CSEM_FUNC7_END          1021
-#define XPB_COMMON_START        1021
+#define CSEM_FUNC7_END          984
+#define XPB_COMMON_START        984
        {OP_WR, GRCBASE_XPB + PB_REG_CONTROL, 0x20},
-#define XPB_COMMON_END          1022
-#define DQ_COMMON_START         1022
+#define XPB_COMMON_END          985
+#define DQ_COMMON_START         985
        {OP_WR, DORQ_REG_MODE_ACT, 0x2},
        {OP_WR, DORQ_REG_NORM_CID_OFST, 0x3},
        {OP_WR, DORQ_REG_OUTST_REQ, 0x4},
@@ -1232,8 +1195,8 @@ static const struct raw_op init_ops[] = {
        {OP_WR, DORQ_REG_DQ_FIFO_AFULL_TH, 0x76c},
        {OP_WR, DORQ_REG_REGN, 0x7c1004},
        {OP_WR, DORQ_REG_IF_EN, 0xf},
-#define DQ_COMMON_END           1040
-#define TIMERS_COMMON_START     1040
+#define DQ_COMMON_END           1003
+#define TIMERS_COMMON_START     1003
        {OP_ZR, TM_REG_CLIN_PRIOR0_CLIENT, 0x2},
        {OP_WR, TM_REG_LIN_SETCLR_FIFO_ALFULL_THR, 0x1c},
        {OP_WR, TM_REG_CFC_AC_CRDCNT_VAL, 0x1},
@@ -1256,14 +1219,14 @@ static const struct raw_op init_ops[] = {
        {OP_WR, TM_REG_EN_CL0_INPUT, 0x1},
        {OP_WR, TM_REG_EN_CL1_INPUT, 0x1},
        {OP_WR, TM_REG_EN_CL2_INPUT, 0x1},
-#define TIMERS_COMMON_END       1062
-#define TIMERS_PORT0_START      1062
+#define TIMERS_COMMON_END       1025
+#define TIMERS_PORT0_START      1025
        {OP_ZR, TM_REG_LIN0_PHY_ADDR, 0x2},
-#define TIMERS_PORT0_END        1063
-#define TIMERS_PORT1_START      1063
+#define TIMERS_PORT0_END        1026
+#define TIMERS_PORT1_START      1026
        {OP_ZR, TM_REG_LIN1_PHY_ADDR, 0x2},
-#define TIMERS_PORT1_END        1064
-#define XSDM_COMMON_START       1064
+#define TIMERS_PORT1_END        1027
+#define XSDM_COMMON_START       1027
        {OP_WR_E1, XSDM_REG_CFC_RSP_START_ADDR, 0x614},
        {OP_WR_E1H, XSDM_REG_CFC_RSP_START_ADDR, 0x424},
        {OP_WR_E1, XSDM_REG_CMP_COUNTER_START_ADDR, 0x600},
@@ -1311,8 +1274,8 @@ static const struct raw_op init_ops[] = {
        {OP_WR_ASIC, XSDM_REG_TIMER_TICK, 0x3e8},
        {OP_WR_EMUL, XSDM_REG_TIMER_TICK, 0x1},
        {OP_WR_FPGA, XSDM_REG_TIMER_TICK, 0xa},
-#define XSDM_COMMON_END         1111
-#define QM_COMMON_START         1111
+#define XSDM_COMMON_END         1074
+#define QM_COMMON_START         1074
        {OP_WR, QM_REG_ACTCTRINITVAL_0, 0x6},
        {OP_WR, QM_REG_ACTCTRINITVAL_1, 0x5},
        {OP_WR, QM_REG_ACTCTRINITVAL_2, 0xa},
@@ -1613,8 +1576,8 @@ static const struct raw_op init_ops[] = {
        {OP_WR_E1H, QM_REG_PQ2PCIFUNC_6, 0x5},
        {OP_WR_E1H, QM_REG_PQ2PCIFUNC_7, 0x7},
        {OP_WR, QM_REG_CMINTEN, 0xff},
-#define QM_COMMON_END           1411
-#define PBF_COMMON_START        1411
+#define QM_COMMON_END           1374
+#define PBF_COMMON_START        1374
        {OP_WR, PBF_REG_INIT, 0x1},
        {OP_WR, PBF_REG_INIT_P4, 0x1},
        {OP_WR, PBF_REG_MAC_LB_ENABLE, 0x1},
@@ -1622,20 +1585,20 @@ static const struct raw_op init_ops[] = {
        {OP_WR, PBF_REG_INIT_P4, 0x0},
        {OP_WR, PBF_REG_INIT, 0x0},
        {OP_WR, PBF_REG_DISABLE_NEW_TASK_PROC_P4, 0x0},
-#define PBF_COMMON_END          1418
-#define PBF_PORT0_START         1418
+#define PBF_COMMON_END          1381
+#define PBF_PORT0_START         1381
        {OP_WR, PBF_REG_INIT_P0, 0x1},
        {OP_WR, PBF_REG_MAC_IF0_ENABLE, 0x1},
        {OP_WR, PBF_REG_INIT_P0, 0x0},
        {OP_WR, PBF_REG_DISABLE_NEW_TASK_PROC_P0, 0x0},
-#define PBF_PORT0_END           1422
-#define PBF_PORT1_START         1422
+#define PBF_PORT0_END           1385
+#define PBF_PORT1_START         1385
        {OP_WR, PBF_REG_INIT_P1, 0x1},
        {OP_WR, PBF_REG_MAC_IF1_ENABLE, 0x1},
        {OP_WR, PBF_REG_INIT_P1, 0x0},
        {OP_WR, PBF_REG_DISABLE_NEW_TASK_PROC_P1, 0x0},
-#define PBF_PORT1_END           1426
-#define XCM_COMMON_START        1426
+#define PBF_PORT1_END           1389
+#define XCM_COMMON_START        1389
        {OP_WR, XCM_REG_XX_OVFL_EVNT_ID, 0x32},
        {OP_WR, XCM_REG_XQM_XCM_HDR_P, 0x3150020},
        {OP_WR, XCM_REG_XQM_XCM_HDR_S, 0x3150020},
@@ -1670,7 +1633,7 @@ static const struct raw_op init_ops[] = {
        {OP_WR_E1, XCM_REG_XX_MSG_NUM, 0x1f},
        {OP_WR_E1H, XCM_REG_XX_MSG_NUM, 0x20},
        {OP_ZR, XCM_REG_XX_TABLE, 0x12},
-       {OP_SW_E1, XCM_REG_XX_DESCR_TABLE, 0x1f02ce},
+       {OP_SW_E1, XCM_REG_XX_DESCR_TABLE, 0x1f02cc},
        {OP_SW_E1H, XCM_REG_XX_DESCR_TABLE, 0x1f0302},
        {OP_WR, XCM_REG_N_SM_CTX_LD_0, 0xf},
        {OP_WR, XCM_REG_N_SM_CTX_LD_1, 0x7},
@@ -1700,8 +1663,8 @@ static const struct raw_op init_ops[] = {
        {OP_WR, XCM_REG_CDU_SM_WR_IFEN, 0x1},
        {OP_WR, XCM_REG_CDU_SM_RD_IFEN, 0x1},
        {OP_WR, XCM_REG_XCM_CFC_IFEN, 0x1},
-#define XCM_COMMON_END          1490
-#define XCM_PORT0_START         1490
+#define XCM_COMMON_END          1453
+#define XCM_PORT0_START         1453
        {OP_WR_E1, XCM_REG_GLB_DEL_ACK_TMR_VAL_0, 0xc8},
        {OP_WR_E1, XCM_REG_GLB_DEL_ACK_MAX_CNT_0, 0x2},
        {OP_WR_E1, XCM_REG_WU_DA_SET_TMR_CNT_FLG_CMD00, 0x0},
@@ -1710,8 +1673,8 @@ static const struct raw_op init_ops[] = {
        {OP_WR_E1, XCM_REG_WU_DA_CNT_CMD10, 0x2},
        {OP_WR_E1, XCM_REG_WU_DA_CNT_UPD_VAL00, 0xff},
        {OP_WR_E1, XCM_REG_WU_DA_CNT_UPD_VAL10, 0xff},
-#define XCM_PORT0_END           1498
-#define XCM_PORT1_START         1498
+#define XCM_PORT0_END           1461
+#define XCM_PORT1_START         1461
        {OP_WR_E1, XCM_REG_GLB_DEL_ACK_TMR_VAL_1, 0xc8},
        {OP_WR_E1, XCM_REG_GLB_DEL_ACK_MAX_CNT_1, 0x2},
        {OP_WR_E1, XCM_REG_WU_DA_SET_TMR_CNT_FLG_CMD01, 0x0},
@@ -1720,8 +1683,8 @@ static const struct raw_op init_ops[] = {
        {OP_WR_E1, XCM_REG_WU_DA_CNT_CMD11, 0x2},
        {OP_WR_E1, XCM_REG_WU_DA_CNT_UPD_VAL01, 0xff},
        {OP_WR_E1, XCM_REG_WU_DA_CNT_UPD_VAL11, 0xff},
-#define XCM_PORT1_END           1506
-#define XCM_FUNC0_START         1506
+#define XCM_PORT1_END           1469
+#define XCM_FUNC0_START         1469
        {OP_WR_E1H, XCM_REG_GLB_DEL_ACK_TMR_VAL_0, 0xc8},
        {OP_WR_E1H, XCM_REG_GLB_DEL_ACK_MAX_CNT_0, 0x2},
        {OP_WR_E1H, XCM_REG_WU_DA_SET_TMR_CNT_FLG_CMD00, 0x0},
@@ -1731,8 +1694,8 @@ static const struct raw_op init_ops[] = {
        {OP_WR_E1H, XCM_REG_WU_DA_CNT_UPD_VAL00, 0xff},
        {OP_WR_E1H, XCM_REG_WU_DA_CNT_UPD_VAL10, 0xff},
        {OP_WR_E1H, XCM_REG_PHYS_QNUM3_0, 0x0},
-#define XCM_FUNC0_END           1515
-#define XCM_FUNC1_START         1515
+#define XCM_FUNC0_END           1478
+#define XCM_FUNC1_START         1478
        {OP_WR_E1H, XCM_REG_GLB_DEL_ACK_TMR_VAL_1, 0xc8},
        {OP_WR_E1H, XCM_REG_GLB_DEL_ACK_MAX_CNT_1, 0x2},
        {OP_WR_E1H, XCM_REG_WU_DA_SET_TMR_CNT_FLG_CMD01, 0x0},
@@ -1742,8 +1705,8 @@ static const struct raw_op init_ops[] = {
        {OP_WR_E1H, XCM_REG_WU_DA_CNT_UPD_VAL01, 0xff},
        {OP_WR_E1H, XCM_REG_WU_DA_CNT_UPD_VAL11, 0xff},
        {OP_WR_E1H, XCM_REG_PHYS_QNUM3_1, 0x0},
-#define XCM_FUNC1_END           1524
-#define XCM_FUNC2_START         1524
+#define XCM_FUNC1_END           1487
+#define XCM_FUNC2_START         1487
        {OP_WR_E1H, XCM_REG_GLB_DEL_ACK_TMR_VAL_0, 0xc8},
        {OP_WR_E1H, XCM_REG_GLB_DEL_ACK_MAX_CNT_0, 0x2},
        {OP_WR_E1H, XCM_REG_WU_DA_SET_TMR_CNT_FLG_CMD00, 0x0},
@@ -1753,8 +1716,8 @@ static const struct raw_op init_ops[] = {
        {OP_WR_E1H, XCM_REG_WU_DA_CNT_UPD_VAL00, 0xff},
        {OP_WR_E1H, XCM_REG_WU_DA_CNT_UPD_VAL10, 0xff},
        {OP_WR_E1H, XCM_REG_PHYS_QNUM3_0, 0x0},
-#define XCM_FUNC2_END           1533
-#define XCM_FUNC3_START         1533
+#define XCM_FUNC2_END           1496
+#define XCM_FUNC3_START         1496
        {OP_WR_E1H, XCM_REG_GLB_DEL_ACK_TMR_VAL_1, 0xc8},
        {OP_WR_E1H, XCM_REG_GLB_DEL_ACK_MAX_CNT_1, 0x2},
        {OP_WR_E1H, XCM_REG_WU_DA_SET_TMR_CNT_FLG_CMD01, 0x0},
@@ -1764,8 +1727,8 @@ static const struct raw_op init_ops[] = {
        {OP_WR_E1H, XCM_REG_WU_DA_CNT_UPD_VAL01, 0xff},
        {OP_WR_E1H, XCM_REG_WU_DA_CNT_UPD_VAL11, 0xff},
        {OP_WR_E1H, XCM_REG_PHYS_QNUM3_1, 0x0},
-#define XCM_FUNC3_END           1542
-#define XCM_FUNC4_START         1542
+#define XCM_FUNC3_END           1505
+#define XCM_FUNC4_START         1505
        {OP_WR_E1H, XCM_REG_GLB_DEL_ACK_TMR_VAL_0, 0xc8},
        {OP_WR_E1H, XCM_REG_GLB_DEL_ACK_MAX_CNT_0, 0x2},
        {OP_WR_E1H, XCM_REG_WU_DA_SET_TMR_CNT_FLG_CMD00, 0x0},
@@ -1775,8 +1738,8 @@ static const struct raw_op init_ops[] = {
        {OP_WR_E1H, XCM_REG_WU_DA_CNT_UPD_VAL00, 0xff},
        {OP_WR_E1H, XCM_REG_WU_DA_CNT_UPD_VAL10, 0xff},
        {OP_WR_E1H, XCM_REG_PHYS_QNUM3_0, 0x0},
-#define XCM_FUNC4_END           1551
-#define XCM_FUNC5_START         1551
+#define XCM_FUNC4_END           1514
+#define XCM_FUNC5_START         1514
        {OP_WR_E1H, XCM_REG_GLB_DEL_ACK_TMR_VAL_1, 0xc8},
        {OP_WR_E1H, XCM_REG_GLB_DEL_ACK_MAX_CNT_1, 0x2},
        {OP_WR_E1H, XCM_REG_WU_DA_SET_TMR_CNT_FLG_CMD01, 0x0},
@@ -1786,8 +1749,8 @@ static const struct raw_op init_ops[] = {
        {OP_WR_E1H, XCM_REG_WU_DA_CNT_UPD_VAL01, 0xff},
        {OP_WR_E1H, XCM_REG_WU_DA_CNT_UPD_VAL11, 0xff},
        {OP_WR_E1H, XCM_REG_PHYS_QNUM3_1, 0x0},
-#define XCM_FUNC5_END           1560
-#define XCM_FUNC6_START         1560
+#define XCM_FUNC5_END           1523
+#define XCM_FUNC6_START         1523
        {OP_WR_E1H, XCM_REG_GLB_DEL_ACK_TMR_VAL_0, 0xc8},
        {OP_WR_E1H, XCM_REG_GLB_DEL_ACK_MAX_CNT_0, 0x2},
        {OP_WR_E1H, XCM_REG_WU_DA_SET_TMR_CNT_FLG_CMD00, 0x0},
@@ -1797,8 +1760,8 @@ static const struct raw_op init_ops[] = {
        {OP_WR_E1H, XCM_REG_WU_DA_CNT_UPD_VAL00, 0xff},
        {OP_WR_E1H, XCM_REG_WU_DA_CNT_UPD_VAL10, 0xff},
        {OP_WR_E1H, XCM_REG_PHYS_QNUM3_0, 0x0},
-#define XCM_FUNC6_END           1569
-#define XCM_FUNC7_START         1569
+#define XCM_FUNC6_END           1532
+#define XCM_FUNC7_START         1532
        {OP_WR_E1H, XCM_REG_GLB_DEL_ACK_TMR_VAL_1, 0xc8},
        {OP_WR_E1H, XCM_REG_GLB_DEL_ACK_MAX_CNT_1, 0x2},
        {OP_WR_E1H, XCM_REG_WU_DA_SET_TMR_CNT_FLG_CMD01, 0x0},
@@ -1808,8 +1771,8 @@ static const struct raw_op init_ops[] = {
        {OP_WR_E1H, XCM_REG_WU_DA_CNT_UPD_VAL01, 0xff},
        {OP_WR_E1H, XCM_REG_WU_DA_CNT_UPD_VAL11, 0xff},
        {OP_WR_E1H, XCM_REG_PHYS_QNUM3_1, 0x0},
-#define XCM_FUNC7_END           1578
-#define XSEM_COMMON_START       1578
+#define XCM_FUNC7_END           1541
+#define XSEM_COMMON_START       1541
        {OP_RD, XSEM_REG_MSG_NUM_FIC0, 0x0},
        {OP_RD, XSEM_REG_MSG_NUM_FIC1, 0x0},
        {OP_RD, XSEM_REG_MSG_NUM_FOC0, 0x0},
@@ -1876,9 +1839,9 @@ static const struct raw_op init_ops[] = {
        {OP_ZR_E1H, XSEM_REG_FAST_MEMORY + 0x9000, 0x2},
        {OP_WR_E1, XSEM_REG_FAST_MEMORY + 0x3368, 0x0},
        {OP_ZR_E1H, XSEM_REG_FAST_MEMORY + 0x21a8, 0x86},
-       {OP_SW_E1, XSEM_REG_FAST_MEMORY + 0x3370, 0x202ed},
+       {OP_SW_E1, XSEM_REG_FAST_MEMORY + 0x3370, 0x202eb},
        {OP_ZR_E1H, XSEM_REG_FAST_MEMORY + 0x2000, 0x20},
-       {OP_SW_E1, XSEM_REG_FAST_MEMORY + 0x3b90, 0x402ef},
+       {OP_SW_E1, XSEM_REG_FAST_MEMORY + 0x3b90, 0x402ed},
        {OP_WR_E1H, XSEM_REG_FAST_MEMORY + 0x23c8, 0x0},
        {OP_WR_E1, XSEM_REG_FAST_MEMORY + 0x1518, 0x1},
        {OP_SW_E1H, XSEM_REG_FAST_MEMORY + 0x23d0, 0x20321},
@@ -1886,29 +1849,29 @@ static const struct raw_op init_ops[] = {
        {OP_SW_E1H, XSEM_REG_FAST_MEMORY + 0x2498, 0x40323},
        {OP_WR_E1, XSEM_REG_FAST_MEMORY + 0x1838, 0x0},
        {OP_WR_E1H, XSEM_REG_FAST_MEMORY + 0x2ac8, 0x0},
-       {OP_SW_E1, XSEM_REG_FAST_MEMORY + 0x1820, 0x202f3},
+       {OP_SW_E1, XSEM_REG_FAST_MEMORY + 0x1820, 0x202f1},
        {OP_WR_E1H, XSEM_REG_FAST_MEMORY + 0x2ab8, 0x0},
        {OP_ZR_E1, XSEM_REG_FAST_MEMORY + 0x4ac0, 0x2},
        {OP_WR_E1H, XSEM_REG_FAST_MEMORY + 0x3010, 0x1},
        {OP_ZR_E1, XSEM_REG_FAST_MEMORY + 0x4b00, 0x4},
        {OP_ZR_E1H, XSEM_REG_FAST_MEMORY + 0x4040, 0x10},
-       {OP_SW_E1, XSEM_REG_FAST_MEMORY + 0x1f50, 0x202f5},
+       {OP_SW_E1, XSEM_REG_FAST_MEMORY + 0x1f50, 0x202f3},
        {OP_SW_E1H, XSEM_REG_FAST_MEMORY + 0x4000, 0x100327},
        {OP_ZR_E1H, XSEM_REG_FAST_MEMORY + 0x6ac0, 0x2},
        {OP_ZR_E1H, XSEM_REG_FAST_MEMORY + 0x6b00, 0x4},
        {OP_SW_E1H, XSEM_REG_FAST_MEMORY + 0x83b0, 0x20337},
        {OP_WR, XSEM_REG_FAST_MEMORY + 0x10800, 0x0},
-       {OP_SW_E1, XSEM_REG_FAST_MEMORY + 0x10c00, 0x1002f7},
+       {OP_SW_E1, XSEM_REG_FAST_MEMORY + 0x10c00, 0x1002f5},
        {OP_SW_E1H, XSEM_REG_FAST_MEMORY + 0x10c00, 0x100339},
        {OP_WR, XSEM_REG_FAST_MEMORY + 0x10800, 0x1000000},
-       {OP_SW_E1, XSEM_REG_FAST_MEMORY + 0x10c40, 0x80307},
+       {OP_SW_E1, XSEM_REG_FAST_MEMORY + 0x10c40, 0x80305},
        {OP_SW_E1H, XSEM_REG_FAST_MEMORY + 0x10c40, 0x80349},
        {OP_WR, XSEM_REG_FAST_MEMORY + 0x10800, 0x2000000},
-       {OP_SW_E1, XSEM_REG_FAST_MEMORY + 0x10c60, 0x8030f},
+       {OP_SW_E1, XSEM_REG_FAST_MEMORY + 0x10c60, 0x8030d},
        {OP_SW_E1H, XSEM_REG_FAST_MEMORY + 0x10c60, 0x80351},
        {OP_ZP_E1, XSEM_REG_INT_TABLE, 0xa90000},
        {OP_ZP_E1H, XSEM_REG_INT_TABLE, 0xac0000},
-       {OP_WR_64_E1, XSEM_REG_INT_TABLE + 0x368, 0x130317},
+       {OP_WR_64_E1, XSEM_REG_INT_TABLE + 0x368, 0x130315},
        {OP_WR_64_E1H, XSEM_REG_INT_TABLE + 0x368, 0x130359},
        {OP_ZP_E1, XSEM_REG_PRAM, 0x344e0000},
        {OP_ZP_E1H, XSEM_REG_PRAM, 0x34620000},
@@ -1918,10 +1881,10 @@ static const struct raw_op init_ops[] = {
        {OP_ZP_E1H, XSEM_REG_PRAM + 0x10000, 0x3e971b22},
        {OP_ZP_E1, XSEM_REG_PRAM + 0x18000, 0x1dd02ad2},
        {OP_ZP_E1H, XSEM_REG_PRAM + 0x18000, 0x21542ac8},
-       {OP_WR_64_E1, XSEM_REG_PRAM + 0x1c0d0, 0x47e60319},
+       {OP_WR_64_E1, XSEM_REG_PRAM + 0x1c0d0, 0x47e60317},
        {OP_WR_64_E1H, XSEM_REG_PRAM + 0x1c8d0, 0x46e6035b},
-#define XSEM_COMMON_END         1688
-#define XSEM_PORT0_START        1688
+#define XSEM_COMMON_END         1651
+#define XSEM_PORT0_START        1651
        {OP_ZR_E1, XSEM_REG_FAST_MEMORY + 0x3ba0, 0x10},
        {OP_ZR_E1H, XSEM_REG_FAST_MEMORY + 0xc000, 0xfc},
        {OP_ZR_E1, XSEM_REG_FAST_MEMORY + 0x3c20, 0x1c},
@@ -1934,7 +1897,7 @@ static const struct raw_op init_ops[] = {
        {OP_ZR_E1H, XSEM_REG_FAST_MEMORY + 0x26e8, 0x1c},
        {OP_WR_E1, XSEM_REG_FAST_MEMORY + 0x3b58, 0x0},
        {OP_ZR_E1H, XSEM_REG_FAST_MEMORY + 0x27c8, 0x1c},
-       {OP_SW_E1, XSEM_REG_FAST_MEMORY + 0x3d10, 0x10031b},
+       {OP_SW_E1, XSEM_REG_FAST_MEMORY + 0x3d10, 0x100319},
        {OP_ZR_E1H, XSEM_REG_FAST_MEMORY + 0xa000, 0x28},
        {OP_WR_E1, XSEM_REG_FAST_MEMORY + 0x1500, 0x0},
        {OP_ZR_E1H, XSEM_REG_FAST_MEMORY + 0xa140, 0xc},
@@ -1950,12 +1913,12 @@ static const struct raw_op init_ops[] = {
        {OP_SW_E1H, XSEM_REG_FAST_MEMORY + 0x6ac8, 0x2035d},
        {OP_WR_E1, XSEM_REG_FAST_MEMORY + 0x50b8, 0x1},
        {OP_ZR_E1H, XSEM_REG_FAST_MEMORY + 0x6b10, 0x42},
-       {OP_SW_E1, XSEM_REG_FAST_MEMORY + 0x4ac8, 0x2032b},
+       {OP_SW_E1, XSEM_REG_FAST_MEMORY + 0x4ac8, 0x20329},
        {OP_ZR_E1H, XSEM_REG_FAST_MEMORY + 0x6d20, 0x4},
        {OP_ZR_E1, XSEM_REG_FAST_MEMORY + 0x4b10, 0x42},
        {OP_ZR_E1, XSEM_REG_FAST_MEMORY + 0x4d20, 0x4},
-#define XSEM_PORT0_END          1720
-#define XSEM_PORT1_START        1720
+#define XSEM_PORT0_END          1683
+#define XSEM_PORT1_START        1683
        {OP_ZR_E1, XSEM_REG_FAST_MEMORY + 0x3be0, 0x10},
        {OP_ZR_E1H, XSEM_REG_FAST_MEMORY + 0xc3f0, 0xfc},
        {OP_ZR_E1, XSEM_REG_FAST_MEMORY + 0x3c90, 0x1c},
@@ -1968,7 +1931,7 @@ static const struct raw_op init_ops[] = {
        {OP_ZR_E1H, XSEM_REG_FAST_MEMORY + 0x2758, 0x1c},
        {OP_WR_E1, XSEM_REG_FAST_MEMORY + 0x3b5c, 0x0},
        {OP_ZR_E1H, XSEM_REG_FAST_MEMORY + 0x2838, 0x1c},
-       {OP_SW_E1, XSEM_REG_FAST_MEMORY + 0x3d50, 0x10032d},
+       {OP_SW_E1, XSEM_REG_FAST_MEMORY + 0x3d50, 0x10032b},
        {OP_ZR_E1H, XSEM_REG_FAST_MEMORY + 0xa0a0, 0x28},
        {OP_WR_E1, XSEM_REG_FAST_MEMORY + 0x1504, 0x0},
        {OP_ZR_E1H, XSEM_REG_FAST_MEMORY + 0xa170, 0xc},
@@ -1984,65 +1947,65 @@ static const struct raw_op init_ops[] = {
        {OP_SW_E1H, XSEM_REG_FAST_MEMORY + 0x6ad0, 0x2035f},
        {OP_WR_E1, XSEM_REG_FAST_MEMORY + 0x50bc, 0x1},
        {OP_ZR_E1H, XSEM_REG_FAST_MEMORY + 0x6c18, 0x42},
-       {OP_SW_E1, XSEM_REG_FAST_MEMORY + 0x4ad0, 0x2033d},
+       {OP_SW_E1, XSEM_REG_FAST_MEMORY + 0x4ad0, 0x2033b},
        {OP_ZR_E1H, XSEM_REG_FAST_MEMORY + 0x6d30, 0x4},
        {OP_ZR_E1, XSEM_REG_FAST_MEMORY + 0x4c18, 0x42},
        {OP_ZR_E1, XSEM_REG_FAST_MEMORY + 0x4d30, 0x4},
-#define XSEM_PORT1_END          1752
-#define XSEM_FUNC0_START        1752
+#define XSEM_PORT1_END          1715
+#define XSEM_FUNC0_START        1715
        {OP_WR_E1H, XSEM_REG_FAST_MEMORY + 0xc7e0, 0x0},
        {OP_SW_E1H, XSEM_REG_FAST_MEMORY + 0x28b8, 0x100361},
        {OP_ZR_E1H, XSEM_REG_FAST_MEMORY + 0x5048, 0xe},
-#define XSEM_FUNC0_END          1755
-#define XSEM_FUNC1_START        1755
+#define XSEM_FUNC0_END          1718
+#define XSEM_FUNC1_START        1718
        {OP_WR_E1H, XSEM_REG_FAST_MEMORY + 0xc7e4, 0x0},
        {OP_SW_E1H, XSEM_REG_FAST_MEMORY + 0x28f8, 0x100371},
        {OP_ZR_E1H, XSEM_REG_FAST_MEMORY + 0x5080, 0xe},
-#define XSEM_FUNC1_END          1758
-#define XSEM_FUNC2_START        1758
+#define XSEM_FUNC1_END          1721
+#define XSEM_FUNC2_START        1721
        {OP_WR_E1H, XSEM_REG_FAST_MEMORY + 0xc7e8, 0x0},
        {OP_SW_E1H, XSEM_REG_FAST_MEMORY + 0x2938, 0x100381},
        {OP_ZR_E1H, XSEM_REG_FAST_MEMORY + 0x50b8, 0xe},
-#define XSEM_FUNC2_END          1761
-#define XSEM_FUNC3_START        1761
+#define XSEM_FUNC2_END          1724
+#define XSEM_FUNC3_START        1724
        {OP_WR_E1H, XSEM_REG_FAST_MEMORY + 0xc7ec, 0x0},
        {OP_SW_E1H, XSEM_REG_FAST_MEMORY + 0x2978, 0x100391},
        {OP_ZR_E1H, XSEM_REG_FAST_MEMORY + 0x50f0, 0xe},
-#define XSEM_FUNC3_END          1764
-#define XSEM_FUNC4_START        1764
+#define XSEM_FUNC3_END          1727
+#define XSEM_FUNC4_START        1727
        {OP_WR_E1H, XSEM_REG_FAST_MEMORY + 0xc7f0, 0x0},
        {OP_SW_E1H, XSEM_REG_FAST_MEMORY + 0x29b8, 0x1003a1},
        {OP_ZR_E1H, XSEM_REG_FAST_MEMORY + 0x5128, 0xe},
-#define XSEM_FUNC4_END          1767
-#define XSEM_FUNC5_START        1767
+#define XSEM_FUNC4_END          1730
+#define XSEM_FUNC5_START        1730
        {OP_WR_E1H, XSEM_REG_FAST_MEMORY + 0xc7f4, 0x0},
        {OP_SW_E1H, XSEM_REG_FAST_MEMORY + 0x29f8, 0x1003b1},
        {OP_ZR_E1H, XSEM_REG_FAST_MEMORY + 0x5160, 0xe},
-#define XSEM_FUNC5_END          1770
-#define XSEM_FUNC6_START        1770
+#define XSEM_FUNC5_END          1733
+#define XSEM_FUNC6_START        1733
        {OP_WR_E1H, XSEM_REG_FAST_MEMORY + 0xc7f8, 0x0},
        {OP_SW_E1H, XSEM_REG_FAST_MEMORY + 0x2a38, 0x1003c1},
        {OP_ZR_E1H, XSEM_REG_FAST_MEMORY + 0x5198, 0xe},
-#define XSEM_FUNC6_END          1773
-#define XSEM_FUNC7_START        1773
+#define XSEM_FUNC6_END          1736
+#define XSEM_FUNC7_START        1736
        {OP_WR_E1H, XSEM_REG_FAST_MEMORY + 0xc7fc, 0x0},
        {OP_SW_E1H, XSEM_REG_FAST_MEMORY + 0x2a78, 0x1003d1},
        {OP_ZR_E1H, XSEM_REG_FAST_MEMORY + 0x51d0, 0xe},
-#define XSEM_FUNC7_END          1776
-#define CDU_COMMON_START        1776
+#define XSEM_FUNC7_END          1739
+#define CDU_COMMON_START        1739
        {OP_WR, CDU_REG_CDU_CONTROL0, 0x1},
        {OP_WR_E1H, CDU_REG_MF_MODE, 0x1},
        {OP_WR, CDU_REG_CDU_CHK_MASK0, 0x3d000},
        {OP_WR, CDU_REG_CDU_CHK_MASK1, 0x3d},
-       {OP_WB_E1, CDU_REG_L1TT, 0x200033f},
+       {OP_WB_E1, CDU_REG_L1TT, 0x200033d},
        {OP_WB_E1H, CDU_REG_L1TT, 0x20003e1},
-       {OP_WB_E1, CDU_REG_MATT, 0x20053f},
+       {OP_WB_E1, CDU_REG_MATT, 0x20053d},
        {OP_WB_E1H, CDU_REG_MATT, 0x2805e1},
        {OP_ZR_E1, CDU_REG_MATT + 0x80, 0x2},
-       {OP_WB_E1, CDU_REG_MATT + 0x88, 0x6055f},
+       {OP_WB_E1, CDU_REG_MATT + 0x88, 0x6055d},
        {OP_ZR, CDU_REG_MATT + 0xa0, 0x18},
-#define CDU_COMMON_END          1787
-#define DMAE_COMMON_START       1787
+#define CDU_COMMON_END          1750
+#define DMAE_COMMON_START       1750
        {OP_ZR, DMAE_REG_CMD_MEM, 0xe0},
        {OP_WR, DMAE_REG_CRC16C_INIT, 0x0},
        {OP_WR, DMAE_REG_CRC16T10_INIT, 0x1},
@@ -2050,24 +2013,24 @@ static const struct raw_op init_ops[] = {
        {OP_WR_E1H, DMAE_REG_PXP_REQ_INIT_CRD, 0x2},
        {OP_WR, DMAE_REG_PCI_IFEN, 0x1},
        {OP_WR, DMAE_REG_GRC_IFEN, 0x1},
-#define DMAE_COMMON_END         1794
-#define PXP_COMMON_START        1794
-       {OP_WB_E1, PXP_REG_HST_INBOUND_INT + 0x400, 0x50565},
+#define DMAE_COMMON_END         1757
+#define PXP_COMMON_START        1757
+       {OP_WB_E1, PXP_REG_HST_INBOUND_INT + 0x400, 0x50563},
        {OP_WB_E1H, PXP_REG_HST_INBOUND_INT + 0x400, 0x50609},
-       {OP_WB_E1, PXP_REG_HST_INBOUND_INT + 0x420, 0x5056a},
+       {OP_WB_E1, PXP_REG_HST_INBOUND_INT + 0x420, 0x50568},
        {OP_WB_E1H, PXP_REG_HST_INBOUND_INT, 0x5060e},
-       {OP_WB_E1, PXP_REG_HST_INBOUND_INT, 0x5056f},
-#define PXP_COMMON_END          1799
-#define CFC_COMMON_START        1799
+       {OP_WB_E1, PXP_REG_HST_INBOUND_INT, 0x5056d},
+#define PXP_COMMON_END          1762
+#define CFC_COMMON_START        1762
        {OP_ZR_E1H, CFC_REG_LINK_LIST, 0x100},
        {OP_WR, CFC_REG_CONTROL0, 0x10},
        {OP_WR, CFC_REG_DISABLE_ON_ERROR, 0x3fff},
        {OP_WR, CFC_REG_LCREQ_WEIGHTS, 0x84924a},
-#define CFC_COMMON_END          1803
-#define HC_COMMON_START         1803
+#define CFC_COMMON_END          1766
+#define HC_COMMON_START         1766
        {OP_ZR_E1, HC_REG_USTORM_ADDR_FOR_COALESCE, 0x4},
-#define HC_COMMON_END           1804
-#define HC_PORT0_START          1804
+#define HC_COMMON_END           1767
+#define HC_PORT0_START          1767
        {OP_WR_E1, HC_REG_CONFIG_0, 0x1080},
        {OP_ZR_E1, HC_REG_UC_RAM_ADDR_0, 0x2},
        {OP_WR_E1, HC_REG_ATTN_NUM_P0, 0x10},
@@ -2086,8 +2049,8 @@ static const struct raw_op init_ops[] = {
        {OP_ZR_E1, HC_REG_STATISTIC_COUNTERS + 0x120, 0x4a},
        {OP_ZR_E1, HC_REG_STATISTIC_COUNTERS + 0x370, 0x4a},
        {OP_ZR_E1, HC_REG_STATISTIC_COUNTERS + 0x5c0, 0x4a},
-#define HC_PORT0_END            1822
-#define HC_PORT1_START          1822
+#define HC_PORT0_END            1785
+#define HC_PORT1_START          1785
        {OP_WR_E1, HC_REG_CONFIG_1, 0x1080},
        {OP_ZR_E1, HC_REG_UC_RAM_ADDR_1, 0x2},
        {OP_WR_E1, HC_REG_ATTN_NUM_P1, 0x10},
@@ -2106,8 +2069,8 @@ static const struct raw_op init_ops[] = {
        {OP_ZR_E1, HC_REG_STATISTIC_COUNTERS + 0x248, 0x4a},
        {OP_ZR_E1, HC_REG_STATISTIC_COUNTERS + 0x498, 0x4a},
        {OP_ZR_E1, HC_REG_STATISTIC_COUNTERS + 0x6e8, 0x4a},
-#define HC_PORT1_END            1840
-#define HC_FUNC0_START          1840
+#define HC_PORT1_END            1803
+#define HC_FUNC0_START          1803
        {OP_WR_E1H, HC_REG_CONFIG_0, 0x1080},
        {OP_WR_E1H, HC_REG_FUNC_NUM_P0, 0x0},
        {OP_WR_E1H, HC_REG_ATTN_NUM_P0, 0x10},
@@ -2123,8 +2086,8 @@ static const struct raw_op init_ops[] = {
        {OP_ZR_E1H, HC_REG_STATISTIC_COUNTERS + 0x120, 0x4a},
        {OP_ZR_E1H, HC_REG_STATISTIC_COUNTERS + 0x370, 0x4a},
        {OP_ZR_E1H, HC_REG_STATISTIC_COUNTERS + 0x5c0, 0x4a},
-#define HC_FUNC0_END            1855
-#define HC_FUNC1_START          1855
+#define HC_FUNC0_END            1818
+#define HC_FUNC1_START          1818
        {OP_WR_E1H, HC_REG_CONFIG_1, 0x1080},
        {OP_WR_E1H, HC_REG_FUNC_NUM_P1, 0x1},
        {OP_WR_E1H, HC_REG_ATTN_NUM_P1, 0x10},
@@ -2140,8 +2103,8 @@ static const struct raw_op init_ops[] = {
        {OP_ZR_E1H, HC_REG_STATISTIC_COUNTERS + 0x248, 0x4a},
        {OP_ZR_E1H, HC_REG_STATISTIC_COUNTERS + 0x498, 0x4a},
        {OP_ZR_E1H, HC_REG_STATISTIC_COUNTERS + 0x6e8, 0x4a},
-#define HC_FUNC1_END            1870
-#define HC_FUNC2_START          1870
+#define HC_FUNC1_END            1833
+#define HC_FUNC2_START          1833
        {OP_WR_E1H, HC_REG_CONFIG_0, 0x1080},
        {OP_WR_E1H, HC_REG_FUNC_NUM_P0, 0x2},
        {OP_WR_E1H, HC_REG_ATTN_NUM_P0, 0x10},
@@ -2157,8 +2120,8 @@ static const struct raw_op init_ops[] = {
        {OP_ZR_E1H, HC_REG_STATISTIC_COUNTERS + 0x120, 0x4a},
        {OP_ZR_E1H, HC_REG_STATISTIC_COUNTERS + 0x370, 0x4a},
        {OP_ZR_E1H, HC_REG_STATISTIC_COUNTERS + 0x5c0, 0x4a},
-#define HC_FUNC2_END            1885
-#define HC_FUNC3_START          1885
+#define HC_FUNC2_END            1848
+#define HC_FUNC3_START          1848
        {OP_WR_E1H, HC_REG_CONFIG_1, 0x1080},
        {OP_WR_E1H, HC_REG_FUNC_NUM_P1, 0x3},
        {OP_WR_E1H, HC_REG_ATTN_NUM_P1, 0x10},
@@ -2174,8 +2137,8 @@ static const struct raw_op init_ops[] = {
        {OP_ZR_E1H, HC_REG_STATISTIC_COUNTERS + 0x248, 0x4a},
        {OP_ZR_E1H, HC_REG_STATISTIC_COUNTERS + 0x498, 0x4a},
        {OP_ZR_E1H, HC_REG_STATISTIC_COUNTERS + 0x6e8, 0x4a},
-#define HC_FUNC3_END            1900
-#define HC_FUNC4_START          1900
+#define HC_FUNC3_END            1863
+#define HC_FUNC4_START          1863
        {OP_WR_E1H, HC_REG_CONFIG_0, 0x1080},
        {OP_WR_E1H, HC_REG_FUNC_NUM_P0, 0x4},
        {OP_WR_E1H, HC_REG_ATTN_NUM_P0, 0x10},
@@ -2191,8 +2154,8 @@ static const struct raw_op init_ops[] = {
        {OP_ZR_E1H, HC_REG_STATISTIC_COUNTERS + 0x120, 0x4a},
        {OP_ZR_E1H, HC_REG_STATISTIC_COUNTERS + 0x370, 0x4a},
        {OP_ZR_E1H, HC_REG_STATISTIC_COUNTERS + 0x5c0, 0x4a},
-#define HC_FUNC4_END            1915
-#define HC_FUNC5_START          1915
+#define HC_FUNC4_END            1878
+#define HC_FUNC5_START          1878
        {OP_WR_E1H, HC_REG_CONFIG_1, 0x1080},
        {OP_WR_E1H, HC_REG_FUNC_NUM_P1, 0x5},
        {OP_WR_E1H, HC_REG_ATTN_NUM_P1, 0x10},
@@ -2208,8 +2171,8 @@ static const struct raw_op init_ops[] = {
        {OP_ZR_E1H, HC_REG_STATISTIC_COUNTERS + 0x248, 0x4a},
        {OP_ZR_E1H, HC_REG_STATISTIC_COUNTERS + 0x498, 0x4a},
        {OP_ZR_E1H, HC_REG_STATISTIC_COUNTERS + 0x6e8, 0x4a},
-#define HC_FUNC5_END            1930
-#define HC_FUNC6_START          1930
+#define HC_FUNC5_END            1893
+#define HC_FUNC6_START          1893
        {OP_WR_E1H, HC_REG_CONFIG_0, 0x1080},
        {OP_WR_E1H, HC_REG_FUNC_NUM_P0, 0x6},
        {OP_WR_E1H, HC_REG_ATTN_NUM_P0, 0x10},
@@ -2225,8 +2188,8 @@ static const struct raw_op init_ops[] = {
        {OP_ZR_E1H, HC_REG_STATISTIC_COUNTERS + 0x120, 0x4a},
        {OP_ZR_E1H, HC_REG_STATISTIC_COUNTERS + 0x370, 0x4a},
        {OP_ZR_E1H, HC_REG_STATISTIC_COUNTERS + 0x5c0, 0x4a},
-#define HC_FUNC6_END            1945
-#define HC_FUNC7_START          1945
+#define HC_FUNC6_END            1908
+#define HC_FUNC7_START          1908
        {OP_WR_E1H, HC_REG_CONFIG_1, 0x1080},
        {OP_WR_E1H, HC_REG_FUNC_NUM_P1, 0x7},
        {OP_WR_E1H, HC_REG_ATTN_NUM_P1, 0x10},
@@ -2242,8 +2205,8 @@ static const struct raw_op init_ops[] = {
        {OP_ZR_E1H, HC_REG_STATISTIC_COUNTERS + 0x248, 0x4a},
        {OP_ZR_E1H, HC_REG_STATISTIC_COUNTERS + 0x498, 0x4a},
        {OP_ZR_E1H, HC_REG_STATISTIC_COUNTERS + 0x6e8, 0x4a},
-#define HC_FUNC7_END            1960
-#define PXP2_COMMON_START       1960
+#define HC_FUNC7_END            1923
+#define PXP2_COMMON_START       1923
        {OP_WR_E1, PXP2_REG_PGL_CONTROL0, 0xe38340},
        {OP_WR_E1H, PXP2_REG_RQ_DRAM_ALIGN, 0x1},
        {OP_WR, PXP2_REG_PGL_CONTROL1, 0x3c10},
@@ -2361,8 +2324,8 @@ static const struct raw_op init_ops[] = {
        {OP_WR_E1H, PXP2_REG_RQ_ILT_MODE, 0x1},
        {OP_WR, PXP2_REG_RQ_RBC_DONE, 0x1},
        {OP_WR_E1H, PXP2_REG_PGL_CONTROL0, 0xe38340},
-#define PXP2_COMMON_END         2077
-#define MISC_AEU_COMMON_START   2077
+#define PXP2_COMMON_END         2040
+#define MISC_AEU_COMMON_START   2040
        {OP_ZR, MISC_REG_AEU_GENERAL_ATTN_0, 0x16},
        {OP_WR_E1H, MISC_REG_AEU_ENABLE1_NIG_0, 0x55540000},
        {OP_WR_E1H, MISC_REG_AEU_ENABLE2_NIG_0, 0x55555555},
@@ -2382,8 +2345,8 @@ static const struct raw_op init_ops[] = {
        {OP_WR_E1H, MISC_REG_AEU_ENABLE4_PXP_1, 0x0},
        {OP_WR_E1H, MISC_REG_AEU_CLR_LATCH_SIGNAL, 0xc00},
        {OP_WR_E1H, MISC_REG_AEU_GENERAL_MASK, 0x3},
-#define MISC_AEU_COMMON_END     2096
-#define MISC_AEU_PORT0_START    2096
+#define MISC_AEU_COMMON_END     2059
+#define MISC_AEU_PORT0_START    2059
        {OP_WR_E1, MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0, 0xbf5c0000},
        {OP_WR_E1H, MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0, 0xff5c0000},
        {OP_WR_E1, MISC_REG_AEU_ENABLE2_FUNC_0_OUT_0, 0xfff51fef},
@@ -2416,8 +2379,8 @@ static const struct raw_op init_ops[] = {
        {OP_WR_E1, MISC_REG_AEU_INVERTER_1_FUNC_0, 0x0},
        {OP_ZR_E1, MISC_REG_AEU_INVERTER_2_FUNC_0, 0x3},
        {OP_WR_E1, MISC_REG_AEU_MASK_ATTN_FUNC_0, 0x7},
-#define MISC_AEU_PORT0_END      2128
-#define MISC_AEU_PORT1_START    2128
+#define MISC_AEU_PORT0_END      2091
+#define MISC_AEU_PORT1_START    2091
        {OP_WR_E1, MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0, 0xbf5c0000},
        {OP_WR_E1H, MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0, 0xff5c0000},
        {OP_WR_E1, MISC_REG_AEU_ENABLE2_FUNC_1_OUT_0, 0xfff51fef},
@@ -2450,7 +2413,7 @@ static const struct raw_op init_ops[] = {
        {OP_WR_E1, MISC_REG_AEU_INVERTER_1_FUNC_1, 0x0},
        {OP_ZR_E1, MISC_REG_AEU_INVERTER_2_FUNC_1, 0x3},
        {OP_WR_E1, MISC_REG_AEU_MASK_ATTN_FUNC_1, 0x7},
-#define MISC_AEU_PORT1_END      2160
+#define MISC_AEU_PORT1_END      2123
 
 };
 
@@ -2560,103 +2523,92 @@ static const u32 init_data_e1[] = {
        0x00049c00, 0x00051f80, 0x0005a300, 0x00062680, 0x0006aa00, 0x00072d80,
        0x0007b100, 0x00083480, 0x0008b800, 0x00093b80, 0x0009bf00, 0x000a4280,
        0x000ac600, 0x000b4980, 0x000bcd00, 0x000c5080, 0x000cd400, 0x000d5780,
-       0x000ddb00, 0x00001900, 0x00000028, 0x00000000, 0x00100000, 0x00000000,
-       0x00000000, 0xffffffff, 0x40000000, 0x40000000, 0x40000000, 0x40000000,
+       0x000ddb00, 0x00001900, 0x00100000, 0x00000000, 0x00000000, 0xffffffff,
        0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000,
        0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000,
        0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000,
        0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000,
-       0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x00000000, 0x00007ff8,
-       0x00000000, 0x00001500, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
-       0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0x40000000, 0x40000000,
        0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000,
+       0x40000000, 0x40000000, 0x00000000, 0x00007ff8, 0x00000000, 0x00001500,
+       0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
+       0xffffffff, 0xffffffff, 0x40000000, 0x40000000, 0x40000000, 0x40000000,
        0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000,
        0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000,
        0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000,
        0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000,
-       0x00000000, 0x00007ff8, 0x00000000, 0x00003500, 0x00001000, 0x00002080,
-       0x00003100, 0x00004180, 0x00005200, 0x00006280, 0x00007300, 0x00008380,
-       0x00009400, 0x0000a480, 0x0000b500, 0x0000c580, 0x0000d600, 0x0000e680,
-       0x0000f700, 0x00010780, 0x00011800, 0x00012880, 0x00013900, 0x00014980,
-       0x00015a00, 0x00016a80, 0x00017b00, 0x00018b80, 0x00019c00, 0x0001ac80,
-       0x0001bd00, 0x0001cd80, 0x0001de00, 0x0001ee80, 0x0001ff00, 0x00000000,
-       0x00010001, 0x00000604, 0xccccccc1, 0xffffffff, 0xffffffff, 0xcccc0201,
-       0xcccccccc, 0x00000000, 0xffffffff, 0x40000000, 0x40000000, 0x40000000,
+       0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x00000000, 0x00007ff8,
+       0x00000000, 0x00003500, 0x00001000, 0x00002080, 0x00003100, 0x00004180,
+       0x00005200, 0x00006280, 0x00007300, 0x00008380, 0x00009400, 0x0000a480,
+       0x0000b500, 0x0000c580, 0x0000d600, 0x0000e680, 0x0000f700, 0x00010780,
+       0x00011800, 0x00012880, 0x00013900, 0x00014980, 0x00015a00, 0x00016a80,
+       0x00017b00, 0x00018b80, 0x00019c00, 0x0001ac80, 0x0001bd00, 0x0001cd80,
+       0x0001de00, 0x0001ee80, 0x0001ff00, 0x00000000, 0x00010001, 0x00000604,
+       0xccccccc1, 0xffffffff, 0xffffffff, 0xcccc0201, 0xcccccccc, 0x00000000,
+       0xffffffff, 0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000,
        0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000,
        0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000,
        0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000,
        0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000,
-       0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x00000000,
-       0x00007ff8, 0x00000000, 0x00003500, 0x0000ffff, 0x00000000, 0x0000ffff,
+       0x40000000, 0x40000000, 0x40000000, 0x00000000, 0x00007ff8, 0x00000000,
+       0x00003500, 0x0000ffff, 0x00000000, 0x0000ffff, 0x00000000, 0x0000ffff,
        0x00000000, 0x0000ffff, 0x00000000, 0x0000ffff, 0x00000000, 0x0000ffff,
+       0x00000000, 0x0000ffff, 0x00000000, 0x0000ffff, 0x00000000, 0x00100000,
        0x00000000, 0x0000ffff, 0x00000000, 0x0000ffff, 0x00000000, 0x0000ffff,
-       0x00000000, 0x00100000, 0x00000000, 0x0000ffff, 0x00000000, 0x0000ffff,
        0x00000000, 0x0000ffff, 0x00000000, 0x0000ffff, 0x00000000, 0x0000ffff,
-       0x00000000, 0x0000ffff, 0x00000000, 0x0000ffff, 0x00000000, 0x0000ffff,
-       0x00000000, 0x00100000, 0x00000000, 0xfffffff3, 0x320fffff, 0x0c30c30c,
-       0xc30c30c3, 0xcf3cf300, 0xf3cf3cf3, 0x0000cf3c, 0xcdcdcdcd, 0xfffffff1,
-       0x30efffff, 0x0c30c30c, 0xc30c30c3, 0xcf3cf300, 0xf3cf3cf3, 0x0001cf3c,
-       0xcdcdcdcd, 0xfffffff6, 0x305fffff, 0x0c30c30c, 0xc30c30c3, 0xcf3cf300,
-       0xf3cf3cf3, 0x0002cf3c, 0xcdcdcdcd, 0xfffff406, 0x1cbfffff, 0x0c30c305,
-       0xc30c30c3, 0xcf300014, 0xf3cf3cf3, 0x0004cf3c, 0xcdcdcdcd, 0xfffffff2,
-       0x304fffff, 0x0c30c30c, 0xc30c30c3, 0xcf3cf300, 0xf3cf3cf3, 0x0008cf3c,
-       0xcdcdcdcd, 0xfffffffa, 0x302fffff, 0x0c30c30c, 0xc30c30c3, 0xcf3cf300,
-       0xf3cf3cf3, 0x0010cf3c, 0xcdcdcdcd, 0xfffffff7, 0x31efffff, 0x0c30c30c,
-       0xc30c30c3, 0xcf3cf300, 0xf3cf3cf3, 0x0020cf3c, 0xcdcdcdcd, 0xfffffff5,
-       0x302fffff, 0x0c30c30c, 0xc30c30c3, 0xcf3cf300, 0xf3cf3cf3, 0x0040cf3c,
-       0xcdcdcdcd, 0xfffffff3, 0x310fffff, 0x0c30c30c, 0xc30c30c3, 0xcf3cf300,
-       0xf3cf3cf3, 0x0000cf3c, 0xcdcdcdcd, 0xfffffff1, 0x310fffff, 0x0c30c30c,
+       0x00000000, 0x0000ffff, 0x00000000, 0x0000ffff, 0x00000000, 0x00100000,
+       0x00000000, 0xfffffff3, 0x320fffff, 0x0c30c30c, 0xc30c30c3, 0xcf3cf300,
+       0xf3cf3cf3, 0x0000cf3c, 0xcdcdcdcd, 0xfffffff1, 0x30efffff, 0x0c30c30c,
        0xc30c30c3, 0xcf3cf300, 0xf3cf3cf3, 0x0001cf3c, 0xcdcdcdcd, 0xfffffff6,
        0x305fffff, 0x0c30c30c, 0xc30c30c3, 0xcf3cf300, 0xf3cf3cf3, 0x0002cf3c,
        0xcdcdcdcd, 0xfffff406, 0x1cbfffff, 0x0c30c305, 0xc30c30c3, 0xcf300014,
        0xf3cf3cf3, 0x0004cf3c, 0xcdcdcdcd, 0xfffffff2, 0x304fffff, 0x0c30c30c,
        0xc30c30c3, 0xcf3cf300, 0xf3cf3cf3, 0x0008cf3c, 0xcdcdcdcd, 0xfffffffa,
        0x302fffff, 0x0c30c30c, 0xc30c30c3, 0xcf3cf300, 0xf3cf3cf3, 0x0010cf3c,
-       0xcdcdcdcd, 0xfffffff7, 0x30efffff, 0x0c30c30c, 0xc30c30c3, 0xcf3cf300,
-       0xf3cf3cf3, 0x0020cf3c, 0xcdcdcdcd, 0xfffffff5, 0x304fffff, 0x0c30c30c,
+       0xcdcdcdcd, 0xfffffff7, 0x31efffff, 0x0c30c30c, 0xc30c30c3, 0xcf3cf300,
+       0xf3cf3cf3, 0x0020cf3c, 0xcdcdcdcd, 0xfffffff5, 0x302fffff, 0x0c30c30c,
        0xc30c30c3, 0xcf3cf300, 0xf3cf3cf3, 0x0040cf3c, 0xcdcdcdcd, 0xfffffff3,
-       0x31efffff, 0x0c30c30c, 0xc30c30c3, 0xcf3cf300, 0xf3cf3cf3, 0x0000cf3c,
+       0x310fffff, 0x0c30c30c, 0xc30c30c3, 0xcf3cf300, 0xf3cf3cf3, 0x0000cf3c,
        0xcdcdcdcd, 0xfffffff1, 0x310fffff, 0x0c30c30c, 0xc30c30c3, 0xcf3cf300,
        0xf3cf3cf3, 0x0001cf3c, 0xcdcdcdcd, 0xfffffff6, 0x305fffff, 0x0c30c30c,
        0xc30c30c3, 0xcf3cf300, 0xf3cf3cf3, 0x0002cf3c, 0xcdcdcdcd, 0xfffff406,
        0x1cbfffff, 0x0c30c305, 0xc30c30c3, 0xcf300014, 0xf3cf3cf3, 0x0004cf3c,
        0xcdcdcdcd, 0xfffffff2, 0x304fffff, 0x0c30c30c, 0xc30c30c3, 0xcf3cf300,
        0xf3cf3cf3, 0x0008cf3c, 0xcdcdcdcd, 0xfffffffa, 0x302fffff, 0x0c30c30c,
-       0xc30c30c3, 0xcf3cf300, 0xf3cf3cf3, 0x0010cf3c, 0xcdcdcdcd, 0xffffff97,
-       0x056fffff, 0x0c30c30c, 0xc30c30c3, 0xcf3cc000, 0xf3cf3cf3, 0x0020cf3c,
-       0xcdcdcdcd, 0xfffffff5, 0x310fffff, 0x0c30c30c, 0xc30c30c3, 0xcf3cf300,
-       0xf3cf3cf3, 0x0040cf3c, 0xcdcdcdcd, 0xfffffff3, 0x320fffff, 0x0c30c30c,
+       0xc30c30c3, 0xcf3cf300, 0xf3cf3cf3, 0x0010cf3c, 0xcdcdcdcd, 0xfffffff7,
+       0x30efffff, 0x0c30c30c, 0xc30c30c3, 0xcf3cf300, 0xf3cf3cf3, 0x0020cf3c,
+       0xcdcdcdcd, 0xfffffff5, 0x304fffff, 0x0c30c30c, 0xc30c30c3, 0xcf3cf300,
+       0xf3cf3cf3, 0x0040cf3c, 0xcdcdcdcd, 0xfffffff3, 0x31efffff, 0x0c30c30c,
        0xc30c30c3, 0xcf3cf300, 0xf3cf3cf3, 0x0000cf3c, 0xcdcdcdcd, 0xfffffff1,
        0x310fffff, 0x0c30c30c, 0xc30c30c3, 0xcf3cf300, 0xf3cf3cf3, 0x0001cf3c,
        0xcdcdcdcd, 0xfffffff6, 0x305fffff, 0x0c30c30c, 0xc30c30c3, 0xcf3cf300,
        0xf3cf3cf3, 0x0002cf3c, 0xcdcdcdcd, 0xfffff406, 0x1cbfffff, 0x0c30c305,
        0xc30c30c3, 0xcf300014, 0xf3cf3cf3, 0x0004cf3c, 0xcdcdcdcd, 0xfffffff2,
        0x304fffff, 0x0c30c30c, 0xc30c30c3, 0xcf3cf300, 0xf3cf3cf3, 0x0008cf3c,
-       0xcdcdcdcd, 0xffffff8a, 0x042fffff, 0x0c30c30c, 0xc30c30c3, 0xcf3cc000,
-       0xf3cf3cf3, 0x0010cf3c, 0xcdcdcdcd, 0xffffff97, 0x05cfffff, 0x0c30c30c,
+       0xcdcdcdcd, 0xfffffffa, 0x302fffff, 0x0c30c30c, 0xc30c30c3, 0xcf3cf300,
+       0xf3cf3cf3, 0x0010cf3c, 0xcdcdcdcd, 0xffffff97, 0x056fffff, 0x0c30c30c,
        0xc30c30c3, 0xcf3cc000, 0xf3cf3cf3, 0x0020cf3c, 0xcdcdcdcd, 0xfffffff5,
        0x310fffff, 0x0c30c30c, 0xc30c30c3, 0xcf3cf300, 0xf3cf3cf3, 0x0040cf3c,
-       0xcdcdcdcd, 0xfffffff3, 0x300fffff, 0x0c30c30c, 0xc30c30c3, 0xcf3cf300,
-       0xf3cf3cf3, 0x0000cf3c, 0xcdcdcdcd, 0xfffffff1, 0x300fffff, 0x0c30c30c,
+       0xcdcdcdcd, 0xfffffff3, 0x320fffff, 0x0c30c30c, 0xc30c30c3, 0xcf3cf300,
+       0xf3cf3cf3, 0x0000cf3c, 0xcdcdcdcd, 0xfffffff1, 0x310fffff, 0x0c30c30c,
        0xc30c30c3, 0xcf3cf300, 0xf3cf3cf3, 0x0001cf3c, 0xcdcdcdcd, 0xfffffff6,
        0x305fffff, 0x0c30c30c, 0xc30c30c3, 0xcf3cf300, 0xf3cf3cf3, 0x0002cf3c,
        0xcdcdcdcd, 0xfffff406, 0x1cbfffff, 0x0c30c305, 0xc30c30c3, 0xcf300014,
        0xf3cf3cf3, 0x0004cf3c, 0xcdcdcdcd, 0xfffffff2, 0x304fffff, 0x0c30c30c,
-       0xc30c30c3, 0xcf3cf300, 0xf3cf3cf3, 0x0008cf3c, 0xcdcdcdcd, 0xfffffffa,
-       0x302fffff, 0x0c30c30c, 0xc30c30c3, 0xcf3cf300, 0xf3cf3cf3, 0x0010cf3c,
-       0xcdcdcdcd, 0xffffff97, 0x040fffff, 0x0c30c30c, 0xc30c30c3, 0xcf3cc000,
-       0xf3cf3cf3, 0x0020cf3c, 0xcdcdcdcd, 0xfffffff5, 0x300fffff, 0x0c30c30c,
-       0xc30c30c3, 0xcf3cf300, 0xf3cf3cf3, 0x0040cf3c, 0xcdcdcdcd, 0xffffffff,
-       0x30cfffff, 0x0c30c30c, 0xc30c30c3, 0xcf3cf3cc, 0xf3cf3cf3, 0x0000cf3c,
-       0xcdcdcdcd, 0xffffffff, 0x30cfffff, 0x0c30c30c, 0xc30c30c3, 0xcf3cf3cc,
-       0xf3cf3cf3, 0x0001cf3c, 0xcdcdcdcd, 0xffffffff, 0x30cfffff, 0x0c30c30c,
-       0xc30c30c3, 0xcf3cf3cc, 0xf3cf3cf3, 0x0002cf3c, 0xcdcdcdcd, 0xffffffff,
-       0x30cfffff, 0x0c30c30c, 0xc30c30c3, 0xcf3cf3cc, 0xf3cf3cf3, 0x0004cf3c,
-       0xcdcdcdcd, 0xffffffff, 0x30cfffff, 0x0c30c30c, 0xc30c30c3, 0xcf3cf3cc,
-       0xf3cf3cf3, 0x0008cf3c, 0xcdcdcdcd, 0xffffffff, 0x30cfffff, 0x0c30c30c,
-       0xc30c30c3, 0xcf3cf3cc, 0xf3cf3cf3, 0x0010cf3c, 0xcdcdcdcd, 0xffffffff,
-       0x30cfffff, 0x0c30c30c, 0xc30c30c3, 0xcf3cf3cc, 0xf3cf3cf3, 0x0020cf3c,
-       0xcdcdcdcd, 0xffffffff, 0x30cfffff, 0x0c30c30c, 0xc30c30c3, 0xcf3cf3cc,
+       0xc30c30c3, 0xcf3cf300, 0xf3cf3cf3, 0x0008cf3c, 0xcdcdcdcd, 0xffffff8a,
+       0x042fffff, 0x0c30c30c, 0xc30c30c3, 0xcf3cc000, 0xf3cf3cf3, 0x0010cf3c,
+       0xcdcdcdcd, 0xffffff97, 0x05cfffff, 0x0c30c30c, 0xc30c30c3, 0xcf3cc000,
+       0xf3cf3cf3, 0x0020cf3c, 0xcdcdcdcd, 0xfffffff5, 0x310fffff, 0x0c30c30c,
+       0xc30c30c3, 0xcf3cf300, 0xf3cf3cf3, 0x0040cf3c, 0xcdcdcdcd, 0xfffffff3,
+       0x300fffff, 0x0c30c30c, 0xc30c30c3, 0xcf3cf300, 0xf3cf3cf3, 0x0000cf3c,
+       0xcdcdcdcd, 0xfffffff1, 0x300fffff, 0x0c30c30c, 0xc30c30c3, 0xcf3cf300,
+       0xf3cf3cf3, 0x0001cf3c, 0xcdcdcdcd, 0xfffffff6, 0x305fffff, 0x0c30c30c,
+       0xc30c30c3, 0xcf3cf300, 0xf3cf3cf3, 0x0002cf3c, 0xcdcdcdcd, 0xfffff406,
+       0x1cbfffff, 0x0c30c305, 0xc30c30c3, 0xcf300014, 0xf3cf3cf3, 0x0004cf3c,
+       0xcdcdcdcd, 0xfffffff2, 0x304fffff, 0x0c30c30c, 0xc30c30c3, 0xcf3cf300,
+       0xf3cf3cf3, 0x0008cf3c, 0xcdcdcdcd, 0xfffffffa, 0x302fffff, 0x0c30c30c,
+       0xc30c30c3, 0xcf3cf300, 0xf3cf3cf3, 0x0010cf3c, 0xcdcdcdcd, 0xffffff97,
+       0x040fffff, 0x0c30c30c, 0xc30c30c3, 0xcf3cc000, 0xf3cf3cf3, 0x0020cf3c,
+       0xcdcdcdcd, 0xfffffff5, 0x300fffff, 0x0c30c30c, 0xc30c30c3, 0xcf3cf300,
        0xf3cf3cf3, 0x0040cf3c, 0xcdcdcdcd, 0xffffffff, 0x30cfffff, 0x0c30c30c,
        0xc30c30c3, 0xcf3cf3cc, 0xf3cf3cf3, 0x0000cf3c, 0xcdcdcdcd, 0xffffffff,
        0x30cfffff, 0x0c30c30c, 0xc30c30c3, 0xcf3cf3cc, 0xf3cf3cf3, 0x0001cf3c,
@@ -2678,16 +2630,27 @@ static const u32 init_data_e1[] = {
        0x30cfffff, 0x0c30c30c, 0xc30c30c3, 0xcf3cf3cc, 0xf3cf3cf3, 0x0010cf3c,
        0xcdcdcdcd, 0xffffffff, 0x30cfffff, 0x0c30c30c, 0xc30c30c3, 0xcf3cf3cc,
        0xf3cf3cf3, 0x0020cf3c, 0xcdcdcdcd, 0xffffffff, 0x30cfffff, 0x0c30c30c,
-       0xc30c30c3, 0xcf3cf3cc, 0xf3cf3cf3, 0x0040cf3c, 0xcdcdcdcd, 0x00100000,
-       0x00070100, 0x00028170, 0x000b8198, 0x00020250, 0x00010270, 0x000f0280,
-       0x00010370, 0x00080000, 0x00080080, 0x00028100, 0x000b8128, 0x000201e0,
-       0x00010200, 0x00070210, 0x00020280, 0x000f0000, 0x000800f0, 0x00028170,
-       0x000b8198, 0x00020250, 0x00010270, 0x000b8280, 0x00080338, 0x00100000,
-       0x00080100, 0x00028180, 0x000b81a8, 0x00020260, 0x00018280, 0x000e8298,
-       0x00080380, 0x00028000, 0x000b8028, 0x000200e0, 0x00010100, 0x00008110,
-       0x00000118, 0xcccccccc, 0xcccccccc, 0xcccccccc, 0xcccccccc, 0x00002000,
-       0xcccccccc, 0xcccccccc, 0xcccccccc, 0xcccccccc, 0x00002000, 0xcccccccc,
-       0xcccccccc, 0xcccccccc, 0xcccccccc, 0x00002000
+       0xc30c30c3, 0xcf3cf3cc, 0xf3cf3cf3, 0x0040cf3c, 0xcdcdcdcd, 0xffffffff,
+       0x30cfffff, 0x0c30c30c, 0xc30c30c3, 0xcf3cf3cc, 0xf3cf3cf3, 0x0000cf3c,
+       0xcdcdcdcd, 0xffffffff, 0x30cfffff, 0x0c30c30c, 0xc30c30c3, 0xcf3cf3cc,
+       0xf3cf3cf3, 0x0001cf3c, 0xcdcdcdcd, 0xffffffff, 0x30cfffff, 0x0c30c30c,
+       0xc30c30c3, 0xcf3cf3cc, 0xf3cf3cf3, 0x0002cf3c, 0xcdcdcdcd, 0xffffffff,
+       0x30cfffff, 0x0c30c30c, 0xc30c30c3, 0xcf3cf3cc, 0xf3cf3cf3, 0x0004cf3c,
+       0xcdcdcdcd, 0xffffffff, 0x30cfffff, 0x0c30c30c, 0xc30c30c3, 0xcf3cf3cc,
+       0xf3cf3cf3, 0x0008cf3c, 0xcdcdcdcd, 0xffffffff, 0x30cfffff, 0x0c30c30c,
+       0xc30c30c3, 0xcf3cf3cc, 0xf3cf3cf3, 0x0010cf3c, 0xcdcdcdcd, 0xffffffff,
+       0x30cfffff, 0x0c30c30c, 0xc30c30c3, 0xcf3cf3cc, 0xf3cf3cf3, 0x0020cf3c,
+       0xcdcdcdcd, 0xffffffff, 0x30cfffff, 0x0c30c30c, 0xc30c30c3, 0xcf3cf3cc,
+       0xf3cf3cf3, 0x0040cf3c, 0xcdcdcdcd, 0x00100000, 0x00070100, 0x00028170,
+       0x000b8198, 0x00020250, 0x00010270, 0x000f0280, 0x00010370, 0x00080000,
+       0x00080080, 0x00028100, 0x000b8128, 0x000201e0, 0x00010200, 0x00070210,
+       0x00020280, 0x000f0000, 0x000800f0, 0x00028170, 0x000b8198, 0x00020250,
+       0x00010270, 0x000b8280, 0x00080338, 0x00100000, 0x00080100, 0x00028180,
+       0x000b81a8, 0x00020260, 0x00018280, 0x000e8298, 0x00080380, 0x00028000,
+       0x000b8028, 0x000200e0, 0x00010100, 0x00008110, 0x00000118, 0xcccccccc,
+       0xcccccccc, 0xcccccccc, 0xcccccccc, 0x00002000, 0xcccccccc, 0xcccccccc,
+       0xcccccccc, 0xcccccccc, 0x00002000, 0xcccccccc, 0xcccccccc, 0xcccccccc,
+       0xcccccccc, 0x00002000
 };
 
 static const u32 init_data_e1h[] = {
index ff2743db10d9ef69081a0d96762fcefe96d2de51..8b92c6ad0759107131e4d65211dad419c0b5e60f 100644 (file)
 
 /********************************************************/
 #define SUPPORT_CL73 0 /* Currently no */
-#define ETH_HLEN                       14
+#define ETH_HLEN                       14
 #define ETH_OVREHEAD           (ETH_HLEN + 8)/* 8 for CRC + VLAN*/
 #define ETH_MIN_PACKET_SIZE            60
 #define ETH_MAX_PACKET_SIZE            1500
 #define ETH_MAX_JUMBO_PACKET_SIZE      9600
 #define MDIO_ACCESS_TIMEOUT            1000
 #define BMAC_CONTROL_RX_ENABLE 2
-#define MAX_MTU_SIZE           5000
 
 /***********************************************************/
-/*                       Shortcut definitions              */
+/*                     Shortcut definitions               */
 /***********************************************************/
 
 #define NIG_STATUS_XGXS0_LINK10G \
 
 #define AUTONEG_CL37           SHARED_HW_CFG_AN_ENABLE_CL37
 #define AUTONEG_CL73           SHARED_HW_CFG_AN_ENABLE_CL73
-#define AUTONEG_BAM                    SHARED_HW_CFG_AN_ENABLE_BAM
-#define AUTONEG_PARALLEL               \
+#define AUTONEG_BAM            SHARED_HW_CFG_AN_ENABLE_BAM
+#define AUTONEG_PARALLEL \
                                SHARED_HW_CFG_AN_ENABLE_PARALLEL_DETECTION
-#define AUTONEG_SGMII_FIBER_AUTODET    \
+#define AUTONEG_SGMII_FIBER_AUTODET \
                                SHARED_HW_CFG_AN_EN_SGMII_FIBER_AUTO_DETECT
-#define AUTONEG_REMOTE_PHY             SHARED_HW_CFG_AN_ENABLE_REMOTE_PHY
+#define AUTONEG_REMOTE_PHY     SHARED_HW_CFG_AN_ENABLE_REMOTE_PHY
 
 #define GP_STATUS_PAUSE_RSOLUTION_TXSIDE \
                        MDIO_GP_STATUS_TOP_AN_STATUS1_PAUSE_RSOLUTION_TXSIDE
@@ -202,11 +201,10 @@ static void bnx2x_emac_init(struct link_params *params,
        /* init emac - use read-modify-write */
        /* self clear reset */
        val = REG_RD(bp, emac_base + EMAC_REG_EMAC_MODE);
-       EMAC_WR(EMAC_REG_EMAC_MODE, (val | EMAC_MODE_RESET));
+       EMAC_WR(bp, EMAC_REG_EMAC_MODE, (val | EMAC_MODE_RESET));
 
        timeout = 200;
-       do
-       {
+       do {
                val = REG_RD(bp, emac_base + EMAC_REG_EMAC_MODE);
                DP(NETIF_MSG_LINK, "EMAC reset reg is %u\n", val);
                if (!timeout) {
@@ -214,18 +212,18 @@ static void bnx2x_emac_init(struct link_params *params,
                        return;
                }
                timeout--;
-       }while (val & EMAC_MODE_RESET);
+       } while (val & EMAC_MODE_RESET);
 
        /* Set mac address */
        val = ((params->mac_addr[0] << 8) |
                params->mac_addr[1]);
-       EMAC_WR(EMAC_REG_EMAC_MAC_MATCH, val);
+       EMAC_WR(bp, EMAC_REG_EMAC_MAC_MATCH, val);
 
        val = ((params->mac_addr[2] << 24) |
               (params->mac_addr[3] << 16) |
               (params->mac_addr[4] << 8) |
                params->mac_addr[5]);
-       EMAC_WR(EMAC_REG_EMAC_MAC_MATCH + 4, val);
+       EMAC_WR(bp, EMAC_REG_EMAC_MAC_MATCH + 4, val);
 }
 
 static u8 bnx2x_emac_enable(struct link_params *params,
@@ -286,7 +284,7 @@ static u8 bnx2x_emac_enable(struct link_params *params,
        if (CHIP_REV_IS_SLOW(bp)) {
                /* config GMII mode */
                val = REG_RD(bp, emac_base + EMAC_REG_EMAC_MODE);
-               EMAC_WR(EMAC_REG_EMAC_MODE,
+               EMAC_WR(bp, EMAC_REG_EMAC_MODE,
                            (val | EMAC_MODE_PORT_GMII));
        } else { /* ASIC */
                /* pause enable/disable */
@@ -298,17 +296,19 @@ static u8 bnx2x_emac_enable(struct link_params *params,
                                    EMAC_RX_MODE_FLOW_EN);
 
                bnx2x_bits_dis(bp,  emac_base + EMAC_REG_EMAC_TX_MODE,
-                              EMAC_TX_MODE_EXT_PAUSE_EN);
+                            (EMAC_TX_MODE_EXT_PAUSE_EN |
+                             EMAC_TX_MODE_FLOW_EN));
                if (vars->flow_ctrl & FLOW_CTRL_TX)
                        bnx2x_bits_en(bp, emac_base +
                                    EMAC_REG_EMAC_TX_MODE,
-                                     EMAC_TX_MODE_EXT_PAUSE_EN);
+                                  (EMAC_TX_MODE_EXT_PAUSE_EN |
+                                   EMAC_TX_MODE_FLOW_EN));
        }
 
        /* KEEP_VLAN_TAG, promiscuous */
        val = REG_RD(bp, emac_base + EMAC_REG_EMAC_RX_MODE);
        val |= EMAC_RX_MODE_KEEP_VLAN_TAG | EMAC_RX_MODE_PROMISCUOUS;
-       EMAC_WR(EMAC_REG_EMAC_RX_MODE, val);
+       EMAC_WR(bp, EMAC_REG_EMAC_RX_MODE, val);
 
        /* Set Loopback */
        val = REG_RD(bp, emac_base + EMAC_REG_EMAC_MODE);
@@ -316,10 +316,10 @@ static u8 bnx2x_emac_enable(struct link_params *params,
                val |= 0x810;
        else
                val &= ~0x810;
-       EMAC_WR(EMAC_REG_EMAC_MODE, val);
+       EMAC_WR(bp, EMAC_REG_EMAC_MODE, val);
 
        /* enable emac for jumbo packets */
-       EMAC_WR(EMAC_REG_EMAC_RX_MTU_SIZE,
+       EMAC_WR(bp, EMAC_REG_EMAC_RX_MTU_SIZE,
                (EMAC_RX_MTU_SIZE_JUMBO_ENA |
                 (ETH_MAX_JUMBO_PACKET_SIZE + ETH_OVREHEAD)));
 
@@ -591,9 +591,9 @@ void bnx2x_link_status_update(struct link_params *params,
                        vars->flow_ctrl &= ~FLOW_CTRL_RX;
 
                if (vars->phy_flags & PHY_XGXS_FLAG) {
-                       if (params->req_line_speed &&
-                           ((params->req_line_speed == SPEED_10) ||
-                            (params->req_line_speed == SPEED_100))) {
+                       if (vars->line_speed &&
+                           ((vars->line_speed == SPEED_10) ||
+                            (vars->line_speed == SPEED_100))) {
                                vars->phy_flags |= PHY_SGMII_FLAG;
                        } else {
                                vars->phy_flags &= ~PHY_SGMII_FLAG;
@@ -645,7 +645,7 @@ static void bnx2x_bmac_rx_disable(struct bnx2x *bp, u8 port)
        u32 bmac_addr = port ? NIG_REG_INGRESS_BMAC1_MEM :
                NIG_REG_INGRESS_BMAC0_MEM;
        u32 wb_data[2];
-    u32 nig_bmac_enable = REG_RD(bp, NIG_REG_BMAC0_REGS_OUT_EN + port*4);
+       u32 nig_bmac_enable = REG_RD(bp, NIG_REG_BMAC0_REGS_OUT_EN + port*4);
 
        /* Only if the bmac is out of reset */
        if (REG_RD(bp, MISC_REG_RESET_REG_2) &
@@ -670,7 +670,6 @@ static u8 bnx2x_pbf_update(struct link_params *params, u32 flow_ctrl,
        u8 port = params->port;
        u32 init_crd, crd;
        u32 count = 1000;
-       u32 pause = 0;
 
        /* disable port */
        REG_WR(bp, PBF_REG_DISABLE_NEW_TASK_PROC_P0 + port*4, 0x1);
@@ -693,33 +692,25 @@ static u8 bnx2x_pbf_update(struct link_params *params, u32 flow_ctrl,
                return -EINVAL;
        }
 
-       if (flow_ctrl & FLOW_CTRL_RX)
-               pause = 1;
-       REG_WR(bp, PBF_REG_P0_PAUSE_ENABLE + port*4, pause);
-       if (pause) {
+       if (flow_ctrl & FLOW_CTRL_RX ||
+           line_speed == SPEED_10 ||
+           line_speed == SPEED_100 ||
+           line_speed == SPEED_1000 ||
+           line_speed == SPEED_2500) {
+               REG_WR(bp, PBF_REG_P0_PAUSE_ENABLE + port*4, 1);
                /* update threshold */
                REG_WR(bp, PBF_REG_P0_ARB_THRSH + port*4, 0);
                /* update init credit */
-               init_crd = 778;         /* (800-18-4) */
+               init_crd = 778;         /* (800-18-4) */
 
        } else {
                u32 thresh = (ETH_MAX_JUMBO_PACKET_SIZE +
                              ETH_OVREHEAD)/16;
-
+               REG_WR(bp, PBF_REG_P0_PAUSE_ENABLE + port*4, 0);
                /* update threshold */
                REG_WR(bp, PBF_REG_P0_ARB_THRSH + port*4, thresh);
                /* update init credit */
                switch (line_speed) {
-               case SPEED_10:
-               case SPEED_100:
-               case SPEED_1000:
-                       init_crd = thresh + 55 - 22;
-                       break;
-
-               case SPEED_2500:
-                       init_crd = thresh + 138 - 22;
-                       break;
-
                case SPEED_10000:
                        init_crd = thresh + 553 - 22;
                        break;
@@ -764,10 +755,10 @@ static u32 bnx2x_get_emac_base(u32 ext_phy_type, u8 port)
                emac_base = GRCBASE_EMAC0;
                break;
        case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073:
-               emac_base = (port) ? GRCBASE_EMAC0: GRCBASE_EMAC1;
+               emac_base = (port) ? GRCBASE_EMAC0 : GRCBASE_EMAC1;
                break;
        default:
-               emac_base = (port) ? GRCBASE_EMAC1: GRCBASE_EMAC0;
+               emac_base = (port) ? GRCBASE_EMAC1 : GRCBASE_EMAC0;
                break;
        }
        return emac_base;
@@ -1044,7 +1035,7 @@ static void bnx2x_set_swap_lanes(struct link_params *params)
 }
 
 static void bnx2x_set_parallel_detection(struct link_params *params,
-                                      u8                phy_flags)
+                                      u8                phy_flags)
 {
        struct bnx2x *bp = params->bp;
        u16 control2;
@@ -1114,7 +1105,7 @@ static void bnx2x_set_autoneg(struct link_params *params,
                              MDIO_COMBO_IEEE0_MII_CONTROL, &reg_val);
 
        /* CL37 Autoneg Enabled */
-       if (params->req_line_speed == SPEED_AUTO_NEG)
+       if (vars->line_speed == SPEED_AUTO_NEG)
                reg_val |= MDIO_COMBO_IEEO_MII_CONTROL_AN_EN;
        else /* CL37 Autoneg Disabled */
                reg_val &= ~(MDIO_COMBO_IEEO_MII_CONTROL_AN_EN |
@@ -1132,7 +1123,7 @@ static void bnx2x_set_autoneg(struct link_params *params,
                              MDIO_REG_BANK_SERDES_DIGITAL,
                              MDIO_SERDES_DIGITAL_A_1000X_CONTROL1, &reg_val);
        reg_val &= ~MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_SIGNAL_DETECT_EN;
-       if (params->req_line_speed == SPEED_AUTO_NEG)
+       if (vars->line_speed == SPEED_AUTO_NEG)
                reg_val |= MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_AUTODET;
        else
                reg_val &= ~MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_AUTODET;
@@ -1148,7 +1139,7 @@ static void bnx2x_set_autoneg(struct link_params *params,
                              MDIO_REG_BANK_BAM_NEXT_PAGE,
                              MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL,
                          &reg_val);
-       if (params->req_line_speed == SPEED_AUTO_NEG) {
+       if (vars->line_speed == SPEED_AUTO_NEG) {
                /* Enable BAM aneg Mode and TetonII aneg Mode */
                reg_val |= (MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL_BAM_MODE |
                            MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL_TETON_AN);
@@ -1164,7 +1155,7 @@ static void bnx2x_set_autoneg(struct link_params *params,
                              reg_val);
 
        /* Enable Clause 73 Aneg */
-       if ((params->req_line_speed == SPEED_AUTO_NEG) &&
+       if ((vars->line_speed == SPEED_AUTO_NEG) &&
            (SUPPORT_CL73)) {
                /* Enable BAM Station Manager */
 
@@ -1226,7 +1217,8 @@ static void bnx2x_set_autoneg(struct link_params *params,
 }
 
 /* program SerDes, forced speed */
-static void bnx2x_program_serdes(struct link_params *params)
+static void bnx2x_program_serdes(struct link_params *params,
+                              struct link_vars *vars)
 {
        struct bnx2x *bp = params->bp;
        u16 reg_val;
@@ -1248,28 +1240,35 @@ static void bnx2x_program_serdes(struct link_params *params)
 
        /* program speed
           - needed only if the speed is greater than 1G (2.5G or 10G) */
-       if (!((params->req_line_speed == SPEED_1000) ||
-             (params->req_line_speed == SPEED_100) ||
-             (params->req_line_speed == SPEED_10))) {
-               CL45_RD_OVER_CL22(bp, params->port,
+       CL45_RD_OVER_CL22(bp, params->port,
                                      params->phy_addr,
                                      MDIO_REG_BANK_SERDES_DIGITAL,
                                      MDIO_SERDES_DIGITAL_MISC1, &reg_val);
-               /* clearing the speed value before setting the right speed */
-               reg_val &= ~MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_MASK;
+       /* clearing the speed value before setting the right speed */
+       DP(NETIF_MSG_LINK, "MDIO_REG_BANK_SERDES_DIGITAL = 0x%x\n", reg_val);
+
+       reg_val &= ~(MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_MASK |
+                    MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_SEL);
+
+       if (!((vars->line_speed == SPEED_1000) ||
+             (vars->line_speed == SPEED_100) ||
+             (vars->line_speed == SPEED_10))) {
+
                reg_val |= (MDIO_SERDES_DIGITAL_MISC1_REFCLK_SEL_156_25M |
                            MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_SEL);
-               if (params->req_line_speed == SPEED_10000)
+               if (vars->line_speed == SPEED_10000)
                        reg_val |=
                                MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_10G_CX4;
-               if (params->req_line_speed == SPEED_13000)
+               if (vars->line_speed == SPEED_13000)
                        reg_val |=
                                MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_13G;
-               CL45_WR_OVER_CL22(bp, params->port,
+       }
+
+       CL45_WR_OVER_CL22(bp, params->port,
                                      params->phy_addr,
                                      MDIO_REG_BANK_SERDES_DIGITAL,
                                      MDIO_SERDES_DIGITAL_MISC1, reg_val);
-       }
+
 }
 
 static void bnx2x_set_brcm_cl37_advertisment(struct link_params *params)
@@ -1295,48 +1294,49 @@ static void bnx2x_set_brcm_cl37_advertisment(struct link_params *params)
                              MDIO_OVER_1G_UP3, 0);
 }
 
-static void bnx2x_set_ieee_aneg_advertisment(struct link_params *params,
-                                          u32 *ieee_fc)
+static void bnx2x_calc_ieee_aneg_adv(struct link_params *params, u32 *ieee_fc)
 {
-       struct bnx2x *bp = params->bp;
-       /* for AN, we are always publishing full duplex */
-       u16 an_adv = MDIO_COMBO_IEEE0_AUTO_NEG_ADV_FULL_DUPLEX;
-
+       *ieee_fc = MDIO_COMBO_IEEE0_AUTO_NEG_ADV_FULL_DUPLEX;
        /* resolve pause mode and advertisement
         * Please refer to Table 28B-3 of the 802.3ab-1999 spec */
 
        switch (params->req_flow_ctrl) {
        case FLOW_CTRL_AUTO:
-               if (params->mtu <= MAX_MTU_SIZE) {
-                       an_adv |=
+               if (params->req_fc_auto_adv == FLOW_CTRL_BOTH) {
+                       *ieee_fc |=
                             MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH;
                } else {
-                       an_adv |=
+                       *ieee_fc |=
                       MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC;
                }
                break;
        case FLOW_CTRL_TX:
-               an_adv |=
+               *ieee_fc |=
                       MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC;
                break;
 
        case FLOW_CTRL_RX:
        case FLOW_CTRL_BOTH:
-               an_adv |= MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH;
+               *ieee_fc |= MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH;
                break;
 
        case FLOW_CTRL_NONE:
        default:
-               an_adv |= MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_NONE;
+               *ieee_fc |= MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_NONE;
                break;
        }
+}
 
-       *ieee_fc = an_adv;
+static void bnx2x_set_ieee_aneg_advertisment(struct link_params *params,
+                                          u32 ieee_fc)
+{
+       struct bnx2x *bp = params->bp;
+       /* for AN, we are always publishing full duplex */
 
        CL45_WR_OVER_CL22(bp, params->port,
                              params->phy_addr,
                              MDIO_REG_BANK_COMBO_IEEE0,
-                             MDIO_COMBO_IEEE0_AUTO_NEG_ADV, an_adv);
+                             MDIO_COMBO_IEEE0_AUTO_NEG_ADV, (u16)ieee_fc);
 }
 
 static void bnx2x_restart_autoneg(struct link_params *params)
@@ -1382,7 +1382,8 @@ static void bnx2x_restart_autoneg(struct link_params *params)
        }
 }
 
-static void bnx2x_initialize_sgmii_process(struct link_params *params)
+static void bnx2x_initialize_sgmii_process(struct link_params *params,
+                                        struct link_vars *vars)
 {
        struct bnx2x *bp = params->bp;
        u16 control1;
@@ -1406,7 +1407,7 @@ static void bnx2x_initialize_sgmii_process(struct link_params *params)
                              control1);
 
        /* if forced speed */
-       if (!(params->req_line_speed == SPEED_AUTO_NEG)) {
+       if (!(vars->line_speed == SPEED_AUTO_NEG)) {
                /* set speed, disable autoneg */
                u16 mii_control;
 
@@ -1419,7 +1420,7 @@ static void bnx2x_initialize_sgmii_process(struct link_params *params)
                                 MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_MASK|
                                 MDIO_COMBO_IEEO_MII_CONTROL_FULL_DUPLEX);
 
-               switch (params->req_line_speed) {
+               switch (vars->line_speed) {
                case SPEED_100:
                        mii_control |=
                                MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_100;
@@ -1433,8 +1434,8 @@ static void bnx2x_initialize_sgmii_process(struct link_params *params)
                        break;
                default:
                        /* invalid speed for SGMII */
-                       DP(NETIF_MSG_LINK, "Invalid req_line_speed 0x%x\n",
-                                 params->req_line_speed);
+                       DP(NETIF_MSG_LINK, "Invalid line_speed 0x%x\n",
+                                 vars->line_speed);
                        break;
                }
 
@@ -1460,20 +1461,20 @@ static void bnx2x_initialize_sgmii_process(struct link_params *params)
  */
 
 static void bnx2x_pause_resolve(struct link_vars *vars, u32 pause_result)
-{
-       switch (pause_result) {                 /* ASYM P ASYM P */
-       case 0xb:                               /*   1  0   1  1 */
+{                                              /*  LD      LP   */
+       switch (pause_result) {                 /* ASYM P ASYM P */
+       case 0xb:                               /*   1  0   1  1 */
                vars->flow_ctrl = FLOW_CTRL_TX;
                break;
 
-       case 0xe:                               /*   1  1   1  0 */
+       case 0xe:                               /*   1  1   1  0 */
                vars->flow_ctrl = FLOW_CTRL_RX;
                break;
 
-       case 0x5:                               /*   0  1   0  1 */
-       case 0x7:                               /*   0  1   1  1 */
-       case 0xd:                               /*   1  1   0  1 */
-       case 0xf:                               /*   1  1   1  1 */
+       case 0x5:                               /*   0  1   0  1 */
+       case 0x7:                               /*   0  1   1  1 */
+       case 0xd:                               /*   1  1   0  1 */
+       case 0xf:                               /*   1  1   1  1 */
                vars->flow_ctrl = FLOW_CTRL_BOTH;
                break;
 
@@ -1531,6 +1532,28 @@ static u8 bnx2x_ext_phy_resove_fc(struct link_params *params,
                DP(NETIF_MSG_LINK, "Ext PHY pause result 0x%x \n",
                   pause_result);
                bnx2x_pause_resolve(vars, pause_result);
+               if (vars->flow_ctrl == FLOW_CTRL_NONE &&
+                    ext_phy_type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073) {
+                       bnx2x_cl45_read(bp, port,
+                                     ext_phy_type,
+                                     ext_phy_addr,
+                                     MDIO_AN_DEVAD,
+                                     MDIO_AN_REG_CL37_FC_LD, &ld_pause);
+
+                       bnx2x_cl45_read(bp, port,
+                                     ext_phy_type,
+                                     ext_phy_addr,
+                                     MDIO_AN_DEVAD,
+                                     MDIO_AN_REG_CL37_FC_LP, &lp_pause);
+                       pause_result = (ld_pause &
+                               MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) >> 5;
+                       pause_result |= (lp_pause &
+                               MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) >> 7;
+
+                       bnx2x_pause_resolve(vars, pause_result);
+                       DP(NETIF_MSG_LINK, "Ext PHY CL37 pause result 0x%x \n",
+                                pause_result);
+               }
        }
        return ret;
 }
@@ -1541,8 +1564,8 @@ static void bnx2x_flow_ctrl_resolve(struct link_params *params,
                                  u32 gp_status)
 {
        struct bnx2x *bp = params->bp;
-       u16 ld_pause;   /* local driver */
-       u16 lp_pause;   /* link partner */
+       u16 ld_pause;   /* local driver */
+       u16 lp_pause;   /* link partner */
        u16 pause_result;
 
        vars->flow_ctrl = FLOW_CTRL_NONE;
@@ -1573,13 +1596,10 @@ static void bnx2x_flow_ctrl_resolve(struct link_params *params,
                   (bnx2x_ext_phy_resove_fc(params, vars))) {
                return;
        } else {
-               vars->flow_ctrl = params->req_flow_ctrl;
-               if (vars->flow_ctrl == FLOW_CTRL_AUTO) {
-                       if (params->mtu <= MAX_MTU_SIZE)
-                               vars->flow_ctrl = FLOW_CTRL_BOTH;
-                       else
-                               vars->flow_ctrl = FLOW_CTRL_TX;
-               }
+               if (params->req_flow_ctrl == FLOW_CTRL_AUTO)
+                       vars->flow_ctrl = params->req_fc_auto_adv;
+               else
+                       vars->flow_ctrl = params->req_flow_ctrl;
        }
        DP(NETIF_MSG_LINK, "flow_ctrl 0x%x\n", vars->flow_ctrl);
 }
@@ -1590,6 +1610,7 @@ static u8 bnx2x_link_settings_status(struct link_params *params,
                                      u32 gp_status)
 {
        struct bnx2x *bp = params->bp;
+
        u8 rc = 0;
        vars->link_status = 0;
 
@@ -1690,7 +1711,11 @@ static u8 bnx2x_link_settings_status(struct link_params *params,
 
                vars->link_status |= LINK_STATUS_SERDES_LINK;
 
-               if (params->req_line_speed == SPEED_AUTO_NEG) {
+               if ((params->req_line_speed == SPEED_AUTO_NEG) &&
+                   ((XGXS_EXT_PHY_TYPE(params->ext_phy_config) ==
+                    PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT) ||
+                   (XGXS_EXT_PHY_TYPE(params->ext_phy_config) ==
+                    PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8705))) {
                        vars->autoneg = AUTO_NEG_ENABLED;
 
                        if (gp_status & MDIO_AN_CL73_OR_37_COMPLETE) {
@@ -1705,18 +1730,18 @@ static u8 bnx2x_link_settings_status(struct link_params *params,
 
                }
                if (vars->flow_ctrl & FLOW_CTRL_TX)
-                      vars->link_status |=
-                       LINK_STATUS_TX_FLOW_CONTROL_ENABLED;
+                       vars->link_status |=
+                               LINK_STATUS_TX_FLOW_CONTROL_ENABLED;
 
                if (vars->flow_ctrl & FLOW_CTRL_RX)
-                      vars->link_status |=
-                       LINK_STATUS_RX_FLOW_CONTROL_ENABLED;
+                       vars->link_status |=
+                               LINK_STATUS_RX_FLOW_CONTROL_ENABLED;
 
        } else { /* link_down */
                DP(NETIF_MSG_LINK, "phy link down\n");
 
                vars->phy_link_up = 0;
-               vars->line_speed = 0;
+
                vars->duplex = DUPLEX_FULL;
                vars->flow_ctrl = FLOW_CTRL_NONE;
                vars->autoneg = AUTO_NEG_DISABLED;
@@ -1817,15 +1842,15 @@ static u8 bnx2x_emac_program(struct link_params *params,
 }
 
 /*****************************************************************************/
-/*                           External Phy section                            */
+/*                          External Phy section                            */
 /*****************************************************************************/
-static void bnx2x_hw_reset(struct bnx2x *bp)
+static void bnx2x_hw_reset(struct bnx2x *bp, u8 port)
 {
        bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_1,
-                      MISC_REGISTERS_GPIO_OUTPUT_LOW);
+                      MISC_REGISTERS_GPIO_OUTPUT_LOW, port);
        msleep(1);
        bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_1,
-                     MISC_REGISTERS_GPIO_OUTPUT_HIGH);
+                     MISC_REGISTERS_GPIO_OUTPUT_HIGH, port);
 }
 
 static void bnx2x_ext_phy_reset(struct link_params *params,
@@ -1854,10 +1879,11 @@ static void bnx2x_ext_phy_reset(struct link_params *params,
 
                        /* Restore normal power mode*/
                        bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2,
-                                     MISC_REGISTERS_GPIO_OUTPUT_HIGH);
+                                     MISC_REGISTERS_GPIO_OUTPUT_HIGH,
+                                         params->port);
 
                        /* HW reset */
-                       bnx2x_hw_reset(bp);
+                       bnx2x_hw_reset(bp, params->port);
 
                        bnx2x_cl45_write(bp, params->port,
                                       ext_phy_type,
@@ -1869,7 +1895,8 @@ static void bnx2x_ext_phy_reset(struct link_params *params,
                        /* Unset Low Power Mode and SW reset */
                        /* Restore normal power mode*/
                        bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2,
-                                     MISC_REGISTERS_GPIO_OUTPUT_HIGH);
+                                     MISC_REGISTERS_GPIO_OUTPUT_HIGH,
+                                         params->port);
 
                        DP(NETIF_MSG_LINK, "XGXS 8072\n");
                        bnx2x_cl45_write(bp, params->port,
@@ -1887,19 +1914,14 @@ static void bnx2x_ext_phy_reset(struct link_params *params,
 
                        /* Restore normal power mode*/
                        bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2,
-                                     MISC_REGISTERS_GPIO_OUTPUT_HIGH);
+                                     MISC_REGISTERS_GPIO_OUTPUT_HIGH,
+                                         params->port);
 
                        bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_1,
-                                     MISC_REGISTERS_GPIO_OUTPUT_HIGH);
+                                     MISC_REGISTERS_GPIO_OUTPUT_HIGH,
+                                         params->port);
 
                        DP(NETIF_MSG_LINK, "XGXS 8073\n");
-                       bnx2x_cl45_write(bp,
-                                      params->port,
-                                      ext_phy_type,
-                                      ext_phy_addr,
-                                      MDIO_PMA_DEVAD,
-                                      MDIO_PMA_REG_CTRL,
-                                      1<<15);
                        }
                        break;
 
@@ -1908,10 +1930,11 @@ static void bnx2x_ext_phy_reset(struct link_params *params,
 
                        /* Restore normal power mode*/
                        bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2,
-                                     MISC_REGISTERS_GPIO_OUTPUT_HIGH);
+                                     MISC_REGISTERS_GPIO_OUTPUT_HIGH,
+                                         params->port);
 
                        /* HW reset */
-                       bnx2x_hw_reset(bp);
+                       bnx2x_hw_reset(bp, params->port);
 
                        break;
 
@@ -1934,7 +1957,7 @@ static void bnx2x_ext_phy_reset(struct link_params *params,
 
                case PORT_HW_CFG_SERDES_EXT_PHY_TYPE_BCM5482:
                        DP(NETIF_MSG_LINK, "SerDes 5482\n");
-                       bnx2x_hw_reset(bp);
+                       bnx2x_hw_reset(bp, params->port);
                        break;
 
                default:
@@ -2098,42 +2121,45 @@ static u8 bnx2x_bcm8073_xaui_wa(struct link_params *params)
 
 }
 
-static void bnx2x_bcm8073_external_rom_boot(struct link_params *params)
+static void bnx2x_bcm8073_external_rom_boot(struct bnx2x *bp, u8 port,
+                                         u8 ext_phy_addr)
 {
-       struct bnx2x *bp = params->bp;
-       u8 port = params->port;
-       u8 ext_phy_addr = ((params->ext_phy_config &
-                            PORT_HW_CFG_XGXS_EXT_PHY_ADDR_MASK) >>
-                           PORT_HW_CFG_XGXS_EXT_PHY_ADDR_SHIFT);
-       u32 ext_phy_type = XGXS_EXT_PHY_TYPE(params->ext_phy_config);
-       u16 fw_ver1, fw_ver2, val;
-       /* Need to wait 100ms after reset */
-       msleep(100);
-       /* Boot port from external ROM  */
+       u16 fw_ver1, fw_ver2;
+       /* Boot port from external ROM  */
        /* EDC grst */
-       bnx2x_cl45_write(bp, port, ext_phy_type, ext_phy_addr,
+       bnx2x_cl45_write(bp, port,
+                      PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073,
+                      ext_phy_addr,
                       MDIO_PMA_DEVAD,
                       MDIO_PMA_REG_GEN_CTRL,
                       0x0001);
 
        /* ucode reboot and rst */
-       bnx2x_cl45_write(bp, port, ext_phy_type, ext_phy_addr,
+       bnx2x_cl45_write(bp, port,
+                      PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073,
+                      ext_phy_addr,
                       MDIO_PMA_DEVAD,
                       MDIO_PMA_REG_GEN_CTRL,
                       0x008c);
 
-       bnx2x_cl45_write(bp, port, ext_phy_type, ext_phy_addr,
+       bnx2x_cl45_write(bp, port,
+                      PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073,
+                      ext_phy_addr,
                       MDIO_PMA_DEVAD,
                       MDIO_PMA_REG_MISC_CTRL1, 0x0001);
 
        /* Reset internal microprocessor */
-       bnx2x_cl45_write(bp, port, ext_phy_type, ext_phy_addr,
+       bnx2x_cl45_write(bp, port,
+                      PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073,
+                      ext_phy_addr,
                       MDIO_PMA_DEVAD,
                       MDIO_PMA_REG_GEN_CTRL,
                       MDIO_PMA_REG_GEN_CTRL_ROM_MICRO_RESET);
 
        /* Release srst bit */
-       bnx2x_cl45_write(bp, port, ext_phy_type, ext_phy_addr,
+       bnx2x_cl45_write(bp, port,
+                      PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073,
+                      ext_phy_addr,
                       MDIO_PMA_DEVAD,
                       MDIO_PMA_REG_GEN_CTRL,
                       MDIO_PMA_REG_GEN_CTRL_ROM_RESET_INTERNAL_MP);
@@ -2142,35 +2168,52 @@ static void bnx2x_bcm8073_external_rom_boot(struct link_params *params)
        msleep(100);
 
        /* Clear ser_boot_ctl bit */
-       bnx2x_cl45_write(bp, port, ext_phy_type, ext_phy_addr,
+       bnx2x_cl45_write(bp, port,
+                      PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073,
+                      ext_phy_addr,
                       MDIO_PMA_DEVAD,
                       MDIO_PMA_REG_MISC_CTRL1, 0x0000);
 
-       bnx2x_cl45_read(bp, port, ext_phy_type, ext_phy_addr,
-                      MDIO_PMA_DEVAD,
-                      MDIO_PMA_REG_ROM_VER1, &fw_ver1);
-       bnx2x_cl45_read(bp, port, ext_phy_type, ext_phy_addr,
-                      MDIO_PMA_DEVAD,
-                      MDIO_PMA_REG_ROM_VER2, &fw_ver2);
+       bnx2x_cl45_read(bp, port, PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073,
+                     ext_phy_addr,
+                     MDIO_PMA_DEVAD,
+                     MDIO_PMA_REG_ROM_VER1, &fw_ver1);
+       bnx2x_cl45_read(bp, port,
+                     PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073,
+                     ext_phy_addr,
+                     MDIO_PMA_DEVAD,
+                     MDIO_PMA_REG_ROM_VER2, &fw_ver2);
        DP(NETIF_MSG_LINK, "8073 FW version 0x%x:0x%x\n", fw_ver1, fw_ver2);
 
-       /* Only set bit 10 = 1 (Tx power down) */
-       bnx2x_cl45_read(bp, port, ext_phy_type, ext_phy_addr,
-                      MDIO_PMA_DEVAD,
-                      MDIO_PMA_REG_TX_POWER_DOWN, &val);
+}
+
+static void bnx2x_bcm807x_force_10G(struct link_params *params)
+{
+       struct bnx2x *bp = params->bp;
+       u8 port = params->port;
+       u8 ext_phy_addr = ((params->ext_phy_config &
+                               PORT_HW_CFG_XGXS_EXT_PHY_ADDR_MASK) >>
+                               PORT_HW_CFG_XGXS_EXT_PHY_ADDR_SHIFT);
+       u32 ext_phy_type = XGXS_EXT_PHY_TYPE(params->ext_phy_config);
 
+       /* Force KR or KX */
        bnx2x_cl45_write(bp, port, ext_phy_type, ext_phy_addr,
                       MDIO_PMA_DEVAD,
-                      MDIO_PMA_REG_TX_POWER_DOWN, (val | 1<<10));
-
-       msleep(600);
-       /* Release bit 10 (Release Tx power down) */
+                      MDIO_PMA_REG_CTRL,
+                      0x2040);
        bnx2x_cl45_write(bp, port, ext_phy_type, ext_phy_addr,
                       MDIO_PMA_DEVAD,
-                      MDIO_PMA_REG_TX_POWER_DOWN, (val & (~(1<<10))));
-
+                      MDIO_PMA_REG_10G_CTRL2,
+                      0x000b);
+       bnx2x_cl45_write(bp, port, ext_phy_type, ext_phy_addr,
+                      MDIO_PMA_DEVAD,
+                      MDIO_PMA_REG_BCM_CTRL,
+                      0x0000);
+       bnx2x_cl45_write(bp, port, ext_phy_type, ext_phy_addr,
+                      MDIO_AN_DEVAD,
+                      MDIO_AN_REG_CTRL,
+                      0x0000);
 }
-
 static void bnx2x_bcm8073_set_xaui_low_power_mode(struct link_params *params)
 {
        struct bnx2x *bp = params->bp;
@@ -2236,32 +2279,51 @@ static void bnx2x_bcm8073_set_xaui_low_power_mode(struct link_params *params)
        bnx2x_cl45_write(bp, port, ext_phy_type, ext_phy_addr,
                       MDIO_XS_DEVAD, MDIO_XS_PLL_SEQUENCER, val);
 }
-static void bnx2x_bcm807x_force_10G(struct link_params *params)
+
+static void bnx2x_8073_set_pause_cl37(struct link_params *params,
+                                 struct link_vars *vars)
 {
+
        struct bnx2x *bp = params->bp;
-       u8 port = params->port;
+       u16 cl37_val;
        u8 ext_phy_addr = ((params->ext_phy_config &
                                PORT_HW_CFG_XGXS_EXT_PHY_ADDR_MASK) >>
                                PORT_HW_CFG_XGXS_EXT_PHY_ADDR_SHIFT);
        u32 ext_phy_type = XGXS_EXT_PHY_TYPE(params->ext_phy_config);
 
-       /* Force KR or KX */
-       bnx2x_cl45_write(bp, port, ext_phy_type, ext_phy_addr,
-                      MDIO_PMA_DEVAD,
-                      MDIO_PMA_REG_CTRL,
-                      0x2040);
-       bnx2x_cl45_write(bp, port, ext_phy_type, ext_phy_addr,
-                      MDIO_PMA_DEVAD,
-                      MDIO_PMA_REG_10G_CTRL2,
-                      0x000b);
-       bnx2x_cl45_write(bp, port, ext_phy_type, ext_phy_addr,
-                      MDIO_PMA_DEVAD,
-                      MDIO_PMA_REG_BCM_CTRL,
-                      0x0000);
-       bnx2x_cl45_write(bp, port, ext_phy_type, ext_phy_addr,
+       bnx2x_cl45_read(bp, params->port,
+                     ext_phy_type,
+                     ext_phy_addr,
+                     MDIO_AN_DEVAD,
+                     MDIO_AN_REG_CL37_FC_LD, &cl37_val);
+
+       cl37_val &= ~MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH;
+       /* Please refer to Table 28B-3 of 802.3ab-1999 spec. */
+
+       if ((vars->ieee_fc &
+           MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_SYMMETRIC) ==
+           MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_SYMMETRIC) {
+               cl37_val |=  MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_SYMMETRIC;
+       }
+       if ((vars->ieee_fc &
+           MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC) ==
+           MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC) {
+               cl37_val |=  MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC;
+       }
+       if ((vars->ieee_fc &
+           MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) ==
+           MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) {
+               cl37_val |= MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH;
+       }
+       DP(NETIF_MSG_LINK,
+                "Ext phy AN advertize cl37 0x%x\n", cl37_val);
+
+       bnx2x_cl45_write(bp, params->port,
+                      ext_phy_type,
+                      ext_phy_addr,
                       MDIO_AN_DEVAD,
-                      MDIO_AN_REG_CTRL,
-                      0x0000);
+                      MDIO_AN_REG_CL37_FC_LD, cl37_val);
+       msleep(500);
 }
 
 static void bnx2x_ext_phy_set_pause(struct link_params *params,
@@ -2282,13 +2344,16 @@ static void bnx2x_ext_phy_set_pause(struct link_params *params,
                      MDIO_AN_REG_ADV_PAUSE, &val);
 
        val &= ~MDIO_AN_REG_ADV_PAUSE_BOTH;
+
        /* Please refer to Table 28B-3 of 802.3ab-1999 spec. */
 
-       if (vars->ieee_fc &
+       if ((vars->ieee_fc &
+           MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC) ==
            MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC) {
                val |=  MDIO_AN_REG_ADV_PAUSE_ASYMMETRIC;
        }
-       if (vars->ieee_fc &
+       if ((vars->ieee_fc &
+           MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) ==
            MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) {
                val |=
                 MDIO_AN_REG_ADV_PAUSE_PAUSE;
@@ -2302,6 +2367,65 @@ static void bnx2x_ext_phy_set_pause(struct link_params *params,
                       MDIO_AN_REG_ADV_PAUSE, val);
 }
 
+
+static void bnx2x_init_internal_phy(struct link_params *params,
+                               struct link_vars *vars)
+{
+       struct bnx2x *bp = params->bp;
+       u8 port = params->port;
+       if (!(vars->phy_flags & PHY_SGMII_FLAG)) {
+               u16 bank, rx_eq;
+
+               rx_eq = ((params->serdes_config &
+                         PORT_HW_CFG_SERDES_RX_DRV_EQUALIZER_MASK) >>
+                        PORT_HW_CFG_SERDES_RX_DRV_EQUALIZER_SHIFT);
+
+               DP(NETIF_MSG_LINK, "setting rx eq to 0x%x\n", rx_eq);
+               for (bank = MDIO_REG_BANK_RX0; bank <= MDIO_REG_BANK_RX_ALL;
+                     bank += (MDIO_REG_BANK_RX1-MDIO_REG_BANK_RX0)) {
+                       CL45_WR_OVER_CL22(bp, port,
+                                             params->phy_addr,
+                                             bank ,
+                                             MDIO_RX0_RX_EQ_BOOST,
+                                             ((rx_eq &
+                               MDIO_RX0_RX_EQ_BOOST_EQUALIZER_CTRL_MASK) |
+                               MDIO_RX0_RX_EQ_BOOST_OFFSET_CTRL));
+               }
+
+               /* forced speed requested? */
+               if (vars->line_speed != SPEED_AUTO_NEG) {
+                       DP(NETIF_MSG_LINK, "not SGMII, no AN\n");
+
+                       /* disable autoneg */
+                       bnx2x_set_autoneg(params, vars);
+
+                       /* program speed and duplex */
+                       bnx2x_program_serdes(params, vars);
+
+               } else { /* AN_mode */
+                       DP(NETIF_MSG_LINK, "not SGMII, AN\n");
+
+                       /* AN enabled */
+                       bnx2x_set_brcm_cl37_advertisment(params);
+
+                       /* program duplex & pause advertisement (for aneg) */
+                       bnx2x_set_ieee_aneg_advertisment(params,
+                                                      vars->ieee_fc);
+
+                       /* enable autoneg */
+                       bnx2x_set_autoneg(params, vars);
+
+                       /* enable and restart AN */
+                       bnx2x_restart_autoneg(params);
+               }
+
+       } else { /* SGMII mode */
+               DP(NETIF_MSG_LINK, "SGMII\n");
+
+               bnx2x_initialize_sgmii_process(params, vars);
+       }
+}
+
 static u8 bnx2x_ext_phy_init(struct link_params *params, struct link_vars *vars)
 {
        struct bnx2x *bp = params->bp;
@@ -2343,7 +2467,6 @@ static u8 bnx2x_ext_phy_init(struct link_params *params, struct link_vars *vars)
 
                switch (ext_phy_type) {
                case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT:
-                       DP(NETIF_MSG_LINK, "XGXS Direct\n");
                        break;
 
                case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8705:
@@ -2419,7 +2542,7 @@ static u8 bnx2x_ext_phy_init(struct link_params *params, struct link_vars *vars)
                                               ext_phy_type,
                                               ext_phy_addr,
                                               MDIO_AN_DEVAD,
-                                              MDIO_AN_REG_CL37_FD,
+                                              MDIO_AN_REG_CL37_FC_LP,
                                               0x0020);
                                /* Enable CL37 AN */
                                bnx2x_cl45_write(bp, params->port,
@@ -2458,54 +2581,43 @@ static u8 bnx2x_ext_phy_init(struct link_params *params, struct link_vars *vars)
                                rx_alarm_ctrl_val = 0x400;
                                lasi_ctrl_val = 0x0004;
                        } else {
-                               /* In 8073, port1 is directed through emac0 and
-                                * port0 is directed through emac1
-                                */
                                rx_alarm_ctrl_val = (1<<2);
-                               /*lasi_ctrl_val = 0x0005;*/
                                lasi_ctrl_val = 0x0004;
                        }
 
-                       /* Wait for soft reset to get cleared upto 1 sec */
-                       for (cnt = 0; cnt < 1000; cnt++) {
-                               bnx2x_cl45_read(bp, params->port,
-                                             ext_phy_type,
-                                             ext_phy_addr,
-                                             MDIO_PMA_DEVAD,
-                                             MDIO_PMA_REG_CTRL,
-                                             &ctrl);
-                               if (!(ctrl & (1<<15)))
-                                       break;
-                               msleep(1);
-                       }
-                       DP(NETIF_MSG_LINK,
-                               "807x control reg 0x%x (after %d ms)\n",
-                               ctrl, cnt);
+                       /* enable LASI */
+                       bnx2x_cl45_write(bp, params->port,
+                                  ext_phy_type,
+                                  ext_phy_addr,
+                                  MDIO_PMA_DEVAD,
+                                  MDIO_PMA_REG_RX_ALARM_CTRL,
+                                  rx_alarm_ctrl_val);
+
+                       bnx2x_cl45_write(bp, params->port,
+                                      ext_phy_type,
+                                      ext_phy_addr,
+                                      MDIO_PMA_DEVAD,
+                                      MDIO_PMA_REG_LASI_CTRL,
+                                      lasi_ctrl_val);
+
+                       bnx2x_8073_set_pause_cl37(params, vars);
 
                        if (ext_phy_type ==
                            PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8072){
                                bnx2x_bcm8072_external_rom_boot(params);
                        } else {
-                               bnx2x_bcm8073_external_rom_boot(params);
+
                                /* In case of 8073 with long xaui lines,
                                don't set the 8073 xaui low power*/
                                bnx2x_bcm8073_set_xaui_low_power_mode(params);
                        }
 
-                       /* enable LASI */
-                       bnx2x_cl45_write(bp, params->port,
-                                      ext_phy_type,
-                                      ext_phy_addr,
-                                      MDIO_PMA_DEVAD,
-                                      MDIO_PMA_REG_RX_ALARM_CTRL,
-                                      rx_alarm_ctrl_val);
-
-                       bnx2x_cl45_write(bp, params->port,
-                                      ext_phy_type,
-                                      ext_phy_addr,
-                                      MDIO_PMA_DEVAD,
-                                      MDIO_PMA_REG_LASI_CTRL,
-                                      lasi_ctrl_val);
+                       bnx2x_cl45_read(bp, params->port,
+                                     ext_phy_type,
+                                     ext_phy_addr,
+                                     MDIO_PMA_DEVAD,
+                                     0xca13,
+                                     &tmp1);
 
                        bnx2x_cl45_read(bp, params->port,
                                      ext_phy_type,
@@ -2519,12 +2631,21 @@ static u8 bnx2x_ext_phy_init(struct link_params *params, struct link_vars *vars)
                        /* If this is forced speed, set to KR or KX
                         * (all other are not supported)
                         */
-                       if (!(params->req_line_speed == SPEED_AUTO_NEG)) {
-                       if (params->req_line_speed == SPEED_10000) {
-                                       bnx2x_bcm807x_force_10G(params);
-                                       DP(NETIF_MSG_LINK,
-                                          "Forced speed 10G on 807X\n");
-                                       break;
+                       if (params->loopback_mode == LOOPBACK_EXT) {
+                               bnx2x_bcm807x_force_10G(params);
+                               DP(NETIF_MSG_LINK,
+                                       "Forced speed 10G on 807X\n");
+                               break;
+                       } else {
+                               bnx2x_cl45_write(bp, params->port,
+                                              ext_phy_type, ext_phy_addr,
+                                              MDIO_PMA_DEVAD,
+                                              MDIO_PMA_REG_BCM_CTRL,
+                                              0x0002);
+                       }
+                       if (params->req_line_speed != SPEED_AUTO_NEG) {
+                               if (params->req_line_speed == SPEED_10000) {
+                                       val = (1<<7);
                                } else if (params->req_line_speed ==
                                           SPEED_2500) {
                                        val = (1<<5);
@@ -2539,11 +2660,14 @@ static u8 bnx2x_ext_phy_init(struct link_params *params, struct link_vars *vars)
                                        PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)
                                        val |= (1<<7);
 
+                               /* Note that 2.5G works only when
+                               used with 1G advertisment */
                                if (params->speed_cap_mask &
-                                       PORT_HW_CFG_SPEED_CAPABILITY_D0_1G)
+                                       (PORT_HW_CFG_SPEED_CAPABILITY_D0_1G |
+                                        PORT_HW_CFG_SPEED_CAPABILITY_D0_2_5G))
                                        val |= (1<<5);
-                               DP(NETIF_MSG_LINK, "807x autoneg val = 0x%x\n", val);
-                               /*val = ((1<<5)|(1<<7));*/
+                               DP(NETIF_MSG_LINK,
+                                        "807x autoneg val = 0x%x\n", val);
                        }
 
                        bnx2x_cl45_write(bp, params->port,
@@ -2554,20 +2678,19 @@ static u8 bnx2x_ext_phy_init(struct link_params *params, struct link_vars *vars)
 
                        if (ext_phy_type ==
                            PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073) {
-                               /* Disable 2.5Ghz */
+
                                bnx2x_cl45_read(bp, params->port,
                                              ext_phy_type,
                                              ext_phy_addr,
                                              MDIO_AN_DEVAD,
                                              0x8329, &tmp1);
-/* SUPPORT_SPEED_CAPABILITY
-                               (Due to the nature of the link order, its not
-                               possible to enable 2.5G within the autoneg
-                               capabilities)
-                               if (params->speed_cap_mask &
-                               PORT_HW_CFG_SPEED_CAPABILITY_D0_2_5G)
-*/
-                               if (params->req_line_speed == SPEED_2500) {
+
+                               if (((params->speed_cap_mask &
+                                     PORT_HW_CFG_SPEED_CAPABILITY_D0_2_5G) &&
+                                    (params->req_line_speed ==
+                                     SPEED_AUTO_NEG)) ||
+                                   (params->req_line_speed ==
+                                    SPEED_2500)) {
                                        u16 phy_ver;
                                        /* Allow 2.5G for A1 and above */
                                        bnx2x_cl45_read(bp, params->port,
@@ -2575,49 +2698,53 @@ static u8 bnx2x_ext_phy_init(struct link_params *params, struct link_vars *vars)
                                         ext_phy_addr,
                                         MDIO_PMA_DEVAD,
                                         0xc801, &p