]> nv-tegra.nvidia Code Review - linux-2.6.git/commitdiff
[ARM] 4343/1: iop13xx: automatically detect the internal bus frequency
authorDan Williams <dan.j.williams@intel.com>
Sun, 29 Apr 2007 08:32:51 +0000 (09:32 +0100)
committerRussell King <rmk+kernel@arm.linux.org.uk>
Mon, 30 Apr 2007 14:24:54 +0000 (15:24 +0100)
Signed-off-by: Dan Williams <dan.j.williams@intel.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
arch/arm/mach-iop13xx/iq81340mc.c
arch/arm/mach-iop13xx/iq81340sc.c
include/asm-arm/arch-iop13xx/iop13xx.h
include/asm-arm/arch-iop13xx/time.h

index a519d707571c81e678c81b0e2ed8d7a639943635..1ae08cc04b484a6ee3043d9ae49342ab32085b61 100644 (file)
@@ -79,7 +79,9 @@ static void __init iq81340mc_init(void)
 
 static void __init iq81340mc_timer_init(void)
 {
-       iop_init_time(400000000);
+       unsigned long bus_freq = iop13xx_core_freq() / iop13xx_xsi_bus_ratio();
+       printk(KERN_DEBUG "%s: bus frequency: %lu\n", __FUNCTION__, bus_freq);
+       iop_init_time(bus_freq);
 }
 
 static struct sys_timer iq81340mc_timer = {
index 0e71fbcabe00a3dbafa3d85713a2182bf57fc10c..0f8801406f23eb271a0ee1e1bfd6c9b9973ae123 100644 (file)
@@ -81,7 +81,9 @@ static void __init iq81340sc_init(void)
 
 static void __init iq81340sc_timer_init(void)
 {
-       iop_init_time(400000000);
+       unsigned long bus_freq = iop13xx_core_freq() / iop13xx_xsi_bus_ratio();
+       printk(KERN_DEBUG "%s: bus frequency: %lu\n", __FUNCTION__, bus_freq);
+       iop_init_time(bus_freq);
 }
 
 static struct sys_timer iq81340sc_timer = {
index 2d1e23ba67c62c96738dbe90bbcef2aa32c266be..c8762ae8f628f71442470bde8463fc216f525922 100644 (file)
@@ -455,4 +455,5 @@ static inline int iop13xx_cpu_id(void)
 #define IOP13XX_PBI_BAR1               IOP13XX_PBI_OFFSET(0x10)
 #define IOP13XX_PBI_LR1                IOP13XX_PBI_OFFSET(0x14)
 
+#define IOP13XX_PROCESSOR_FREQ         IOP13XX_REG_ADDR32(0x2180)
 #endif /* _IOP13XX_HW_H_ */
index 77a837a02dec00a255585d9baf488ccb1f91aea9..49213d9d7cad5c6538f4999de573fe2d50e2b82d 100644 (file)
@@ -7,9 +7,65 @@
 #define IOP_TMR_PRIVILEGED 0x08
 #define IOP_TMR_RATIO_1_1  0x00
 
+#define IOP13XX_XSI_FREQ_RATIO_MASK    (3 << 19)
+#define IOP13XX_XSI_FREQ_RATIO_2       (0 << 19)
+#define IOP13XX_XSI_FREQ_RATIO_3       (1 << 19)
+#define IOP13XX_XSI_FREQ_RATIO_4       (2 << 19)
+#define IOP13XX_CORE_FREQ_MASK         (7 << 16)
+#define IOP13XX_CORE_FREQ_600          (0 << 16)
+#define IOP13XX_CORE_FREQ_667          (1 << 16)
+#define IOP13XX_CORE_FREQ_800          (2 << 16)
+#define IOP13XX_CORE_FREQ_933          (3 << 16)
+#define IOP13XX_CORE_FREQ_1000         (4 << 16)
+#define IOP13XX_CORE_FREQ_1200         (5 << 16)
+
 void iop_init_time(unsigned long tickrate);
 unsigned long iop_gettimeoffset(void);
 
+static inline unsigned long iop13xx_core_freq(void)
+{
+       unsigned long freq = __raw_readl(IOP13XX_PROCESSOR_FREQ);
+       freq &= IOP13XX_CORE_FREQ_MASK;
+       switch (freq) {
+       case IOP13XX_CORE_FREQ_600:
+               return 600000000;
+       case IOP13XX_CORE_FREQ_667:
+               return 667000000;
+       case IOP13XX_CORE_FREQ_800:
+               return 800000000;
+       case IOP13XX_CORE_FREQ_933:
+               return 933000000;
+       case IOP13XX_CORE_FREQ_1000:
+               return 1000000000;
+       case IOP13XX_CORE_FREQ_1200:
+               return 1200000000;
+       default:
+               printk("%s: warning unknown frequency, defaulting to 800Mhz\n",
+                       __FUNCTION__);
+       }
+
+       return 800000000;
+}
+
+static inline unsigned long iop13xx_xsi_bus_ratio(void)
+{
+       unsigned long  ratio = __raw_readl(IOP13XX_PROCESSOR_FREQ);
+       ratio &= IOP13XX_XSI_FREQ_RATIO_MASK;
+       switch (ratio) {
+       case IOP13XX_XSI_FREQ_RATIO_2:
+               return 2;
+       case IOP13XX_XSI_FREQ_RATIO_3:
+               return 3;
+       case IOP13XX_XSI_FREQ_RATIO_4:
+               return 4;
+       default:
+               printk("%s: warning unknown ratio, defaulting to 2\n",
+                       __FUNCTION__);
+       }
+
+       return 2;
+}
+
 static inline void write_tmr0(u32 val)
 {
        asm volatile("mcr p6, 0, %0, c0, c9, 0" : : "r" (val));