]> nv-tegra.nvidia Code Review - linux-2.6.git/commitdiff
[PATCH] m68knommu: 532x UART support
authorGreg Ungerer <gerg@snapgear.com>
Mon, 26 Jun 2006 00:33:10 +0000 (10:33 +1000)
committerLinus Torvalds <torvalds@g5.osdl.org>
Mon, 26 Jun 2006 00:43:33 +0000 (17:43 -0700)
ColdFire serial driver support for the new 532x CPU family UARTs.

Patch submitted by Matt Waddel <Matt.Waddel@freescale.com>.

Signed-off-by: Greg Ungerer <gerg@uclinux.org>
Signed-off-by: Linus Torvalds <torvalds@osdl.org>
drivers/serial/mcfserial.c

index 8cbbb954df2cbdf4b4d360f469f7a5408ffbfa15..8ad242934368e43f66b7fbe1cbff628a047e9bc1 100644 (file)
@@ -60,11 +60,11 @@ struct timer_list mcfrs_timer_struct;
 #if defined(CONFIG_HW_FEITH)
 #define        CONSOLE_BAUD_RATE       38400
 #define        DEFAULT_CBAUD           B38400
-#elif defined(CONFIG_MOD5272) || defined(CONFIG_M5208EVB)
+#elif defined(CONFIG_MOD5272) || defined(CONFIG_M5208EVB) || defined(CONFIG_M5329EVB)
 #define CONSOLE_BAUD_RATE      115200
 #define DEFAULT_CBAUD          B115200
 #elif defined(CONFIG_ARNEWSH) || defined(CONFIG_FREESCALE) || \
-      defined(CONFIG_senTec) || defined(CONFIG_SNEHA)
+      defined(CONFIG_senTec) || defined(CONFIG_SNEHA) || defined(CONFIG_AVNET)
 #define        CONSOLE_BAUD_RATE       19200
 #define        DEFAULT_CBAUD           B19200
 #endif
@@ -93,7 +93,7 @@ static struct tty_driver *mcfrs_serial_driver;
 #undef SERIAL_DEBUG_FLOW
 
 #if defined(CONFIG_M523x) || defined(CONFIG_M527x) || defined(CONFIG_M528x) || \
-    defined(CONFIG_M520x)
+    defined(CONFIG_M520x) || defined(CONFIG_M532x)
 #define        IRQBASE (MCFINT_VECBASE+MCFINT_UART0)
 #else
 #define        IRQBASE 73
@@ -1545,6 +1545,28 @@ static void mcfrs_irqinit(struct mcf_serial *info)
                        *feci2c_par |=  MCF_GPIO_PAR_FECI2C_PAR_SCL_UTXD2
                                    | MCF_GPIO_PAR_FECI2C_PAR_SDA_URXD2;
                }
+#elif defined(CONFIG_M532x)
+       volatile unsigned char *uartp;
+       uartp = info->addr;
+       switch (info->line) {
+       case 0:
+               MCF_INTC0_ICR26 = 0x3;
+               MCF_INTC0_CIMR = 26;
+               /* GPIO initialization */
+               MCF_GPIO_PAR_UART |= 0x000F;
+               break;
+       case 1:
+               MCF_INTC0_ICR27 = 0x3;
+               MCF_INTC0_CIMR = 27;
+               /* GPIO initialization */
+               MCF_GPIO_PAR_UART |= 0x0FF0;
+               break;
+       case 2:
+               MCF_INTC0_ICR28 = 0x3;
+               MCF_INTC0_CIMR = 28;
+               /* GPIOs also must be initalized, depends on board */
+               break;
+       }
 #else
        volatile unsigned char  *icrp, *uartp;