[MIPS] Sibyte: Fix interrupt timer off by one bug.
authorRalf Baechle <ralf@linux-mips.org>
Tue, 14 Mar 2006 23:52:47 +0000 (23:52 +0000)
committerRalf Baechle <ralf@linux-mips.org>
Sat, 18 Mar 2006 16:59:30 +0000 (16:59 +0000)
From Dave Johnson <djohnson+linuxmips@sw.starentnetworks.com>:

The timers need to be loaded with 1 less than the desired interval not
the interval itself.

Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
arch/mips/sibyte/sb1250/time.c

index 511c89d65f3821371ac34a59f4362e830f45f6e5..adc0b5271a069603de5cafea58a557d6055ff277 100644 (file)
@@ -75,10 +75,10 @@ void sb1250_time_init(void)
        /* Disable the timer and set up the count */
        __raw_writeq(0, IOADDR(A_SCD_TIMER_REGISTER(cpu, R_SCD_TIMER_CFG)));
 #ifdef CONFIG_SIMULATION
        /* Disable the timer and set up the count */
        __raw_writeq(0, IOADDR(A_SCD_TIMER_REGISTER(cpu, R_SCD_TIMER_CFG)));
 #ifdef CONFIG_SIMULATION
-       __raw_writeq(50000 / HZ,
+       __raw_writeq((50000 / HZ) - 1,
                     IOADDR(A_SCD_TIMER_REGISTER(cpu, R_SCD_TIMER_INIT)));
 #else
                     IOADDR(A_SCD_TIMER_REGISTER(cpu, R_SCD_TIMER_INIT)));
 #else
-       __raw_writeq(1000000 / HZ,
+       __raw_writeq((V_SCD_TIMER_FREQ / HZ) - 1,
                     IOADDR(A_SCD_TIMER_REGISTER(cpu, R_SCD_TIMER_INIT)));
 #endif
 
                     IOADDR(A_SCD_TIMER_REGISTER(cpu, R_SCD_TIMER_INIT)));
 #endif