Merge branch 'for-linus' of master.kernel.org:/home/rmk/linux-2.6-arm
authorLinus Torvalds <torvalds@linux-foundation.org>
Sat, 17 May 2008 22:17:10 +0000 (15:17 -0700)
committerLinus Torvalds <torvalds@linux-foundation.org>
Sat, 17 May 2008 22:17:10 +0000 (15:17 -0700)
* 'for-linus' of master.kernel.org:/home/rmk/linux-2.6-arm:
  [ARM] pxa: spitz wants PXA27x UDC definitions
  [ARM] pxa: fix pxafb build when cpufreq is enabled
  [ARM] fix parenthesis in include/asm-arm/arch-omap/control.h
  [ARM] colibri: fix support for DM9000 ethernet device
  [ARM] arm/kernel/arthur.c: add MODULE_LICENSE
  [ARM] 5037/1: Orion: fix DNS323/Kurobox Pro PCI initialisation
  [ARM] 5034/1: fix arm{925,926,940,946} dma_flush_range() in WT mode
  [ARM] export copy_page
  [ARM] 5026/1: locomo: add .settype for gpio and several small fixes
  ARM: OMAP: Fixed comments on global PRM register usage
  ARM: OMAP: Add PARENT_CONTROLS_CLOCK flag to dpll5_m2_ck
  ARM: OMAP: PRCM fixes to ssi clock handling
  ARM: OMAP: Add fuctional clock enabler for iva2
  ARM: OMAP: Fix 34xx to use correct shift values for gpio2-6 fclks
  ARM: OMAP: Keymap fix for palmte and palmz71
  ARM: OMAP: Fix Unbalanced enable for IRQ in omap mailbox
  ARM: OMAP: DMA: Fix incorrect channel linking
  ARM: OMAP: Warn on disabling clocks with no users
  ARM: OMAP: Add calls to omap2_set_globals_*()
  ARM: OMAP: Update MMC header to fix compile

666 files changed:
Documentation/cgroups.txt
Documentation/feature-removal-schedule.txt
Documentation/hwmon/adt7473
Documentation/i2c/functionality
Documentation/i2c/smbus-protocol
Documentation/kernel-parameters.txt
Documentation/memory-barriers.txt
Documentation/video4linux/CARDLIST.cx23885
Documentation/video4linux/CARDLIST.em28xx
MAINTAINERS
Makefile
arch/arm/mach-at91/at91sam9261_devices.c
arch/arm/mach-at91/at91sam9rl_devices.c
arch/ia64/Kconfig
arch/ia64/Makefile
arch/ia64/ia32/ia32_support.c
arch/ia64/kernel/acpi.c
arch/ia64/kernel/entry.S
arch/ia64/kernel/palinfo.c
arch/ia64/kernel/perfmon.c
arch/ia64/kernel/process.c
arch/ia64/kernel/sal.c
arch/ia64/kernel/setup.c
arch/ia64/mm/init.c
arch/ia64/uv/Makefile [new file with mode: 0644]
arch/ia64/uv/kernel/Makefile [new file with mode: 0644]
arch/ia64/uv/kernel/machvec.c [new file with mode: 0644]
arch/ia64/uv/kernel/setup.c [new file with mode: 0644]
arch/m68knommu/Kconfig
arch/m68knommu/kernel/vmlinux.lds.S
arch/mips/au1000/common/Makefile
arch/mips/au1000/common/au1xxx_irqmap.c
arch/mips/au1000/common/clocks.c
arch/mips/au1000/common/cputable.c
arch/mips/au1000/common/dbdma.c
arch/mips/au1000/common/dbg_io.c
arch/mips/au1000/common/dma.c
arch/mips/au1000/common/gpio.c
arch/mips/au1000/common/irq.c
arch/mips/au1000/common/pci.c
arch/mips/au1000/common/platform.c
arch/mips/au1000/common/power.c
arch/mips/au1000/common/prom.c
arch/mips/au1000/common/puts.c
arch/mips/au1000/common/reset.c
arch/mips/au1000/common/setup.c
arch/mips/au1000/common/time.c
arch/mips/au1000/db1x00/Makefile
arch/mips/au1000/db1x00/board_setup.c
arch/mips/au1000/db1x00/init.c
arch/mips/au1000/db1x00/irqmap.c
arch/mips/au1000/mtx-1/Makefile
arch/mips/au1000/mtx-1/board_setup.c
arch/mips/au1000/mtx-1/init.c
arch/mips/au1000/mtx-1/irqmap.c
arch/mips/au1000/mtx-1/platform.c
arch/mips/au1000/pb1000/Makefile
arch/mips/au1000/pb1000/board_setup.c
arch/mips/au1000/pb1000/init.c
arch/mips/au1000/pb1100/Makefile
arch/mips/au1000/pb1100/board_setup.c
arch/mips/au1000/pb1100/init.c
arch/mips/au1000/pb1100/irqmap.c
arch/mips/au1000/pb1200/Makefile
arch/mips/au1000/pb1200/board_setup.c
arch/mips/au1000/pb1200/init.c
arch/mips/au1000/pb1200/irqmap.c
arch/mips/au1000/pb1500/Makefile
arch/mips/au1000/pb1500/board_setup.c
arch/mips/au1000/pb1500/init.c
arch/mips/au1000/pb1500/irqmap.c
arch/mips/au1000/pb1550/Makefile
arch/mips/au1000/pb1550/board_setup.c
arch/mips/au1000/pb1550/init.c
arch/mips/au1000/pb1550/irqmap.c
arch/mips/au1000/xxs1500/Makefile
arch/mips/au1000/xxs1500/board_setup.c
arch/mips/au1000/xxs1500/init.c
arch/mips/au1000/xxs1500/irqmap.c
arch/mips/emma2rh/markeins/setup.c
arch/mips/kernel/Makefile
arch/mips/kernel/cpu-bugs64.c
arch/mips/kernel/irixelf.c
arch/mips/kernel/kspd.c
arch/mips/kernel/rtlx.c
arch/mips/kernel/setup.c
arch/mips/kernel/smp.c
arch/mips/kernel/vpe.c
arch/mips/mm/highmem.c
arch/mips/oprofile/op_model_mipsxx.c
arch/mips/pci/fixup-au1000.c
arch/mips/pci/ops-au1000.c
arch/mips/pmc-sierra/msp71xx/msp_hwbutton.c
arch/mips/sgi-ip27/ip27-timer.c
arch/mn10300/boot/install.sh
arch/parisc/hpux/gate.S
arch/parisc/hpux/wrappers.S
arch/parisc/kernel/Makefile
arch/parisc/kernel/entry.S
arch/parisc/kernel/head.S
arch/parisc/kernel/hpmc.S
arch/parisc/kernel/inventory.c
arch/parisc/kernel/pacache.S
arch/parisc/kernel/perf_asm.S
arch/parisc/kernel/real2.S
arch/parisc/kernel/syscall.S
arch/parisc/kernel/traps.c
arch/parisc/kernel/unaligned.c
arch/parisc/lib/fixup.S
arch/parisc/lib/lusercopy.S
arch/parisc/lib/memcpy.c
arch/parisc/mm/init.c
arch/powerpc/boot/dts/mpc8377_mds.dts
arch/powerpc/boot/dts/mpc8610_hpcd.dts
arch/powerpc/boot/dts/sbc8548.dts
arch/powerpc/configs/mpc8610_hpcd_defconfig
arch/powerpc/kernel/Makefile
arch/powerpc/kernel/cputable.c
arch/powerpc/lib/Makefile
arch/powerpc/mm/hash_utils_64.c
arch/powerpc/mm/init_64.c
arch/powerpc/mm/slb.c
arch/powerpc/mm/slb_low.S
arch/powerpc/platforms/85xx/mpc85xx_mds.c
arch/powerpc/platforms/85xx/sbc8548.c
arch/powerpc/platforms/86xx/mpc8610_hpcd.c
arch/powerpc/platforms/cell/io-workarounds.c
arch/powerpc/platforms/cell/io-workarounds.h
arch/powerpc/platforms/cell/spufs/file.c
arch/powerpc/platforms/cell/spufs/sched.c
arch/ppc/Makefile
arch/ppc/kernel/ppc_ksyms.c
arch/ppc/kernel/setup.c
arch/ppc/platforms/residual.c
arch/s390/kernel/debug.c
arch/s390/kernel/irq.c
arch/s390/kernel/smp.c
arch/s390/mm/vmem.c
arch/sh/kernel/kgdb_stub.c
arch/sparc/kernel/entry.S
arch/sparc/kernel/process.c
arch/sparc/kernel/ptrace.c
arch/sparc/kernel/rtrap.S
arch/sparc/kernel/signal.c
arch/sparc/kernel/sys_sparc.c
arch/sparc64/defconfig
arch/sparc64/kernel/etrap.S
arch/sparc64/kernel/ptrace.c
arch/sparc64/kernel/rtrap.S
arch/sparc64/kernel/signal.c
arch/sparc64/kernel/signal32.c
arch/sparc64/kernel/sys_sparc.c
arch/sparc64/kernel/sys_sparc32.c
arch/sparc64/mm/init.c
arch/um/Kconfig.char
arch/um/drivers/chan_user.c
arch/um/drivers/cow_sys.h
arch/um/drivers/daemon_user.c
arch/um/drivers/fd.c
arch/um/drivers/hostaudio_kern.c
arch/um/drivers/mcast_user.c
arch/um/drivers/net_user.c
arch/um/drivers/port_user.c
arch/um/drivers/pty.c
arch/um/drivers/random.c
arch/um/drivers/slip_user.c
arch/um/drivers/tty.c
arch/um/drivers/ubd_kern.c
arch/um/drivers/xterm.c
arch/um/include/as-layout.h
arch/um/include/line.h
arch/um/include/os.h
arch/um/include/process.h
arch/um/include/skas_ptrace.h
arch/um/include/sysdep-i386/ptrace_user.h
arch/um/include/sysdep-i386/sigcontext.h
arch/um/include/sysdep-x86_64/ptrace_user.h
arch/um/include/um_malloc.h
arch/um/kernel/dyn.lds.S
arch/um/kernel/mem.c
arch/um/kernel/time.c
arch/um/kernel/um_arch.c
arch/um/kernel/uml.lds.S
arch/um/os-Linux/drivers/ethertap_user.c
arch/um/os-Linux/helper.c
arch/um/os-Linux/main.c
arch/um/os-Linux/sigio.c
arch/um/os-Linux/signal.c
arch/um/os-Linux/skas/process.c
arch/um/os-Linux/start_up.c
arch/um/os-Linux/sys-i386/registers.c
arch/um/os-Linux/time.c
arch/um/sys-i386/ptrace.c
arch/um/sys-i386/user-offsets.c
arch/um/sys-x86_64/user-offsets.c
arch/x86/kernel/acpi/realmode/wakeup.lds.S
arch/x86/kernel/pci-dma.c
arch/x86/kernel/process.c
arch/x86/kernel/ptrace.c
arch/x86/kernel/setup.c
arch/x86/kernel/setup_64.c
arch/x86/kernel/smp.c
arch/x86/kernel/smpboot.c
arch/x86/kernel/x8664_ksyms_64.c
arch/x86/lib/csum-partial_64.c
arch/x86/mm/init_32.c
arch/x86/mm/pat.c
arch/x86/pci/i386.c
block/blk-core.c
block/blk-settings.c
block/blktrace.c
block/compat_ioctl.c
block/genhd.c
drivers/base/class.c
drivers/base/memory.c
drivers/base/power/main.c
drivers/char/Kconfig
drivers/char/ipmi/ipmi_si_intf.c
drivers/char/n_tty.c
drivers/char/snsc_event.c
drivers/char/synclink_gt.c
drivers/char/tty_io.c
drivers/i2c/busses/i2c-au1550.c
drivers/i2c/busses/i2c-mpc.c
drivers/i2c/busses/i2c-piix4.c
drivers/i2c/busses/i2c-sibyte.c
drivers/i2c/i2c-core.c
drivers/ide/Kconfig
drivers/ide/ide-iops.c
drivers/ide/mips/swarm.c
drivers/ide/pci/alim15x3.c
drivers/ide/pci/cs5520.c
drivers/infiniband/hw/cxgb3/cxio_hal.c
drivers/infiniband/hw/ipath/ipath_driver.c
drivers/infiniband/hw/ipath/ipath_file_ops.c
drivers/infiniband/hw/ipath/ipath_kernel.h
drivers/infiniband/hw/ipath/ipath_qp.c
drivers/infiniband/hw/ipath/ipath_rc.c
drivers/infiniband/hw/ipath/ipath_ruc.c
drivers/infiniband/hw/ipath/ipath_uc.c
drivers/infiniband/hw/ipath/ipath_ud.c
drivers/infiniband/hw/ipath/ipath_user_sdma.h
drivers/infiniband/hw/ipath/ipath_verbs.c
drivers/infiniband/hw/ipath/ipath_verbs.h
drivers/infiniband/hw/nes/nes.c
drivers/infiniband/hw/nes/nes.h
drivers/infiniband/hw/nes/nes_hw.c
drivers/macintosh/adb.c
drivers/md/linear.c
drivers/md/multipath.c
drivers/md/raid0.c
drivers/md/raid1.c
drivers/md/raid10.c
drivers/md/raid5.c
drivers/media/Kconfig
drivers/media/common/tuners/Kconfig
drivers/media/common/tuners/Makefile
drivers/media/common/tuners/mxl5005s.c [new file with mode: 0644]
drivers/media/common/tuners/mxl5005s.h [new file with mode: 0644]
drivers/media/common/tuners/tda18271-common.c
drivers/media/common/tuners/tda18271-fe.c
drivers/media/common/tuners/tda18271-priv.h
drivers/media/common/tuners/tea5767.c
drivers/media/common/tuners/xc5000.c
drivers/media/common/tuners/xc5000.h
drivers/media/common/tuners/xc5000_priv.h
drivers/media/dvb/b2c2/flexcop-fe-tuner.c
drivers/media/dvb/bt8xx/Kconfig
drivers/media/dvb/cinergyT2/Kconfig
drivers/media/dvb/dvb-core/dvb_ca_en50221.c
drivers/media/dvb/dvb-usb/Kconfig
drivers/media/dvb/frontends/Kconfig
drivers/media/dvb/frontends/itd1000.c
drivers/media/dvb/frontends/mt312.c
drivers/media/dvb/frontends/mt312.h
drivers/media/dvb/ttpci/Kconfig
drivers/media/dvb/ttusb-dec/Kconfig
drivers/media/video/Kconfig
drivers/media/video/Makefile
drivers/media/video/au0828/Kconfig
drivers/media/video/au0828/au0828-dvb.c
drivers/media/video/bt8xx/Kconfig
drivers/media/video/cx18/Kconfig
drivers/media/video/cx18/cx18-cards.c
drivers/media/video/cx18/cx18-cards.h
drivers/media/video/cx18/cx18-driver.c
drivers/media/video/cx18/cx18-driver.h
drivers/media/video/cx18/cx18-dvb.c
drivers/media/video/cx18/cx18-fileops.c
drivers/media/video/cx18/cx18-fileops.h
drivers/media/video/cx18/cx18-gpio.c
drivers/media/video/cx18/cx18-i2c.c
drivers/media/video/cx18/cx18-queue.c
drivers/media/video/cx18/cx18-queue.h
drivers/media/video/cx18/cx18-streams.c
drivers/media/video/cx18/cx18-streams.h
drivers/media/video/cx23885/Kconfig
drivers/media/video/cx23885/cx23885-cards.c
drivers/media/video/cx23885/cx23885-dvb.c
drivers/media/video/cx25840/Kconfig
drivers/media/video/cx88/Kconfig
drivers/media/video/cx88/cx88-dvb.c
drivers/media/video/em28xx/Kconfig
drivers/media/video/em28xx/em28xx-cards.c
drivers/media/video/em28xx/em28xx-dvb.c
drivers/media/video/et61x251/et61x251_core.c
drivers/media/video/ivtv/Kconfig
drivers/media/video/ivtv/ivtv-controls.c
drivers/media/video/ivtv/ivtv-driver.c
drivers/media/video/ivtv/ivtv-fileops.c
drivers/media/video/ivtv/ivtv-ioctl.c
drivers/media/video/ivtv/ivtv-ioctl.h
drivers/media/video/ivtv/ivtv-queue.c
drivers/media/video/ivtv/ivtv-streams.c
drivers/media/video/ivtv/ivtv-streams.h
drivers/media/video/ivtv/ivtv-vbi.c
drivers/media/video/ivtv/ivtv-yuv.c
drivers/media/video/ivtv/ivtvfb.c
drivers/media/video/mt9m001.c
drivers/media/video/mt9v022.c
drivers/media/video/pvrusb2/Kconfig
drivers/media/video/saa7134/Kconfig
drivers/media/video/saa7134/saa7134-core.c
drivers/media/video/saa7134/saa7134-dvb.c
drivers/media/video/sn9c102/sn9c102_core.c
drivers/media/video/stk-webcam.c
drivers/media/video/tcm825x.c
drivers/media/video/tlv320aic23b.c
drivers/media/video/tuner-core.c
drivers/media/video/tvaudio.c
drivers/media/video/tveeprom.c
drivers/media/video/usbvision/Kconfig
drivers/media/video/zc0301/zc0301_core.c
drivers/media/video/zoran_device.c
drivers/media/video/zoran_driver.c
drivers/misc/sgi-xp/xp.h
drivers/misc/sgi-xp/xp_main.c
drivers/misc/sgi-xp/xpc.h
drivers/misc/sgi-xp/xpc_channel.c
drivers/misc/sgi-xp/xpc_main.c
drivers/misc/sgi-xp/xpc_partition.c
drivers/misc/sgi-xp/xpnet.c
drivers/mmc/host/sdhci.h
drivers/net/Kconfig
drivers/net/atlx/atl1.c
drivers/net/atlx/atl1.h
drivers/net/atlx/atlx.c
drivers/net/atlx/atlx.h
drivers/net/cxgb3/adapter.h
drivers/net/cxgb3/common.h
drivers/net/cxgb3/cxgb3_main.c
drivers/net/cxgb3/regs.h
drivers/net/cxgb3/sge.c
drivers/net/cxgb3/t3_hw.c
drivers/net/dm9000.c
drivers/net/ehea/ehea.h
drivers/net/ehea/ehea_main.c
drivers/net/ehea/ehea_qmr.c
drivers/net/gianfar.c
drivers/net/myri10ge/myri10ge.c
drivers/net/myri10ge/myri10ge_mcp.h
drivers/net/myri10ge/myri10ge_mcp_gen_header.h
drivers/net/niu.c
drivers/net/niu.h
drivers/net/ppp_generic.c
drivers/net/pppol2tp.c
drivers/net/ps3_gelic_wireless.c
drivers/net/sfc/Makefile
drivers/net/sfc/boards.h
drivers/net/sfc/efx.c
drivers/net/sfc/enum.h
drivers/net/sfc/ethtool.c
drivers/net/sfc/falcon.c
drivers/net/sfc/falcon_hwdefs.h
drivers/net/sfc/falcon_xmac.c
drivers/net/sfc/mdio_10g.c
drivers/net/sfc/mdio_10g.h
drivers/net/sfc/net_driver.h
drivers/net/sfc/rx.c
drivers/net/sfc/selftest.c [new file with mode: 0644]
drivers/net/sfc/selftest.h [new file with mode: 0644]
drivers/net/sfc/sfe4001.c
drivers/net/sfc/tenxpress.c
drivers/net/sfc/tx.c
drivers/net/sfc/xfp_phy.c
drivers/net/sky2.h
drivers/net/wan/Kconfig
drivers/net/wan/cosa.c
drivers/net/wan/hdlc_ppp.c
drivers/net/wan/hostess_sv11.c
drivers/net/wan/lmc/lmc_main.c
drivers/net/wan/sealevel.c
drivers/net/wireless/atmel.c
drivers/net/wireless/iwlwifi/iwl-3945.c
drivers/net/wireless/iwlwifi/iwl-4965-rs.c
drivers/net/wireless/iwlwifi/iwl-4965.c
drivers/net/wireless/prism54/islpci_dev.c
drivers/net/wireless/rt2x00/rt2x00dev.c
drivers/net/wireless/rt2x00/rt2x00pci.c
drivers/net/wireless/rt2x00/rt61pci.c
drivers/net/wireless/strip.c
drivers/net/wireless/wavelan.c
drivers/net/wireless/wavelan_cs.c
drivers/net/wireless/zd1211rw/zd_usb.c
drivers/of/base.c
drivers/oprofile/cpu_buffer.c
drivers/oprofile/cpu_buffer.h
drivers/parisc/asp.c
drivers/parisc/ccio-dma.c
drivers/parisc/dino.c
drivers/parisc/gsc.c
drivers/parisc/lasi.c
drivers/parisc/lba_pci.c
drivers/parisc/led.c
drivers/parisc/sba_iommu.c
drivers/parisc/wax.c
drivers/pci/intel-iommu.c
drivers/pci/pci-acpi.c
drivers/pci/quirks.c
drivers/pnp/base.h
drivers/pnp/interface.c
drivers/pnp/quirks.c
drivers/pnp/resource.c
drivers/pnp/support.c
drivers/rtc/rtc-lib.c
drivers/rtc/rtc-m41t80.c
drivers/rtc/rtc-s35390a.c
drivers/s390/block/dasd.c
drivers/s390/block/dasd_devmap.c
drivers/s390/block/dasd_int.h
drivers/s390/char/tape_core.c
drivers/s390/char/vmlogrdr.c
drivers/s390/cio/blacklist.c
drivers/s390/cio/device_pgid.c
drivers/scsi/aha152x.c
drivers/scsi/gdth.c
drivers/scsi/libiscsi.c
drivers/scsi/qla1280.c
drivers/serial/Kconfig
drivers/serial/crisv10.c
drivers/serial/mcfserial.c
drivers/spi/Kconfig
drivers/spi/mpc52xx_psc_spi.c
drivers/spi/pxa2xx_spi.c
drivers/spi/spi_mpc83xx.c
drivers/usb/c67x00/c67x00-ll-hpi.c
drivers/usb/class/cdc-acm.c
drivers/usb/core/endpoint.c
drivers/usb/core/message.c
drivers/usb/core/sysfs.c
drivers/usb/core/usb.c
drivers/usb/core/usb.h
drivers/usb/gadget/amd5536udc.c
drivers/usb/gadget/atmel_usba_udc.c
drivers/usb/gadget/pxa27x_udc.c
drivers/usb/gadget/pxa27x_udc.h
drivers/usb/gadget/serial.c
drivers/usb/host/isp1760-hcd.c
drivers/usb/host/isp1760-if.c
drivers/usb/host/ohci-sm501.c
drivers/usb/misc/ldusb.c
drivers/usb/misc/usbtest.c
drivers/usb/serial/Kconfig
drivers/usb/serial/Makefile
drivers/usb/serial/cp2101.c
drivers/usb/serial/moto_modem.c [new file with mode: 0644]
drivers/usb/serial/option.c
drivers/usb/storage/unusual_devs.h
drivers/video/Kconfig
drivers/video/atmel_lcdfb.c
drivers/video/bw2.c
drivers/video/cg14.c
drivers/video/cg3.c
drivers/video/cg6.c
drivers/video/console/fbcon.c
drivers/video/ffb.c
drivers/video/geode/lxfb_ops.c
drivers/video/leo.c
drivers/video/logo/Kconfig
drivers/video/logo/Makefile
drivers/video/logo/logo.c
drivers/video/logo/logo_blackfin_clut224.ppm [new file with mode: 0644]
drivers/video/logo/logo_blackfin_vga16.ppm [new file with mode: 0644]
drivers/video/p9100.c
drivers/video/pnx4008/pnxrgbfb.c
drivers/video/sbuslib.c
drivers/video/sbuslib.h
drivers/video/sunxvr2500.c
drivers/video/sunxvr500.c
drivers/video/tcx.c
drivers/video/tridentfb.c
fs/9p/fid.h
fs/9p/v9fs.c
fs/9p/v9fs.h
fs/9p/vfs_addr.c
fs/9p/vfs_dir.c
fs/9p/vfs_file.c
fs/9p/vfs_inode.c
fs/9p/vfs_super.c
fs/befs/endian.h
fs/cifs/cifspdu.h
fs/cifs/cifssmb.c
fs/cifs/connect.c
fs/cifs/dir.c
fs/cifs/inode.c
fs/dquot.c
fs/ecryptfs/inode.c
fs/ecryptfs/miscdev.c
fs/exec.c
fs/ext3/xattr.c
fs/ext4/balloc.c
fs/ext4/mballoc.c
fs/ext4/super.c
fs/ext4/xattr.c
fs/fuse/file.c
fs/fuse/fuse_i.h
fs/fuse/inode.c
fs/hfsplus/inode.c
fs/hppfs/Makefile
fs/hppfs/hppfs.c [moved from fs/hppfs/hppfs_kern.c with 92% similarity]
fs/jbd/commit.c
fs/jbd2/commit.c
fs/jbd2/journal.c
fs/locks.c
fs/proc/array.c
fs/ufs/ufs.h
include/asm-alpha/barrier.h
include/asm-alpha/param.h
include/asm-alpha/pgtable.h
include/asm-frv/system.h
include/asm-h8300/param.h
include/asm-ia64/machvec.h
include/asm-ia64/machvec_uv.h [new file with mode: 0644]
include/asm-ia64/uv/uv_hub.h [new file with mode: 0644]
include/asm-ia64/uv/uv_mmrs.h [new file with mode: 0644]
include/asm-mips/bitops.h
include/asm-mips/compiler.h
include/asm-mips/mach-au1x00/au1000.h
include/asm-mips/mach-au1x00/au1000_dma.h
include/asm-mips/mach-au1x00/au1000_gpio.h
include/asm-mips/mach-au1x00/au1550_spi.h
include/asm-mips/mach-au1x00/au1xxx.h
include/asm-mips/mach-au1x00/au1xxx_dbdma.h
include/asm-mips/mach-au1x00/au1xxx_ide.h
include/asm-mips/mach-au1x00/au1xxx_psc.h
include/asm-mips/mach-db1x00/db1200.h
include/asm-mips/mach-db1x00/db1x00.h
include/asm-mips/mach-pb1x00/pb1000.h
include/asm-mips/mach-pb1x00/pb1100.h
include/asm-mips/mach-pb1x00/pb1200.h
include/asm-mips/mach-pb1x00/pb1500.h
include/asm-mips/mach-pb1x00/pb1550.h
include/asm-mips/rtlx.h
include/asm-parisc/assembly.h
include/asm-parisc/ioctl.h
include/asm-parisc/ioctls.h
include/asm-parisc/termbits.h
include/asm-parisc/termios.h
include/asm-powerpc/mmu-hash64.h
include/asm-powerpc/pgtable-ppc64.h
include/asm-powerpc/uaccess.h
include/asm-ppc/system.h
include/asm-s390/debug.h
include/asm-s390/types.h
include/asm-sparc/mman.h
include/asm-sparc/psr.h
include/asm-sparc/ptrace.h
include/asm-sparc/signal.h
include/asm-sparc64/mman.h
include/asm-sparc64/psrcompat.h
include/asm-sparc64/pstate.h
include/asm-sparc64/ptrace.h
include/asm-sparc64/signal.h
include/asm-sparc64/thread_info.h
include/asm-sparc64/ttable.h
include/asm-um/irq.h
include/asm-um/keyboard.h [deleted file]
include/asm-um/page.h
include/asm-um/param.h
include/asm-v850/param.h
include/asm-x86/pgtable.h
include/asm-xtensa/param.h
include/linux/bitmap.h
include/linux/cpumask.h
include/linux/device.h
include/linux/fuse.h
include/linux/genhd.h
include/linux/i2c.h
include/linux/ide.h
include/linux/kallsyms.h
include/linux/kernel.h
include/linux/libata.h
include/linux/mm_types.h
include/linux/netdevice.h
include/linux/parser.h
include/linux/percpu.h
include/linux/sched.h
include/linux/usb/association.h [new file with mode: 0644]
include/media/v4l2-i2c-drv-legacy.h
include/media/v4l2-i2c-drv.h
include/net/9p/9p.h
include/net/9p/client.h
include/net/9p/transport.h
include/net/irda/discovery.h
include/net/syncppp.h
include/sound/soc.h
init/do_mounts.c
init/main.c
kernel/kgdb.c
kernel/sched.c
lib/bitmap.c
lib/hexdump.c
lib/lmb.c
lib/parser.c
mm/filemap.c
mm/memory.c
mm/memory_hotplug.c
mm/mprotect.c
mm/page_alloc.c
mm/pdflush.c
mm/vmstat.c
net/9p/Kconfig
net/9p/Makefile
net/9p/client.c
net/9p/conv.c
net/9p/error.c
net/9p/fcprint.c
net/9p/mod.c
net/9p/trans_fd.c
net/9p/trans_virtio.c
net/9p/util.c
net/core/netpoll.c
net/core/sock.c
net/econet/af_econet.c
net/ipv4/arp.c
net/ipv4/cipso_ipv4.c
net/ipv4/igmp.c
net/ipv4/ipconfig.c
net/ipv4/raw.c
net/ipv4/tcp_input.c
net/ipv6/ip6_output.c
net/ipv6/mcast.c
net/ipv6/ndisc.c
net/ipv6/raw.c
net/irda/discovery.c
net/irda/irlmp.c
net/irda/irnet/irnet_irda.c
net/mac80211/debugfs_key.c
net/mac80211/iface.c
net/mac80211/mesh.c
net/mac80211/mesh_hwmp.c
net/mac80211/mesh_pathtbl.c
net/mac80211/mlme.c
net/mac80211/rx.c
net/mac80211/tx.c
net/mac80211/util.c
net/mac80211/wme.c
net/netfilter/nf_conntrack_netlink.c
net/netfilter/xt_iprange.c
net/packet/af_packet.c
net/sctp/sm_make_chunk.c
net/xfrm/xfrm_output.c
sound/soc/codecs/tlv320aic3x.c
sound/soc/fsl/fsl_ssi.c
sound/soc/omap/n810.c
sound/synth/emux/emux_synth.c

index c298a6690e0d67700b08b933a65a3eb4fd97cd96..824fc02744719ecb02b29177c11c55034229af35 100644 (file)
@@ -310,8 +310,8 @@ and then start a subshell 'sh' in that cgroup:
   cd /dev/cgroup
   mkdir Charlie
   cd Charlie
-  /bin/echo 2-3 > cpus
-  /bin/echo 1 > mems
+  /bin/echo 2-3 > cpuset.cpus
+  /bin/echo 1 > cpuset.mems
   /bin/echo $$ > tasks
   sh
   # The subshell 'sh' is now running in cgroup Charlie
index 3c35d452b1a968439cdbb2b270bcaa75b26b762d..5b3f31faed56872b84fbd293494613f6d627a987 100644 (file)
@@ -289,6 +289,14 @@ Who:       Glauber Costa <gcosta@redhat.com>
 
 ---------------------------
 
+What:  old style serial driver for ColdFire (CONFIG_SERIAL_COLDFIRE)
+When:  2.6.28
+Why:   This driver still uses the old interface and has been replaced
+       by CONFIG_SERIAL_MCF.
+Who:   Sebastian Siewior <sebastian@breakpoint.cc>
+
+---------------------------
+
 What:  /sys/o2cb symlink
 When:  January 2010
 Why:   /sys/fs/o2cb is the proper location for this information - /sys/o2cb
index 22d8b19046abcac7a7222daa9a916c895f975f71..2126de34c71161a3e6f22ddbfe082725b01cfc24 100644 (file)
@@ -69,7 +69,8 @@ point2: Set the pwm speed at a higher temperature bound.
 
 The ADT7473 will scale the pwm between the lower and higher pwm speed when
 the temperature is between the two temperature boundaries.  PWM values range
-from 0 (off) to 255 (full speed).
+from 0 (off) to 255 (full speed).  Fan speed will be set to maximum when the
+temperature sensor associated with the PWM control exceeds temp#_max.
 
 Notes
 -----
index 60cca249e452d759fcfa9dde1e04c0c431480773..42c17c1fb3cdf74e25a12e11d4416dd41e5f1f9a 100644 (file)
@@ -51,26 +51,38 @@ A few combinations of the above flags are also defined for your convenience:
                                   the transparent emulation layer)
 
 
-ALGORITHM/ADAPTER IMPLEMENTATION
---------------------------------
+ADAPTER IMPLEMENTATION
+----------------------
 
-When you write a new algorithm driver, you will have to implement a
-function callback `functionality', that gets an i2c_adapter structure
-pointer as its only parameter:
+When you write a new adapter driver, you will have to implement a
+function callback `functionality'. Typical implementations are given
+below.
 
-  struct i2c_algorithm {
-       /* Many other things of course; check <linux/i2c.h>! */
-       u32 (*functionality) (struct i2c_adapter *);
+A typical SMBus-only adapter would list all the SMBus transactions it
+supports. This example comes from the i2c-piix4 driver:
+
+  static u32 piix4_func(struct i2c_adapter *adapter)
+  {
+       return I2C_FUNC_SMBUS_QUICK | I2C_FUNC_SMBUS_BYTE |
+              I2C_FUNC_SMBUS_BYTE_DATA | I2C_FUNC_SMBUS_WORD_DATA |
+              I2C_FUNC_SMBUS_BLOCK_DATA;
   }
 
-A typically implementation is given below, from i2c-algo-bit.c:
+A typical full-I2C adapter would use the following (from the i2c-pxa
+driver):
 
-  static u32 bit_func(struct i2c_adapter *adap)
+  static u32 i2c_pxa_functionality(struct i2c_adapter *adap)
   {
-       return I2C_FUNC_SMBUS_EMUL | I2C_FUNC_10BIT_ADDR | 
-              I2C_FUNC_PROTOCOL_MANGLING;
+       return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
   }
 
+I2C_FUNC_SMBUS_EMUL includes all the SMBus transactions (with the
+addition of I2C block transactions) which i2c-core can emulate using
+I2C_FUNC_I2C without any help from the adapter driver. The idea is
+to let the client drivers check for the support of SMBus functions
+without having to care whether the said functions are implemented in
+hardware by the adapter, or emulated in software by i2c-core on top
+of an I2C adapter.
 
 
 CLIENT CHECKING
@@ -78,36 +90,33 @@ CLIENT CHECKING
 
 Before a client tries to attach to an adapter, or even do tests to check
 whether one of the devices it supports is present on an adapter, it should
-check whether the needed functionality is present. There are two functions
-defined which should be used instead of calling the functionality hook
-in the algorithm structure directly:
-
-  /* Return the functionality mask */
-  extern u32 i2c_get_functionality (struct i2c_adapter *adap);
-
-  /* Return 1 if adapter supports everything we need, 0 if not. */
-  extern int i2c_check_functionality (struct i2c_adapter *adap, u32 func);
+check whether the needed functionality is present. The typical way to do
+this is (from the lm75 driver):
 
-This is a typical way to use these functions (from the writing-clients
-document):
-  int foo_detect_client(struct i2c_adapter *adapter, int address, 
-                          unsigned short flags, int kind)
+  static int lm75_detect(...)
   {
-       /* Define needed variables */
-
-       /* As the very first action, we check whether the adapter has the
-          needed functionality: we need the SMBus read_word_data,
-           write_word_data and write_byte functions in this example. */
-       if (!i2c_check_functionality(adapter,I2C_FUNC_SMBUS_WORD_DATA |
-                                            I2C_FUNC_SMBUS_WRITE_BYTE))
-               goto ERROR0;
-
-       /* Now we can do the real detection */
-
-       ERROR0:
-               /* Return an error */
+       (...)
+       if (!i2c_check_functionality(adapter, I2C_FUNC_SMBUS_BYTE_DATA |
+                                    I2C_FUNC_SMBUS_WORD_DATA))
+               goto exit;
+       (...)
   }
 
+Here, the lm75 driver checks if the adapter can do both SMBus byte data
+and SMBus word data transactions. If not, then the driver won't work on
+this adapter and there's no point in going on. If the check above is
+successful, then the driver knows that it can call the following
+functions: i2c_smbus_read_byte_data(), i2c_smbus_write_byte_data(),
+i2c_smbus_read_word_data() and i2c_smbus_write_word_data(). As a rule of
+thumb, the functionality constants you test for with
+i2c_check_functionality() should match exactly the i2c_smbus_* functions
+which you driver is calling.
+
+Note that the check above doesn't tell whether the functionalities are
+implemented in hardware by the underlying adapter or emulated in
+software by i2c-core. Client drivers don't have to care about this, as
+i2c-core will transparently implement SMBus transactions on top of I2C
+adapters.
 
 
 CHECKING THROUGH /DEV
@@ -116,19 +125,19 @@ CHECKING THROUGH /DEV
 If you try to access an adapter from a userspace program, you will have
 to use the /dev interface. You will still have to check whether the
 functionality you need is supported, of course. This is done using
-the I2C_FUNCS ioctl. An example, adapted from the lm_sensors i2cdetect
-program, is below:
+the I2C_FUNCS ioctl. An example, adapted from the i2cdetect program, is
+below:
 
   int file;
-  if (file = open("/dev/i2c-0",O_RDWR) < 0) {
+  if (file = open("/dev/i2c-0", O_RDWR) < 0) {
        /* Some kind of error handling */
        exit(1);
   }
-  if (ioctl(file,I2C_FUNCS,&funcs) < 0) {
+  if (ioctl(file, I2C_FUNCS, &funcs) < 0) {
        /* Some kind of error handling */
        exit(1);
   }
-  if (! (funcs & I2C_FUNC_SMBUS_QUICK)) {
+  if (!(funcs & I2C_FUNC_SMBUS_QUICK)) {
        /* Oops, the needed functionality (SMBus write_quick function) is
            not available! */
        exit(1);
index 8a653c60d25a22d1bde489b947e58b0847d6e324..03f08fb491ccca6edcbcc6ce6fd1e0dda6eae2ad 100644 (file)
@@ -1,5 +1,6 @@
 SMBus Protocol Summary
 ======================
+
 The following is a summary of the SMBus protocol. It applies to
 all revisions of the protocol (1.0, 1.1, and 2.0).
 Certain protocol features which are not supported by
@@ -8,6 +9,7 @@ this package are briefly described at the end of this document.
 Some adapters understand only the SMBus (System Management Bus) protocol,
 which is a subset from the I2C protocol. Fortunately, many devices use
 only the same subset, which makes it possible to put them on an SMBus.
+
 If you write a driver for some I2C device, please try to use the SMBus
 commands if at all possible (if the device uses only that subset of the
 I2C protocol). This makes it possible to use the device driver on both
@@ -15,7 +17,12 @@ SMBus adapters and I2C adapters (the SMBus command set is automatically
 translated to I2C on I2C adapters, but plain I2C commands can not be
 handled at all on most pure SMBus adapters).
 
-Below is a list of SMBus commands.
+Below is a list of SMBus protocol operations, and the functions executing
+them.  Note that the names used in the SMBus protocol specifications usually
+don't match these function names.  For some of the operations which pass a
+single data byte, the functions using SMBus protocol operation names execute
+a different protocol operation entirely.
+
 
 Key to symbols
 ==============
@@ -35,17 +42,16 @@ Count (8 bits): A data byte containing the length of a block operation.
 [..]: Data sent by I2C device, as opposed to data sent by the host adapter.
 
 
-SMBus Write Quick
-=================
+SMBus Quick Command:  i2c_smbus_write_quick()
+=============================================
 
 This sends a single bit to the device, at the place of the Rd/Wr bit.
-There is no equivalent Read Quick command.
 
 A Addr Rd/Wr [A] P
 
 
-SMBus Read Byte
-===============
+SMBus Receive Byte:  i2c_smbus_read_byte()
+==========================================
 
 This reads a single byte from a device, without specifying a device
 register. Some devices are so simple that this interface is enough; for
@@ -55,17 +61,17 @@ the previous SMBus command.
 S Addr Rd [A] [Data] NA P
 
 
-SMBus Write Byte
-================
+SMBus Send Byte:  i2c_smbus_write_byte()
+========================================
 
-This is the reverse of Read Byte: it sends a single byte to a device.
-See Read Byte for more information.
+This operation is the reverse of Receive Byte: it sends a single byte
+to a device.  See Receive Byte for more information.
 
 S Addr Wr [A] Data [A] P
 
 
-SMBus Read Byte Data
-====================
+SMBus Read Byte:  i2c_smbus_read_byte_data()
+============================================
 
 This reads a single byte from a device, from a designated register.
 The register is specified through the Comm byte.
@@ -73,30 +79,30 @@ The register is specified through the Comm byte.
 S Addr Wr [A] Comm [A] S Addr Rd [A] [Data] NA P
 
 
-SMBus Read Word Data
-====================
+SMBus Read Word:  i2c_smbus_read_word_data()
+============================================
 
-This command is very like Read Byte Data; again, data is read from a
+This operation is very like Read Byte; again, data is read from a
 device, from a designated register that is specified through the Comm
 byte. But this time, the data is a complete word (16 bits).
 
 S Addr Wr [A] Comm [A] S Addr Rd [A] [DataLow] A [DataHigh] NA P
 
 
-SMBus Write Byte Data
-=====================
+SMBus Write Byte:  i2c_smbus_write_byte_data()
+==============================================
 
 This writes a single byte to a device, to a designated register. The
 register is specified through the Comm byte. This is the opposite of
-the Read Byte Data command.
+the Read Byte operation.
 
 S Addr Wr [A] Comm [A] Data [A] P
 
 
-SMBus Write Word Data
-=====================
+SMBus Write Word:  i2c_smbus_write_word_data()
+==============================================
 
-This is the opposite operation of the Read Word Data command. 16 bits
+This is the opposite of the Read Word operation. 16 bits
 of data is written to a device, to the designated register that is
 specified through the Comm byte. 
 
@@ -113,8 +119,8 @@ S Addr Wr [A] Comm [A] DataLow [A] DataHigh [A]
                              S Addr Rd [A] [DataLow] A [DataHigh] NA P
 
 
-SMBus Block Read
-================
+SMBus Block Read:  i2c_smbus_read_block_data()
+==============================================
 
 This command reads a block of up to 32 bytes from a device, from a 
 designated register that is specified through the Comm byte. The amount
@@ -124,8 +130,8 @@ S Addr Wr [A] Comm [A]
            S Addr Rd [A] [Count] A [Data] A [Data] A ... A [Data] NA P
 
 
-SMBus Block Write
-=================
+SMBus Block Write:  i2c_smbus_write_block_data()
+================================================
 
 The opposite of the Block Read command, this writes up to 32 bytes to 
 a device, to a designated register that is specified through the
@@ -134,10 +140,11 @@ Comm byte. The amount of data is specified in the Count byte.
 S Addr Wr [A] Comm [A] Count [A] Data [A] Data [A] ... [A] Data [A] P
 
 
-SMBus Block Process Call
-========================
+SMBus Block Write - Block Read Process Call
+===========================================
 
-SMBus Block Process Call was introduced in Revision 2.0 of the specification.
+SMBus Block Write - Block Read Process Call was introduced in
+Revision 2.0 of the specification.
 
 This command selects a device register (through the Comm byte), sends
 1 to 31 bytes of data to it, and reads 1 to 31 bytes of data in return.
@@ -159,13 +166,16 @@ alerting device's address.
 
 Packet Error Checking (PEC)
 ===========================
+
 Packet Error Checking was introduced in Revision 1.1 of the specification.
 
-PEC adds a CRC-8 error-checking byte to all transfers.
+PEC adds a CRC-8 error-checking byte to transfers using it, immediately
+before the terminating STOP.
 
 
 Address Resolution Protocol (ARP)
 =================================
+
 The Address Resolution Protocol was introduced in Revision 2.0 of
 the specification. It is a higher-layer protocol which uses the
 messages above.
@@ -177,14 +187,17 @@ require PEC checksums.
 
 I2C Block Transactions
 ======================
+
 The following I2C block transactions are supported by the
 SMBus layer and are described here for completeness.
+They are *NOT* defined by the SMBus specification.
+
 I2C block transactions do not limit the number of bytes transferred
 but the SMBus layer places a limit of 32 bytes.
 
 
-I2C Block Read
-==============
+I2C Block Read:  i2c_smbus_read_i2c_block_data()
+================================================
 
 This command reads a block of bytes from a device, from a 
 designated register that is specified through the Comm byte.
@@ -203,8 +216,8 @@ S Addr Wr [A] Comm1 [A] Comm2 [A]
            S Addr Rd [A] [Data] A [Data] A ... A [Data] NA P
 
 
-I2C Block Write
-===============
+I2C Block Write:  i2c_smbus_write_i2c_block_data()
+==================================================
 
 The opposite of the Block Read command, this writes bytes to 
 a device, to a designated register that is specified through the
@@ -212,5 +225,3 @@ Comm byte. Note that command lengths of 0, 2, or more bytes are
 supported as they are indistinguishable from data.
 
 S Addr Wr [A] Comm [A] Data [A] Data [A] ... [A] Data [A] P
-
-
index cdd5b934f43ea89865f1f605ecc5f295b03192d3..e07c432c731ff9a516fe8b23228af0fe6fa1d29a 100644 (file)
@@ -398,9 +398,6 @@ and is between 256 and 4096 characters. It is defined in the file
        cio_ignore=     [S390]
                        See Documentation/s390/CommonIO for details.
 
-       cio_msg=        [S390]
-                       See Documentation/s390/CommonIO for details.
-
        clock=          [BUGS=X86-32, HW] gettimeofday clocksource override.
                        [Deprecated]
                        Forces specified clocksource (if available) to be used
@@ -689,6 +686,12 @@ and is between 256 and 4096 characters. It is defined in the file
        floppy=         [HW]
                        See Documentation/floppy.txt.
 
+       force_pal_cache_flush
+                       [IA-64] Avoid check_sal_cache_flush which may hang on
+                       buggy SAL_CACHE_FLUSH implementations. Using this
+                       parameter will force ia64_sal_cache_flush to call
+                       ia64_pal_cache_flush instead of SAL_CACHE_FLUSH.
+
        gamecon.map[2|3]=
                        [HW,JOY] Multisystem joystick and NES/SNES/PSX pad
                        support via parallel port (up to 5 devices per port)
index e5a819a4f0c99588fecaef9f96632e5922b5c4b4..f5b7127f54acb6af1d9f997a40e099b60c0b7571 100644 (file)
@@ -994,7 +994,17 @@ The Linux kernel has eight basic CPU memory barriers:
        DATA DEPENDENCY read_barrier_depends()  smp_read_barrier_depends()
 
 
-All CPU memory barriers unconditionally imply compiler barriers.
+All memory barriers except the data dependency barriers imply a compiler
+barrier. Data dependencies do not impose any additional compiler ordering.
+
+Aside: In the case of data dependencies, the compiler would be expected to
+issue the loads in the correct order (eg. `a[b]` would have to load the value
+of b before loading a[b]), however there is no guarantee in the C specification
+that the compiler may not speculate the value of b (eg. is equal to 1) and load
+a before b (eg. tmp = a[1]; if (b != 1) tmp = a[b]; ). There is also the
+problem of a compiler reloading b after having loaded a[b], thus having a newer
+copy of b than a[b]. A consensus has not yet been reached about these problems,
+however the ACCESS_ONCE macro is a good place to start looking.
 
 SMP memory barriers are reduced to compiler barriers on uniprocessor compiled
 systems because it is assumed that a CPU will appear to be self-consistent,
index 929b90c8387fafc30ed3e0715171a504e257b0e7..191194ea1e25ce694217259eb64fe0f583a33462 100644 (file)
@@ -5,6 +5,6 @@
   4 -> DViCO FusionHDTV5 Express                           [18ac:d500]
   5 -> Hauppauge WinTV-HVR1500Q                            [0070:7790,0070:7797]
   6 -> Hauppauge WinTV-HVR1500                             [0070:7710,0070:7717]
-  7 -> Hauppauge WinTV-HVR1200                             [0070:71d1]
+  7 -> Hauppauge WinTV-HVR1200                             [0070:71d1,0070:71d3]
   8 -> Hauppauge WinTV-HVR1700                             [0070:8101]
   9 -> Hauppauge WinTV-HVR1400                             [0070:8010]
index f40e09296f306152aa5c89b4cfef0d3edf02d851..1d6a245c828f45f7b9c9c6ea4de824feb1990520 100644 (file)
@@ -14,4 +14,4 @@
  13 -> Terratec Prodigy XS                      (em2880)        [0ccd:0047]
  14 -> Pixelview Prolink PlayTV USB 2.0         (em2820/em2840)
  15 -> V-Gear PocketTV                          (em2800)
- 16 -> Hauppauge WinTV HVR 950                  (em2880)        [2040:6513]
+ 16 -> Hauppauge WinTV HVR 950                  (em2880)        [2040:6513,2040:6517,2040:651b,2040:651f]
index f5583dc7ea39f1ec8c94cda7a3503bc484df3fba..bc1c0088dc4919094f5c270a04a385a8c6a3dfaa 100644 (file)
@@ -367,12 +367,12 @@ S:        Maintained for 2.4; PCI support for 2.6.
 AMD GEODE CS5536 USB DEVICE CONTROLLER DRIVER
 P:     Thomas Dahlmann
 M:     thomas.dahlmann@amd.com
-L:     info-linux@geode.amd.com        (subscribers-only)
+L:     linux-geode@lists.infradead.org (moderated for non-subscribers)
 S:     Supported
 
 AMD GEODE PROCESSOR/CHIPSET SUPPORT
 P:     Jordan Crouse
-L:     info-linux@geode.amd.com        (subscribers-only)
+L:     linux-geode@lists.infradead.org (moderated for non-subscribers)
 W:     http://www.amd.com/us-en/ConnectivitySolutions/TechnicalResources/0,,50_2334_2452_11363,00.html
 S:     Supported
 
@@ -1230,6 +1230,15 @@ P:       Jaya Kumar
 M:     jayakumar.alsa@gmail.com
 S:     Maintained
 
+CX18 VIDEO4LINUX DRIVER
+P:     Hans Verkuil, Andy Walls
+M:     hverkuil@xs4all.nl, awalls@radix.net
+L:     ivtv-devel@ivtvdriver.org
+L:     ivtv-users@ivtvdriver.org
+L:     video4linux-list@redhat.com
+W:     http://linuxtv.org
+S:     Maintained
+
 CYBERPRO FB DRIVER
 P:     Russell King
 M:     rmk@arm.linux.org.uk
index 4492984efc09ab72ff6219a7bc21fb6a957c4cd5..3140145fdfe2b3475a8b5f6a604ca19e9b20acae 100644 (file)
--- a/Makefile
+++ b/Makefile
@@ -1,7 +1,7 @@
 VERSION = 2
 PATCHLEVEL = 6
 SUBLEVEL = 26
-EXTRAVERSION = -rc1
+EXTRAVERSION = -rc2
 NAME = Funky Weasel is Jiggy wit it
 
 # *DOCUMENTATION*
index 728bb8f394415fc683d3e8b4620cdaec984992a8..0babb645b83c055ea1120706b2344c9c286d3ca2 100644 (file)
@@ -544,10 +544,10 @@ void __init at91_add_device_lcdc(struct atmel_lcdfb_info *data)
                struct resource *fb_res = &lcdc_resources[2];
                size_t fb_len = fb_res->end - fb_res->start + 1;
 
-               fb = ioremap_writecombine(fb_res->start, fb_len);
+               fb = ioremap(fb_res->start, fb_len);
                if (fb) {
                        memset(fb, 0, fb_len);
-                       iounmap(fb, fb_len);
+                       iounmap(fb);
                }
        }
        lcdc_data = *data;
index 054689804e77571213012852f4dc771f5f70501e..450db304936ffea07453e4319d51fa7b5eb2244b 100644 (file)
@@ -332,13 +332,6 @@ static struct resource lcdc_resources[] = {
                .end    = AT91SAM9RL_ID_LCDC,
                .flags  = IORESOURCE_IRQ,
        },
-#if defined(CONFIG_FB_INTSRAM)
-       [2] = {
-               .start  = AT91SAM9RL_SRAM_BASE,
-               .end    = AT91SAM9RL_SRAM_BASE + AT91SAM9RL_SRAM_SIZE - 1,
-               .flags  = IORESOURCE_MEM,
-       },
-#endif
 };
 
 static struct platform_device at91_lcdc_device = {
@@ -381,20 +374,6 @@ void __init at91_add_device_lcdc(struct atmel_lcdfb_info *data)
        at91_set_B_periph(AT91_PIN_PC24, 0);    /* LCDD22 */
        at91_set_B_periph(AT91_PIN_PC25, 0);    /* LCDD23 */
 
-#ifdef CONFIG_FB_INTSRAM
-       {
-               void __iomem *fb;
-               struct resource *fb_res = &lcdc_resources[2];
-               size_t fb_len = fb_res->end - fb_res->start + 1;
-
-               fb = ioremap_writecombine(fb_res->start, fb_len);
-               if (fb) {
-                       memset(fb, 0, fb_len);
-                       iounmap(fb, fb_len);
-               }
-       }
-#endif
-
        lcdc_data = *data;
        platform_device_register(&at91_lcdc_device);
 }
index 0df5f6f75edf7a016d7033a85519e778d4cfcc7c..16be41446b5bd60bed0730db3b2f152ab851d085 100644 (file)
@@ -135,6 +135,7 @@ config IA64_GENERIC
          HP-zx1/sx1000         For HP systems
          HP-zx1/sx1000+swiotlb For HP systems with (broken) DMA-constrained devices.
          SGI-SN2               For SGI Altix systems
+         SGI-UV                For SGI UV systems
          Ski-simulator         For the HP simulator <http://www.hpl.hp.com/research/linux/ski/>
 
          If you don't know what to do, choose "generic".
@@ -170,6 +171,18 @@ config IA64_SGI_SN2
          to select this option.  If in doubt, select ia64 generic support
          instead.
 
+config IA64_SGI_UV`
+       bool "SGI-UV`"
+       select NUMA
+       select ACPI_NUMA
+       select SWIOTLB
+       help
+         Selecting this option will optimize the kernel for use on UV based
+         systems, but the resulting kernel binary will not run on other
+         types of ia64 systems.  If you have an SGI UV system, it's safe
+         to select this option.  If in doubt, select ia64 generic support
+         instead.
+
 config IA64_HP_SIM
        bool "Ski-simulator"
        select SWIOTLB
index ec4cca477f491c31cf74b79f184e1fce812cf4dc..88f1a55c6c94461c9967dbb54dec198abd9935ca 100644 (file)
@@ -63,7 +63,7 @@ drivers-$(CONFIG_PCI)         += arch/ia64/pci/
 drivers-$(CONFIG_IA64_HP_SIM)  += arch/ia64/hp/sim/
 drivers-$(CONFIG_IA64_HP_ZX1)  += arch/ia64/hp/common/ arch/ia64/hp/zx1/
 drivers-$(CONFIG_IA64_HP_ZX1_SWIOTLB) += arch/ia64/hp/common/ arch/ia64/hp/zx1/
-drivers-$(CONFIG_IA64_GENERIC) += arch/ia64/hp/common/ arch/ia64/hp/zx1/ arch/ia64/hp/sim/ arch/ia64/sn/
+drivers-$(CONFIG_IA64_GENERIC) += arch/ia64/hp/common/ arch/ia64/hp/zx1/ arch/ia64/hp/sim/ arch/ia64/sn/ arch/ia64/uv/
 drivers-$(CONFIG_OPROFILE)     += arch/ia64/oprofile/
 
 boot := arch/ia64/hp/sim/boot
index 896b1ebbfb268381bc87eb2e766e9c75e7d75f84..a6965ddafc46c90b188cdf0e7f1f9ede463abdbb 100644 (file)
@@ -15,7 +15,6 @@
 #include <linux/kernel.h>
 #include <linux/init.h>
 #include <linux/mm.h>
-#include <linux/personality.h>
 #include <linux/sched.h>
 
 #include <asm/intrinsics.h>
@@ -29,7 +28,6 @@
 
 extern int die_if_kernel (char *str, struct pt_regs *regs, long err);
 
-struct exec_domain ia32_exec_domain;
 struct page *ia32_shared_page[NR_CPUS];
 unsigned long *ia32_boot_gdt;
 unsigned long *cpu_gdt_table[NR_CPUS];
@@ -240,14 +238,6 @@ ia32_cpu_init (void)
 static int __init
 ia32_init (void)
 {
-       ia32_exec_domain.name = "Linux/x86";
-       ia32_exec_domain.handler = NULL;
-       ia32_exec_domain.pers_low = PER_LINUX32;
-       ia32_exec_domain.pers_high = PER_LINUX32;
-       ia32_exec_domain.signal_map = default_exec_domain.signal_map;
-       ia32_exec_domain.signal_invmap = default_exec_domain.signal_invmap;
-       register_exec_domain(&ia32_exec_domain);
-
 #if PAGE_SHIFT > IA32_PAGE_SHIFT
        {
                extern struct kmem_cache *ia64_partial_page_cachep;
index 19709a0796351e408a30fcd74ebc3a6ac92ec279..853d1f11be005f9e0b3443d8b33cdcbd72e53edd 100644 (file)
@@ -117,7 +117,10 @@ acpi_get_sysname(void)
        if (!strcmp(hdr->oem_id, "HP")) {
                return "hpzx1";
        } else if (!strcmp(hdr->oem_id, "SGI")) {
-               return "sn2";
+               if (!strcmp(hdr->oem_table_id + 4, "UV"))
+                       return "uv";
+               else
+                       return "sn2";
        }
 
        return "dig";
@@ -130,6 +133,8 @@ acpi_get_sysname(void)
        return "hpzx1_swiotlb";
 # elif defined (CONFIG_IA64_SGI_SN2)
        return "sn2";
+# elif defined (CONFIG_IA64_SGI_UV)
+       return "uv";
 # elif defined (CONFIG_IA64_DIG)
        return "dig";
 # else
@@ -622,6 +627,9 @@ void acpi_unregister_gsi(u32 gsi)
        if (acpi_irq_model == ACPI_IRQ_MODEL_PLATFORM)
                return;
 
+       if (has_8259 && gsi < 16)
+               return;
+
        iosapic_unregister_intr(gsi);
 }
 
index e49ad8c5dc6954303f47dd3d050525ff3353c800..ca2bb95726de7c24fad1f00013d37ca483d7217a 100644 (file)
@@ -1156,6 +1156,9 @@ skip_rbs_switch:
         *      r31 = current->thread_info->flags
         * On exit:
         *      p6 = TRUE if work-pending-check needs to be redone
+        *
+        * Interrupts are disabled on entry, reenabled depend on work, and
+        * disabled on exit.
         */
 .work_pending_syscall:
        add r2=-8,r2
@@ -1164,16 +1167,16 @@ skip_rbs_switch:
        st8 [r2]=r8
        st8 [r3]=r10
 .work_pending:
-       tbit.z p6,p0=r31,TIF_NEED_RESCHED               // current_thread_info()->need_resched==0?
+       tbit.z p6,p0=r31,TIF_NEED_RESCHED       // is resched not needed?
 (p6)   br.cond.sptk.few .notify
 #ifdef CONFIG_PREEMPT
 (pKStk) dep r21=-1,r0,PREEMPT_ACTIVE_BIT,1
        ;;
 (pKStk) st4 [r20]=r21
-       ssm psr.i               // enable interrupts
 #endif
+       ssm psr.i               // enable interrupts
        br.call.spnt.many rp=schedule
-.ret9: cmp.eq p6,p0=r0,r0                              // p6 <- 1
+.ret9: cmp.eq p6,p0=r0,r0      // p6 <- 1 (re-check)
        rsm psr.i               // disable interrupts
        ;;
 #ifdef CONFIG_PREEMPT
@@ -1182,13 +1185,13 @@ skip_rbs_switch:
 (pKStk)        st4 [r20]=r0            // preempt_count() <- 0
 #endif
 (pLvSys)br.cond.sptk.few  .work_pending_syscall_end
-       br.cond.sptk.many .work_processed_kernel        // re-check
+       br.cond.sptk.many .work_processed_kernel
 
 .notify:
 (pUStk)        br.call.spnt.many rp=notify_resume_user
-.ret10:        cmp.ne p6,p0=r0,r0                              // p6 <- 0
+.ret10:        cmp.ne p6,p0=r0,r0      // p6 <- 0 (don't re-check)
 (pLvSys)br.cond.sptk.few  .work_pending_syscall_end
-       br.cond.sptk.many .work_processed_kernel        // don't re-check
+       br.cond.sptk.many .work_processed_kernel
 
 .work_pending_syscall_end:
        adds r2=PT(R8)+16,r12
@@ -1196,7 +1199,7 @@ skip_rbs_switch:
        ;;
        ld8 r8=[r2]
        ld8 r10=[r3]
-       br.cond.sptk.many .work_processed_syscall       // re-check
+       br.cond.sptk.many .work_processed_syscall
 
 END(ia64_leave_kernel)
 
@@ -1234,9 +1237,12 @@ GLOBAL_ENTRY(ia64_invoke_schedule_tail)
 END(ia64_invoke_schedule_tail)
 
        /*
-        * Setup stack and call do_notify_resume_user().  Note that pSys and pNonSys need to
-        * be set up by the caller.  We declare 8 input registers so the system call
-        * args get preserved, in case we need to restart a system call.
+        * Setup stack and call do_notify_resume_user(), keeping interrupts
+        * disabled.
+        *
+        * Note that pSys and pNonSys need to be set up by the caller.
+        * We declare 8 input registers so the system call args get preserved,
+        * in case we need to restart a system call.
         */
 ENTRY(notify_resume_user)
        .prologue ASM_UNW_PRLG_RP|ASM_UNW_PRLG_PFS, ASM_UNW_PRLG_GRSAVE(8)
index 4547a2092af9d4717273883247b6e854749c819d..9dc00f7fe10e8f6c08cccaa37df20c6eba739e4f 100644 (file)
@@ -900,12 +900,6 @@ static void
 palinfo_smp_call(void *info)
 {
        palinfo_smp_data_t *data = (palinfo_smp_data_t *)info;
-       if (data == NULL) {
-               printk(KERN_ERR "palinfo: data pointer is NULL\n");
-               data->ret = 0; /* no output */
-               return;
-       }
-       /* does this actual call */
        data->ret = (*data->func)(data->page);
 }
 
index c1ad27de2dd2080e0bdea8a845147fcc6f855dba..71d05133f556000530d930537c9dc14c543037c9 100644 (file)
@@ -5013,12 +5013,13 @@ pfm_context_force_terminate(pfm_context_t *ctx, struct pt_regs *regs)
 }
 
 static int pfm_ovfl_notify_user(pfm_context_t *ctx, unsigned long ovfl_pmds);
+
  /*
   * pfm_handle_work() can be called with interrupts enabled
   * (TIF_NEED_RESCHED) or disabled. The down_interruptible
   * call may sleep, therefore we must re-enable interrupts
   * to avoid deadlocks. It is safe to do so because this function
-  * is called ONLY when returning to user level (PUStk=1), in which case
+  * is called ONLY when returning to user level (pUStk=1), in which case
   * there is no risk of kernel stack overflow due to deep
   * interrupt nesting.
   */
@@ -5034,7 +5035,8 @@ pfm_handle_work(void)
 
        ctx = PFM_GET_CTX(current);
        if (ctx == NULL) {
-               printk(KERN_ERR "perfmon: [%d] has no PFM context\n", task_pid_nr(current));
+               printk(KERN_ERR "perfmon: [%d] has no PFM context\n",
+                       task_pid_nr(current));
                return;
        }
 
@@ -5058,11 +5060,12 @@ pfm_handle_work(void)
        /*
         * must be done before we check for simple-reset mode
         */
-       if (ctx->ctx_fl_going_zombie || ctx->ctx_state == PFM_CTX_ZOMBIE) goto do_zombie;
-
+       if (ctx->ctx_fl_going_zombie || ctx->ctx_state == PFM_CTX_ZOMBIE)
+               goto do_zombie;
 
        //if (CTX_OVFL_NOBLOCK(ctx)) goto skip_blocking;
-       if (reason == PFM_TRAP_REASON_RESET) goto skip_blocking;
+       if (reason == PFM_TRAP_REASON_RESET)
+               goto skip_blocking;
 
        /*
         * restore interrupt mask to what it was on entry.
@@ -5110,7 +5113,8 @@ do_zombie:
        /*
         * in case of interruption of down() we don't restart anything
         */
-       if (ret < 0) goto nothing_to_do;
+       if (ret < 0)
+               goto nothing_to_do;
 
 skip_blocking:
        pfm_resume_after_ovfl(ctx, ovfl_regs, regs);
index 58dcfac5ea882ec5529ffdec98d3219cbb58b27d..a3a34b4eb038e6d03d6b487ec3916748605a1025 100644 (file)
@@ -167,11 +167,18 @@ void tsk_clear_notify_resume(struct task_struct *tsk)
        clear_ti_thread_flag(task_thread_info(tsk), TIF_NOTIFY_RESUME);
 }
 
+/*
+ * do_notify_resume_user():
+ *     Called from notify_resume_user at entry.S, with interrupts disabled.
+ */
 void
-do_notify_resume_user (sigset_t *unused, struct sigscratch *scr, long in_syscall)
+do_notify_resume_user(sigset_t *unused, struct sigscratch *scr, long in_syscall)
 {
        if (fsys_mode(current, &scr->pt)) {
-               /* defer signal-handling etc. until we return to privilege-level 0.  */
+               /*
+                * defer signal-handling etc. until we return to
+                * privilege-level 0.
+                */
                if (!ia64_psr(&scr->pt)->lp)
                        ia64_psr(&scr->pt)->lp = 1;
                return;
@@ -179,16 +186,26 @@ do_notify_resume_user (sigset_t *unused, struct sigscratch *scr, long in_syscall
 
 #ifdef CONFIG_PERFMON
        if (current->thread.pfm_needs_checking)
+               /*
+                * Note: pfm_handle_work() allow us to call it with interrupts
+                * disabled, and may enable interrupts within the function.
+                */
                pfm_handle_work();
 #endif
 
        /* deal with pending signal delivery */
-       if (test_thread_flag(TIF_SIGPENDING))
+       if (test_thread_flag(TIF_SIGPENDING)) {
+               local_irq_enable();     /* force interrupt enable */
                ia64_do_signal(scr, in_syscall);
+       }
 
        /* copy user rbs to kernel rbs */
-       if (unlikely(test_thread_flag(TIF_RESTORE_RSE)))
+       if (unlikely(test_thread_flag(TIF_RESTORE_RSE))) {
+               local_irq_enable();     /* force interrupt enable */
                ia64_sync_krbs();
+       }
+
+       local_irq_disable();    /* force interrupt disable */
 }
 
 static int pal_halt        = 1;
index a3022dc48ef8432a437256948d5a25080b1cf24d..7e0259709c0415081c6f42396e7e2d446c9c5479 100644 (file)
@@ -229,6 +229,14 @@ static void __init sal_desc_ap_wakeup(void *p) { }
  */
 static int sal_cache_flush_drops_interrupts;
 
+static int __init
+force_pal_cache_flush(char *str)
+{
+       sal_cache_flush_drops_interrupts = 1;
+       return 0;
+}
+early_param("force_pal_cache_flush", force_pal_cache_flush);
+
 void __init
 check_sal_cache_flush (void)
 {
@@ -237,6 +245,9 @@ check_sal_cache_flush (void)
        u64 vector, cache_type = 3;
        struct ia64_sal_retval isrv;
 
+       if (sal_cache_flush_drops_interrupts)
+               return;
+
        cpu = get_cpu();
        local_irq_save(flags);
 
index 5015ca1275ca0520f4e0530e94fd57eae9b7cbef..e9596cd0cdab21595f7c5f85d7da7d2952beb5d6 100644 (file)
@@ -239,6 +239,25 @@ __initcall(register_memory);
 
 
 #ifdef CONFIG_KEXEC
+
+/*
+ * This function checks if the reserved crashkernel is allowed on the specific
+ * IA64 machine flavour. Machines without an IO TLB use swiotlb and require
+ * some memory below 4 GB (i.e. in 32 bit area), see the implementation of
+ * lib/swiotlb.c. The hpzx1 architecture has an IO TLB but cannot use that
+ * in kdump case. See the comment in sba_init() in sba_iommu.c.
+ *
+ * So, the only machvec that really supports loading the kdump kernel
+ * over 4 GB is "sn2".
+ */
+static int __init check_crashkernel_memory(unsigned long pbase, size_t size)
+{
+       if (ia64_platform_is("sn2") || ia64_platform_is("uv"))
+               return 1;
+       else
+               return pbase < (1UL << 32);
+}
+
 static void __init setup_crashkernel(unsigned long total, int *n)
 {
        unsigned long long base = 0, size = 0;
@@ -252,6 +271,16 @@ static void __init setup_crashkernel(unsigned long total, int *n)
                        base = kdump_find_rsvd_region(size,
                                        rsvd_region, *n);
                }
+
+               if (!check_crashkernel_memory(base, size)) {
+                       pr_warning("crashkernel: There would be kdump memory "
+                               "at %ld GB but this is unusable because it "
+                               "must\nbe below 4 GB. Change the memory "
+                               "configuration of the machine.\n",
+                               (unsigned long)(base >> 30));
+                       return;
+               }
+
                if (base != ~0UL) {
                        printk(KERN_INFO "Reserving %ldMB of memory at %ldMB "
                                        "for crashkernel (System RAM: %ldMB)\n",
index fc6c6636ffdac444b280e1cf4bc29fa140483ba5..200100ea7610883ae8fc90768a64ba185aa68d3c 100644 (file)
@@ -719,3 +719,28 @@ out:
 EXPORT_SYMBOL_GPL(remove_memory);
 #endif /* CONFIG_MEMORY_HOTREMOVE */
 #endif
+
+/*
+ * Even when CONFIG_IA32_SUPPORT is not enabled it is
+ * useful to have the Linux/x86 domain registered to
+ * avoid an attempted module load when emulators call
+ * personality(PER_LINUX32). This saves several milliseconds
+ * on each such call.
+ */
+static struct exec_domain ia32_exec_domain;
+
+static int __init
+per_linux32_init(void)
+{
+       ia32_exec_domain.name = "Linux/x86";
+       ia32_exec_domain.handler = NULL;
+       ia32_exec_domain.pers_low = PER_LINUX32;
+       ia32_exec_domain.pers_high = PER_LINUX32;
+       ia32_exec_domain.signal_map = default_exec_domain.signal_map;
+       ia32_exec_domain.signal_invmap = default_exec_domain.signal_invmap;
+       register_exec_domain(&ia32_exec_domain);
+
+       return 0;
+}
+
+__initcall(per_linux32_init);
diff --git a/arch/ia64/uv/Makefile b/arch/ia64/uv/Makefile
new file mode 100644 (file)
index 0000000..aa9f919
--- /dev/null
@@ -0,0 +1,12 @@
+# arch/ia64/uv/Makefile
+#
+# This file is subject to the terms and conditions of the GNU General Public
+# License.  See the file "COPYING" in the main directory of this archive
+# for more details.
+#
+# Copyright (C) 2008 Silicon Graphics, Inc.  All Rights Reserved.
+#
+# Makefile for the sn uv subplatform
+#
+
+obj-y += kernel/
diff --git a/arch/ia64/uv/kernel/Makefile b/arch/ia64/uv/kernel/Makefile
new file mode 100644 (file)
index 0000000..8d92b46
--- /dev/null
@@ -0,0 +1,13 @@
+# arch/ia64/uv/kernel/Makefile
+#
+# This file is subject to the terms and conditions of the GNU General Public
+# License.  See the file "COPYING" in the main directory of this archive
+# for more details.
+#
+# Copyright (C) 2008 Silicon Graphics, Inc.  All Rights Reserved.
+#
+
+EXTRA_CFLAGS += -Iarch/ia64/sn/include
+
+obj-y                          += setup.o
+obj-$(CONFIG_IA64_GENERIC)      += machvec.o
diff --git a/arch/ia64/uv/kernel/machvec.c b/arch/ia64/uv/kernel/machvec.c
new file mode 100644 (file)
index 0000000..50737a9
--- /dev/null
@@ -0,0 +1,11 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (c) 2008 Silicon Graphics, Inc.  All Rights Reserved.
+ */
+
+#define MACHVEC_PLATFORM_NAME  uv
+#define MACHVEC_PLATFORM_HEADER        <asm/machvec_uv.h>
+#include <asm/machvec_init.h>
diff --git a/arch/ia64/uv/kernel/setup.c b/arch/ia64/uv/kernel/setup.c
new file mode 100644 (file)
index 0000000..9aa7432
--- /dev/null
@@ -0,0 +1,98 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * SGI UV Core Functions
+ *
+ * Copyright (C) 2008 Silicon Graphics, Inc. All rights reserved.
+ */
+
+#include <linux/module.h>
+#include <linux/percpu.h>
+#include <asm/sn/simulator.h>
+#include <asm/uv/uv_mmrs.h>
+#include <asm/uv/uv_hub.h>
+
+DEFINE_PER_CPU(struct uv_hub_info_s, __uv_hub_info);
+EXPORT_PER_CPU_SYMBOL_GPL(__uv_hub_info);
+
+
+struct redir_addr {
+       unsigned long redirect;
+       unsigned long alias;
+};
+
+#define DEST_SHIFT UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_0_MMR_DEST_BASE_SHFT
+
+static __initdata struct redir_addr redir_addrs[] = {
+       {UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_0_MMR, UVH_SI_ALIAS0_OVERLAY_CONFIG},
+       {UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_1_MMR, UVH_SI_ALIAS1_OVERLAY_CONFIG},
+       {UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_2_MMR, UVH_SI_ALIAS2_OVERLAY_CONFIG},
+};
+
+static __init void get_lowmem_redirect(unsigned long *base, unsigned long *size)
+{
+       union uvh_si_alias0_overlay_config_u alias;
+       union uvh_rh_gam_alias210_redirect_config_2_mmr_u redirect;
+       int i;
+
+       for (i = 0; i < ARRAY_SIZE(redir_addrs); i++) {
+               alias.v = uv_read_local_mmr(redir_addrs[i].alias);
+               if (alias.s.base == 0) {
+                       *size = (1UL << alias.s.m_alias);
+                       redirect.v = uv_read_local_mmr(redir_addrs[i].redirect);
+                       *base = (unsigned long)redirect.s.dest_base << DEST_SHIFT;
+                       return;
+               }
+       }
+       BUG();
+}
+
+void __init uv_setup(char **cmdline_p)
+{
+       union uvh_si_addr_map_config_u m_n_config;
+       union uvh_node_id_u node_id;
+       unsigned long gnode_upper;
+       int nid, cpu, m_val, n_val;
+       unsigned long mmr_base, lowmem_redir_base, lowmem_redir_size;
+
+       if (IS_MEDUSA()) {
+               lowmem_redir_base = 0;
+               lowmem_redir_size = 0;
+               node_id.v = 0;
+               m_n_config.s.m_skt = 37;
+               m_n_config.s.n_skt = 0;
+               mmr_base = 0;
+       } else {
+               get_lowmem_redirect(&lowmem_redir_base, &lowmem_redir_size);
+               node_id.v = uv_read_local_mmr(UVH_NODE_ID);
+               m_n_config.v = uv_read_local_mmr(UVH_SI_ADDR_MAP_CONFIG);
+               mmr_base =
+                       uv_read_local_mmr(UVH_RH_GAM_MMR_OVERLAY_CONFIG_MMR) &
+                               ~UV_MMR_ENABLE;
+       }
+
+       m_val = m_n_config.s.m_skt;
+       n_val = m_n_config.s.n_skt;
+       printk(KERN_DEBUG "UV: global MMR base 0x%lx\n", mmr_base);
+
+       gnode_upper = (((unsigned long)node_id.s.node_id) &
+                      ~((1 << n_val) - 1)) << m_val;
+
+       for_each_present_cpu(cpu) {
+               nid = cpu_to_node(cpu);
+               uv_cpu_hub_info(cpu)->lowmem_remap_base = lowmem_redir_base;
+               uv_cpu_hub_info(cpu)->lowmem_remap_top =
+                       lowmem_redir_base + lowmem_redir_size;
+               uv_cpu_hub_info(cpu)->m_val = m_val;
+               uv_cpu_hub_info(cpu)->n_val = m_val;
+               uv_cpu_hub_info(cpu)->pnode_mask = (1 << n_val) -1;
+               uv_cpu_hub_info(cpu)->gpa_mask = (1 << (m_val + n_val)) - 1;
+               uv_cpu_hub_info(cpu)->gnode_upper = gnode_upper;
+               uv_cpu_hub_info(cpu)->global_mmr_base = mmr_base;
+               uv_cpu_hub_info(cpu)->coherency_domain_number = 0;/* ZZZ */
+               printk(KERN_DEBUG "UV cpu %d, nid %d\n", cpu, nid);
+       }
+}
+
index 07eb4c4bab8243723ead643a13d6f5611a42d032..8e8441587c22bcb566976360ec34e53d6145fcd8 100644 (file)
@@ -671,6 +671,9 @@ config ROMKERNEL
 
 endchoice
 
+if COLDFIRE
+source "kernel/Kconfig.preempt"
+endif
 source "mm/Kconfig"
 
 endmenu
index 5592e0bf951f555f9efb18c55838215b80cc9db8..93e69236ed6f8bfd1b6b38408aa380fc43d247de 100644 (file)
@@ -114,6 +114,16 @@ SECTIONS {
                *(__kcrctab_gpl)
                __stop___kcrctab_gpl = .;
 
+               /* Kernel symbol table: Normal unused symbols */
+               __start___kcrctab_unused = .;
+               *(__kcrctab_unused)
+               __stop___kcrctab_unused = .;
+
+               /* Kernel symbol table: GPL-only unused symbols */
+               __start___kcrctab_unused_gpl = .;
+               *(__kcrctab_unused_gpl)
+               __stop___kcrctab_unused_gpl = .;
+
                /* Kernel symbol table: GPL-future symbols */
                __start___kcrctab_gpl_future = .;
                *(__kcrctab_gpl_future)
index 90e2d7a46e8e2c7d96a86fb61500b11c9ddad4f5..dd0e19dacfcff444ab7b4ff07912ff8b0bcde082 100644 (file)
@@ -1,9 +1,8 @@
 #
-#  Copyright 2000 MontaVista Software Inc.
-#  Author: MontaVista Software, Inc.
-#      ppopov@mvista.com or source@mvista.com
+#  Copyright 2000, 2008 MontaVista Software Inc.
+#  Author: MontaVista Software, Inc. <source@mvista.com>
 #
-# Makefile for the Alchemy Au1000 CPU, generic files.
+# Makefile for the Alchemy Au1xx0 CPUs, generic files.
 #
 
 obj-y += prom.o irq.o puts.o time.o reset.o \
index 37a10a01de9d30619c2a7c5feeabfac77cbb2c5f..c7ca1596394cc2a4e18c2f83c0f735ed7171d2b6 100644 (file)
 struct au1xxx_irqmap __initdata au1xxx_ic0_map[] = {
 
 #if defined(CONFIG_SOC_AU1000)
-       { AU1000_UART0_INT, INTC_INT_HIGH_LEVEL, 0},
-       { AU1000_UART1_INT, INTC_INT_HIGH_LEVEL, 0},
-       { AU1000_UART2_INT, INTC_INT_HIGH_LEVEL, 0},
-       { AU1000_UART3_INT, INTC_INT_HIGH_LEVEL, 0},
-       { AU1000_SSI0_INT, INTC_INT_HIGH_LEVEL, 0},
-       { AU1000_SSI1_INT, INTC_INT_HIGH_LEVEL, 0},
-       { AU1000_DMA_INT_BASE, INTC_INT_HIGH_LEVEL, 0},
-       { AU1000_DMA_INT_BASE+1, INTC_INT_HIGH_LEVEL, 0},
-       { AU1000_DMA_INT_BASE+2, INTC_INT_HIGH_LEVEL, 0},
-       { AU1000_DMA_INT_BASE+3, INTC_INT_HIGH_LEVEL, 0},
-       { AU1000_DMA_INT_BASE+4, INTC_INT_HIGH_LEVEL, 0},
-       { AU1000_DMA_INT_BASE+5, INTC_INT_HIGH_LEVEL, 0},
-       { AU1000_DMA_INT_BASE+6, INTC_INT_HIGH_LEVEL, 0},
-       { AU1000_DMA_INT_BASE+7, INTC_INT_HIGH_LEVEL, 0},
+       { AU1000_UART0_INT, INTC_INT_HIGH_LEVEL, 0 },
+       { AU1000_UART1_INT, INTC_INT_HIGH_LEVEL, 0 },
+       { AU1000_UART2_INT, INTC_INT_HIGH_LEVEL, 0 },
+       { AU1000_UART3_INT, INTC_INT_HIGH_LEVEL, 0 },
+       { AU1000_SSI0_INT, INTC_INT_HIGH_LEVEL, 0 },
+       { AU1000_SSI1_INT, INTC_INT_HIGH_LEVEL, 0 },
+       { AU1000_DMA_INT_BASE, INTC_INT_HIGH_LEVEL, 0 },
+       { AU1000_DMA_INT_BASE+1, INTC_INT_HIGH_LEVEL, 0 },
+       { AU1000_DMA_INT_BASE+2, INTC_INT_HIGH_LEVEL, 0 },
+       { AU1000_DMA_INT_BASE+3, INTC_INT_HIGH_LEVEL, 0 },
+       { AU1000_DMA_INT_BASE+4, INTC_INT_HIGH_LEVEL, 0 },
+       { AU1000_DMA_INT_BASE+5, INTC_INT_HIGH_LEVEL, 0 },
+       { AU1000_DMA_INT_BASE+6, INTC_INT_HIGH_LEVEL, 0 },
+       { AU1000_DMA_INT_BASE+7, INTC_INT_HIGH_LEVEL, 0 },
        { AU1000_TOY_INT, INTC_INT_RISE_EDGE, 0 },
        { AU1000_TOY_MATCH0_INT, INTC_INT_RISE_EDGE, 0 },
        { AU1000_TOY_MATCH1_INT, INTC_INT_RISE_EDGE, 0 },
@@ -62,32 +62,32 @@ struct au1xxx_irqmap __initdata au1xxx_ic0_map[] = {
        { AU1000_RTC_MATCH0_INT, INTC_INT_RISE_EDGE, 0 },
        { AU1000_RTC_MATCH1_INT, INTC_INT_RISE_EDGE, 0 },
        { AU1000_RTC_MATCH2_INT, INTC_INT_RISE_EDGE, 0 },
-       { AU1000_IRDA_TX_INT, INTC_INT_HIGH_LEVEL, 0},
-       { AU1000_IRDA_RX_INT, INTC_INT_HIGH_LEVEL, 0},
+       { AU1000_IRDA_TX_INT, INTC_INT_HIGH_LEVEL, 0 },
+       { AU1000_IRDA_RX_INT, INTC_INT_HIGH_LEVEL, 0 },
        { AU1000_USB_DEV_REQ_INT, INTC_INT_HIGH_LEVEL, 0 },
        { AU1000_USB_DEV_SUS_INT, INTC_INT_RISE_EDGE, 0 },
        { AU1000_USB_HOST_INT, INTC_INT_LOW_LEVEL, 0 },
        { AU1000_ACSYNC_INT, INTC_INT_RISE_EDGE, 0 },
-       { AU1000_MAC0_DMA_INT, INTC_INT_HIGH_LEVEL, 0},
-       { AU1000_MAC1_DMA_INT, INTC_INT_HIGH_LEVEL, 0},
+       { AU1000_MAC0_DMA_INT, INTC_INT_HIGH_LEVEL, 0 },
+       { AU1000_MAC1_DMA_INT, INTC_INT_HIGH_LEVEL, 0 },
        { AU1000_AC97C_INT, INTC_INT_RISE_EDGE, 0 },
 
 #elif defined(CONFIG_SOC_AU1500)
 
-       { AU1500_UART0_INT, INTC_INT_HIGH_LEVEL, 0},
+       { AU1500_UART0_INT, INTC_INT_HIGH_LEVEL, 0 },
        { AU1000_PCI_INTA, INTC_INT_LOW_LEVEL, 0 },
        { AU1000_PCI_INTB, INTC_INT_LOW_LEVEL, 0 },
-       { AU1500_UART3_INT, INTC_INT_HIGH_LEVEL, 0},
+       { AU1500_UART3_INT, INTC_INT_HIGH_LEVEL, 0 },
        { AU1000_PCI_INTC, INTC_INT_LOW_LEVEL, 0 },
        { AU1000_PCI_INTD, INTC_INT_LOW_LEVEL, 0 },
-       { AU1000_DMA_INT_BASE, INTC_INT_HIGH_LEVEL, 0},
-       { AU1000_DMA_INT_BASE+1, INTC_INT_HIGH_LEVEL, 0},
-       { AU1000_DMA_INT_BASE+2, INTC_INT_HIGH_LEVEL, 0},
-       { AU1000_DMA_INT_BASE+3, INTC_INT_HIGH_LEVEL, 0},
-       { AU1000_DMA_INT_BASE+4, INTC_INT_HIGH_LEVEL, 0},
-       { AU1000_DMA_INT_BASE+5, INTC_INT_HIGH_LEVEL, 0},
-       { AU1000_DMA_INT_BASE+6, INTC_INT_HIGH_LEVEL, 0},
-       { AU1000_DMA_INT_BASE+7, INTC_INT_HIGH_LEVEL, 0},
+       { AU1000_DMA_INT_BASE, INTC_INT_HIGH_LEVEL, 0 },
+       { AU1000_DMA_INT_BASE+1, INTC_INT_HIGH_LEVEL, 0 },
+       { AU1000_DMA_INT_BASE+2, INTC_INT_HIGH_LEVEL, 0 },
+       { AU1000_DMA_INT_BASE+3, INTC_INT_HIGH_LEVEL, 0 },
+       { AU1000_DMA_INT_BASE+4, INTC_INT_HIGH_LEVEL, 0 },
+       { AU1000_DMA_INT_BASE+5, INTC_INT_HIGH_LEVEL, 0 },
+       { AU1000_DMA_INT_BASE+6, INTC_INT_HIGH_LEVEL, 0 },
+       { AU1000_DMA_INT_BASE+7, INTC_INT_HIGH_LEVEL, 0 },
        { AU1000_TOY_INT, INTC_INT_RISE_EDGE, 0 },
        { AU1000_TOY_MATCH0_INT, INTC_INT_RISE_EDGE, 0 },
        { AU1000_TOY_MATCH1_INT, INTC_INT_RISE_EDGE, 0 },
@@ -100,26 +100,26 @@ struct au1xxx_irqmap __initdata au1xxx_ic0_map[] = {
        { AU1000_USB_DEV_SUS_INT, INTC_INT_RISE_EDGE, 0 },
        { AU1000_USB_HOST_INT, INTC_INT_LOW_LEVEL, 0 },
        { AU1000_ACSYNC_INT, INTC_INT_RISE_EDGE, 0 },
-       { AU1500_MAC0_DMA_INT, INTC_INT_HIGH_LEVEL, 0},
-       { AU1500_MAC1_DMA_INT, INTC_INT_HIGH_LEVEL, 0},
+       { AU1500_MAC0_DMA_INT, INTC_INT_HIGH_LEVEL, 0 },
+       { AU1500_MAC1_DMA_INT, INTC_INT_HIGH_LEVEL, 0 },
        { AU1000_AC97C_INT, INTC_INT_RISE_EDGE, 0 },
 
 #elif defined(CONFIG_SOC_AU1100)
 
-       { AU1100_UART0_INT, INTC_INT_HIGH_LEVEL, 0},
-       { AU1100_UART1_INT, INTC_INT_HIGH_LEVEL, 0},
-       { AU1100_SD_INT, INTC_INT_HIGH_LEVEL, 0},
-       { AU1100_UART3_INT, INTC_INT_HIGH_LEVEL, 0},
-       { AU1000_SSI0_INT, INTC_INT_HIGH_LEVEL, 0},
-       { AU1000_SSI1_INT, INTC_INT_HIGH_LEVEL, 0},
-       { AU1000_DMA_INT_BASE, INTC_INT_HIGH_LEVEL, 0},
-       { AU1000_DMA_INT_BASE+1, INTC_INT_HIGH_LEVEL, 0},
-       { AU1000_DMA_INT_BASE+2, INTC_INT_HIGH_LEVEL, 0},
-       { AU1000_DMA_INT_BASE+3, INTC_INT_HIGH_LEVEL, 0},
-       { AU1000_DMA_INT_BASE+4, INTC_INT_HIGH_LEVEL, 0},
-       { AU1000_DMA_INT_BASE+5, INTC_INT_HIGH_LEVEL, 0},
-       { AU1000_DMA_INT_BASE+6, INTC_INT_HIGH_LEVEL, 0},
-       { AU1000_DMA_INT_BASE+7, INTC_INT_HIGH_LEVEL, 0},
+       { AU1100_UART0_INT, INTC_INT_HIGH_LEVEL, 0 },
+       { AU1100_UART1_INT, INTC_INT_HIGH_LEVEL, 0 },
+       { AU1100_SD_INT, INTC_INT_HIGH_LEVEL, 0 },
+       { AU1100_UART3_INT, INTC_INT_HIGH_LEVEL, 0 },
+       { AU1000_SSI0_INT, INTC_INT_HIGH_LEVEL, 0 },
+       { AU1000_SSI1_INT, INTC_INT_HIGH_LEVEL, 0 },
+       { AU1000_DMA_INT_BASE, INTC_INT_HIGH_LEVEL, 0 },
+       { AU1000_DMA_INT_BASE+1, INTC_INT_HIGH_LEVEL, 0 },
+       { AU1000_DMA_INT_BASE+2, INTC_INT_HIGH_LEVEL, 0 },
+       { AU1000_DMA_INT_BASE+3, INTC_INT_HIGH_LEVEL, 0 },
+       { AU1000_DMA_INT_BASE+4, INTC_INT_HIGH_LEVEL, 0 },
+       { AU1000_DMA_INT_BASE+5, INTC_INT_HIGH_LEVEL, 0 },
+       { AU1000_DMA_INT_BASE+6, INTC_INT_HIGH_LEVEL, 0 },
+       { AU1000_DMA_INT_BASE+7, INTC_INT_HIGH_LEVEL, 0 },
        { AU1000_TOY_INT, INTC_INT_RISE_EDGE, 0 },
        { AU1000_TOY_MATCH0_INT, INTC_INT_RISE_EDGE, 0 },
        { AU1000_TOY_MATCH1_INT, INTC_INT_RISE_EDGE, 0 },
@@ -128,33 +128,33 @@ struct au1xxx_irqmap __initdata au1xxx_ic0_map[] = {
        { AU1000_RTC_MATCH0_INT, INTC_INT_RISE_EDGE, 0 },
        { AU1000_RTC_MATCH1_INT, INTC_INT_RISE_EDGE, 0 },
        { AU1000_RTC_MATCH2_INT, INTC_INT_RISE_EDGE, 0 },
-       { AU1000_IRDA_TX_INT, INTC_INT_HIGH_LEVEL, 0},
-       { AU1000_IRDA_RX_INT, INTC_INT_HIGH_LEVEL, 0},
+       { AU1000_IRDA_TX_INT, INTC_INT_HIGH_LEVEL, 0 },
+       { AU1000_IRDA_RX_INT, INTC_INT_HIGH_LEVEL, 0 },
        { AU1000_USB_DEV_REQ_INT, INTC_INT_HIGH_LEVEL, 0 },
        { AU1000_USB_DEV_SUS_INT, INTC_INT_RISE_EDGE, 0 },
        { AU1000_USB_HOST_INT, INTC_INT_LOW_LEVEL, 0 },
        { AU1000_ACSYNC_INT, INTC_INT_RISE_EDGE, 0 },
-       { AU1100_MAC0_DMA_INT, INTC_INT_HIGH_LEVEL, 0},
-       /*{ AU1000_GPIO215_208_INT, INTC_INT_HIGH_LEVEL, 0},*/
-       { AU1100_LCD_INT, INTC_INT_HIGH_LEVEL, 0},
+       { AU1100_MAC0_DMA_INT, INTC_INT_HIGH_LEVEL, 0 },
+       /* { AU1000_GPIO215_208_INT, INTC_INT_HIGH_LEVEL, 0 }, */
+       { AU1100_LCD_INT, INTC_INT_HIGH_LEVEL, 0 },
        { AU1000_AC97C_INT, INTC_INT_RISE_EDGE, 0 },
 
 #elif defined(CONFIG_SOC_AU1550)
 
-       { AU1550_UART0_INT, INTC_INT_HIGH_LEVEL, 0},
+       { AU1550_UART0_INT, INTC_INT_HIGH_LEVEL, 0 },
        { AU1550_PCI_INTA, INTC_INT_LOW_LEVEL, 0 },
        { AU1550_PCI_INTB, INTC_INT_LOW_LEVEL, 0 },
-       { AU1550_DDMA_INT, INTC_INT_HIGH_LEVEL, 0},
-       { AU1550_CRYPTO_INT, INTC_INT_HIGH_LEVEL, 0},
+       { AU1550_DDMA_INT, INTC_INT_HIGH_LEVEL, 0 },
+       { AU1550_CRYPTO_INT, INTC_INT_HIGH_LEVEL, 0 },
        { AU1550_PCI_INTC, INTC_INT_LOW_LEVEL, 0 },
        { AU1550_PCI_INTD, INTC_INT_LOW_LEVEL, 0 },
        { AU1550_PCI_RST_INT, INTC_INT_LOW_LEVEL, 0 },
-       { AU1550_UART1_INT, INTC_INT_HIGH_LEVEL, 0},
-       { AU1550_UART3_INT, INTC_INT_HIGH_LEVEL, 0},
-       { AU1550_PSC0_INT, INTC_INT_HIGH_LEVEL, 0},
-       { AU1550_PSC1_INT, INTC_INT_HIGH_LEVEL, 0},
-       { AU1550_PSC2_INT, INTC_INT_HIGH_LEVEL, 0},
-       { AU1550_PSC3_INT, INTC_INT_HIGH_LEVEL, 0},
+       { AU1550_UART1_INT, INTC_INT_HIGH_LEVEL, 0 },
+       { AU1550_UART3_INT, INTC_INT_HIGH_LEVEL, 0 },
+       { AU1550_PSC0_INT, INTC_INT_HIGH_LEVEL, 0 },
+       { AU1550_PSC1_INT, INTC_INT_HIGH_LEVEL, 0 },
+       { AU1550_PSC2_INT, INTC_INT_HIGH_LEVEL, 0 },
+       { AU1550_PSC3_INT, INTC_INT_HIGH_LEVEL, 0 },
        { AU1000_TOY_INT, INTC_INT_RISE_EDGE, 0 },
        { AU1000_TOY_MATCH0_INT, INTC_INT_RISE_EDGE, 0 },
        { AU1000_TOY_MATCH1_INT, INTC_INT_RISE_EDGE, 0 },
@@ -163,26 +163,26 @@ struct au1xxx_irqmap __initdata au1xxx_ic0_map[] = {
        { AU1000_RTC_MATCH0_INT, INTC_INT_RISE_EDGE, 0 },
        { AU1000_RTC_MATCH1_INT, INTC_INT_RISE_EDGE, 0 },
        { AU1000_RTC_MATCH2_INT, INTC_INT_RISE_EDGE, 0 },
-       { AU1550_NAND_INT, INTC_INT_RISE_EDGE, 0},
+       { AU1550_NAND_INT, INTC_INT_RISE_EDGE, 0 },
        { AU1550_USB_DEV_REQ_INT, INTC_INT_HIGH_LEVEL, 0 },
        { AU1550_USB_DEV_SUS_INT, INTC_INT_RISE_EDGE, 0 },
        { AU1550_USB_HOST_INT, INTC_INT_LOW_LEVEL, 0 },
-       { AU1550_MAC0_DMA_INT, INTC_INT_HIGH_LEVEL, 0},
-       { AU1550_MAC1_DMA_INT, INTC_INT_HIGH_LEVEL, 0},
+       { AU1550_MAC0_DMA_INT, INTC_INT_HIGH_LEVEL, 0 },
+       { AU1550_MAC1_DMA_INT, INTC_INT_HIGH_LEVEL, 0 },
 
 #elif defined(CONFIG_SOC_AU1200)
 
-       { AU1200_UART0_INT, INTC_INT_HIGH_LEVEL, 0},
+       { AU1200_UART0_INT, INTC_INT_HIGH_LEVEL, 0 },
        { AU1200_SWT_INT, INTC_INT_RISE_EDGE, 0 },
-       { AU1200_SD_INT, INTC_INT_HIGH_LEVEL, 0},
-       { AU1200_DDMA_INT, INTC_INT_HIGH_LEVEL, 0},
+       { AU1200_SD_INT, INTC_INT_HIGH_LEVEL, 0 },
+       { AU1200_DDMA_INT, INTC_INT_HIGH_LEVEL, 0 },
        { AU1200_MAE_BE_INT, INTC_INT_HIGH_LEVEL, 0 },
-       { AU1200_UART1_INT, INTC_INT_HIGH_LEVEL, 0},
+       { AU1200_UART1_INT, INTC_INT_HIGH_LEVEL, 0 },
        { AU1200_MAE_FE_INT, INTC_INT_HIGH_LEVEL, 0 },
-       { AU1200_PSC0_INT, INTC_INT_HIGH_LEVEL, 0},
-       { AU1200_PSC1_INT, INTC_INT_HIGH_LEVEL, 0},
-       { AU1200_AES_INT, INTC_INT_HIGH_LEVEL, 0},
-       { AU1200_CAMERA_INT, INTC_INT_HIGH_LEVEL, 0},
+       { AU1200_PSC0_INT, INTC_INT_HIGH_LEVEL, 0 },
+       { AU1200_PSC1_INT, INTC_INT_HIGH_LEVEL, 0 },
+       { AU1200_AES_INT, INTC_INT_HIGH_LEVEL, 0 },
+       { AU1200_CAMERA_INT, INTC_INT_HIGH_LEVEL, 0 },
        { AU1000_TOY_INT, INTC_INT_RISE_EDGE, 0 },
        { AU1000_TOY_MATCH0_INT, INTC_INT_RISE_EDGE, 0 },
        { AU1000_TOY_MATCH1_INT, INTC_INT_RISE_EDGE, 0 },
@@ -191,10 +191,10 @@ struct au1xxx_irqmap __initdata au1xxx_ic0_map[] = {
        { AU1000_RTC_MATCH0_INT, INTC_INT_RISE_EDGE, 0 },
        { AU1000_RTC_MATCH1_INT, INTC_INT_RISE_EDGE, 0 },
        { AU1000_RTC_MATCH2_INT, INTC_INT_RISE_EDGE, 0 },
-       { AU1200_NAND_INT, INTC_INT_RISE_EDGE, 0},
+       { AU1200_NAND_INT, INTC_INT_RISE_EDGE, 0 },
        { AU1200_USB_INT, INTC_INT_HIGH_LEVEL, 0 },
-       { AU1200_LCD_INT, INTC_INT_HIGH_LEVEL, 0},
-       { AU1200_MAE_BOTH_INT, INTC_INT_HIGH_LEVEL, 0},
+       { AU1200_LCD_INT, INTC_INT_HIGH_LEVEL, 0 },
+       { AU1200_MAE_BOTH_INT, INTC_INT_HIGH_LEVEL, 0 },
 
 #else
 #error "Error: Unknown Alchemy SOC"
@@ -203,4 +203,3 @@ struct au1xxx_irqmap __initdata au1xxx_ic0_map[] = {
 };
 
 int __initdata au1xxx_ic0_nr_irqs = ARRAY_SIZE(au1xxx_ic0_map);
-
index 3ce6cace0eb0d618294f0701228f0a9761c74e59..46f8ee0e265771be26b8833d54e19d949344ed3d 100644 (file)
@@ -1,10 +1,9 @@
 /*
  * BRIEF MODULE DESCRIPTION
- *     Simple Au1000 clocks routines.
+ *     Simple Au1xx0 clocks routines.
  *
- * Copyright 2001 MontaVista Software Inc.
- * Author: MontaVista Software, Inc.
- *             ppopov@mvista.com or source@mvista.com
+ * Copyright 2001, 2008 MontaVista Software Inc.
+ * Author: MontaVista Software, Inc. <source@mvista.com>
  *
  *  This program is free software; you can redistribute         it and/or modify it
  *  under  the terms of         the GNU General  Public License as published by the
@@ -30,8 +29,8 @@
 #include <linux/module.h>
 #include <asm/mach-au1x00/au1000.h>
 
-static unsigned int au1x00_clock; // Hz
-static unsigned int lcd_clock;    // KHz
+static unsigned int au1x00_clock; /*  Hz */
+static unsigned int lcd_clock;    /* KHz */
 static unsigned long uart_baud_base;
 
 /*
@@ -47,8 +46,6 @@ unsigned int get_au1x00_speed(void)
        return au1x00_clock;
 }
 
-
-
 /*
  * The UART baud base is not known at compile time ... if
  * we want to be able to use the same code on different
@@ -73,24 +70,23 @@ void set_au1x00_uart_baud_base(unsigned long new_baud_base)
 void set_au1x00_lcd_clock(void)
 {
        unsigned int static_cfg0;
-       unsigned int sys_busclk =
-               (get_au1x00_speed()/1000) /
-               ((int)(au_readl(SYS_POWERCTRL)&0x03) + 2);
+       unsigned int sys_busclk = (get_au1x00_speed() / 1000) /
+                                 ((int)(au_readl(SYS_POWERCTRL) & 0x03) + 2);
 
        static_cfg0 = au_readl(MEM_STCFG0);
 
-       if (static_cfg0 & (1<<11))
+       if (static_cfg0 & (1 << 11))
                lcd_clock = sys_busclk / 5; /* note: BCLK switching fails with D5 */
        else
                lcd_clock = sys_busclk / 4;
 
        if (lcd_clock > 50000) /* Epson MAX */
-               printk("warning: LCD clock too high (%d KHz)\n", lcd_clock);
+               printk(KERN_WARNING "warning: LCD clock too high (%u KHz)\n",
+                                   lcd_clock);
 }
 
 unsigned int get_au1x00_lcd_clock(void)
 {
        return lcd_clock;
 }
-
 EXPORT_SYMBOL(get_au1x00_lcd_clock);
index 8c93a05d73826e804ff82781ae5f50d28ed35029..ba6430bc2d0300d78b9b66d3fa4870a12083eb82 100644 (file)
@@ -14,7 +14,7 @@
 
 #include <asm/mach-au1x00/au1000.h>
 
-struct cpu_speccur_cpu_spec[NR_CPUS];
+struct cpu_spec *cur_cpu_spec[NR_CPUS];
 
 /* With some thought, we can probably use the mask to reduce the
  * size of the table.
@@ -39,8 +39,7 @@ struct cpu_spec cpu_specs[] = {
        { 0x00000000, 0x00000000, "Unknown Au1xxx", 1, 0, 0 }
 };
 
-void
-set_cpuspec(void)
+void set_cpuspec(void)
 {
        struct  cpu_spec *sp;
        u32     prid;
index 53377dfc0640da33d85db3b7f47db242872ca5b1..42d555236de15bbd4bc731554fb54a8ab305d6d1 100644 (file)
  */
 static DEFINE_SPINLOCK(au1xxx_dbdma_spin_lock);
 
-/* I couldn't find a macro that did this......
-*/
+/* I couldn't find a macro that did this... */
 #define ALIGN_ADDR(x, a)       ((((u32)(x)) + (a-1)) & ~(a-1))
 
 static dbdma_global_t *dbdma_gptr = (dbdma_global_t *)DDMA_GLOBAL_BASE;
-static int dbdma_initialized=0;
+static int dbdma_initialized;
 static void au1xxx_dbdma_init(void);
 
 static dbdev_tab_t dbdev_tab[] = {
@@ -149,7 +148,7 @@ static dbdev_tab_t dbdev_tab[] = {
 
        { DSCR_CMD0_NAND_FLASH, DEV_FLAGS_IN, 0, 0, 0x00000000, 0, 0 },
 
-#endif // CONFIG_SOC_AU1200
+#endif /* CONFIG_SOC_AU1200 */
 
        { DSCR_CMD0_THROTTLE, DEV_FLAGS_ANYUSE, 0, 0, 0x00000000, 0, 0 },
        { DSCR_CMD0_ALWAYS, DEV_FLAGS_ANYUSE, 0, 0, 0x00000000, 0, 0 },
@@ -177,8 +176,7 @@ static dbdev_tab_t dbdev_tab[] = {
 
 static chan_tab_t *chan_tab_ptr[NUM_DBDMA_CHANS];
 
-static dbdev_tab_t *
-find_dbdev_id(u32 id)
+static dbdev_tab_t *find_dbdev_id(u32 id)
 {
        int i;
        dbdev_tab_t *p;
@@ -190,29 +188,27 @@ find_dbdev_id(u32 id)
        return NULL;
 }
 
-void * au1xxx_ddma_get_nextptr_virt(au1x_ddma_desc_t *dp)
+void *au1xxx_ddma_get_nextptr_virt(au1x_ddma_desc_t *dp)
 {
-        return phys_to_virt(DSCR_GET_NXTPTR(dp->dscr_nxtptr));
+       return phys_to_virt(DSCR_GET_NXTPTR(dp->dscr_nxtptr));
 }
 EXPORT_SYMBOL(au1xxx_ddma_get_nextptr_virt);
 
-u32
-au1xxx_ddma_add_device(dbdev_tab_t *dev)
+u32 au1xxx_ddma_add_device(dbdev_tab_t *dev)
 {
        u32 ret = 0;
-       dbdev_tab_t *p=NULL;
-       static u16 new_id=0x1000;
+       dbdev_tab_t *p;
+       static u16 new_id = 0x1000;
 
        p = find_dbdev_id(~0);
-       if ( NULL != p )
-       {
+       if (NULL != p) {
                memcpy(p, dev, sizeof(dbdev_tab_t));
                p->dev_id = DSCR_DEV2CUSTOM_ID(new_id, dev->dev_id);
                ret = p->dev_id;
                new_id++;
 #if 0
-               printk("add_device: id:%x flags:%x padd:%x\n",
-                               p->dev_id, p->dev_flags, p->dev_physaddr );
+               printk(KERN_DEBUG "add_device: id:%x flags:%x padd:%x\n",
+                                 p->dev_id, p->dev_flags, p->dev_physaddr);
 #endif
        }
 
@@ -220,10 +216,8 @@ au1xxx_ddma_add_device(dbdev_tab_t *dev)
 }
 EXPORT_SYMBOL(au1xxx_ddma_add_device);
 
-/* Allocate a channel and return a non-zero descriptor if successful.
-*/
-u32
-au1xxx_dbdma_chan_alloc(u32 srcid, u32 destid,
+/* Allocate a channel and return a non-zero descriptor if successful. */
+u32 au1xxx_dbdma_chan_alloc(u32 srcid, u32 destid,
        void (*callback)(int, void *), void *callparam)
 {
        unsigned long   flags;
@@ -234,7 +228,8 @@ au1xxx_dbdma_chan_alloc(u32 srcid, u32 destid,
        chan_tab_t      *ctp;
        au1x_dma_chan_t *cp;
 
-       /* We do the intialization on the first channel allocation.
+       /*
+        * We do the intialization on the first channel allocation.
         * We have to wait because of the interrupt handler initialization
         * which can't be done successfully during board set up.
         */
@@ -242,16 +237,17 @@ au1xxx_dbdma_chan_alloc(u32 srcid, u32 destid,
                au1xxx_dbdma_init();
        dbdma_initialized = 1;
 
-       if ((stp = find_dbdev_id(srcid)) == NULL)
+       stp = find_dbdev_id(srcid);
+       if (stp == NULL)
                return 0;
-       if ((dtp = find_dbdev_id(destid)) == NULL)
+       dtp = find_dbdev_id(destid);
+       if (dtp == NULL)
                return 0;
 
        used = 0;
        rv = 0;
 
-       /* Check to see if we can get both channels.
-       */
+       /* Check to see if we can get both channels. */
        spin_lock_irqsave(&au1xxx_dbdma_spin_lock, flags);
        if (!(stp->dev_flags & DEV_FLAGS_INUSE) ||
             (stp->dev_flags & DEV_FLAGS_ANYUSE)) {
@@ -261,35 +257,30 @@ au1xxx_dbdma_chan_alloc(u32 srcid, u32 destid,
                     (dtp->dev_flags & DEV_FLAGS_ANYUSE)) {
                        /* Got destination */
                        dtp->dev_flags |= DEV_FLAGS_INUSE;
-               }
-               else {
-                       /* Can't get dest.  Release src.
-                       */
+               } else {
+                       /* Can't get dest.  Release src. */
                        stp->dev_flags &= ~DEV_FLAGS_INUSE;
                        used++;
                }
-       }
-       else {
+       } else
                used++;
-       }
        spin_unlock_irqrestore(&au1xxx_dbdma_spin_lock, flags);
 
        if (!used) {
-               /* Let's see if we can allocate a channel for it.
-               */
+               /* Let's see if we can allocate a channel for it. */
                ctp = NULL;
                chan = 0;
                spin_lock_irqsave(&au1xxx_dbdma_spin_lock, flags);
-               for (i=0; i<NUM_DBDMA_CHANS; i++) {
+               for (i = 0; i < NUM_DBDMA_CHANS; i++)
                        if (chan_tab_ptr[i] == NULL) {
-                               /* If kmalloc fails, it is caught below same
+                               /*
+                                * If kmalloc fails, it is caught below same
                                 * as a channel not available.
                                 */
                                ctp = kmalloc(sizeof(chan_tab_t), GFP_ATOMIC);
                                chan_tab_ptr[i] = ctp;
                                break;
                        }
-               }
                spin_unlock_irqrestore(&au1xxx_dbdma_spin_lock, flags);
 
                if (ctp != NULL) {
@@ -304,8 +295,7 @@ au1xxx_dbdma_chan_alloc(u32 srcid, u32 destid,
                        ctp->chan_callback = callback;
                        ctp->chan_callparam = callparam;
 
-                       /* Initialize channel configuration.
-                       */
+                       /* Initialize channel configuration. */
                        i = 0;
                        if (stp->dev_intlevel)
                                i |= DDMA_CFG_SED;
@@ -326,8 +316,7 @@ au1xxx_dbdma_chan_alloc(u32 srcid, u32 destid,
                         * operations.
                         */
                        rv = (u32)(&chan_tab_ptr[chan]);
-               }
-               else {
+               } else {
                        /* Release devices */
                        stp->dev_flags &= ~DEV_FLAGS_INUSE;
                        dtp->dev_flags &= ~DEV_FLAGS_INUSE;
@@ -337,11 +326,11 @@ au1xxx_dbdma_chan_alloc(u32 srcid, u32 destid,
 }
 EXPORT_SYMBOL(au1xxx_dbdma_chan_alloc);
 
-/* Set the device width if source or destination is a FIFO.
+/*
+ * Set the device width if source or destination is a FIFO.
  * Should be 8, 16, or 32 bits.
  */
-u32
-au1xxx_dbdma_set_devwidth(u32 chanid, int bits)
+u32 au1xxx_dbdma_set_devwidth(u32 chanid, int bits)
 {
        u32             rv;
        chan_tab_t      *ctp;
@@ -365,10 +354,8 @@ au1xxx_dbdma_set_devwidth(u32 chanid, int bits)
 }
 EXPORT_SYMBOL(au1xxx_dbdma_set_devwidth);
 
-/* Allocate a descriptor ring, initializing as much as possible.
-*/
-u32
-au1xxx_dbdma_ring_alloc(u32 chanid, int entries)
+/* Allocate a descriptor ring, initializing as much as possible. */
+u32 au1xxx_dbdma_ring_alloc(u32 chanid, int entries)
 {
        int                     i;
        u32                     desc_base, srcid, destid;
@@ -378,43 +365,45 @@ au1xxx_dbdma_ring_alloc(u32 chanid, int entries)
        dbdev_tab_t             *stp, *dtp;
        au1x_ddma_desc_t        *dp;
 
-       /* I guess we could check this to be within the
+       /*
+        * I guess we could check this to be within the
         * range of the table......
         */
        ctp = *((chan_tab_t **)chanid);
        stp = ctp->chan_src;
        dtp = ctp->chan_dest;
 
-       /* The descriptors must be 32-byte aligned.  There is a
+       /*
+        * The descriptors must be 32-byte aligned.  There is a
         * possibility the allocation will give us such an address,
         * and if we try that first we are likely to not waste larger
         * slabs of memory.
         */
        desc_base = (u32)kmalloc(entries * sizeof(au1x_ddma_desc_t),
-                       GFP_KERNEL|GFP_DMA);
+                                GFP_KERNEL|GFP_DMA);
        if (desc_base == 0)
                return 0;
 
        if (desc_base & 0x1f) {
-               /* Lost....do it again, allocate extra, and round
+               /*
+                * Lost....do it again, allocate extra, and round
                 * the address base.
                 */
                kfree((const void *)desc_base);
                i = entries * sizeof(au1x_ddma_desc_t);
                i += (sizeof(au1x_ddma_desc_t) - 1);
-               if ((desc_base = (u32)kmalloc(i, GFP_KERNEL|GFP_DMA)) == 0)
+               desc_base = (u32)kmalloc(i, GFP_KERNEL|GFP_DMA);
+               if (desc_base == 0)
                        return 0;
 
                desc_base = ALIGN_ADDR(desc_base, sizeof(au1x_ddma_desc_t));
        }
        dp = (au1x_ddma_desc_t *)desc_base;
 
-       /* Keep track of the base descriptor.
-       */
+       /* Keep track of the base descriptor. */
        ctp->chan_desc_base = dp;
 
-       /* Initialize the rings with as much information as we know.
-        */
+       /* Initialize the rings with as much information as we know. */
        srcid = stp->dev_id;
        destid = dtp->dev_id;
 
@@ -426,11 +415,12 @@ au1xxx_dbdma_ring_alloc(u32 chanid, int entries)
        cmd0 |= DSCR_CMD0_IE | DSCR_CMD0_CV;
        cmd0 |= DSCR_CMD0_ST(DSCR_CMD0_ST_NOCHANGE);
 
-        /* is it mem to mem transfer? */
-        if(((DSCR_CUSTOM2DEV_ID(srcid) == DSCR_CMD0_THROTTLE) || (DSCR_CUSTOM2DEV_ID(srcid) == DSCR_CMD0_ALWAYS)) &&
-           ((DSCR_CUSTOM2DEV_ID(destid) == DSCR_CMD0_THROTTLE) || (DSCR_CUSTOM2DEV_ID(destid) == DSCR_CMD0_ALWAYS))) {
-               cmd0 |= DSCR_CMD0_MEM;
-        }
+       /* Is it mem to mem transfer? */
+       if (((DSCR_CUSTOM2DEV_ID(srcid) == DSCR_CMD0_THROTTLE) ||
+            (DSCR_CUSTOM2DEV_ID(srcid) == DSCR_CMD0_ALWAYS)) &&
+           ((DSCR_CUSTOM2DEV_ID(destid) == DSCR_CMD0_THROTTLE) ||
+            (DSCR_CUSTOM2DEV_ID(destid) == DSCR_CMD0_ALWAYS)))
+               cmd0 |= DSCR_CMD0_MEM;
 
        switch (stp->dev_devwidth) {
        case 8:
@@ -458,15 +448,17 @@ au1xxx_dbdma_ring_alloc(u32 chanid, int entries)
                break;
        }
 
-       /* If the device is marked as an in/out FIFO, ensure it is
+       /*
+        * If the device is marked as an in/out FIFO, ensure it is
         * set non-coherent.
         */
        if (stp->dev_flags & DEV_FLAGS_IN)
-               cmd0 |= DSCR_CMD0_SN;           /* Source in fifo */
+               cmd0 |= DSCR_CMD0_SN;           /* Source in FIFO */
        if (dtp->dev_flags & DEV_FLAGS_OUT)
-               cmd0 |= DSCR_CMD0_DN;           /* Destination out fifo */
+               cmd0 |= DSCR_CMD0_DN;           /* Destination out FIFO */
 
-       /* Set up source1.  For now, assume no stride and increment.
+       /*
+        * Set up source1.  For now, assume no stride and increment.
         * A channel attribute update can change this later.
         */
        switch (stp->dev_tsize) {
@@ -485,19 +477,19 @@ au1xxx_dbdma_ring_alloc(u32 chanid, int entries)
                break;
        }
 
-       /* If source input is fifo, set static address.
-       */
+       /* If source input is FIFO, set static address. */
        if (stp->dev_flags & DEV_FLAGS_IN) {
-               if ( stp->dev_flags & DEV_FLAGS_BURSTABLE )
+               if (stp->dev_flags & DEV_FLAGS_BURSTABLE)
                        src1 |= DSCR_SRC1_SAM(DSCR_xAM_BURST);
                else
-               src1 |= DSCR_SRC1_SAM(DSCR_xAM_STATIC);
-
+                       src1 |= DSCR_SRC1_SAM(DSCR_xAM_STATIC);
        }
+
        if (stp->dev_physaddr)
                src0 = stp->dev_physaddr;
 
-       /* Set up dest1.  For now, assume no stride and increment.
+       /*
+        * Set up dest1.  For now, assume no stride and increment.
         * A channel attribute update can change this later.
         */
        switch (dtp->dev_tsize) {
@@ -516,22 +508,24 @@ au1xxx_dbdma_ring_alloc(u32 chanid, int entries)
                break;
        }
 
-       /* If destination output is fifo, set static address.
-       */
+       /* If destination output is FIFO, set static address. */
        if (dtp->dev_flags & DEV_FLAGS_OUT) {
-               if ( dtp->dev_flags & DEV_FLAGS_BURSTABLE )
-                       dest1 |= DSCR_DEST1_DAM(DSCR_xAM_BURST);
-                               else
-               dest1 |= DSCR_DEST1_DAM(DSCR_xAM_STATIC);
+               if (dtp->dev_flags & DEV_FLAGS_BURSTABLE)
+                       dest1 |= DSCR_DEST1_DAM(DSCR_xAM_BURST);
+               else
+                       dest1 |= DSCR_DEST1_DAM(DSCR_xAM_STATIC);
        }
+
        if (dtp->dev_physaddr)
                dest0 = dtp->dev_physaddr;
 
 #if 0
-               printk("did:%x sid:%x cmd0:%x cmd1:%x source0:%x source1:%x dest0:%x dest1:%x\n",
-                       dtp->dev_id, stp->dev_id, cmd0, cmd1, src0, src1, dest0, dest1 );
+               printk(KERN_DEBUG "did:%x sid:%x cmd0:%x cmd1:%x source0:%x "
+                                 "source1:%x dest0:%x dest1:%x\n",
+                                 dtp->dev_id, stp->dev_id, cmd0, cmd1, src0,
+                                 src1, dest0, dest1);
 #endif
-       for (i=0; i<entries; i++) {
+       for (i = 0; i < entries; i++) {
                dp->dscr_cmd0 = cmd0;
                dp->dscr_cmd1 = cmd1;
                dp->dscr_source0 = src0;
@@ -545,49 +539,49 @@ au1xxx_dbdma_ring_alloc(u32 chanid, int entries)
                dp++;
        }
 
-       /* Make last descrptor point to the first.
-       */
+       /* Make last descrptor point to the first. */
        dp--;
        dp->dscr_nxtptr = DSCR_NXTPTR(virt_to_phys(ctp->chan_desc_base));
        ctp->get_ptr = ctp->put_ptr = ctp->cur_ptr = ctp->chan_desc_base;
 
-       return (u32)(ctp->chan_desc_base);
+       return (u32)ctp->chan_desc_base;
 }
 EXPORT_SYMBOL(au1xxx_dbdma_ring_alloc);
 
-/* Put a source buffer into the DMA ring.
+/*
+ * Put a source buffer into the DMA ring.
  * This updates the source pointer and byte count.  Normally used
  * for memory to fifo transfers.
  */
-u32
-_au1xxx_dbdma_put_source(u32 chanid, void *buf, int nbytes, u32 flags)
+u32 _au1xxx_dbdma_put_source(u32 chanid, void *buf, int nbytes, u32 flags)
 {
        chan_tab_t              *ctp;
        au1x_ddma_desc_t        *dp;
 
-       /* I guess we could check this to be within the
+       /*
+        * I guess we could check this to be within the
         * range of the table......
         */
-       ctp = *((chan_tab_t **)chanid);
+       ctp = *(chan_tab_t **)chanid;
 
-       /* We should have multiple callers for a particular channel,
+       /*
+        * We should have multiple callers for a particular channel,
         * an interrupt doesn't affect this pointer nor the descriptor,
         * so no locking should be needed.
         */
        dp = ctp->put_ptr;
 
-       /* If the descriptor is valid, we are way ahead of the DMA
+       /*
+        * If the descriptor is valid, we are way ahead of the DMA
         * engine, so just return an error condition.
         */
-       if (dp->dscr_cmd0 & DSCR_CMD0_V) {
+       if (dp->dscr_cmd0 & DSCR_CMD0_V)
                return 0;
-       }
 
-       /* Load up buffer address and byte count.
-       */
+       /* Load up buffer address and byte count. */
        dp->dscr_source0 = virt_to_phys(buf);
        dp->dscr_cmd1 = nbytes;
-       /* Check flags  */
+       /* Check flags */
        if (flags & DDMA_FLAGS_IE)
                dp->dscr_cmd0 |= DSCR_CMD0_IE;
        if (flags & DDMA_FLAGS_NOIE)
@@ -595,23 +589,21 @@ _au1xxx_dbdma_put_source(u32 chanid, void *buf, int nbytes, u32 flags)
 
        /*
         * There is an errata on the Au1200/Au1550 parts that could result
-        * in "stale" data being DMA'd. It has to do with the snoop logic on
-        * the dache eviction buffer.  NONCOHERENT_IO is on by default for
-        * these parts. If it is fixedin the future, these dma_cache_inv will
+        * in "stale" data being DMA'ed. It has to do with the snoop logic on
+        * the cache eviction buffer.  DMA_NONCOHERENT is on by default for
+        * these parts. If it is fixed in the future, these dma_cache_inv will
         * just be nothing more than empty macros. See io.h.
-        * */
+        */
        dma_cache_wback_inv((unsigned long)buf, nbytes);
-        dp->dscr_cmd0 |= DSCR_CMD0_V;        /* Let it rip */
+       dp->dscr_cmd0 |= DSCR_CMD0_V;   /* Let it rip */
        au_sync();
        dma_cache_wback_inv((unsigned long)dp, sizeof(dp));
-        ctp->chan_ptr->ddma_dbell = 0;
+       ctp->chan_ptr->ddma_dbell = 0;
 
-       /* Get next descriptor pointer.
-       */
+       /* Get next descriptor pointer. */
        ctp->put_ptr = phys_to_virt(DSCR_GET_NXTPTR(dp->dscr_nxtptr));
 
-       /* return something not zero.
-       */
+       /* Return something non-zero. */
        return nbytes;
 }
 EXPORT_SYMBOL(_au1xxx_dbdma_put_source);
@@ -654,81 +646,77 @@ _au1xxx_dbdma_put_dest(u32 chanid, void *buf, int nbytes, u32 flags)
        dp->dscr_dest0 = virt_to_phys(buf);
        dp->dscr_cmd1 = nbytes;
 #if 0
-       printk("cmd0:%x cmd1:%x source0:%x source1:%x dest0:%x dest1:%x\n",
-                       dp->dscr_cmd0, dp->dscr_cmd1, dp->dscr_source0,
-                       dp->dscr_source1, dp->dscr_dest0, dp->dscr_dest1 );
+       printk(KERN_DEBUG "cmd0:%x cmd1:%x source0:%x source1:%x dest0:%x dest1:%x\n",
+                         dp->dscr_cmd0, dp->dscr_cmd1, dp->dscr_source0,
+                         dp->dscr_source1, dp->dscr_dest0, dp->dscr_dest1);
 #endif
        /*
         * There is an errata on the Au1200/Au1550 parts that could result in
-        * "stale" data being DMA'd. It has to do with the snoop logic on the
-        * dache eviction buffer. NONCOHERENT_IO is on by default for these
-        * parts. If it is fixedin the future, these dma_cache_inv will just
+        * "stale" data being DMA'ed. It has to do with the snoop logic on the
+        * cache eviction buffer.  DMA_NONCOHERENT is on by default for these
+        * parts. If it is fixed in the future, these dma_cache_inv will just
         * be nothing more than empty macros. See io.h.
-        * */
+        */
        dma_cache_inv((unsigned long)buf, nbytes);
        dp->dscr_cmd0 |= DSCR_CMD0_V;   /* Let it rip */
        au_sync();
        dma_cache_wback_inv((unsigned long)dp, sizeof(dp));
-        ctp->chan_ptr->ddma_dbell = 0;
+       ctp->chan_ptr->ddma_dbell = 0;
 
-       /* Get next descriptor pointer.
-       */
+       /* Get next descriptor pointer. */
        ctp->put_ptr = phys_to_virt(DSCR_GET_NXTPTR(dp->dscr_nxtptr));
 
-       /* return something not zero.
-       */
+       /* Return something non-zero. */
        return nbytes;
 }
 EXPORT_SYMBOL(_au1xxx_dbdma_put_dest);
 
-/* Get a destination buffer into the DMA ring.
+/*
+ * Get a destination buffer into the DMA ring.
  * Normally used to get a full buffer from the ring during fifo
  * to memory transfers.  This does not set the valid bit, you will
  * have to put another destination buffer to keep the DMA going.
  */
-u32
-au1xxx_dbdma_get_dest(u32 chanid, void **buf, int *nbytes)
+u32 au1xxx_dbdma_get_dest(u32 chanid, void **buf, int *nbytes)
 {
        chan_tab_t              *ctp;
        au1x_ddma_desc_t        *dp;
        u32                     rv;
 
-       /* I guess we could check this to be within the
+       /*
+        * I guess we could check this to be within the
         * range of the table......
         */
        ctp = *((chan_tab_t **)chanid);
 
-       /* We should have multiple callers for a particular channel,
+       /*
+        * We should have multiple callers for a particular channel,
         * an interrupt doesn't affect this pointer nor the descriptor,
         * so no locking should be needed.
         */
        dp = ctp->get_ptr;
 
-       /* If the descriptor is valid, we are way ahead of the DMA
+       /*
+        * If the descriptor is valid, we are way ahead of the DMA
         * engine, so just return an error condition.
         */
        if (dp->dscr_cmd0 & DSCR_CMD0_V)
                return 0;
 
-       /* Return buffer address and byte count.
-       */
+       /* Return buffer address and byte count. */
        *buf = (void *)(phys_to_virt(dp->dscr_dest0));
        *nbytes = dp->dscr_cmd1;
        rv = dp->dscr_stat;
 
-       /* Get next descriptor pointer.
-       */
+       /* Get next descriptor pointer. */
        ctp->get_ptr = phys_to_virt(DSCR_GET_NXTPTR(dp->dscr_nxtptr));
 
-       /* return something not zero.
-       */
+       /* Return something non-zero. */
        return rv;
 }
-
 EXPORT_SYMBOL_GPL(au1xxx_dbdma_get_dest);
 
-void
-au1xxx_dbdma_stop(u32 chanid)
+void au1xxx_dbdma_stop(u32 chanid)
 {
        chan_tab_t      *ctp;
        au1x_dma_chan_t *cp;
@@ -743,7 +731,7 @@ au1xxx_dbdma_stop(u32 chanid)
                udelay(1);
                halt_timeout++;
                if (halt_timeout > 100) {
-                       printk("warning: DMA channel won't halt\n");
+                       printk(KERN_WARNING "warning: DMA channel won't halt\n");
                        break;
                }
        }
@@ -753,12 +741,12 @@ au1xxx_dbdma_stop(u32 chanid)
 }
 EXPORT_SYMBOL(au1xxx_dbdma_stop);
 
-/* Start using the current descriptor pointer.  If the dbdma encounters
- * a not valid descriptor, it will stop.  In this case, we can just
+/*
+ * Start using the current descriptor pointer.  If the DBDMA encounters
+ * a non-valid descriptor, it will stop.  In this case, we can just
  * continue by adding a buffer to the list and starting again.
  */
-void
-au1xxx_dbdma_start(u32 chanid)
+void au1xxx_dbdma_start(u32 chanid)
 {
        chan_tab_t      *ctp;
        au1x_dma_chan_t *cp;
@@ -773,8 +761,7 @@ au1xxx_dbdma_start(u32 chanid)
 }
 EXPORT_SYMBOL(au1xxx_dbdma_start);
 
-void
-au1xxx_dbdma_reset(u32 chanid)
+void au1xxx_dbdma_reset(u32 chanid)
 {
        chan_tab_t              *ctp;
        au1x_ddma_desc_t        *dp;
@@ -784,14 +771,14 @@ au1xxx_dbdma_reset(u32 chanid)
        ctp = *((chan_tab_t **)chanid);
        ctp->get_ptr = ctp->put_ptr = ctp->cur_ptr = ctp->chan_desc_base;
 
-       /* Run through the descriptors and reset the valid indicator.
-       */
+       /* Run through the descriptors and reset the valid indicator. */
        dp = ctp->chan_desc_base;
 
        do {
                dp->dscr_cmd0 &= ~DSCR_CMD0_V;
-               /* reset our SW status -- this is used to determine
-                * if a descriptor is in use by upper level SW. Since
+               /*
+                * Reset our software status -- this is used to determine
+                * if a descriptor is in use by upper level software. Since
                 * posting can reset 'V' bit.
                 */
                dp->sw_status = 0;
@@ -800,8 +787,7 @@ au1xxx_dbdma_reset(u32 chanid)
 }
 EXPORT_SYMBOL(au1xxx_dbdma_reset);
 
-u32
-au1xxx_get_dma_residue(u32 chanid)
+u32 au1xxx_get_dma_residue(u32 chanid)
 {
        chan_tab_t      *ctp;
        au1x_dma_chan_t *cp;
@@ -810,18 +796,15 @@ au1xxx_get_dma_residue(u32 chanid)
        ctp = *((chan_tab_t **)chanid);
        cp = ctp->chan_ptr;
 
-       /* This is only valid if the channel is stopped.
-       */
+       /* This is only valid if the channel is stopped. */
        rv = cp->ddma_bytecnt;
        au_sync();
 
        return rv;
 }
-
 EXPORT_SYMBOL_GPL(au1xxx_get_dma_residue);
 
-void
-au1xxx_dbdma_chan_free(u32 chanid)
+void au1xxx_dbdma_chan_free(u32 chanid)
 {
        chan_tab_t      *ctp;
        dbdev_tab_t     *stp, *dtp;
@@ -842,8 +825,7 @@ au1xxx_dbdma_chan_free(u32 chanid)
 }
 EXPORT_SYMBOL(au1xxx_dbdma_chan_free);
 
-static irqreturn_t
-dbdma_interrupt(int irq, void *dev_id)
+static irqreturn_t dbdma_interrupt(int irq, void *dev_id)
 {
        u32 intstat;
        u32 chan_index;
@@ -859,13 +841,12 @@ dbdma_interrupt(int irq, void *dev_id)
        cp = ctp->chan_ptr;
        dp = ctp->cur_ptr;
 
-       /* Reset interrupt.
-       */
+       /* Reset interrupt. */
        cp->ddma_irq = 0;
        au_sync();
 
        if (ctp->chan_callback)
-               (ctp->chan_callback)(irq, ctp->chan_callparam);
+               ctp->chan_callback(irq, ctp->chan_callparam);
 
        ctp->cur_ptr = phys_to_virt(DSCR_GET_NXTPTR(dp->dscr_nxtptr));
        return IRQ_RETVAL(1);
@@ -890,47 +871,47 @@ static void au1xxx_dbdma_init(void)
 
        if (request_irq(irq_nr, dbdma_interrupt, IRQF_DISABLED,
                        "Au1xxx dbdma", (void *)dbdma_gptr))
-               printk("Can't get 1550 dbdma irq");
+               printk(KERN_ERR "Can't get 1550 dbdma irq");
 }
 
-void
-au1xxx_dbdma_dump(u32 chanid)
+void au1xxx_dbdma_dump(u32 chanid)
 {
-       chan_tab_t              *ctp;
-       au1x_ddma_desc_t        *dp;
-       dbdev_tab_t             *stp, *dtp;
-       au1x_dma_chan_t *cp;
-               u32                     i = 0;
+       chan_tab_t       *ctp;
+       au1x_ddma_desc_t *dp;
+       dbdev_tab_t      *stp, *dtp;
+       au1x_dma_chan_t  *cp;
+       u32 i            = 0;
 
        ctp = *((chan_tab_t **)chanid);
        stp = ctp->chan_src;
        dtp = ctp->chan_dest;
        cp = ctp->chan_ptr;
 
-       printk("Chan %x, stp %x (dev %d)  dtp %x (dev %d) \n",
-               (u32)ctp, (u32)stp, stp - dbdev_tab, (u32)dtp, dtp - dbdev_tab);
-       printk("desc base %x, get %x, put %x, cur %x\n",
-               (u32)(ctp->chan_desc_base), (u32)(ctp->get_ptr),
-               (u32)(ctp->put_ptr), (u32)(ctp->cur_ptr));
-
-       printk("dbdma chan %x\n", (u32)cp);
-       printk("cfg %08x, desptr %08x, statptr %08x\n",
-               cp->ddma_cfg, cp->ddma_desptr, cp->ddma_statptr);
-       printk("dbell %08x, irq %08x, stat %08x, bytecnt %08x\n",
-               cp->ddma_dbell, cp->ddma_irq, cp->ddma_stat, cp->ddma_bytecnt);
-
-
-       /* Run through the descriptors
-       */
+       printk(KERN_DEBUG "Chan %x, stp %x (dev %d)  dtp %x (dev %d) \n",
+                         (u32)ctp, (u32)stp, stp - dbdev_tab, (u32)dtp,
+                         dtp - dbdev_tab);
+       printk(KERN_DEBUG "desc base %x, get %x, put %x, cur %x\n",
+                         (u32)(ctp->chan_desc_base), (u32)(ctp->get_ptr),
+                         (u32)(ctp->put_ptr), (u32)(ctp->cur_ptr));
+
+       printk(KERN_DEBUG "dbdma chan %x\n", (u32)cp);
+       printk(KERN_DEBUG "cfg %08x, desptr %08x, statptr %08x\n",
+                         cp->ddma_cfg, cp->ddma_desptr, cp->ddma_statptr);
+       printk(KERN_DEBUG "dbell %08x, irq %08x, stat %08x, bytecnt %08x\n",
+                         cp->ddma_dbell, cp->ddma_irq, cp->ddma_stat,
+                         cp->ddma_bytecnt);
+
+       /* Run through the descriptors */
        dp = ctp->chan_desc_base;
 
        do {
-                printk("Dp[%d]= %08x, cmd0 %08x, cmd1 %08x\n",
-                        i++, (u32)dp, dp->dscr_cmd0, dp->dscr_cmd1);
-                printk("src0 %08x, src1 %08x, dest0 %08x, dest1 %08x\n",
-                        dp->dscr_source0, dp->dscr_source1, dp->dscr_dest0, dp->dscr_dest1);
-                printk("stat %08x, nxtptr %08x\n",
-                        dp->dscr_stat, dp->dscr_nxtptr);
+               printk(KERN_DEBUG "Dp[%d]= %08x, cmd0 %08x, cmd1 %08x\n",
+                                 i++, (u32)dp, dp->dscr_cmd0, dp->dscr_cmd1);
+               printk(KERN_DEBUG "src0 %08x, src1 %08x, dest0 %08x, dest1 %08x\n",
+                                 dp->dscr_source0, dp->dscr_source1,
+                                 dp->dscr_dest0, dp->dscr_dest1);
+               printk(KERN_DEBUG "stat %08x, nxtptr %08x\n",
+                                 dp->dscr_stat, dp->dscr_nxtptr);
                dp = phys_to_virt(DSCR_GET_NXTPTR(dp->dscr_nxtptr));
        } while (dp != ctp->chan_desc_base);
 }
@@ -938,32 +919,33 @@ au1xxx_dbdma_dump(u32 chanid)
 /* Put a descriptor into the DMA ring.
  * This updates the source/destination pointers and byte count.
  */
-u32
-au1xxx_dbdma_put_dscr(u32 chanid, au1x_ddma_desc_t *dscr )
+u32 au1xxx_dbdma_put_dscr(u32 chanid, au1x_ddma_desc_t *dscr)
 {
        chan_tab_t *ctp;
        au1x_ddma_desc_t *dp;
-       u32 nbytes=0;
+       u32 nbytes = 0;
 
-       /* I guess we could check this to be within the
-       * range of the table......
-       */
+       /*
+        * I guess we could check this to be within the
+        * range of the table......
+        */
        ctp = *((chan_tab_t **)chanid);
 
-       /* We should have multiple callers for a particular channel,
-       * an interrupt doesn't affect this pointer nor the descriptor,
-       * so no locking should be needed.
-       */
+       /*
+        * We should have multiple callers for a particular channel,
+        * an interrupt doesn't affect this pointer nor the descriptor,
+        * so no locking should be needed.
+        */
        dp = ctp->put_ptr;
 
-       /* If the descriptor is valid, we are way ahead of the DMA
-       * engine, so just return an error condition.
-       */
+       /*
+        * If the descriptor is valid, we are way ahead of the DMA
+        * engine, so just return an error condition.
+        */
        if (dp->dscr_cmd0 & DSCR_CMD0_V)
                return 0;
 
-       /* Load up buffer addresses and byte count.
-       */
+       /* Load up buffer addresses and byte count. */
        dp->dscr_dest0 = dscr->dscr_dest0;
        dp->dscr_source0 = dscr->dscr_source0;
        dp->dscr_dest1 = dscr->dscr_dest1;
@@ -975,14 +957,11 @@ au1xxx_dbdma_put_dscr(u32 chanid, au1x_ddma_desc_t *dscr )
        dp->dscr_cmd0 |= dscr->dscr_cmd0 | DSCR_CMD0_V;
        ctp->chan_ptr->ddma_dbell = 0;
 
-       /* Get next descriptor pointer.
-       */
+       /* Get next descriptor pointer. */
        ctp->put_ptr = phys_to_virt(DSCR_GET_NXTPTR(dp->dscr_nxtptr));
 
-       /* return something not zero.
-       */
+       /* Return something non-zero. */
        return nbytes;
 }
 
 #endif /* defined(CONFIG_SOC_AU1550) || defined(CONFIG_SOC_AU1200) */
-
index eae1bb2ca26e72ab115c35e97030fbe52a5d877a..af5be7df2f2a9f379d9c0a06125d20542479029b 100644 (file)
@@ -1,3 +1,4 @@
+#include <linux/types.h>
 
 #include <asm/mach-au1x00/au1000.h>
 
@@ -8,12 +9,6 @@
  * uart to be used for debugging.
  */
 #define DEBUG_BASE  UART_DEBUG_BASE
-/**/
-
-/* we need uint32 uint8 */
-/* #include "types.h" */
-typedef         unsigned char uint8;
-typedef         unsigned int  uint32;
 
 #define         UART16550_BAUD_2400             2400
 #define         UART16550_BAUD_4800             4800
@@ -51,17 +46,15 @@ typedef         unsigned int  uint32;
 #define UART_MOD_CNTRL 0x100   /* Module Control */
 
 /* memory-mapped read/write of the port */
-#define UART16550_READ(y)    (au_readl(DEBUG_BASE + y) & 0xff)
-#define UART16550_WRITE(y, z) (au_writel(z&0xff, DEBUG_BASE + y))
+#define UART16550_READ(y)     (au_readl(DEBUG_BASE + y) & 0xff)
+#define UART16550_WRITE(y, z) (au_writel(z & 0xff, DEBUG_BASE + y))
 
 extern unsigned long calc_clock(void);
 
-void debugInit(uint32 baud, uint8 data, uint8 parity, uint8 stop)
+void debugInit(u32 baud, u8 data, u8 parity, u8 stop)
 {
-
-       if (UART16550_READ(UART_MOD_CNTRL) != 0x3) {
+       if (UART16550_READ(UART_MOD_CNTRL) != 0x3)
                UART16550_WRITE(UART_MOD_CNTRL, 3);
-       }
        calc_clock();
 
        /* disable interrupts */
@@ -69,7 +62,7 @@ void debugInit(uint32 baud, uint8 data, uint8 parity, uint8 stop)
 
        /* set up baud rate */
        {
-               uint32 divisor;
+               u32 divisor;
 
                /* set divisor */
                divisor = get_au1x00_uart_baud_base() / baud;
@@ -80,9 +73,9 @@ void debugInit(uint32 baud, uint8 data, uint8 parity, uint8 stop)
        UART16550_WRITE(UART_LCR, (data | parity | stop));
 }
 
-static int remoteDebugInitialized = 0;
+static int remoteDebugInitialized;
 
-uint8 getDebugChar(void)
+u8 getDebugChar(void)
 {
        if (!remoteDebugInitialized) {
                remoteDebugInitialized = 1;
@@ -92,15 +85,13 @@ uint8 getDebugChar(void)
                          UART16550_STOP_1BIT);
        }
 
-       while((UART16550_READ(UART_LSR) & 0x1) == 0);
+       while ((UART16550_READ(UART_LSR) & 0x1) == 0);
        return UART16550_READ(UART_RX);
 }
 
 
-int putDebugChar(uint8 byte)
+int putDebugChar(u8 byte)
 {
-//     int i;
-
        if (!remoteDebugInitialized) {
                remoteDebugInitialized = 1;
                debugInit(UART16550_BAUD_115200,
@@ -109,9 +100,8 @@ int putDebugChar(uint8 byte)
                          UART16550_STOP_1BIT);
        }
 
-       while ((UART16550_READ(UART_LSR)&0x40) == 0);
+       while ((UART16550_READ(UART_LSR) & 0x40) == 0);
        UART16550_WRITE(UART_TX, byte);
-       //for (i=0;i<0xfff;i++);
 
        return 1;
 }
index 95f69ea146e90a49d5ffdca4605af5fbb64df99e..d6fbda232e6ae5b8cdf92eee346dbdae091fe1f2 100644 (file)
@@ -1,12 +1,11 @@
 /*
  *
  * BRIEF MODULE DESCRIPTION
- *      A DMA channel allocator for Au1000. API is modeled loosely off of
+ *      A DMA channel allocator for Au1x00. API is modeled loosely off of
  *      linux/kernel/dma.c.
  *
- * Copyright 2000 MontaVista Software Inc.
- * Author: MontaVista Software, Inc.
- *             stevel@mvista.com or source@mvista.com
+ * Copyright 2000, 2008 MontaVista Software Inc.
+ * Author: MontaVista Software, Inc. <source@mvista.com>
  * Copyright (C) 2005 Ralf Baechle (ralf@linux-mips.org)
  *
  *  This program is free software; you can redistribute  it and/or modify it
@@ -39,7 +38,8 @@
 #include <asm/mach-au1x00/au1000.h>
 #include <asm/mach-au1x00/au1000_dma.h>
 
-#if defined(CONFIG_SOC_AU1000) || defined(CONFIG_SOC_AU1500) || defined(CONFIG_SOC_AU1100)
+#if defined(CONFIG_SOC_AU1000) || defined(CONFIG_SOC_AU1500) || \
+    defined(CONFIG_SOC_AU1100)
 /*
  * A note on resource allocation:
  *
@@ -56,7 +56,6 @@
  * returned from request_dma.
  */
 
-
 DEFINE_SPINLOCK(au1000_dma_spin_lock);
 
 struct dma_chan au1000_dma_table[NUM_AU1000_DMA_CHANNELS] = {
@@ -71,7 +70,7 @@ struct dma_chan au1000_dma_table[NUM_AU1000_DMA_CHANNELS] = {
 };
 EXPORT_SYMBOL(au1000_dma_table);
 
-// Device FIFO addresses and default DMA modes
+/* Device FIFO addresses and default DMA modes */
 static const struct dma_dev {
        unsigned int fifo_addr;
        unsigned int dma_mode;
@@ -80,8 +79,8 @@ static const struct dma_dev {
        {UART0_ADDR + UART_RX, 0},
        {0, 0},
        {0, 0},
-       {AC97C_DATA, DMA_DW16 },          // coherent
-       {AC97C_DATA, DMA_DR | DMA_DW16 }, // coherent
+       {AC97C_DATA, DMA_DW16 },          /* coherent */
+       {AC97C_DATA, DMA_DR | DMA_DW16 }, /* coherent */
        {UART3_ADDR + UART_TX, DMA_DW8 | DMA_NC},
        {UART3_ADDR + UART_RX, DMA_DR | DMA_DW8 | DMA_NC},
        {USBD_EP0RD, DMA_DR | DMA_DW8 | DMA_NC},
@@ -101,10 +100,10 @@ int au1000_dma_read_proc(char *buf, char **start, off_t fpos,
        struct dma_chan *chan;
 
        for (i = 0; i < NUM_AU1000_DMA_CHANNELS; i++) {
-               if ((chan = get_dma_chan(i)) != NULL) {
+               chan = get_dma_chan(i);
+               if (chan != NULL)
                        len += sprintf(buf + len, "%2d: %s\n",
                                       i, chan->dev_str);
-               }
        }
 
        if (fpos >= len) {
@@ -113,18 +112,19 @@ int au1000_dma_read_proc(char *buf, char **start, off_t fpos,
                return 0;
        }
        *start = buf + fpos;
-       if ((len -= fpos) > length)
+       len -= fpos;
+       if (len > length)
                return length;
        *eof = 1;
        return len;
 }
 
-// Device FIFO addresses and default DMA modes - 2nd bank
+/* Device FIFO addresses and default DMA modes - 2nd bank */
 static const struct dma_dev dma_dev_table_bank2[DMA_NUM_DEV_BANK2] = {
-       {SD0_XMIT_FIFO, DMA_DS | DMA_DW8},              // coherent
-       {SD0_RECV_FIFO, DMA_DS | DMA_DR | DMA_DW8},     // coherent
-       {SD1_XMIT_FIFO, DMA_DS | DMA_DW8},              // coherent
-       {SD1_RECV_FIFO, DMA_DS | DMA_DR | DMA_DW8}      // coherent
+       { SD0_XMIT_FIFO, DMA_DS | DMA_DW8 },            /* coherent */
+       { SD0_RECV_FIFO, DMA_DS | DMA_DR | DMA_DW8 },   /* coherent */
+       { SD1_XMIT_FIFO, DMA_DS | DMA_DW8 },            /* coherent */
+       { SD1_RECV_FIFO, DMA_DS | DMA_DR | DMA_DW8 }    /* coherent */
 };
 
 void dump_au1000_dma_channel(unsigned int dmanr)
@@ -150,7 +150,6 @@ void dump_au1000_dma_channel(unsigned int dmanr)
               au_readl(chan->io + DMA_BUFFER1_COUNT));
 }
 
-
 /*
  * Finds a free channel, and binds the requested device to it.
  * Returns the allocated channel number, or negative on error.
@@ -169,14 +168,14 @@ int request_au1000_dma(int dev_id, const char *dev_str,
        if (dev_id < 0 || dev_id >= (DMA_NUM_DEV + DMA_NUM_DEV_BANK2))
                return -EINVAL;
 #else
-       if (dev_id < 0 || dev_id >= DMA_NUM_DEV)
+       if (dev_id < 0 || dev_id >= DMA_NUM_DEV)
                return -EINVAL;
 #endif
 
-       for (i = 0; i < NUM_AU1000_DMA_CHANNELS; i++) {
+       for (i = 0; i < NUM_AU1000_DMA_CHANNELS; i++)
                if (au1000_dma_table[i].dev_id < 0)
                        break;
-       }
+
        if (i == NUM_AU1000_DMA_CHANNELS)
                return -ENODEV;
 
@@ -185,15 +184,15 @@ int request_au1000_dma(int dev_id, const char *dev_str,
        if (dev_id >= DMA_NUM_DEV) {
                dev_id -= DMA_NUM_DEV;
                dev = &dma_dev_table_bank2[dev_id];
-       } else {
+       } else
                dev = &dma_dev_table[dev_id];
-       }
 
        if (irqhandler) {
                chan->irq = AU1000_DMA_INT_BASE + i;
                chan->irq_dev = irq_dev_id;
-               if ((ret = request_irq(chan->irq, irqhandler, irqflags,
-                                      dev_str, chan->irq_dev))) {
+               ret = request_irq(chan->irq, irqhandler, irqflags, dev_str,
+                                 chan->irq_dev);
+               if (ret) {
                        chan->irq = 0;
                        chan->irq_dev = NULL;
                        return ret;
@@ -203,7 +202,7 @@ int request_au1000_dma(int dev_id, const char *dev_str,
                chan->irq_dev = NULL;
        }
 
-       // fill it in
+       /* fill it in */
        chan->io = DMA_CHANNEL_BASE + i * DMA_CHANNEL_LEN;
        chan->dev_id = dev_id;
        chan->dev_str = dev_str;
@@ -220,8 +219,9 @@ EXPORT_SYMBOL(request_au1000_dma);
 void free_au1000_dma(unsigned int dmanr)
 {
        struct dma_chan *chan = get_dma_chan(dmanr);
+
        if (!chan) {
-               printk("Trying to free DMA%d\n", dmanr);
+               printk(KERN_ERR "Error trying to free DMA%d\n", dmanr);
                return;
        }
 
@@ -235,4 +235,4 @@ void free_au1000_dma(unsigned int dmanr)
 }
 EXPORT_SYMBOL(free_au1000_dma);
 
-#endif // AU1000 AU1500 AU1100
+#endif /* AU1000 AU1500 AU1100 */
index 52545258997157c5bd849f637ca7acef02a8a4fd..b485d94ce8a5055d4e28b35f8dec1c7fc3b2af9e 100644 (file)
@@ -69,7 +69,7 @@ static int au1xxx_gpio2_direction_output(unsigned gpio, int value)
 
 static int au1xxx_gpio1_read(unsigned gpio)
 {
-       return ((gpio1->pinstaterd >> gpio) & 0x01);
+       return (gpio1->pinstaterd >> gpio) & 0x01;
 }
 
 static void au1xxx_gpio1_write(unsigned gpio, int value)
@@ -104,7 +104,6 @@ int au1xxx_gpio_get_value(unsigned gpio)
        else
                return au1xxx_gpio1_read(gpio);
 }
-
 EXPORT_SYMBOL(au1xxx_gpio_get_value);
 
 void au1xxx_gpio_set_value(unsigned gpio, int value)
@@ -118,7 +117,6 @@ void au1xxx_gpio_set_value(unsigned gpio, int value)
        else
                au1xxx_gpio1_write(gpio, value);
 }
-
 EXPORT_SYMBOL(au1xxx_gpio_set_value);
 
 int au1xxx_gpio_direction_input(unsigned gpio)
@@ -132,7 +130,6 @@ int au1xxx_gpio_direction_input(unsigned gpio)
 
        return au1xxx_gpio1_direction_input(gpio);
 }
-
 EXPORT_SYMBOL(au1xxx_gpio_direction_input);
 
 int au1xxx_gpio_direction_output(unsigned gpio, int value)
@@ -146,5 +143,4 @@ int au1xxx_gpio_direction_output(unsigned gpio, int value)
 
        return au1xxx_gpio1_direction_output(gpio, value);
 }
-
 EXPORT_SYMBOL(au1xxx_gpio_direction_output);
index f0626992fd75fce7b4f735d91c9db199ccdaba55..40c6ceceb5f9149f4f5a352c504cb6301b22a6fc 100644 (file)
@@ -210,10 +210,8 @@ static inline void mask_and_ack_either_edge_irq(unsigned int irq_nr)
        au_sync();
 }
 
-
 static inline void mask_and_ack_level_irq(unsigned int irq_nr)
 {
-
        local_disable_irq(irq_nr);
        au_sync();
 #if defined(CONFIG_MIPS_PB1000)
@@ -263,14 +261,14 @@ void restore_local_and_enable(int controller, unsigned long mask)
        unsigned long flags, new_mask;
 
        spin_lock_irqsave(&irq_lock, flags);
-       for (i = 0; i < 32; i++) {
+       for (i = 0; i < 32; i++)
                if (mask & (1 << i)) {
                        if (controller)
                                local_enable_irq(i + 32);
                        else
                                local_enable_irq(i);
                }
-       }
+
        if (controller)
                new_mask = au_readl(IC1_MASKSET);
        else
index 7e966b31e3e1e2a383eaff451ba6b572aa2e2592..7866cf50cf99ce7ca5943a8f5a1a9217375d9ea4 100644 (file)
@@ -2,9 +2,8 @@
  * BRIEF MODULE DESCRIPTION
  *     Alchemy/AMD Au1x00 PCI support.
  *
- * Copyright 2001-2003, 2007 MontaVista Software Inc.
- * Author: MontaVista Software, Inc.
- *             ppopov@mvista.com or source@mvista.com
+ * Copyright 2001-2003, 2007-2008 MontaVista Software Inc.
+ * Author: MontaVista Software, Inc. <source@mvista.com>
  *
  * Copyright (C) 2004 by Ralf Baechle (ralf@linux-mips.org)
  *
@@ -86,9 +85,9 @@ static int __init au1x_pci_setup(void)
                u32 prid = read_c0_prid();
 
                if ((prid & 0xFF000000) == 0x01000000 && prid < 0x01030202) {
-                      au_writel((1 << 16) | au_readl(Au1500_PCI_CFG),
-                                Au1500_PCI_CFG);
-                      printk("Non-coherent PCI accesses enabled\n");
+                       au_writel((1 << 16) | au_readl(Au1500_PCI_CFG),
+                                 Au1500_PCI_CFG);
+                       printk(KERN_INFO "Non-coherent PCI accesses enabled\n");
                }
        }
 #endif
index 31d2a2270878832354a02e4cd7f6b4b6eaf03516..8cae7753ef79931612eb5070e2236014df07fe78 100644 (file)
@@ -269,8 +269,8 @@ static struct platform_device au1x00_pcmcia_device = {
 #ifdef SMBUS_PSC_BASE
 static struct resource pbdb_smbus_resources[] = {
        {
-               .start  = SMBUS_PSC_BASE,
-               .end    = SMBUS_PSC_BASE + 0x24 - 1,
+               .start  = CPHYSADDR(SMBUS_PSC_BASE),
+               .end    = CPHYSADDR(SMBUS_PSC_BASE + 0xfffff),
                .flags  = IORESOURCE_MEM,
        },
 };
@@ -302,16 +302,17 @@ static struct platform_device *au1xxx_platform_devices[] __initdata = {
 #endif
 };
 
-int __init au1xxx_platform_init(void)
+static int __init au1xxx_platform_init(void)
 {
        unsigned int uartclk = get_au1x00_uart_baud_base() * 16;
        int i;
 
        /* Fill up uartclk. */
-       for (i = 0; au1x00_uart_data[i].flags ; i++)
+       for (i = 0; au1x00_uart_data[i].flags; i++)
                au1x00_uart_data[i].uartclk = uartclk;
 
-       return platform_add_devices(au1xxx_platform_devices, ARRAY_SIZE(au1xxx_platform_devices));
+       return platform_add_devices(au1xxx_platform_devices,
+                                   ARRAY_SIZE(au1xxx_platform_devices));
 }
 
 arch_initcall(au1xxx_platform_init);
index a8cd2c1b9e1b59f313ae98a0c6e8579e0afc6dca..2166b9e1e80cf4fe1fe3452a4db5f8f852662005 100644 (file)
@@ -1,10 +1,9 @@
 /*
  * BRIEF MODULE DESCRIPTION
- *     Au1000 Power Management routines.
+ *     Au1xx0 Power Management routines.
  *
- * Copyright 2001 MontaVista Software Inc.
- * Author: MontaVista Software, Inc.
- *             ppopov@mvista.com or source@mvista.com
+ * Copyright 2001, 2008 MontaVista Software Inc.
+ * Author: MontaVista Software, Inc. <source@mvista.com>
  *
  *  Some of the routines are right out of init/main.c, whose
  *  copyrights apply here.
 #ifdef CONFIG_PM
 
 #define DEBUG 1
-#ifdef DEBUG
-#  define DPRINTK(fmt, args...)        printk("%s: " fmt, __func__, ## args)
+#ifdef DEBUG
+#define DPRINTK(fmt, args...)  printk(KERN_DEBUG "%s: " fmt, __func__, ## args)
 #else
-#  define DPRINTK(fmt, args...)
+#define DPRINTK(fmt, args...)
 #endif
 
 static void au1000_calibrate_delay(void);
@@ -57,7 +56,8 @@ extern void local_enable_irq(unsigned int irq_nr);
 
 static DEFINE_SPINLOCK(pm_lock);
 
-/* We need to save/restore a bunch of core registers that are
+/*
+ * We need to save/restore a bunch of core registers that are
  * either volatile or reset to some state across a processor sleep.
  * If reading a register doesn't provide a proper result for a
  * later restore, we have to provide a function for loading that
@@ -78,24 +78,25 @@ static unsigned int sleep_usbhost_enable;
 static unsigned int    sleep_usbdev_enable;
 static unsigned int    sleep_static_memctlr[4][3];
 
-/* Define this to cause the value you write to /proc/sys/pm/sleep to
+/*
+ * Define this to cause the value you write to /proc/sys/pm/sleep to
  * set the TOY timer for the amount of time you want to sleep.
  * This is done mainly for testing, but may be useful in other cases.
  * The value is number of 32KHz ticks to sleep.
  */
 #define SLEEP_TEST_TIMEOUT 1
-#ifdef SLEEP_TEST_TIMEOUT
-static int     sleep_ticks;
+#ifdef SLEEP_TEST_TIMEOUT
+static int sleep_ticks;
 void wakeup_counter0_set(int ticks);
 #endif
 
-static void
-save_core_regs(void)
+static void save_core_regs(void)
 {
        extern void save_au1xxx_intctl(void);
        extern void pm_eth0_shutdown(void);
 
-       /* Do the serial ports.....these really should be a pm_*
+       /*
+        * Do the serial ports.....these really should be a pm_*
         * registered function by the driver......but of course the
         * standard serial driver doesn't understand our Au1xxx
         * unique registers.
@@ -106,27 +107,24 @@ save_core_regs(void)
        sleep_uart0_clkdiv = au_readl(UART0_ADDR + UART_CLK);
        sleep_uart0_enable = au_readl(UART0_ADDR + UART_MOD_CNTRL);
 
-       /* Shutdown USB host/device.
-       */
+       /* Shutdown USB host/device. */
        sleep_usbhost_enable = au_readl(USB_HOST_CONFIG);
 
-       /* There appears to be some undocumented reset register....
-       */
+       /* There appears to be some undocumented reset register.... */
        au_writel(0, 0xb0100004); au_sync();
        au_writel(0, USB_HOST_CONFIG); au_sync();
 
        sleep_usbdev_enable = au_readl(USBD_ENABLE);
        au_writel(0, USBD_ENABLE); au_sync();
 
-       /* Save interrupt controller state.
-       */
+       /* Save interrupt controller state. */
        save_au1xxx_intctl();
 
-       /* Clocks and PLLs.
-       */
+       /* Clocks and PLLs. */
        sleep_aux_pll_cntrl = au_readl(SYS_AUXPLL);
 
-       /* We don't really need to do this one, but unless we
+       /*
+        * We don't really need to do this one, but unless we
         * write it again it won't have a valid value if we
         * happen to read it.
         */
@@ -134,8 +132,7 @@ save_core_regs(void)
 
        sleep_pin_function = au_readl(SYS_PINFUNC);
 
-       /* Save the static memory controller configuration.
-       */
+       /* Save the static memory controller configuration. */
        sleep_static_memctlr[0][0] = au_readl(MEM_STCFG0);
        sleep_static_memctlr[0][1] = au_readl(MEM_STTIME0);
        sleep_static_memctlr[0][2] = au_readl(MEM_STADDR0);
@@ -150,8 +147,7 @@ save_core_regs(void)
        sleep_static_memctlr[3][2] = au_readl(MEM_STADDR3);
 }
 
-static void
-restore_core_regs(void)
+static void restore_core_regs(void)
 {
        extern void restore_au1xxx_intctl(void);
        extern void wakeup_counter0_adjust(void);
@@ -160,8 +156,7 @@ restore_core_regs(void)
        au_writel(sleep_cpu_pll_cntrl, SYS_CPUPLL); au_sync();
        au_writel(sleep_pin_function, SYS_PINFUNC); au_sync();
 
-       /* Restore the static memory controller configuration.
-       */
+       /* Restore the static memory controller configuration. */
        au_writel(sleep_static_memctlr[0][0], MEM_STCFG0);
        au_writel(sleep_static_memctlr[0][1], MEM_STTIME0);
        au_writel(sleep_static_memctlr[0][2], MEM_STADDR0);
@@ -175,7 +170,8 @@ restore_core_regs(void)
        au_writel(sleep_static_memctlr[3][1], MEM_STTIME3);
        au_writel(sleep_static_memctlr[3][2], MEM_STADDR3);
 
-       /* Enable the UART if it was enabled before sleep.
+       /*
+        * Enable the UART if it was enabled before sleep.
         * I guess I should define module control bits........
         */
        if (sleep_uart0_enable & 0x02) {
@@ -202,7 +198,7 @@ void wakeup_from_suspend(void)
 int au_sleep(void)
 {
        unsigned long wakeup, flags;
-       extern  void    save_and_sleep(void);
+       extern void save_and_sleep(void);
 
        spin_lock_irqsave(&pm_lock, flags);
 
@@ -210,23 +206,22 @@ int au_sleep(void)
 
        flush_cache_all();
 
-       /** The code below is all system dependent and we should probably
+       /**
+        ** The code below is all system dependent and we should probably
         ** have a function call out of here to set this up.  You need
         ** to configure the GPIO or timer interrupts that will bring
         ** you out of sleep.
         ** For testing, the TOY counter wakeup is useful.
         **/
-
 #if 0
        au_writel(au_readl(SYS_PINSTATERD) & ~(1 << 11), SYS_PINSTATERD);
 
-       /* gpio 6 can cause a wake up event */
+       /* GPIO 6 can cause a wake up event */
        wakeup = au_readl(SYS_WAKEMSK);
        wakeup &= ~(1 << 8);    /* turn off match20 wakeup */
-       wakeup |= 1 << 6;       /* turn on gpio 6 wakeup   */
+       wakeup |= 1 << 6;       /* turn on  GPIO  6 wakeup */
 #else
-       /* For testing, allow match20 to wake us up.
-       */
+       /* For testing, allow match20 to wake us up. */
 #ifdef SLEEP_TEST_TIMEOUT
        wakeup_counter0_set(sleep_ticks);
 #endif
@@ -240,7 +235,8 @@ int au_sleep(void)
 
        save_and_sleep();
 
-       /* after a wakeup, the cpu vectors back to 0x1fc00000 so
+       /*
+        * After a wakeup, the cpu vectors back to 0x1fc00000, so
         * it's up to the boot code to get us back here.
         */
        restore_core_regs();
@@ -248,24 +244,22 @@ int au_sleep(void)
        return 0;
 }
 
-static int pm_do_sleep(ctl_table * ctl, int write, struct file *file,
-                      void __user *buffer, size_t * len, loff_t *ppos)
+static int pm_do_sleep(ctl_table *ctl, int write, struct file *file,
+                      void __user *buffer, size_t *len, loff_t *ppos)
 {
 #ifdef SLEEP_TEST_TIMEOUT
 #define TMPBUFLEN2 16
        char buf[TMPBUFLEN2], *p;
 #endif
 
-       if (!write) {
+       if (!write)
                *len = 0;
-       else {
+       else {
 #ifdef SLEEP_TEST_TIMEOUT
-               if (*len > TMPBUFLEN2 - 1) {
+               if (*len > TMPBUFLEN2 - 1)
                        return -EFAULT;
-               }
-               if (copy_from_user(buf, buffer, *len)) {
+               if (copy_from_user(buf, buffer, *len))
                        return -EFAULT;
-               }
                buf[*len] = 0;
                p = buf;
                sleep_ticks = simple_strtoul(p, &p, 0);
@@ -276,8 +270,8 @@ static int pm_do_sleep(ctl_table * ctl, int write, struct file *file,
        return 0;
 }
 
-static int pm_do_freq(ctl_table * ctl, int write, struct file *file,
-                     void __user *buffer, size_t * len, loff_t *ppos)
+static int pm_do_freq(ctl_table *ctl, int write, struct file *file,
+                     void __user *buffer, size_t *len, loff_t *ppos)
 {
        int retval = 0, i;
        unsigned long val, pll;
@@ -285,14 +279,14 @@ static int pm_do_freq(ctl_table * ctl, int write, struct file *file,
 #define MAX_CPU_FREQ 396
        char buf[TMPBUFLEN], *p;
        unsigned long flags, intc0_mask, intc1_mask;
-       unsigned long old_baud_base, old_cpu_freq, baud_rate, old_clk,
-           old_refresh;
+       unsigned long old_baud_base, old_cpu_freq, old_clk, old_refresh;
        unsigned long new_baud_base, new_cpu_freq, new_clk, new_refresh;
+       unsigned long baud_rate;
 
        spin_lock_irqsave(&pm_lock, flags);
-       if (!write) {
+       if (!write)
                *len = 0;
-       else {
+       else {
                /* Parse the new frequency */
                if (*len > TMPBUFLEN - 1) {
                        spin_unlock_irqrestore(&pm_lock, flags);
@@ -312,7 +306,7 @@ static int pm_do_freq(ctl_table * ctl, int write, struct file *file,
 
                pll = val / 12;
                if ((pll > 33) || (pll < 7)) {  /* 396 MHz max, 84 MHz min */
-                       /* revisit this for higher speed cpus */
+                       /* Revisit this for higher speed CPUs */
                        spin_unlock_irqrestore(&pm_lock, flags);
                        return -EFAULT;
                }
@@ -321,30 +315,28 @@ static int pm_do_freq(ctl_table * ctl, int write, struct file *file,
                old_cpu_freq = get_au1x00_speed();
 
                new_cpu_freq = pll * 12 * 1000000;
-               new_baud_base =  (new_cpu_freq / (2 * ((int)(au_readl(SYS_POWERCTRL)&0x03) + 2) * 16));
+               new_baud_base = (new_cpu_freq / (2 * ((int)(au_readl(SYS_POWERCTRL)
+                                                           & 0x03) + 2) * 16));
                set_au1x00_speed(new_cpu_freq);
                set_au1x00_uart_baud_base(new_baud_base);
 
                old_refresh = au_readl(MEM_SDREFCFG) & 0x1ffffff;
-               new_refresh =
-                   ((old_refresh * new_cpu_freq) /
-                    old_cpu_freq) | (au_readl(MEM_SDREFCFG) & ~0x1ffffff);
+               new_refresh = ((old_refresh * new_cpu_freq) / old_cpu_freq) |
+                             (au_readl(MEM_SDREFCFG) & ~0x1ffffff);
 
                au_writel(pll, SYS_CPUPLL);
                au_sync_delay(1);
                au_writel(new_refresh, MEM_SDREFCFG);
                au_sync_delay(1);
 
-               for (i = 0; i < 4; i++) {
-                       if (au_readl
-                           (UART_BASE + UART_MOD_CNTRL +
-                            i * 0x00100000) == 3) {
-                               old_clk =
-                                   au_readl(UART_BASE + UART_CLK +
-                                         i * 0x00100000);
-                               // baud_rate = baud_base/clk
+               for (i = 0; i < 4; i++)
+                       if (au_readl(UART_BASE + UART_MOD_CNTRL +
+                                    i * 0x00100000) == 3) {
+                               old_clk = au_readl(UART_BASE + UART_CLK +
+                                                  i * 0x00100000);
                                baud_rate = old_baud_base / old_clk;
-                               /* we won't get an exact baud rate and the error
+                               /*
+                                * We won't get an exact baud rate and the error
                                 * could be significant enough that our new
                                 * calculation will result in a clock that will
                                 * give us a baud rate that's too far off from
@@ -359,18 +351,14 @@ static int pm_do_freq(ctl_table * ctl, int write, struct file *file,
                                else if (baud_rate > 17000)
                                        baud_rate = 19200;
                                else
-                                       (baud_rate = 9600);
-                               // new_clk = new_baud_base/baud_rate
+                                       baud_rate = 9600;
                                new_clk = new_baud_base / baud_rate;
-                               au_writel(new_clk,
-                                      UART_BASE + UART_CLK +
-                                      i * 0x00100000);
+                               au_writel(new_clk, UART_BASE + UART_CLK +
+                                         i * 0x00100000);
                                au_sync_delay(10);
                        }
-               }
        }
 
-
        /*
         * We don't want _any_ interrupts other than match20. Otherwise our
         * au1000_calibrate_delay() calculation will be off, potentially a lot.
@@ -428,14 +416,15 @@ static int __init pm_init(void)
 
 __initcall(pm_init);
 
-
 /*
  * This is right out of init/main.c
  */
 
-/* This is the number of bits of precision for the loops_per_jiffy.  Each
-   bit takes on average 1.5/HZ seconds.  This (like the original) is a little
-   better than 1% */
+/*
+ * This is the number of bits of precision for the loops_per_jiffy.
+ * Each bit takes on average 1.5/HZ seconds.  This (like the original)
+ * is a little better than 1%.
+ */
 #define LPS_PREC 8
 
 static void au1000_calibrate_delay(void)
@@ -443,14 +432,14 @@ static void au1000_calibrate_delay(void)
        unsigned long ticks, loopbit;
        int lps_precision = LPS_PREC;
 
-       loops_per_jiffy = (1 << 12);
+       loops_per_jiffy = 1 << 12;
 
        while (loops_per_jiffy <<= 1) {
-               /* wait for "start of" clock tick */
+               /* Wait for "start of" clock tick */
                ticks = jiffies;
                while (ticks == jiffies)
                        /* nothing */ ;
-               /* Go .. */
+               /* Go ... */
                ticks = jiffies;
                __delay(loops_per_jiffy);
                ticks = jiffies - ticks;
@@ -458,8 +447,10 @@ static void au1000_calibrate_delay(void)
                        break;
        }
 
-/* Do a binary approximation to get loops_per_jiffy set to equal one clock
-   (up to lps_precision bits) */
+       /*
+        * Do a binary approximation to get loops_per_jiffy set to be equal
+        * one clock (up to lps_precision bits)
+        */
        loops_per_jiffy >>= 1;
        loopbit = loops_per_jiffy;
        while (lps_precision-- && (loopbit >>= 1)) {
@@ -472,4 +463,4 @@ static void au1000_calibrate_delay(void)
                        loops_per_jiffy &= ~loopbit;
        }
 }
-#endif                         /* CONFIG_PM */
+#endif /* CONFIG_PM */
index f10af829e4ec02b1292df103f6c98fca511ab258..18b310b475ca28195904f653637aedbd9bb57d7c 100644 (file)
@@ -3,9 +3,8 @@
  * BRIEF MODULE DESCRIPTION
  *    PROM library initialisation code, supports YAMON and U-Boot.
  *
- * Copyright 2000, 2001, 2006 MontaVista Software Inc.
- * Author: MontaVista Software, Inc.
- *             ppopov@mvista.com or source@mvista.com
+ * Copyright 2000-2001, 2006, 2008 MontaVista Software Inc.
+ * Author: MontaVista Software, Inc. <source@mvista.com>
  *
  * This file was derived from Carsten Langgaard's
  * arch/mips/mips-boards/xx files.
@@ -57,7 +56,7 @@ void prom_init_cmdline(void)
        actr = 1; /* Always ignore argv[0] */
 
        cp = &(arcs_cmdline[0]);
-       while(actr < prom_argc) {
+       while (actr < prom_argc) {
                strcpy(cp, prom_argv[actr]);
                cp += strlen(prom_argv[actr]);
                *cp++ = ' ';
@@ -84,10 +83,8 @@ char *prom_getenv(char *envname)
                if (yamon) {
                        if (strcmp(envname, *env++) == 0)
                                return *env;
-               } else {
-                       if (strncmp(envname, *env, i) == 0 && (*env)[i] == '=')
-                               return *env + i + 1;
-               }
+               } else if (strncmp(envname, *env, i) == 0 && (*env)[i] == '=')
+                       return *env + i + 1;
                env++;
        }
 
@@ -110,13 +107,13 @@ static inline void str2eaddr(unsigned char *ea, unsigned char *str)
 {
        int i;
 
-       for(i = 0; i < 6; i++) {
+       for (i = 0; i < 6; i++) {
                unsigned char num;
 
-               if((*str == '.') || (*str == ':'))
+               if ((*str == '.') || (*str == ':'))
                        str++;
-               num = str2hexnum(*str++) << 4;
-               num |= (str2hexnum(*str++));
+               num  = str2hexnum(*str++) << 4;
+               num |= str2hexnum(*str++);
                ea[i] = num;
        }
 }
index e34c67e892937527fe42f96bb9364c6d59f54475..55bbe24d45b6943e0689161525912171d669c630 100644 (file)
@@ -1,11 +1,10 @@
 /*
  *
  * BRIEF MODULE DESCRIPTION
- *     Low level uart routines to directly access a 16550 uart.
+ *     Low level UART routines to directly access Alchemy UART.
  *
- * Copyright 2001 MontaVista Software Inc.
- * Author: MontaVista Software, Inc.
- *             ppopov@mvista.com or source@mvista.com
+ * Copyright 2001, 2008 MontaVista Software Inc.
+ * Author: MontaVista Software, Inc. <source@mvista.com>
  *
  *  This program is free software; you can redistribute  it and/or modify it
  *  under  the terms of  the GNU General  Public License as published by the
 
 static volatile unsigned long * const com1 = (unsigned long *)SERIAL_BASE;
 
-
 #ifdef SLOW_DOWN
 static inline void slow_down(void)
 {
-    int k;
-    for (k=0; k<10000; k++);
+       int k;
+
+       for (k = 0; k < 10000; k++);
 }
 #else
 #define slow_down()
@@ -54,16 +53,16 @@ static inline void slow_down(void)
 void
 prom_putchar(const unsigned char c)
 {
-    unsigned char ch;
-    int i = 0;
+       unsigned char ch;
+       int i = 0;
+
+       do {
+               ch = com1[SER_CMD];
+               slow_down();
+               i++;
+               if (i > TIMEOUT)
+                       break;
+       } while (0 == (ch & TX_BUSY));
 
-    do {
-        ch = com1[SER_CMD];
-        slow_down();
-        i++;
-        if (i>TIMEOUT) {
-            break;
-        }
-    } while (0 == (ch & TX_BUSY));
-    com1[SER_DATA] = c;
+       com1[SER_DATA] = c;
 }
index 60cec537c7450cd4bb6d129f8dc83a16591f1044..d555429c8d6fff683fb8941cf872d83f3f022950 100644 (file)
@@ -1,11 +1,10 @@
 /*
  *
  * BRIEF MODULE DESCRIPTION
- *     Au1000 reset routines.
+ *     Au1xx0 reset routines.
  *
- * Copyright 2001 MontaVista Software Inc.
- * Author: MontaVista Software, Inc.
- *             ppopov@mvista.com or source@mvista.com
+ * Copyright 2001, 2006, 2008 MontaVista Software Inc.
+ * Author: MontaVista Software, Inc. <source@mvista.com>
  *
  *  This program is free software; you can redistribute  it and/or modify it
  *  under  the terms of  the GNU General  Public License as published by the
  *  675 Mass Ave, Cambridge, MA 02139, USA.
  */
 
+#include <asm/cacheflush.h>
+
 #include <asm/mach-au1x00/au1000.h>
 
 extern int au_sleep(void);
-extern void (*flush_cache_all)(void);
 
 void au1000_restart(char *command)
 {
@@ -40,8 +40,8 @@ void au1000_restart(char *command)
        u32 prid = read_c0_prid();
 
        printk(KERN_NOTICE "\n** Resetting Integrated Peripherals\n");
-       switch (prid & 0xFF000000)
-       {
+
+       switch (prid & 0xFF000000) {
        case 0x00000000: /* Au1000 */
                au_writel(0x02, 0xb0000010); /* ac97_enable */
                au_writel(0x08, 0xb017fffc); /* usbh_enable - early errata */
@@ -138,9 +138,6 @@ void au1000_restart(char *command)
                au_writel(0x00, 0xb1900064); /* sys_auxpll */
                au_writel(0x00, 0xb1900100); /* sys_pininputen */
                break;
-
-       default:
-               break;
        }
 
        set_c0_status(ST0_BEV | ST0_ERL);
@@ -158,25 +155,25 @@ void au1000_restart(char *command)
 void au1000_halt(void)
 {
 #if defined(CONFIG_MIPS_PB1550) || defined(CONFIG_MIPS_DB1550)
-       /* power off system */
-       printk("\n** Powering off...\n");
-       au_writew(au_readw(0xAF00001C) | (3<<14), 0xAF00001C);
+       /* Power off system */
+       printk(KERN_NOTICE "\n** Powering off...\n");
+       au_writew(au_readw(0xAF00001C) | (3 << 14), 0xAF00001C);
        au_sync();
-       while(1); /* should not get here */
+       while (1); /* should not get here */
 #else
        printk(KERN_NOTICE "\n** You can safely turn off the power\n");
 #ifdef CONFIG_MIPS_MIRAGE
        au_writel((1 << 26) | (1 << 10), GPIO2_OUTPUT);
 #endif
 #ifdef CONFIG_MIPS_DB1200
-       au_writew(au_readw(0xB980001C) | (1<<14), 0xB980001C);
+       au_writew(au_readw(0xB980001C) | (1 << 14), 0xB980001C);
 #endif
 #ifdef CONFIG_PM
        au_sleep();
 
-       /* should not get here */
-       printk(KERN_ERR "Unable to put cpu in sleep mode\n");
-       while(1);
+       /* Should not get here */
+       printk(KERN_ERR "Unable to put CPU in sleep mode\n");
+       while (1);
 #else
        while (1)
                __asm__(".set\tmips3\n\t"
index 0e86f7a6b4a7f5ad60fa1a24cab5b14d7c815508..1ac6b06f42a369ef8e8d578bf33c72ef99eafe44 100644 (file)
@@ -1,7 +1,6 @@
 /*
- * Copyright 2000 MontaVista Software Inc.
- * Author: MontaVista Software, Inc.
- *             ppopov@mvista.com or source@mvista.com
+ * Copyright 2000, 2007-2008 MontaVista Software Inc.
+ * Author: MontaVista Software, Inc. <source@mvista.com
  *
  * Updates to 2.6, Pete Popov, Embedded Alley Solutions, Inc.
  *
@@ -48,7 +47,7 @@ void __init plat_mem_setup(void)
 {
        struct  cpu_spec *sp;
        char *argptr;
-       unsigned long prid, cpufreq, bclk = 1;
+       unsigned long prid, cpufreq, bclk;
 
        set_cpuspec();
        sp = cur_cpu_spec[0];
@@ -66,42 +65,39 @@ void __init plat_mem_setup(void)
                cpufreq = (au_readl(SYS_CPUPLL) & 0x3F) * 12;
        printk(KERN_INFO "(PRID %08lx) @ %ld MHz\n", prid, cpufreq);
 
-       bclk = sp->cpu_bclk;
-       if (bclk)
-       {
+       if (sp->cpu_bclk) {
                /* Enable BCLK switching */
-               bclk = au_readl(0xB190003C);
-               au_writel(bclk | 0x60, 0xB190003C);
-               printk("BCLK switching enabled!\n");
+               bclk = au_readl(SYS_POWERCTRL);
+               au_writel(bclk | 0x60, SYS_POWERCTRL);
+               printk(KERN_INFO "BCLK switching enabled!\n");
        }
 
-       if (sp->cpu_od) {
-               /* Various early Au1000 Errata corrected by this */
-               set_c0_config(1<<19); /* Set Config[OD] */
-       }
-       else {
+       if (sp->cpu_od)
+               /* Various early Au1xx0 errata corrected by this */
+               set_c0_config(1 << 19); /* Set Config[OD] */
+       else
                /* Clear to obtain best system bus performance */
-               clear_c0_config(1<<19); /* Clear Config[OD] */
-       }
+               clear_c0_config(1 << 19); /* Clear Config[OD] */
 
        argptr = prom_getcmdline();
 
 #ifdef CONFIG_SERIAL_8250_CONSOLE
-       if ((argptr = strstr(argptr, "console=")) == NULL) {
+       argptr = strstr(argptr, "console=");
+       if (argptr == NULL) {
                argptr = prom_getcmdline();
                strcat(argptr, " console=ttyS0,115200");
        }
 #endif
 
 #ifdef CONFIG_FB_AU1100
-    if ((argptr = strstr(argptr, "video=")) == NULL) {
-        argptr = prom_getcmdline();
-        /* default panel */
-        /*strcat(argptr, " video=au1100fb:panel:Sharp_320x240_16");*/
-    }
+       argptr = strstr(argptr, "video=");
+       if (argptr == NULL) {
+               argptr = prom_getcmdline();
+               /* default panel */
+               /*strcat(argptr, " video=au1100fb:panel:Sharp_320x240_16");*/
+       }
 #endif
 
-
 #if defined(CONFIG_SOUND_AU1X00) && !defined(CONFIG_SOC_AU1000)
        /* au1000 does not support vra, au1500 and au1100 do */
        strcat(argptr, " au1000_audio=vra");
@@ -129,7 +125,7 @@ void __init plat_mem_setup(void)
 /* This routine should be valid for all Au1x based boards */
 phys_t __fixup_bigphys_addr(phys_t phys_addr, phys_t size)
 {
-       /* Don't fixup 36 bit addresses */
+       /* Don't fixup 36-bit addresses */
        if ((phys_addr >> 32) != 0)
                return phys_addr;
 
@@ -145,17 +141,17 @@ phys_t __fixup_bigphys_addr(phys_t phys_addr, phys_t size)
        }
 #endif
 
-       /* All Au1x SOCs have a pcmcia controller */
-       /* We setup our 32 bit pseudo addresses to be equal to the
-        * 36 bit addr >> 4, to make it easier to check the address
+       /*
+        * All Au1xx0 SOCs have a PCMCIA controller.
+        * We setup our 32-bit pseudo addresses to be equal to the
+        * 36-bit addr >> 4, to make it easier to check the address
         * and fix it.
-        * The Au1x socket 0 phys attribute address is 0xF 4000 0000.
+        * The PCMCIA socket 0 physical attribute address is 0xF 4000 0000.
         * The pseudo address we use is 0xF400 0000. Any address over
-        * 0xF400 0000 is a pcmcia pseudo address.
+        * 0xF400 0000 is a PCMCIA pseudo address.
         */
-       if ((phys_addr >= 0xF4000000) && (phys_addr < 0xFFFFFFFF)) {
+       if ((phys_addr >= 0xF4000000) && (phys_addr < 0xFFFFFFFF))
                return (phys_t)(phys_addr << 4);
-       }
 
        /* default nop */
        return phys_addr;
index bdb6d73b26fb19876ddff6da2da037946f144e10..563d9390a87269889e3dee6118fb8e4dd5f7e9c6 100644 (file)
  *
  * Setting up the clock on the MIPS boards.
  *
- * Update.  Always configure the kernel with CONFIG_NEW_TIME_C.  This
- * will use the user interface gettimeofday() functions from the
- * arch/mips/kernel/time.c, and we provide the clock interrupt processing
- * and the timer offset compute functions.  If CONFIG_PM is selected,
- * we also ensure the 32KHz timer is available.   -- Dan
+ * We provide the clock interrupt processing and the timer offset compute
+ * functions.  If CONFIG_PM is selected, we also ensure the 32KHz timer is
+ * available.  -- Dan
  */
 
 #include <linux/types.h>
@@ -47,8 +45,7 @@ extern int allow_au1k_wait; /* default off for CP0 Counter */
 #if HZ < 100 || HZ > 1000
 #error "unsupported HZ value! Must be in [100,1000]"
 #endif
-#define MATCH20_INC (328*100/HZ) /* magic number 328 is for HZ=100... */
-extern void startup_match20_interrupt(irq_handler_t handler);
+#define MATCH20_INC (328 * 100 / HZ) /* magic number 328 is for HZ=100... */
 static unsigned long last_pc0, last_match20;
 #endif
 
@@ -61,7 +58,7 @@ static irqreturn_t counter0_irq(int irq, void *dev_id)
 {
        unsigned long pc0;
        int time_elapsed;
-       static int jiffie_drift = 0;
+       static int jiffie_drift;
 
        if (au_readl(SYS_COUNTER_CNTRL) & SYS_CNTRL_M20) {
                /* should never happen! */
@@ -70,13 +67,11 @@ static irqreturn_t counter0_irq(int irq, void *dev_id)
        }
 
        pc0 = au_readl(SYS_TOYREAD);
-       if (pc0 < last_match20) {
+       if (pc0 < last_match20)
                /* counter overflowed */
                time_elapsed = (0xffffffff - last_match20) + pc0;
-       }
-       else {
+       else
                time_elapsed = pc0 - last_match20;
-       }
 
        while (time_elapsed > 0) {
                do_timer(1);
@@ -92,8 +87,9 @@ static irqreturn_t counter0_irq(int irq, void *dev_id)
        au_writel(last_match20 + MATCH20_INC, SYS_TOYMATCH2);
        au_sync();
 
-       /* our counter ticks at 10.009765625 ms/tick, we we're running
-        * almost 10uS too slow per tick.
+       /*
+        * Our counter ticks at 10.009765625 ms/tick, we we're running
+        * almost 10 uS too slow per tick.
         */
 
        if (jiffie_drift >= 999) {
@@ -117,20 +113,17 @@ struct irqaction counter0_action = {
 /* When we wakeup from sleep, we have to "catch up" on all of the
  * timer ticks we have missed.
  */
-void
-wakeup_counter0_adjust(void)
+void wakeup_counter0_adjust(void)
 {
        unsigned long pc0;
        int time_elapsed;
 
        pc0 = au_readl(SYS_TOYREAD);
-       if (pc0 < last_match20) {
+       if (pc0 < last_match20)
                /* counter overflowed */
                time_elapsed = (0xffffffff - last_match20) + pc0;
-       }
-       else {
+       else
                time_elapsed = pc0 - last_match20;
-       }
 
        while (time_elapsed > 0) {
                time_elapsed -= MATCH20_INC;
@@ -143,10 +136,8 @@ wakeup_counter0_adjust(void)
 
 }
 
-/* This is just for debugging to set the timer for a sleep delay.
-*/
-void
-wakeup_counter0_set(int ticks)
+/* This is just for debugging to set the timer for a sleep delay. */
+void wakeup_counter0_set(int ticks)
 {
        unsigned long pc0;
 
@@ -157,21 +148,22 @@ wakeup_counter0_set(int ticks)
 }
 #endif
 
-/* I haven't found anyone that doesn't use a 12 MHz source clock,
+/*
+ * I haven't found anyone that doesn't use a 12 MHz source clock,
  * but just in case.....
  */
 #define AU1000_SRC_CLK 12000000
 
 /*
  * We read the real processor speed from the PLL.  This is important
- * because it is more accurate than computing it from the 32KHz
+ * because it is more accurate than computing it from the 32 KHz
  * counter, if it exists.  If we don't have an accurate processor
  * speed, all of the peripherals that derive their clocks based on
  * this advertised speed will introduce error and sometimes not work
  * properly.  This function is futher convoluted to still allow configurations
  * to do that in case they have really, really old silicon with a
- * write-only PLL register, that we need the 32KHz when power management
- * "wait" is enabled, and we need to detect if the 32KHz isn't present
+ * write-only PLL register, that we need the 32 KHz when power management
+ * "wait" is enabled, and we need to detect if the 32 KHz isn't present
  * but requested......got it? :-)              -- Dan
  */
 unsigned long calc_clock(void)
@@ -182,8 +174,7 @@ unsigned long calc_clock(void)
 
        spin_lock_irqsave(&time_lock, flags);
 
-       /* Power management cares if we don't have a 32KHz counter.
-       */
+       /* Power management cares if we don't have a 32 KHz counter. */
        no_au1xxx_32khz = 0;
        counter = au_readl(SYS_COUNTER_CNTRL);
        if (counter & SYS_CNTRL_E0) {
@@ -193,7 +184,7 @@ unsigned long calc_clock(void)
 
                while (au_readl(SYS_COUNTER_CNTRL) & SYS_CNTRL_T1S);
                /* RTC now ticks at 32.768/16 kHz */
-               au_writel(trim_divide-1, SYS_RTCTRIM);
+               au_writel(trim_divide - 1, SYS_RTCTRIM);
                while (au_readl(SYS_COUNTER_CNTRL) & SYS_CNTRL_T1S);
 
                while (au_readl(SYS_COUNTER_CNTRL) & SYS_CNTRL_C1S);
@@ -215,9 +206,11 @@ unsigned long calc_clock(void)
 #endif
        else
                cpu_speed = (au_readl(SYS_CPUPLL) & 0x0000003f) * AU1000_SRC_CLK;
+       /* On Alchemy CPU:counter ratio is 1:1 */
        mips_hpt_frequency = cpu_speed;
-       // Equation: Baudrate = CPU / (SD * 2 * CLKDIV * 16)
-       set_au1x00_uart_baud_base(cpu_speed / (2 * ((int)(au_readl(SYS_POWERCTRL)&0x03) + 2) * 16));
+       /* Equation: Baudrate = CPU / (SD * 2 * CLKDIV * 16) */
+       set_au1x00_uart_baud_base(cpu_speed / (2 * ((int)(au_readl(SYS_POWERCTRL)
+                                                         & 0x03) + 2) * 16));
        spin_unlock_irqrestore(&time_lock, flags);
        return cpu_speed;
 }
@@ -228,10 +221,10 @@ void __init plat_time_init(void)
 
        est_freq += 5000;    /* round */
        est_freq -= est_freq%10000;
-       printk("CPU frequency %d.%02d MHz\n", est_freq/1000000,
-              (est_freq%1000000)*100/1000000);
-       set_au1x00_speed(est_freq);
-       set_au1x00_lcd_clock(); // program the LCD clock
+       printk(KERN_INFO "CPU frequency %u.%02u MHz\n",
+              est_freq / 1000000, ((est_freq % 1000000) * 100) / 1000000);
+       set_au1x00_speed(est_freq);
+       set_au1x00_lcd_clock(); /* program the LCD clock */
 
 #ifdef CONFIG_PM
        /*
@@ -243,30 +236,29 @@ void __init plat_time_init(void)
         * counter 0 interrupt as a special irq and it doesn't show
         * up under /proc/interrupts.
         *
-        * Check to ensure we really have a 32KHz oscillator before
+        * Check to ensure we really have a 32 KHz oscillator before
         * we do this.
         */
        if (no_au1xxx_32khz)
-               printk("WARNING: no 32KHz clock found.\n");
+               printk(KERN_WARNING "WARNING: no 32KHz clock found.\n");
        else {
                while (au_readl(SYS_COUNTER_CNTRL) & SYS_CNTRL_C0S);
                au_writel(0, SYS_TOYWRITE);
                while (au_readl(SYS_COUNTER_CNTRL) & SYS_CNTRL_C0S);
 
-               au_writel(au_readl(SYS_WAKEMSK) | (1<<8), SYS_WAKEMSK);
+               au_writel(au_readl(SYS_WAKEMSK) | (1 << 8), SYS_WAKEMSK);
                au_writel(~0, SYS_WAKESRC);
                au_sync();
                while (au_readl(SYS_COUNTER_CNTRL) & SYS_CNTRL_M20);
 
-               /* setup match20 to interrupt once every HZ */
+               /* Setup match20 to interrupt once every HZ */
                last_pc0 = last_match20 = au_readl(SYS_TOYREAD);
                au_writel(last_match20 + MATCH20_INC, SYS_TOYMATCH2);
                au_sync();
                while (au_readl(SYS_COUNTER_CNTRL) & SYS_CNTRL_M20);
                setup_irq(AU1000_TOY_MATCH2_INT, &counter0_action);
 
-               /* We can use the real 'wait' instruction.
-               */
+               /* We can use the real 'wait' instruction. */
                allow_au1k_wait = 1;
        }
 
index 51d62bd5d900f93ad5408e71a3df031e027ea840..274db3b55d829f5d77336cfde244f3b3ab8dfdae 100644 (file)
@@ -1,8 +1,8 @@
 #
-#  Copyright 2000 MontaVista Software Inc.
-#  Author: MontaVista Software, Inc.
-#      ppopov@mvista.com or source@mvista.com
+#  Copyright 2000, 2008 MontaVista Software Inc.
+#  Author: MontaVista Software, Inc. <source@mvista.com>
+#
+# Makefile for the Alchemy Semiconductor DBAu1xx0 boards.
 #
-# Makefile for the Alchemy Semiconductor Db1x00 board.
 
 lib-y := init.o board_setup.o irqmap.o
index b7dcbad5c5861070b267393f3f44e1fce1c036ff..9e5ccbbfcedd83dc8f11ab0a1b2ac86cf480d01b 100644 (file)
@@ -3,9 +3,8 @@
  * BRIEF MODULE DESCRIPTION
  *     Alchemy Db1x00 board setup.
  *
- * Copyright 2000 MontaVista Software Inc.
- * Author: MontaVista Software, Inc.
- *             ppopov@mvista.com or source@mvista.com
+ * Copyright 2000, 2008 MontaVista Software Inc.
+ * Author: MontaVista Software, Inc. <source@mvista.com>