wl1271: RefClk configuration
authorJuuso Oikarinen <juuso.oikarinen@nokia.com>
Mon, 12 Oct 2009 12:08:49 +0000 (15:08 +0300)
committerJohn W. Linville <linville@tuxdriver.com>
Tue, 27 Oct 2009 20:48:04 +0000 (16:48 -0400)
Updated RefClk configuration based on reference sources. Apparently this
change will improve RF performance.

Signed-off-by: Juuso Oikarinen <juuso.oikarinen@nokia.com>
Reviewed-by: Luciano Coelho <luciano.coelho@nokia.com>
Signed-off-by: Luciano Coelho <luciano.coelho@nokia.com>
Signed-off-by: John W. Linville <linville@tuxdriver.com>
drivers/net/wireless/wl12xx/wl1271_boot.c
drivers/net/wireless/wl12xx/wl1271_boot.h

index 1a3084cca9b830ec7fd9bec037008b41b4b78062..b58657750716f74d12b91fcc81527ab2b11c9297 100644 (file)
@@ -435,13 +435,29 @@ int wl1271_boot(struct wl1271 *wl)
        int ret = 0;
        u32 tmp, clk, pause;
 
        int ret = 0;
        u32 tmp, clk, pause;
 
-       if (REF_CLOCK == 0 || REF_CLOCK == 2)
-               /* ref clk: 19.2/38.4 */
+       if (REF_CLOCK == 0 || REF_CLOCK == 2 || REF_CLOCK == 4)
+               /* ref clk: 19.2/38.4/38.4-XTAL */
                clk = 0x3;
        else if (REF_CLOCK == 1 || REF_CLOCK == 3)
                /* ref clk: 26/52 */
                clk = 0x5;
 
                clk = 0x3;
        else if (REF_CLOCK == 1 || REF_CLOCK == 3)
                /* ref clk: 26/52 */
                clk = 0x5;
 
+       if (REF_CLOCK != 0) {
+               u16 val;
+               /* Set clock type */
+               val = wl1271_top_reg_read(wl, OCP_REG_CLK_TYPE);
+               val &= FREF_CLK_TYPE_BITS;
+               val |= CLK_REQ_PRCM;
+               wl1271_top_reg_write(wl, OCP_REG_CLK_TYPE, val);
+       } else {
+               u16 val;
+               /* Set clock polarity */
+               val = wl1271_top_reg_read(wl, OCP_REG_CLK_POLARITY);
+               val &= FREF_CLK_POLARITY_BITS;
+               val |= CLK_REQ_OUTN_SEL;
+               wl1271_top_reg_write(wl, OCP_REG_CLK_POLARITY, val);
+       }
+
        wl1271_reg_write32(wl, PLL_PARAMETERS, clk);
 
        pause = wl1271_reg_read32(wl, PLL_PARAMETERS);
        wl1271_reg_write32(wl, PLL_PARAMETERS, clk);
 
        pause = wl1271_reg_read32(wl, PLL_PARAMETERS);
index 4501653fb52a2bb78539acf1eb7e183d5d6c5677..412443ee655a6cf8761190a22efb5d96f9670414 100644 (file)
@@ -50,10 +50,17 @@ struct wl1271_static_data {
 #define WU_COUNTER_PAUSE_VAL 0x3FF
 #define WELP_ARM_COMMAND_VAL 0x4
 
 #define WU_COUNTER_PAUSE_VAL 0x3FF
 #define WELP_ARM_COMMAND_VAL 0x4
 
-#define OCP_REG_POLARITY 0x0064
+#define OCP_REG_POLARITY     0x0064
+#define OCP_REG_CLK_TYPE     0x0448
+#define OCP_REG_CLK_POLARITY 0x0cb2
 
 #define CMD_MBOX_ADDRESS 0x407B4
 
 #define POLARITY_LOW BIT(1)
 
 
 #define CMD_MBOX_ADDRESS 0x407B4
 
 #define POLARITY_LOW BIT(1)
 
+#define FREF_CLK_TYPE_BITS     0xfffffe7f
+#define CLK_REQ_PRCM           0x100
+#define FREF_CLK_POLARITY_BITS 0xfffff8ff
+#define CLK_REQ_OUTN_SEL       0x700
+
 #endif
 #endif