Merge /spare/repo/linux-2.6/
authorJeff Garzik <jgarzik@pobox.com>
Tue, 28 Jun 2005 04:46:46 +0000 (00:46 -0400)
committerJeff Garzik <jgarzik@pobox.com>
Tue, 28 Jun 2005 04:46:46 +0000 (00:46 -0400)
31 files changed:
Documentation/networking/README.ipw2100 [new file with mode: 0644]
Documentation/networking/README.ipw2200 [new file with mode: 0644]
drivers/net/skge.c
drivers/net/skge.h
drivers/net/wireless/Kconfig
drivers/net/wireless/Makefile
drivers/net/wireless/atmel.c
drivers/net/wireless/ieee802_11.h [deleted file]
drivers/net/wireless/ipw2100.c [new file with mode: 0644]
drivers/net/wireless/ipw2100.h [new file with mode: 0644]
drivers/net/wireless/ipw2200.c [new file with mode: 0644]
drivers/net/wireless/ipw2200.h [new file with mode: 0644]
drivers/net/wireless/orinoco.c
drivers/net/wireless/wl3501.h
drivers/usb/net/Makefile
drivers/usb/net/zd1201.c
include/linux/etherdevice.h
include/net/ieee80211.h
include/net/ieee80211_crypt.h [new file with mode: 0644]
net/Kconfig
net/Makefile
net/ieee80211/Kconfig [new file with mode: 0644]
net/ieee80211/Makefile [new file with mode: 0644]
net/ieee80211/ieee80211_crypt.c [new file with mode: 0644]
net/ieee80211/ieee80211_crypt_ccmp.c [new file with mode: 0644]
net/ieee80211/ieee80211_crypt_tkip.c [new file with mode: 0644]
net/ieee80211/ieee80211_crypt_wep.c [new file with mode: 0644]
net/ieee80211/ieee80211_module.c [new file with mode: 0644]
net/ieee80211/ieee80211_rx.c [new file with mode: 0644]
net/ieee80211/ieee80211_tx.c [new file with mode: 0644]
net/ieee80211/ieee80211_wx.c [new file with mode: 0644]

diff --git a/Documentation/networking/README.ipw2100 b/Documentation/networking/README.ipw2100
new file mode 100644 (file)
index 0000000..2046948
--- /dev/null
@@ -0,0 +1,246 @@
+
+===========================
+Intel(R) PRO/Wireless 2100 Network Connection Driver for Linux
+README.ipw2100
+
+March 14, 2005
+
+===========================
+Index
+---------------------------
+0. Introduction
+1. Release 1.1.0 Current Features
+2. Command Line Parameters
+3. Sysfs Helper Files
+4. Radio Kill Switch
+5. Dynamic Firmware
+6. Power Management
+7. Support
+8. License
+
+
+===========================
+0. Introduction
+------------ -----   -----       ----       ---       --         -     
+
+This document provides a brief overview of the features supported by the 
+IPW2100 driver project.  The main project website, where the latest 
+development version of the driver can be found, is:
+
+       http://ipw2100.sourceforge.net
+
+There you can find the not only the latest releases, but also information about
+potential fixes and patches, as well as links to the development mailing list
+for the driver project.
+
+
+===========================
+1. Release 1.1.0 Current Supported Features
+---------------------------     
+- Managed (BSS) and Ad-Hoc (IBSS)
+- WEP (shared key and open)
+- Wireless Tools support 
+- 802.1x (tested with XSupplicant 1.0.1)
+
+Enabled (but not supported) features:
+- Monitor/RFMon mode
+- WPA/WPA2
+
+The distinction between officially supported and enabled is a reflection
+on the amount of validation and interoperability testing that has been
+performed on a given feature.
+
+
+===========================
+2. Command Line Parameters
+---------------------------     
+
+If the driver is built as a module, the following optional parameters are used
+by entering them on the command line with the modprobe command using this
+syntax:
+
+       modprobe ipw2100 [<option>=<VAL1><,VAL2>...]
+
+For example, to disable the radio on driver loading, enter:
+
+       modprobe ipw2100 disable=1
+
+The ipw2100 driver supports the following module parameters:
+
+Name           Value           Example:
+debug          0x0-0xffffffff  debug=1024
+mode           0,1,2           mode=1   /* AdHoc */
+channel                int             channel=3 /* Only valid in AdHoc or Monitor */
+associate      boolean         associate=0 /* Do NOT auto associate */
+disable                boolean         disable=1 /* Do not power the HW */
+
+
+===========================
+3. Sysfs Helper Files
+---------------------------     
+
+There are several ways to control the behavior of the driver.  Many of the 
+general capabilities are exposed through the Wireless Tools (iwconfig).  There
+are a few capabilities that are exposed through entries in the Linux Sysfs.
+
+
+----- Driver Level ------
+For the driver level files, look in /sys/bus/pci/drivers/ipw2100/
+
+  debug_level  
+       
+       This controls the same global as the 'debug' module parameter.  For 
+        information on the various debugging levels available, run the 'dvals'
+       script found in the driver source directory.
+
+       NOTE:  'debug_level' is only enabled if CONFIG_IPW2100_DEBUG is turn
+              on.
+
+----- Device Level ------
+For the device level files look in
+       
+       /sys/bus/pci/drivers/ipw2100/{PCI-ID}/
+
+For example:
+       /sys/bus/pci/drivers/ipw2100/0000:02:01.0
+
+For the device level files, see /sys/bus/pci/drivers/ipw2100:
+
+  rf_kill
+       read - 
+       0 = RF kill not enabled (radio on)
+       1 = SW based RF kill active (radio off)
+       2 = HW based RF kill active (radio off)
+       3 = Both HW and SW RF kill active (radio off)
+       write -
+       0 = If SW based RF kill active, turn the radio back on
+       1 = If radio is on, activate SW based RF kill
+
+       NOTE: If you enable the SW based RF kill and then toggle the HW
+       based RF kill from ON -> OFF -> ON, the radio will NOT come back on
+
+
+===========================
+4. Radio Kill Switch
+---------------------------
+Most laptops provide the ability for the user to physically disable the radio.
+Some vendors have implemented this as a physical switch that requires no
+software to turn the radio off and on.  On other laptops, however, the switch
+is controlled through a button being pressed and a software driver then making
+calls to turn the radio off and on.  This is referred to as a "software based
+RF kill switch"
+
+See the Sysfs helper file 'rf_kill' for determining the state of the RF switch
+on your system.
+
+
+===========================
+5. Dynamic Firmware
+---------------------------     
+As the firmware is licensed under a restricted use license, it can not be 
+included within the kernel sources.  To enable the IPW2100 you will need a 
+firmware image to load into the wireless NIC's processors.
+
+You can obtain these images from <http://ipw2100.sf.net/firmware.php>.
+
+See INSTALL for instructions on installing the firmware.
+
+
+===========================
+6. Power Management
+---------------------------     
+The IPW2100 supports the configuration of the Power Save Protocol 
+through a private wireless extension interface.  The IPW2100 supports 
+the following different modes:
+
+       off     No power management.  Radio is always on.
+       on      Automatic power management
+       1-5     Different levels of power management.  The higher the 
+               number the greater the power savings, but with an impact to 
+               packet latencies. 
+
+Power management works by powering down the radio after a certain 
+interval of time has passed where no packets are passed through the 
+radio.  Once powered down, the radio remains in that state for a given 
+period of time.  For higher power savings, the interval between last 
+packet processed to sleep is shorter and the sleep period is longer.
+
+When the radio is asleep, the access point sending data to the station 
+must buffer packets at the AP until the station wakes up and requests 
+any buffered packets.  If you have an AP that does not correctly support 
+the PSP protocol you may experience packet loss or very poor performance 
+while power management is enabled.  If this is the case, you will need 
+to try and find a firmware update for your AP, or disable power 
+management (via `iwconfig eth1 power off`)
+
+To configure the power level on the IPW2100 you use a combination of 
+iwconfig and iwpriv.  iwconfig is used to turn power management on, off, 
+and set it to auto.
+
+       iwconfig eth1 power off    Disables radio power down
+       iwconfig eth1 power on     Enables radio power management to 
+                                  last set level (defaults to AUTO)
+       iwpriv eth1 set_power 0    Sets power level to AUTO and enables 
+                                  power management if not previously 
+                                  enabled.
+       iwpriv eth1 set_power 1-5  Set the power level as specified, 
+                                  enabling power management if not 
+                                  previously enabled.
+
+You can view the current power level setting via:
+       
+       iwpriv eth1 get_power
+
+It will return the current period or timeout that is configured as a string
+in the form of xxxx/yyyy (z) where xxxx is the timeout interval (amount of
+time after packet processing), yyyy is the period to sleep (amount of time to 
+wait before powering the radio and querying the access point for buffered
+packets), and z is the 'power level'.  If power management is turned off the
+xxxx/yyyy will be replaced with 'off' -- the level reported will be the active
+level if `iwconfig eth1 power on` is invoked.
+
+
+===========================
+7. Support
+---------------------------     
+
+For general development information and support,
+go to:
+       
+    http://ipw2100.sf.net/
+
+The ipw2100 1.1.0 driver and firmware can be downloaded from:  
+
+    http://support.intel.com
+
+For installation support on the ipw2100 1.1.0 driver on Linux kernels 
+2.6.8 or greater, email support is available from:  
+
+    http://supportmail.intel.com
+
+===========================
+8. License
+---------------------------     
+
+  Copyright(c) 2003 - 2005 Intel Corporation. All rights reserved.
+
+  This program is free software; you can redistribute it and/or modify it 
+  under the terms of the GNU General Public License (version 2) as 
+  published by the Free Software Foundation.
+  
+  This program is distributed in the hope that it will be useful, but WITHOUT 
+  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 
+  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for 
+  more details.
+  
+  You should have received a copy of the GNU General Public License along with
+  this program; if not, write to the Free Software Foundation, Inc., 59 
+  Temple Place - Suite 330, Boston, MA  02111-1307, USA.
+  
+  The full GNU General Public License is included in this distribution in the
+  file called LICENSE.
+  
+  License Contact Information:
+  James P. Ketrenos <ipw2100-admin@linux.intel.com>
+  Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
+
diff --git a/Documentation/networking/README.ipw2200 b/Documentation/networking/README.ipw2200
new file mode 100644 (file)
index 0000000..6916080
--- /dev/null
@@ -0,0 +1,300 @@
+
+Intel(R) PRO/Wireless 2915ABG Driver for Linux in support of:
+
+Intel(R) PRO/Wireless 2200BG Network Connection 
+Intel(R) PRO/Wireless 2915ABG Network Connection 
+
+Note: The Intel(R) PRO/Wireless 2915ABG Driver for Linux and Intel(R) 
+PRO/Wireless 2200BG Driver for Linux is a unified driver that works on 
+both hardware adapters listed above. In this document the Intel(R) 
+PRO/Wireless 2915ABG Driver for Linux will be used to reference the 
+unified driver.
+
+Copyright (C) 2004-2005, Intel Corporation
+
+README.ipw2200
+
+Version: 1.0.0
+Date   : January 31, 2005
+
+
+Index
+-----------------------------------------------
+1.   Introduction
+1.1. Overview of features
+1.2. Module parameters
+1.3. Wireless Extension Private Methods
+1.4. Sysfs Helper Files
+2.   About the Version Numbers
+3.   Support
+4.   License
+
+
+1.   Introduction
+-----------------------------------------------
+The following sections attempt to provide a brief introduction to using 
+the Intel(R) PRO/Wireless 2915ABG Driver for Linux.
+
+This document is not meant to be a comprehensive manual on 
+understanding or using wireless technologies, but should be sufficient 
+to get you moving without wires on Linux.
+
+For information on building and installing the driver, see the INSTALL
+file.
+
+
+1.1. Overview of Features
+-----------------------------------------------
+The current release (1.0.0) supports the following features:
+
++ BSS mode (Infrastructure, Managed)
++ IBSS mode (Ad-Hoc)
++ WEP (OPEN and SHARED KEY mode)
++ 802.1x EAP via wpa_supplicant and xsupplicant
++ Wireless Extension support 
++ Full B and G rate support (2200 and 2915)
++ Full A rate support (2915 only)
++ Transmit power control
++ S state support (ACPI suspend/resume)
++ long/short preamble support
+
+
+
+1.2. Command Line Parameters
+-----------------------------------------------
+
+Like many modules used in the Linux kernel, the Intel(R) PRO/Wireless 
+2915ABG Driver for Linux allows certain configuration options to be 
+provided as module parameters.  The most common way to specify a module 
+parameter is via the command line.  
+
+The general form is:
+
+% modprobe ipw2200 parameter=value
+
+Where the supported parameter are:
+
+  associate
+       Set to 0 to disable the auto scan-and-associate functionality of the
+       driver.  If disabled, the driver will not attempt to scan 
+       for and associate to a network until it has been configured with 
+       one or more properties for the target network, for example configuring 
+       the network SSID.  Default is 1 (auto-associate)
+       
+       Example: % modprobe ipw2200 associate=0
+
+  auto_create
+       Set to 0 to disable the auto creation of an Ad-Hoc network 
+       matching the channel and network name parameters provided.  
+       Default is 1.
+
+  channel
+       channel number for association.  The normal method for setting
+        the channel would be to use the standard wireless tools
+        (i.e. `iwconfig eth1 channel 10`), but it is useful sometimes
+       to set this while debugging.  Channel 0 means 'ANY'
+
+  debug
+       If using a debug build, this is used to control the amount of debug
+       info is logged.  See the 'dval' and 'load' script for more info on
+       how to use this (the dval and load scripts are provided as part 
+       of the ipw2200 development snapshot releases available from the 
+       SourceForge project at http://ipw2200.sf.net)
+
+  mode
+       Can be used to set the default mode of the adapter.  
+       0 = Managed, 1 = Ad-Hoc
+
+
+1.3. Wireless Extension Private Methods
+-----------------------------------------------
+
+As an interface designed to handle generic hardware, there are certain 
+capabilities not exposed through the normal Wireless Tool interface.  As 
+such, a provision is provided for a driver to declare custom, or 
+private, methods.  The Intel(R) PRO/Wireless 2915ABG Driver for Linux 
+defines several of these to configure various settings.
+
+The general form of using the private wireless methods is:
+
+       % iwpriv $IFNAME method parameters
+
+Where $IFNAME is the interface name the device is registered with 
+(typically eth1, customized via one of the various network interface
+name managers, such as ifrename)
+
+The supported private methods are:
+
+  get_mode
+       Can be used to report out which IEEE mode the driver is 
+       configured to support.  Example:
+       
+       % iwpriv eth1 get_mode
+       eth1    get_mode:802.11bg (6)
+
+  set_mode
+       Can be used to configure which IEEE mode the driver will 
+       support.  
+
+       Usage:
+       % iwpriv eth1 set_mode {mode}
+       Where {mode} is a number in the range 1-7:
+       1       802.11a (2915 only)
+       2       802.11b
+       3       802.11ab (2915 only)
+       4       802.11g 
+       5       802.11ag (2915 only)
+       6       802.11bg
+       7       802.11abg (2915 only)
+
+  get_preamble
+       Can be used to report configuration of preamble length.
+
+  set_preamble
+       Can be used to set the configuration of preamble length:
+
+       Usage:
+       % iwpriv eth1 set_preamble {mode}
+       Where {mode} is one of:
+       1       Long preamble only
+       0       Auto (long or short based on connection)
+       
+
+1.4. Sysfs Helper Files:
+-----------------------------------------------
+
+The Linux kernel provides a pseudo file system that can be used to 
+access various components of the operating system.  The Intel(R) 
+PRO/Wireless 2915ABG Driver for Linux exposes several configuration 
+parameters through this mechanism.
+
+An entry in the sysfs can support reading and/or writing.  You can 
+typically query the contents of a sysfs entry through the use of cat, 
+and can set the contents via echo.  For example:
+
+% cat /sys/bus/pci/drivers/ipw2200/debug_level
+
+Will report the current debug level of the driver's logging subsystem 
+(only available if CONFIG_IPW_DEBUG was configured when the driver was 
+built).
+
+You can set the debug level via:
+
+% echo $VALUE > /sys/bus/pci/drivers/ipw2200/debug_level
+
+Where $VALUE would be a number in the case of this sysfs entry.  The 
+input to sysfs files does not have to be a number.  For example, the 
+firmware loader used by hotplug utilizes sysfs entries for transferring 
+the firmware image from user space into the driver.
+
+The Intel(R) PRO/Wireless 2915ABG Driver for Linux exposes sysfs entries 
+at two levels -- driver level, which apply to all instances of the 
+driver (in the event that there are more than one device installed) and 
+device level, which applies only to the single specific instance.
+
+
+1.4.1 Driver Level Sysfs Helper Files
+-----------------------------------------------
+
+For the driver level files, look in /sys/bus/pci/drivers/ipw2200/
+
+  debug_level  
+       
+       This controls the same global as the 'debug' module parameter
+
+
+1.4.2 Device Level Sysfs Helper Files
+-----------------------------------------------
+
+For the device level files, look in
+       
+       /sys/bus/pci/drivers/ipw2200/{PCI-ID}/
+
+For example:
+       /sys/bus/pci/drivers/ipw2200/0000:02:01.0
+
+For the device level files, see /sys/bus/pci/[drivers/ipw2200:
+
+  rf_kill
+       read - 
+       0 = RF kill not enabled (radio on)
+       1 = SW based RF kill active (radio off)
+       2 = HW based RF kill active (radio off)
+       3 = Both HW and SW RF kill active (radio off)
+       write -
+       0 = If SW based RF kill active, turn the radio back on
+       1 = If radio is on, activate SW based RF kill
+
+       NOTE: If you enable the SW based RF kill and then toggle the HW
+       based RF kill from ON -> OFF -> ON, the radio will NOT come back on
+       
+  ucode 
+       read-only access to the ucode version number
+
+
+2.   About the Version Numbers
+-----------------------------------------------
+
+Due to the nature of open source development projects, there are 
+frequently changes being incorporated that have not gone through 
+a complete validation process.  These changes are incorporated into 
+development snapshot releases.
+
+Releases are numbered with a three level scheme: 
+
+       major.minor.development
+
+Any version where the 'development' portion is 0 (for example
+1.0.0, 1.1.0, etc.) indicates a stable version that will be made 
+available for kernel inclusion.
+
+Any version where the 'development' portion is not a 0 (for
+example 1.0.1, 1.1.5, etc.) indicates a development version that is
+being made available for testing and cutting edge users.  The stability 
+and functionality of the development releases are not know.  We make
+efforts to try and keep all snapshots reasonably stable, but due to the
+frequency of their release, and the desire to get those releases 
+available as quickly as possible, unknown anomalies should be expected.
+
+The major version number will be incremented when significant changes
+are made to the driver.  Currently, there are no major changes planned.
+
+
+3.  Support
+-----------------------------------------------
+
+For installation support of the 1.0.0 version, you can contact 
+http://supportmail.intel.com, or you can use the open source project 
+support.
+
+For general information and support, go to:
+       
+    http://ipw2200.sf.net/
+
+
+4.  License
+-----------------------------------------------
+
+  Copyright(c) 2003 - 2005 Intel Corporation. All rights reserved.
+
+  This program is free software; you can redistribute it and/or modify it 
+  under the terms of the GNU General Public License version 2 as 
+  published by the Free Software Foundation.
+  
+  This program is distributed in the hope that it will be useful, but WITHOUT 
+  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 
+  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for 
+  more details.
+  
+  You should have received a copy of the GNU General Public License along with
+  this program; if not, write to the Free Software Foundation, Inc., 59 
+  Temple Place - Suite 330, Boston, MA  02111-1307, USA.
+  
+  The full GNU General Public License is included in this distribution in the
+  file called LICENSE.
+  
+  Contact Information:
+  James P. Ketrenos <ipw2100-admin@linux.intel.com>
+  Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
+
+
index 30e8d589d167b58684ac6e786dc546991ac75d30..3dbb1cb09ed823d99c669a409f17f0b42570059b 100644 (file)
@@ -7,7 +7,7 @@
  * of the original driver such as link fail-over and link management because
  * those should be done at higher levels.
  *
- * Copyright (C) 2004, Stephen Hemminger <shemminger@osdl.org>
+ * Copyright (C) 2004, 2005 Stephen Hemminger <shemminger@osdl.org>
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
 #include "skge.h"
 
 #define DRV_NAME               "skge"
-#define DRV_VERSION            "0.6"
+#define DRV_VERSION            "0.7"
 #define PFX                    DRV_NAME " "
 
 #define DEFAULT_TX_RING_SIZE   128
 #define DEFAULT_RX_RING_SIZE   512
 #define MAX_TX_RING_SIZE       1024
 #define MAX_RX_RING_SIZE       4096
+#define RX_COPY_THRESHOLD      128
+#define RX_BUF_SIZE            1536
 #define PHY_RETRIES            1000
 #define ETH_JUMBO_MTU          9000
 #define TX_WATCHDOG            (5 * HZ)
 #define NAPI_WEIGHT            64
 #define BLINK_HZ               (HZ/4)
-#define LINK_POLL_HZ           (HZ/10)
 
 MODULE_DESCRIPTION("SysKonnect Gigabit Ethernet driver");
 MODULE_AUTHOR("Stephen Hemminger <shemminger@osdl.org>");
@@ -70,28 +71,17 @@ module_param(debug, int, 0);
 MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
 
 static const struct pci_device_id skge_id_table[] = {
-       { PCI_VENDOR_ID_3COM, PCI_DEVICE_ID_3COM_3C940,
-         PCI_ANY_ID, PCI_ANY_ID },
-       { PCI_VENDOR_ID_3COM, PCI_DEVICE_ID_3COM_3C940B,
-         PCI_ANY_ID, PCI_ANY_ID },
-       { PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_GE,
-         PCI_ANY_ID, PCI_ANY_ID },
-       { PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_YU,
-         PCI_ANY_ID, PCI_ANY_ID },
-       { PCI_VENDOR_ID_SYSKONNECT, 0x9E00, /* SK-9Exx  */
-         PCI_ANY_ID, PCI_ANY_ID },
-       { PCI_VENDOR_ID_DLINK, PCI_DEVICE_ID_DLINK_DGE510T,
-         PCI_ANY_ID, PCI_ANY_ID },
-       { PCI_VENDOR_ID_MARVELL, 0x4320, /* Gigabit Ethernet Controller */
-         PCI_ANY_ID, PCI_ANY_ID },
-       { PCI_VENDOR_ID_MARVELL, 0x5005, /* Marvell (11ab), Belkin */
-         PCI_ANY_ID, PCI_ANY_ID },
-       { PCI_VENDOR_ID_CNET, PCI_DEVICE_ID_CNET_GIGACARD,
-         PCI_ANY_ID, PCI_ANY_ID },
-       { PCI_VENDOR_ID_LINKSYS, PCI_DEVICE_ID_LINKSYS_EG1032,
-         PCI_ANY_ID, PCI_ANY_ID },
-       { PCI_VENDOR_ID_LINKSYS, PCI_DEVICE_ID_LINKSYS_EG1064,
-         PCI_ANY_ID, PCI_ANY_ID },
+       { PCI_DEVICE(PCI_VENDOR_ID_3COM, PCI_DEVICE_ID_3COM_3C940) },
+       { PCI_DEVICE(PCI_VENDOR_ID_3COM, PCI_DEVICE_ID_3COM_3C940B) },
+       { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_GE) },
+       { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_YU) },
+       { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, 0x9E00) }, /* SK-9Exx  */
+       { PCI_DEVICE(PCI_VENDOR_ID_DLINK, PCI_DEVICE_ID_DLINK_DGE510T), },
+       { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4320) },
+       { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x5005) }, /* Belkin */
+       { PCI_DEVICE(PCI_VENDOR_ID_CNET, PCI_DEVICE_ID_CNET_GIGACARD) },
+       { PCI_DEVICE(PCI_VENDOR_ID_LINKSYS, PCI_DEVICE_ID_LINKSYS_EG1032) },
+       { PCI_DEVICE(PCI_VENDOR_ID_LINKSYS, PCI_DEVICE_ID_LINKSYS_EG1064) },
        { 0 }
 };
 MODULE_DEVICE_TABLE(pci, skge_id_table);
@@ -99,19 +89,22 @@ MODULE_DEVICE_TABLE(pci, skge_id_table);
 static int skge_up(struct net_device *dev);
 static int skge_down(struct net_device *dev);
 static void skge_tx_clean(struct skge_port *skge);
-static void skge_xm_phy_write(struct skge_hw *hw, int port, u16 reg, u16 val);
-static void skge_gm_phy_write(struct skge_hw *hw, int port, u16 reg, u16 val);
+static void xm_phy_write(struct skge_hw *hw, int port, u16 reg, u16 val);
+static void gm_phy_write(struct skge_hw *hw, int port, u16 reg, u16 val);
 static void genesis_get_stats(struct skge_port *skge, u64 *data);
 static void yukon_get_stats(struct skge_port *skge, u64 *data);
 static void yukon_init(struct skge_hw *hw, int port);
 static void yukon_reset(struct skge_hw *hw, int port);
 static void genesis_mac_init(struct skge_hw *hw, int port);
 static void genesis_reset(struct skge_hw *hw, int port);
+static void genesis_link_up(struct skge_port *skge);
 
+/* Avoid conditionals by using array */
 static const int txqaddr[] = { Q_XA1, Q_XA2 };
 static const int rxqaddr[] = { Q_R1, Q_R2 };
 static const u32 rxirqmask[] = { IS_R1_F, IS_R2_F };
 static const u32 txirqmask[] = { IS_XA1_F, IS_XA2_F };
+static const u32 portirqmask[] = { IS_PORT_1, IS_PORT_2 };
 
 /* Don't need to look at whole 16K.
  * last interesting register is descriptor poll timer.
@@ -154,7 +147,7 @@ static void skge_get_regs(struct net_device *dev, struct ethtool_regs *regs,
 static int wol_supported(const struct skge_hw *hw)
 {
        return !((hw->chip_id == CHIP_ID_GENESIS ||
-                 (hw->chip_id == CHIP_ID_YUKON && chip_rev(hw) == 0)));
+                 (hw->chip_id == CHIP_ID_YUKON && hw->chip_rev == 0)));
 }
 
 static void skge_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
@@ -170,7 +163,7 @@ static int skge_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
        struct skge_port *skge = netdev_priv(dev);
        struct skge_hw *hw = skge->hw;
 
-       if(wol->wolopts != WAKE_MAGIC && wol->wolopts != 0)
+       if (wol->wolopts != WAKE_MAGIC && wol->wolopts != 0)
                return -EOPNOTSUPP;
 
        if (wol->wolopts == WAKE_MAGIC && !wol_supported(hw))
@@ -190,6 +183,36 @@ static int skge_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
        return 0;
 }
 
+/* Determine supported/adverised modes based on hardware.
+ * Note: ethtoool ADVERTISED_xxx == SUPPORTED_xxx
+ */
+static u32 skge_supported_modes(const struct skge_hw *hw)
+{
+       u32 supported;
+
+       if (iscopper(hw)) {
+               supported = SUPPORTED_10baseT_Half
+                       | SUPPORTED_10baseT_Full
+                       | SUPPORTED_100baseT_Half
+                       | SUPPORTED_100baseT_Full
+                       | SUPPORTED_1000baseT_Half
+                       | SUPPORTED_1000baseT_Full
+                       | SUPPORTED_Autoneg| SUPPORTED_TP;
+
+               if (hw->chip_id == CHIP_ID_GENESIS)
+                       supported &= ~(SUPPORTED_10baseT_Half
+                                            | SUPPORTED_10baseT_Full
+                                            | SUPPORTED_100baseT_Half
+                                            | SUPPORTED_100baseT_Full);
+
+               else if (hw->chip_id == CHIP_ID_YUKON)
+                       supported &= ~SUPPORTED_1000baseT_Half;
+       } else
+               supported = SUPPORTED_1000baseT_Full | SUPPORTED_FIBRE
+                       | SUPPORTED_Autoneg;
+
+       return supported;
+}
 
 static int skge_get_settings(struct net_device *dev,
                             struct ethtool_cmd *ecmd)
@@ -198,38 +221,13 @@ static int skge_get_settings(struct net_device *dev,
        struct skge_hw *hw = skge->hw;
 
        ecmd->transceiver = XCVR_INTERNAL;
+       ecmd->supported = skge_supported_modes(hw);
 
        if (iscopper(hw)) {
-               if (hw->chip_id == CHIP_ID_GENESIS)
-                       ecmd->supported = SUPPORTED_1000baseT_Full
-                               | SUPPORTED_1000baseT_Half
-                               | SUPPORTED_Autoneg | SUPPORTED_TP;
-               else {
-                       ecmd->supported = SUPPORTED_10baseT_Half
-                               | SUPPORTED_10baseT_Full
-                               | SUPPORTED_100baseT_Half
-                               | SUPPORTED_100baseT_Full
-                               | SUPPORTED_1000baseT_Half
-                               | SUPPORTED_1000baseT_Full
-                               | SUPPORTED_Autoneg| SUPPORTED_TP;
-
-                       if (hw->chip_id == CHIP_ID_YUKON)
-                               ecmd->supported &= ~SUPPORTED_1000baseT_Half;
-
-                       else if (hw->chip_id == CHIP_ID_YUKON_FE)
-                               ecmd->supported &= ~(SUPPORTED_1000baseT_Half
-                                                    | SUPPORTED_1000baseT_Full);
-               }
-
                ecmd->port = PORT_TP;
                ecmd->phy_address = hw->phy_addr;
-       } else {
-               ecmd->supported = SUPPORTED_1000baseT_Full
-                       | SUPPORTED_FIBRE
-                       | SUPPORTED_Autoneg;
-
+       } else
                ecmd->port = PORT_FIBRE;
-       }
 
        ecmd->advertising = skge->advertising;
        ecmd->autoneg = skge->autoneg;
@@ -238,65 +236,57 @@ static int skge_get_settings(struct net_device *dev,
        return 0;
 }
 
-static u32 skge_modes(const struct skge_hw *hw)
-{
-       u32 modes = ADVERTISED_Autoneg
-               | ADVERTISED_1000baseT_Full | ADVERTISED_1000baseT_Half
-               | ADVERTISED_100baseT_Full | ADVERTISED_100baseT_Half
-               | ADVERTISED_10baseT_Full | ADVERTISED_10baseT_Half;
-
-       if (iscopper(hw)) {
-               modes |= ADVERTISED_TP;
-               switch(hw->chip_id) {
-               case CHIP_ID_GENESIS:
-                       modes &= ~(ADVERTISED_100baseT_Full
-                                  | ADVERTISED_100baseT_Half
-                                  | ADVERTISED_10baseT_Full
-                                  | ADVERTISED_10baseT_Half);
-                       break;
-
-               case CHIP_ID_YUKON:
-                       modes &= ~ADVERTISED_1000baseT_Half;
-                       break;
-
-               case CHIP_ID_YUKON_FE:
-                       modes &= ~(ADVERTISED_1000baseT_Half|ADVERTISED_1000baseT_Full);
-                       break;
-               }
-       } else {
-               modes |= ADVERTISED_FIBRE;
-               modes &= ~ADVERTISED_1000baseT_Half;
-       }
-       return modes;
-}
-
 static int skge_set_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
 {
        struct skge_port *skge = netdev_priv(dev);
        const struct skge_hw *hw = skge->hw;
+       u32 supported = skge_supported_modes(hw);
 
        if (ecmd->autoneg == AUTONEG_ENABLE) {
-               if (ecmd->advertising & skge_modes(hw))
-                       return -EINVAL;
+               ecmd->advertising = supported;
+               skge->duplex = -1;
+               skge->speed = -1;
        } else {
+               u32 setting;
+
                switch(ecmd->speed) {
                case SPEED_1000:
-                       if (hw->chip_id == CHIP_ID_YUKON_FE)
+                       if (ecmd->duplex == DUPLEX_FULL)
+                               setting = SUPPORTED_1000baseT_Full;
+                       else if (ecmd->duplex == DUPLEX_HALF)
+                               setting = SUPPORTED_1000baseT_Half;
+                       else
                                return -EINVAL;
                        break;
                case SPEED_100:
+                       if (ecmd->duplex == DUPLEX_FULL)
+                               setting = SUPPORTED_100baseT_Full;
+                       else if (ecmd->duplex == DUPLEX_HALF)
+                               setting = SUPPORTED_100baseT_Half;
+                       else
+                               return -EINVAL;
+                       break;
+
                case SPEED_10:
-                       if (iscopper(hw) || hw->chip_id == CHIP_ID_GENESIS)
+                       if (ecmd->duplex == DUPLEX_FULL)
+                               setting = SUPPORTED_10baseT_Full;
+                       else if (ecmd->duplex == DUPLEX_HALF)
+                               setting = SUPPORTED_10baseT_Half;
+                       else
                                return -EINVAL;
                        break;
                default:
                        return -EINVAL;
                }
+
+               if ((setting & supported) == 0)
+                       return -EINVAL;
+
+               skge->speed = ecmd->speed;
+               skge->duplex = ecmd->duplex;
        }
 
        skge->autoneg = ecmd->autoneg;
-       skge->speed = ecmd->speed;
-       skge->duplex = ecmd->duplex;
        skge->advertising = ecmd->advertising;
 
        if (netif_running(dev)) {
@@ -393,7 +383,7 @@ static void skge_get_strings(struct net_device *dev, u32 stringset, u8 *data)
 {
        int i;
 
-       switch(stringset) {
+       switch (stringset) {
        case ETH_SS_STATS:
                for (i = 0; i < ARRAY_SIZE(skge_stats); i++)
                        memcpy(data + i * ETH_GSTRING_LEN,
@@ -511,14 +501,6 @@ static int skge_set_rx_csum(struct net_device *dev, u32 data)
        return 0;
 }
 
-/* Only Yukon II supports TSO (not implemented yet) */
-static int skge_set_tso(struct net_device *dev, u32 data)
-{
-       if (data)
-               return -EOPNOTSUPP;
-       return 0;
-}
-
 static void skge_get_pauseparam(struct net_device *dev,
                                struct ethtool_pauseparam *ecmd)
 {
@@ -540,9 +522,9 @@ static int skge_set_pauseparam(struct net_device *dev,
        skge->autoneg = ecmd->autoneg;
        if (ecmd->rx_pause && ecmd->tx_pause)
                skge->flow_control = FLOW_MODE_SYMMETRIC;
-       else if(ecmd->rx_pause && !ecmd->tx_pause)
+       else if (ecmd->rx_pause && !ecmd->tx_pause)
                skge->flow_control = FLOW_MODE_REM_SEND;
-       else if(!ecmd->rx_pause && ecmd->tx_pause)
+       else if (!ecmd->rx_pause && ecmd->tx_pause)
                skge->flow_control = FLOW_MODE_LOC_SEND;
        else
                skge->flow_control = FLOW_MODE_NONE;
@@ -559,8 +541,6 @@ static inline u32 hwkhz(const struct skge_hw *hw)
 {
        if (hw->chip_id == CHIP_ID_GENESIS)
                return 53215; /* or:  53.125 MHz */
-       else if (hw->chip_id == CHIP_ID_YUKON_EC)
-               return 125000; /* or: 125.000 MHz */
        else
                return 78215; /* or:  78.125 MHz */
 }
@@ -643,30 +623,18 @@ static int skge_set_coalesce(struct net_device *dev,
 static void skge_led_on(struct skge_hw *hw, int port)
 {
        if (hw->chip_id == CHIP_ID_GENESIS) {
-               skge_write8(hw, SKGEMAC_REG(port, LNK_LED_REG), LINKLED_ON);
+               skge_write8(hw, SK_REG(port, LNK_LED_REG), LINKLED_ON);
                skge_write8(hw, B0_LED, LED_STAT_ON);
 
-               skge_write8(hw, SKGEMAC_REG(port, RX_LED_TST), LED_T_ON);
-               skge_write32(hw, SKGEMAC_REG(port, RX_LED_VAL), 100);
-               skge_write8(hw, SKGEMAC_REG(port, RX_LED_CTRL), LED_START);
+               skge_write8(hw, SK_REG(port, RX_LED_TST), LED_T_ON);
+               skge_write32(hw, SK_REG(port, RX_LED_VAL), 100);
+               skge_write8(hw, SK_REG(port, RX_LED_CTRL), LED_START);
 
-               switch (hw->phy_type) {
-               case SK_PHY_BCOM:
-                       skge_xm_phy_write(hw, port, PHY_BCOM_P_EXT_CTRL,
-                                         PHY_B_PEC_LED_ON);
-                       break;
-               case SK_PHY_LONE:
-                       skge_xm_phy_write(hw, port, PHY_LONE_LED_CFG,
-                                         0x0800);
-                       break;
-               default:
-                       skge_write8(hw, SKGEMAC_REG(port, TX_LED_TST), LED_T_ON);
-                       skge_write32(hw, SKGEMAC_REG(port, TX_LED_VAL), 100);
-                       skge_write8(hw, SKGEMAC_REG(port, TX_LED_CTRL), LED_START);
-               }
+               /* For Broadcom Phy only */
+               xm_phy_write(hw, port, PHY_BCOM_P_EXT_CTRL, PHY_B_PEC_LED_ON);
        } else {
-               skge_gm_phy_write(hw, port, PHY_MARV_LED_CTRL, 0);
-               skge_gm_phy_write(hw, port, PHY_MARV_LED_OVER,
+               gm_phy_write(hw, port, PHY_MARV_LED_CTRL, 0);
+               gm_phy_write(hw, port, PHY_MARV_LED_OVER,
                                  PHY_M_LED_MO_DUP(MO_LED_ON)  |
                                  PHY_M_LED_MO_10(MO_LED_ON)   |
                                  PHY_M_LED_MO_100(MO_LED_ON)  |
@@ -678,28 +646,17 @@ static void skge_led_on(struct skge_hw *hw, int port)
 static void skge_led_off(struct skge_hw *hw, int port)
 {
        if (hw->chip_id == CHIP_ID_GENESIS) {
-               skge_write8(hw, SKGEMAC_REG(port, LNK_LED_REG), LINKLED_OFF);
+               skge_write8(hw, SK_REG(port, LNK_LED_REG), LINKLED_OFF);
                skge_write8(hw, B0_LED, LED_STAT_OFF);
 
-               skge_write32(hw, SKGEMAC_REG(port, RX_LED_VAL), 0);
-               skge_write8(hw, SKGEMAC_REG(port, RX_LED_CTRL), LED_T_OFF);
+               skge_write32(hw, SK_REG(port, RX_LED_VAL), 0);
+               skge_write8(hw, SK_REG(port, RX_LED_CTRL), LED_T_OFF);
 
-               switch (hw->phy_type) {
-               case SK_PHY_BCOM:
-                       skge_xm_phy_write(hw, port, PHY_BCOM_P_EXT_CTRL,
-                                         PHY_B_PEC_LED_OFF);
-                       break;
-               case SK_PHY_LONE:
-                       skge_xm_phy_write(hw, port, PHY_LONE_LED_CFG,
-                                         PHY_L_LC_LEDT);
-                       break;
-               default:
-                       skge_write32(hw, SKGEMAC_REG(port, TX_LED_VAL), 0);
-                       skge_write8(hw, SKGEMAC_REG(port, TX_LED_CTRL), LED_T_OFF);
-               }
+               /* Broadcom only */
+               xm_phy_write(hw, port, PHY_BCOM_P_EXT_CTRL, PHY_B_PEC_LED_OFF);
        } else {
-               skge_gm_phy_write(hw, port, PHY_MARV_LED_CTRL, 0);
-               skge_gm_phy_write(hw, port, PHY_MARV_LED_OVER,
+               gm_phy_write(hw, port, PHY_MARV_LED_CTRL, 0);
+               gm_phy_write(hw, port, PHY_MARV_LED_OVER,
                                  PHY_M_LED_MO_DUP(MO_LED_OFF)  |
                                  PHY_M_LED_MO_10(MO_LED_OFF)   |
                                  PHY_M_LED_MO_100(MO_LED_OFF)  |
@@ -730,7 +687,7 @@ static int skge_phys_id(struct net_device *dev, u32 data)
 {
        struct skge_port *skge = netdev_priv(dev);
 
-       if(!data || data > (u32)(MAX_SCHEDULE_TIMEOUT / HZ))
+       if (!data || data > (u32)(MAX_SCHEDULE_TIMEOUT / HZ))
                data = (u32)(MAX_SCHEDULE_TIMEOUT / HZ);
 
        /* start blinking */
@@ -763,8 +720,6 @@ static struct ethtool_ops skge_ethtool_ops = {
        .set_pauseparam = skge_set_pauseparam,
        .get_coalesce   = skge_get_coalesce,
        .set_coalesce   = skge_set_coalesce,
-       .get_tso        = ethtool_op_get_tso,
-       .set_tso        = skge_set_tso,
        .get_sg         = ethtool_op_get_sg,
        .set_sg         = skge_set_sg,
        .get_tx_csum    = ethtool_op_get_tx_csum,
@@ -793,6 +748,7 @@ static int skge_ring_alloc(struct skge_ring *ring, void *vaddr, u64 base)
 
        for (i = 0, e = ring->start, d = vaddr; i < ring->count; i++, e++, d++) {
                e->desc = d;
+               e->skb = NULL;
                if (i == ring->count - 1) {
                        e->next = ring->start;
                        d->next_offset = base;
@@ -806,24 +762,23 @@ static int skge_ring_alloc(struct skge_ring *ring, void *vaddr, u64 base)
        return 0;
 }
 
-/* Setup buffer for receiving */
-static inline int skge_rx_alloc(struct skge_port *skge,
-                               struct skge_element *e)
+static struct sk_buff *skge_rx_alloc(struct net_device *dev, unsigned int size)
 {
-       unsigned long bufsize = skge->netdev->mtu + ETH_HLEN; /* VLAN? */
-       struct skge_rx_desc *rd = e->desc;
-       struct sk_buff *skb;
-       u64 map;
+       struct sk_buff *skb = dev_alloc_skb(size);
 
-       skb = dev_alloc_skb(bufsize + NET_IP_ALIGN);
-       if (unlikely(!skb)) {
-               printk(KERN_DEBUG PFX "%s: out of memory for receive\n",
-                      skge->netdev->name);
-               return -ENOMEM;
+       if (likely(skb)) {
+               skb->dev = dev;
+               skb_reserve(skb, NET_IP_ALIGN);
        }
+       return skb;
+}
 
-       skb->dev = skge->netdev;
-       skb_reserve(skb, NET_IP_ALIGN);
+/* Allocate and setup a new buffer for receiving */
+static void skge_rx_setup(struct skge_port *skge, struct skge_element *e,
+                         struct sk_buff *skb, unsigned int bufsize)
+{
+       struct skge_rx_desc *rd = e->desc;
+       u64 map;
 
        map = pci_map_single(skge->hw->pdev, skb->data, bufsize,
                             PCI_DMA_FROMDEVICE);
@@ -841,55 +796,69 @@ static inline int skge_rx_alloc(struct skge_port *skge,
        rd->control = BMU_OWN | BMU_STF | BMU_IRQ_EOF | BMU_TCP_CHECK | bufsize;
        pci_unmap_addr_set(e, mapaddr, map);
        pci_unmap_len_set(e, maplen, bufsize);
-       return 0;
 }
 
-/* Free all unused buffers in receive ring, assumes receiver stopped */
+/* Resume receiving using existing skb,
+ * Note: DMA address is not changed by chip.
+ *      MTU not changed while receiver active.
+ */
+static void skge_rx_reuse(struct skge_element *e, unsigned int size)
+{
+       struct skge_rx_desc *rd = e->desc;
+
+       rd->csum2 = 0;
+       rd->csum2_start = ETH_HLEN;
+
+       wmb();
+
+       rd->control = BMU_OWN | BMU_STF | BMU_IRQ_EOF | BMU_TCP_CHECK | size;
+}
+
+
+/* Free all  buffers in receive ring, assumes receiver stopped */
 static void skge_rx_clean(struct skge_port *skge)
 {
        struct skge_hw *hw = skge->hw;
        struct skge_ring *ring = &skge->rx_ring;
        struct skge_element *e;
 
-       for (e = ring->to_clean; e != ring->to_use; e = e->next) {
+       e = ring->start;
+       do {
                struct skge_rx_desc *rd = e->desc;
                rd->control = 0;
-
-               pci_unmap_single(hw->pdev,
-                                pci_unmap_addr(e, mapaddr),
-                                pci_unmap_len(e, maplen),
-                                PCI_DMA_FROMDEVICE);
-               dev_kfree_skb(e->skb);
-               e->skb = NULL;
-       }
-       ring->to_clean = e;
+               if (e->skb) {
+                       pci_unmap_single(hw->pdev,
+                                        pci_unmap_addr(e, mapaddr),
+                                        pci_unmap_len(e, maplen),
+                                        PCI_DMA_FROMDEVICE);
+                       dev_kfree_skb(e->skb);
+                       e->skb = NULL;
+               }
+       } while ((e = e->next) != ring->start);
 }
 
+
 /* Allocate buffers for receive ring
- * For receive: to_use   is refill location
- *              to_clean is next received frame.
- *
- * if (to_use == to_clean)
- *      then ring all frames in ring need buffers
- * if (to_use->next == to_clean)
- *      then ring all frames in ring have buffers
+ * For receive:  to_clean is next received frame.
  */
 static int skge_rx_fill(struct skge_port *skge)
 {
        struct skge_ring *ring = &skge->rx_ring;
        struct skge_element *e;
-       int ret = 0;
+       unsigned int bufsize = skge->rx_buf_size;
 
-       for (e = ring->to_use; e->next != ring->to_clean; e = e->next) {
-               if (skge_rx_alloc(skge, e)) {
-                       ret = 1;
-                       break;
-               }
+       e = ring->start;
+       do {
+               struct sk_buff *skb = skge_rx_alloc(skge->netdev, bufsize);
 
-       }
-       ring->to_use = e;
+               if (!skb)
+                       return -ENOMEM;
+
+               skge_rx_setup(skge, e, skb, bufsize);
+       } while ( (e = e->next) != ring->start);
 
-       return ret;
+       ring->to_clean = ring->start;
+       return 0;
 }
 
 static void skge_link_up(struct skge_port *skge)
@@ -919,50 +888,50 @@ static void skge_link_down(struct skge_port *skge)
                printk(KERN_INFO PFX "%s: Link is down.\n", skge->netdev->name);
 }
 
-static u16 skge_xm_phy_read(struct skge_hw *hw, int port,  u16 reg)
+static u16 xm_phy_read(struct skge_hw *hw, int port, u16 reg)
 {
        int i;
        u16 v;
 
-       skge_xm_write16(hw, port, XM_PHY_ADDR, reg | hw->phy_addr);
-       v = skge_xm_read16(hw, port, XM_PHY_DATA);
-       if (hw->phy_type != SK_PHY_XMAC) {
-               for (i = 0; i < PHY_RETRIES; i++) {
-                       udelay(1);
-                       if (skge_xm_read16(hw, port, XM_MMU_CMD)
-                           & XM_MMU_PHY_RDY)
-                               goto ready;
-               }
+       xm_write16(hw, port, XM_PHY_ADDR, reg | hw->phy_addr);
+       v = xm_read16(hw, port, XM_PHY_DATA);
 
-               printk(KERN_WARNING PFX "%s: phy read timed out\n",
-                      hw->dev[port]->name);
-               return 0;
-       ready:
-               v = skge_xm_read16(hw, port, XM_PHY_DATA);
+       /* Need to wait for external PHY */
+       for (i = 0; i < PHY_RETRIES; i++) {
+               udelay(1);
+               if (xm_read16(hw, port, XM_MMU_CMD)
+                   & XM_MMU_PHY_RDY)
+                       goto ready;
        }
 
+       printk(KERN_WARNING PFX "%s: phy read timed out\n",
+              hw->dev[port]->name);
+       return 0;
+ ready:
+       v = xm_read16(hw, port, XM_PHY_DATA);
+
        return v;
 }
 
-static void skge_xm_phy_write(struct skge_hw *hw, int port, u16 reg, u16 val)
+static void xm_phy_write(struct skge_hw *hw, int port, u16 reg, u16 val)
 {
        int i;
 
-       skge_xm_write16(hw, port, XM_PHY_ADDR, reg | hw->phy_addr);
+       xm_write16(hw, port, XM_PHY_ADDR, reg | hw->phy_addr);
        for (i = 0; i < PHY_RETRIES; i++) {
-               if (!(skge_xm_read16(hw, port, XM_MMU_CMD) & XM_MMU_PHY_BUSY))
+               if (!(xm_read16(hw, port, XM_MMU_CMD) & XM_MMU_PHY_BUSY))
                        goto ready;
-               cpu_relax();
+               udelay(1);
        }
        printk(KERN_WARNING PFX "%s: phy write failed to come ready\n",
               hw->dev[port]->name);
 
 
  ready:
-       skge_xm_write16(hw, port, XM_PHY_DATA, val);
+       xm_write16(hw, port, XM_PHY_DATA, val);
        for (i = 0; i < PHY_RETRIES; i++) {
                udelay(1);
-               if (!(skge_xm_read16(hw, port, XM_MMU_CMD) & XM_MMU_PHY_BUSY))
+               if (!(xm_read16(hw, port, XM_MMU_CMD) & XM_MMU_PHY_BUSY))
                        return;
        }
        printk(KERN_WARNING PFX "%s: phy write timed out\n",
@@ -999,34 +968,112 @@ static void genesis_init(struct skge_hw *hw)
 
 static void genesis_reset(struct skge_hw *hw, int port)
 {
-       int i;
-       u64 zero = 0;
+       const u8 zero[8]  = { 0 };
 
        /* reset the statistics module */
-       skge_xm_write32(hw, port, XM_GP_PORT, XM_GP_RES_STAT);
-       skge_xm_write16(hw, port, XM_IMSK, 0xffff);     /* disable XMAC IRQs */
-       skge_xm_write32(hw, port, XM_MODE, 0);          /* clear Mode Reg */
-       skge_xm_write16(hw, port, XM_TX_CMD, 0);        /* reset TX CMD Reg */
-       skge_xm_write16(hw, port, XM_RX_CMD, 0);        /* reset RX CMD Reg */
+       xm_write32(hw, port, XM_GP_PORT, XM_GP_RES_STAT);
+       xm_write16(hw, port, XM_IMSK, 0xffff);  /* disable XMAC IRQs */
+       xm_write32(hw, port, XM_MODE, 0);               /* clear Mode Reg */
+       xm_write16(hw, port, XM_TX_CMD, 0);     /* reset TX CMD Reg */
+       xm_write16(hw, port, XM_RX_CMD, 0);     /* reset RX CMD Reg */
 
-       /* disable all PHY IRQs */
-       if  (hw->phy_type == SK_PHY_BCOM)
-               skge_xm_write16(hw, port, PHY_BCOM_INT_MASK, 0xffff);
+       /* disable Broadcom PHY IRQ */
+       xm_write16(hw, port, PHY_BCOM_INT_MASK, 0xffff);
 
-       skge_xm_outhash(hw, port, XM_HSM, (u8 *) &zero);
-       for (i = 0; i < 15; i++)
-               skge_xm_outaddr(hw, port, XM_EXM(i), (u8 *) &zero);
-       skge_xm_outhash(hw, port, XM_SRC_CHK, (u8 *) &zero);
+       xm_outhash(hw, port, XM_HSM, zero);
 }
 
 
-static void genesis_mac_init(struct skge_hw *hw, int port)
+/* Convert mode to MII values  */
+static const u16 phy_pause_map[] = {
+       [FLOW_MODE_NONE] =      0,
+       [FLOW_MODE_LOC_SEND] =  PHY_AN_PAUSE_ASYM,
+       [FLOW_MODE_SYMMETRIC] = PHY_AN_PAUSE_CAP,
+       [FLOW_MODE_REM_SEND]  = PHY_AN_PAUSE_CAP | PHY_AN_PAUSE_ASYM,
+};
+
+
+/* Check status of Broadcom phy link */
+static void bcom_check_link(struct skge_hw *hw, int port)
 {
-       struct skge_port *skge = netdev_priv(hw->dev[port]);
+       struct net_device *dev = hw->dev[port];
+       struct skge_port *skge = netdev_priv(dev);
+       u16 status;
+
+       /* read twice because of latch */
+       (void) xm_phy_read(hw, port, PHY_BCOM_STAT);
+       status = xm_phy_read(hw, port, PHY_BCOM_STAT);
+
+       pr_debug("bcom_check_link status=0x%x\n", status);
+
+       if ((status & PHY_ST_LSYNC) == 0) {
+               u16 cmd = xm_read16(hw, port, XM_MMU_CMD);
+               cmd &= ~(XM_MMU_ENA_RX | XM_MMU_ENA_TX);
+               xm_write16(hw, port, XM_MMU_CMD, cmd);
+               /* dummy read to ensure writing */
+               (void) xm_read16(hw, port, XM_MMU_CMD);
+
+               if (netif_carrier_ok(dev))
+                       skge_link_down(skge);
+       } else {
+               if (skge->autoneg == AUTONEG_ENABLE &&
+                   (status & PHY_ST_AN_OVER)) {
+                       u16 lpa = xm_phy_read(hw, port, PHY_BCOM_AUNE_LP);
+                       u16 aux = xm_phy_read(hw, port, PHY_BCOM_AUX_STAT);
+
+                       if (lpa & PHY_B_AN_RF) {
+                               printk(KERN_NOTICE PFX "%s: remote fault\n",
+                                      dev->name);
+                               return;
+                       }
+
+                       /* Check Duplex mismatch */
+                       switch(aux & PHY_B_AS_AN_RES_MSK) {
+                       case PHY_B_RES_1000FD:
+                               skge->duplex = DUPLEX_FULL;
+                               break;
+                       case PHY_B_RES_1000HD:
+                               skge->duplex = DUPLEX_HALF;
+                               break;
+                       default:
+                               printk(KERN_NOTICE PFX "%s: duplex mismatch\n",
+                                      dev->name);
+                               return;
+                       }
+
+
+                       /* We are using IEEE 802.3z/D5.0 Table 37-4 */
+                       switch (aux & PHY_B_AS_PAUSE_MSK) {
+                       case PHY_B_AS_PAUSE_MSK:
+                               skge->flow_control = FLOW_MODE_SYMMETRIC;
+                               break;
+                       case PHY_B_AS_PRR:
+                               skge->flow_control = FLOW_MODE_REM_SEND;
+                               break;
+                       case PHY_B_AS_PRT:
+                               skge->flow_control = FLOW_MODE_LOC_SEND;
+                               break;
+                       default:
+                               skge->flow_control = FLOW_MODE_NONE;
+                       }
+
+                       skge->speed = SPEED_1000;
+               }
+
+               if (!netif_carrier_ok(dev))
+                       genesis_link_up(skge);
+       }
+}
+
+/* Broadcom 5400 only supports giagabit! SysKonnect did not put an additional
+ * Phy on for 100 or 10Mbit operation
+ */
+static void bcom_phy_init(struct skge_port *skge, int jumbo)
+{
+       struct skge_hw *hw = skge->hw;
+       int port = skge->port;
        int i;
-       u32 r;
-       u16 id1;
-       u16 ctrl1, ctrl2, ctrl3, ctrl4, ctrl5;
+       u16 id1, r, ext, ctl;
 
        /* magic workaround patterns for Broadcom */
        static const struct {
@@ -1042,16 +1089,120 @@ static void genesis_mac_init(struct skge_hw *hw, int port)
                { 0x17, 0x0013 }, { 0x15, 0x0A04 }, { 0x18, 0x0420 },
        };
 
+       pr_debug("bcom_phy_init\n");
+
+       /* read Id from external PHY (all have the same address) */
+       id1 = xm_phy_read(hw, port, PHY_XMAC_ID1);
+
+       /* Optimize MDIO transfer by suppressing preamble. */
+       r = xm_read16(hw, port, XM_MMU_CMD);
+       r |=  XM_MMU_NO_PRE;
+       xm_write16(hw, port, XM_MMU_CMD,r);
+
+       switch(id1) {
+       case PHY_BCOM_ID1_C0:
+               /*
+                * Workaround BCOM Errata for the C0 type.
+                * Write magic patterns to reserved registers.
+                */
+               for (i = 0; i < ARRAY_SIZE(C0hack); i++)
+                       xm_phy_write(hw, port,
+                                    C0hack[i].reg, C0hack[i].val);
+
+               break;
+       case PHY_BCOM_ID1_A1:
+               /*
+                * Workaround BCOM Errata for the A1 type.
+                * Write magic patterns to reserved registers.
+                */
+               for (i = 0; i < ARRAY_SIZE(A1hack); i++)
+                       xm_phy_write(hw, port,
+                                    A1hack[i].reg, A1hack[i].val);
+               break;
+       }
+
+       /*
+        * Workaround BCOM Errata (#10523) for all BCom PHYs.
+        * Disable Power Management after reset.
+        */
+       r = xm_phy_read(hw, port, PHY_BCOM_AUX_CTRL);
+       r |= PHY_B_AC_DIS_PM;
+       xm_phy_write(hw, port, PHY_BCOM_AUX_CTRL, r);
+
+       /* Dummy read */
+       xm_read16(hw, port, XM_ISRC);
+
+       ext = PHY_B_PEC_EN_LTR; /* enable tx led */
+       ctl = PHY_CT_SP1000;    /* always 1000mbit */
+
+       if (skge->autoneg == AUTONEG_ENABLE) {
+               /*
+                * Workaround BCOM Errata #1 for the C5 type.
+                * 1000Base-T Link Acquisition Failure in Slave Mode
+                * Set Repeater/DTE bit 10 of the 1000Base-T Control Register
+                */
+               u16 adv = PHY_B_1000C_RD;
+               if (skge->advertising & ADVERTISED_1000baseT_Half)
+                       adv |= PHY_B_1000C_AHD;
+               if (skge->advertising & ADVERTISED_1000baseT_Full)
+                       adv |= PHY_B_1000C_AFD;
+               xm_phy_write(hw, port, PHY_BCOM_1000T_CTRL, adv);
+
+               ctl |= PHY_CT_ANE | PHY_CT_RE_CFG;
+       } else {
+               if (skge->duplex == DUPLEX_FULL)
+                       ctl |= PHY_CT_DUP_MD;
+               /* Force to slave */
+               xm_phy_write(hw, port, PHY_BCOM_1000T_CTRL, PHY_B_1000C_MSE);
+       }
+
+       /* Set autonegotiation pause parameters */
+       xm_phy_write(hw, port, PHY_BCOM_AUNE_ADV,
+                    phy_pause_map[skge->flow_control] | PHY_AN_CSMA);
+
+       /* Handle Jumbo frames */
+       if (jumbo) {
+               xm_phy_write(hw, port, PHY_BCOM_AUX_CTRL,
+                            PHY_B_AC_TX_TST | PHY_B_AC_LONG_PACK);
+
+               ext |= PHY_B_PEC_HIGH_LA;
+
+       }
+
+       xm_phy_write(hw, port, PHY_BCOM_P_EXT_CTRL, ext);
+       xm_phy_write(hw, port, PHY_BCOM_CTRL, ctl);
+
+       /* Use link status change interrrupt */
+       xm_phy_write(hw, port, PHY_BCOM_INT_MASK, PHY_B_DEF_MSK);
+
+       bcom_check_link(hw, port);
+}
+
+static void genesis_mac_init(struct skge_hw *hw, int port)
+{
+       struct net_device *dev = hw->dev[port];
+       struct skge_port *skge = netdev_priv(dev);
+       int jumbo = hw->dev[port]->mtu > ETH_DATA_LEN;
+       int i;
+       u32 r;
+       const u8 zero[6]  = { 0 };
+
+       /* Clear MIB counters */
+       xm_write16(hw, port, XM_STAT_CMD,
+                       XM_SC_CLR_RXC | XM_SC_CLR_TXC);
+       /* Clear two times according to Errata #3 */
+       xm_write16(hw, port, XM_STAT_CMD,
+                       XM_SC_CLR_RXC | XM_SC_CLR_TXC);
 
        /* initialize Rx, Tx and Link LED */
-       skge_write8(hw, SKGEMAC_REG(port, LNK_LED_REG), LINKLED_ON);
-       skge_write8(hw, SKGEMAC_REG(port, LNK_LED_REG), LINKLED_LINKSYNC_ON);
+       skge_write8(hw, SK_REG(port, LNK_LED_REG), LINKLED_ON);
+       skge_write8(hw, SK_REG(port, LNK_LED_REG), LINKLED_LINKSYNC_ON);
 
-       skge_write8(hw, SKGEMAC_REG(port, RX_LED_CTRL), LED_START);
-       skge_write8(hw, SKGEMAC_REG(port, TX_LED_CTRL), LED_START);
+       skge_write8(hw, SK_REG(port, RX_LED_CTRL), LED_START);
+       skge_write8(hw, SK_REG(port, TX_LED_CTRL), LED_START);
 
        /* Unreset the XMAC. */
-       skge_write16(hw, SKGEMAC_REG(port, TX_MFF_CTRL1), MFF_CLR_MAC_RST);
+       skge_write16(hw, SK_REG(port, TX_MFF_CTRL1), MFF_CLR_MAC_RST);
 
        /*
         * Perform additional initialization for external PHYs,
@@ -1059,67 +1210,56 @@ static void genesis_mac_init(struct skge_hw *hw, int port)
         * GMII mode.
         */
        spin_lock_bh(&hw->phy_lock);
-       if (hw->phy_type != SK_PHY_XMAC) {
-               /* Take PHY out of reset. */
-               r = skge_read32(hw, B2_GP_IO);
-               if (port == 0)
-                       r |= GP_DIR_0|GP_IO_0;
-               else
-                       r |= GP_DIR_2|GP_IO_2;
-
-               skge_write32(hw, B2_GP_IO, r);
-               skge_read32(hw, B2_GP_IO);
-
-               /* Enable GMII mode on the XMAC. */
-               skge_xm_write16(hw, port, XM_HW_CFG, XM_HW_GMII_MD);
-
-               id1 = skge_xm_phy_read(hw, port, PHY_XMAC_ID1);
-
-               /* Optimize MDIO transfer by suppressing preamble. */
-               skge_xm_write16(hw, port, XM_MMU_CMD,
-                               skge_xm_read16(hw, port, XM_MMU_CMD)
-                               | XM_MMU_NO_PRE);
-
-               if (id1 == PHY_BCOM_ID1_C0) {
-                       /*
-                        * Workaround BCOM Errata for the C0 type.
-                        * Write magic patterns to reserved registers.
-                        */
-                       for (i = 0; i < ARRAY_SIZE(C0hack); i++)
-                               skge_xm_phy_write(hw, port,
-                                         C0hack[i].reg, C0hack[i].val);
-
-               } else if (id1 == PHY_BCOM_ID1_A1) {
-                       /*
-                        * Workaround BCOM Errata for the A1 type.
-                        * Write magic patterns to reserved registers.
-                        */
-                       for (i = 0; i < ARRAY_SIZE(A1hack); i++)
-                               skge_xm_phy_write(hw, port,
-                                         A1hack[i].reg, A1hack[i].val);
-               }
+       /* Take external Phy out of reset */
+       r = skge_read32(hw, B2_GP_IO);
+       if (port == 0)
+               r |= GP_DIR_0|GP_IO_0;
+       else
+               r |= GP_DIR_2|GP_IO_2;
 
-               /*
-                * Workaround BCOM Errata (#10523) for all BCom PHYs.
-                * Disable Power Management after reset.
-                */
-               r = skge_xm_phy_read(hw, port, PHY_BCOM_AUX_CTRL);
-               skge_xm_phy_write(hw, port, PHY_BCOM_AUX_CTRL, r | PHY_B_AC_DIS_PM);
-       }
+       skge_write32(hw, B2_GP_IO, r);
+       skge_read32(hw, B2_GP_IO);
+       spin_unlock_bh(&hw->phy_lock);
 
-       /* Dummy read */
-       skge_xm_read16(hw, port, XM_ISRC);
+       /* Enable GMII interfac */
+       xm_write16(hw, port, XM_HW_CFG, XM_HW_GMII_MD);
+
+       bcom_phy_init(skge, jumbo);
+
+       /* Set Station Address */
+       xm_outaddr(hw, port, XM_SA, dev->dev_addr);
+
+       /* We don't use match addresses so clear */
+       for (i = 1; i < 16; i++)
+               xm_outaddr(hw, port, XM_EXM(i), zero);
 
-       r = skge_xm_read32(hw, port, XM_MODE);
-       skge_xm_write32(hw, port, XM_MODE, r|XM_MD_CSA);
+       /* configure Rx High Water Mark (XM_RX_HI_WM) */
+       xm_write16(hw, port, XM_RX_HI_WM, 1450);
 
        /* We don't need the FCS appended to the packet. */
-       r = skge_xm_read16(hw, port, XM_RX_CMD);
-       skge_xm_write16(hw, port, XM_RX_CMD, r | XM_RX_STRIP_FCS);
+       r = XM_RX_LENERR_OK | XM_RX_STRIP_FCS;
+       if (jumbo)
+               r |= XM_RX_BIG_PK_OK;
+
+       if (skge->duplex == DUPLEX_HALF) {
+               /*
+                * If in manual half duplex mode the other side might be in
+                * full duplex mode, so ignore if a carrier extension is not seen
+                * on frames received
+                */
+               r |= XM_RX_DIS_CEXT;
+       }
+       xm_write16(hw, port, XM_RX_CMD, r);
+
 
        /* We want short frames padded to 60 bytes. */
-       r = skge_xm_read16(hw, port, XM_TX_CMD);
-       skge_xm_write16(hw, port, XM_TX_CMD, r | XM_TX_AUTO_PAD);
+       xm_write16(hw, port, XM_TX_CMD, XM_TX_AUTO_PAD);
+
+       /*
+        * Bump up the transmit threshold. This helps hold off transmit
+        * underruns when we're blasting traffic from both ports at once.
+        */
+       xm_write16(hw, port, XM_TX_THR, 512);
 
        /*
         * Enable the reception of all error frames. This is is
@@ -1135,19 +1275,22 @@ static void genesis_mac_init(struct skge_hw *hw, int port)
         * case the XMAC will start transfering frames out of the
         * RX FIFO as soon as the FIFO threshold is reached.
         */
-       r = skge_xm_read32(hw, port, XM_MODE);
-       skge_xm_write32(hw, port, XM_MODE,
-                    XM_MD_RX_CRCE|XM_MD_RX_LONG|XM_MD_RX_RUNT|
-                    XM_MD_RX_ERR|XM_MD_RX_IRLE);
+       xm_write32(hw, port, XM_MODE, XM_DEF_MODE);
 
-       skge_xm_outaddr(hw, port, XM_SA, hw->dev[port]->dev_addr);
-       skge_xm_outaddr(hw, port, XM_EXM(0), hw->dev[port]->dev_addr);
 
        /*
-        * Bump up the transmit threshold. This helps hold off transmit
-        * underruns when we're blasting traffic from both ports at once.
+        * Initialize the Receive Counter Event Mask (XM_RX_EV_MSK)
+        *      - Enable all bits excepting 'Octets Rx OK Low CntOv'
+        *        and 'Octets Rx OK Hi Cnt Ov'.
         */
-       skge_xm_write16(hw, port, XM_TX_THR, 512);
+       xm_write32(hw, port, XM_RX_EV_MSK, XMR_DEF_MSK);
+
+       /*
+        * Initialize the Transmit Counter Event Mask (XM_TX_EV_MSK)
+        *      - Enable all bits excepting 'Octets Tx OK Low CntOv'
+        *        and 'Octets Tx OK Hi Cnt Ov'.
+        */
+       xm_write32(hw, port, XM_TX_EV_MSK, XMT_DEF_MSK);
 
        /* Configure MAC arbiter */
        skge_write16(hw, B3_MA_TO_CTRL, MA_RST_CLR);
@@ -1164,137 +1307,30 @@ static void genesis_mac_init(struct skge_hw *hw, int port)
        skge_write8(hw, B3_MA_RCINI_TX2, 0);
 
        /* Configure Rx MAC FIFO */
-       skge_write8(hw, SKGEMAC_REG(port, RX_MFF_CTRL2), MFF_RST_CLR);
-       skge_write16(hw, SKGEMAC_REG(port, RX_MFF_CTRL1), MFF_ENA_TIM_PAT);
-       skge_write8(hw, SKGEMAC_REG(port, RX_MFF_CTRL2), MFF_ENA_OP_MD);
+       skge_write8(hw, SK_REG(port, RX_MFF_CTRL2), MFF_RST_CLR);
+       skge_write16(hw, SK_REG(port, RX_MFF_CTRL1), MFF_ENA_TIM_PAT);
+       skge_write8(hw, SK_REG(port, RX_MFF_CTRL2), MFF_ENA_OP_MD);
 
        /* Configure Tx MAC FIFO */
-       skge_write8(hw, SKGEMAC_REG(port, TX_MFF_CTRL2), MFF_RST_CLR);
-       skge_write16(hw, SKGEMAC_REG(port, TX_MFF_CTRL1), MFF_TX_CTRL_DEF);
-       skge_write8(hw, SKGEMAC_REG(port, TX_MFF_CTRL2), MFF_ENA_OP_MD);
+       skge_write8(hw, SK_REG(port, TX_MFF_CTRL2), MFF_RST_CLR);
+       skge_write16(hw, SK_REG(port, TX_MFF_CTRL1), MFF_TX_CTRL_DEF);
+       skge_write8(hw, SK_REG(port, TX_MFF_CTRL2), MFF_ENA_OP_MD);
 
-       if (hw->dev[port]->mtu > ETH_DATA_LEN) {
+       if (jumbo) {
                /* Enable frame flushing if jumbo frames used */
-               skge_write16(hw, SKGEMAC_REG(port,RX_MFF_CTRL1), MFF_ENA_FLUSH);
+               skge_write16(hw, SK_REG(port,RX_MFF_CTRL1), MFF_ENA_FLUSH);
        } else {
                /* enable timeout timers if normal frames */
                skge_write16(hw, B3_PA_CTRL,
-                            port == 0 ? PA_ENA_TO_TX1 : PA_ENA_TO_TX2);
+                            (port == 0) ? PA_ENA_TO_TX1 : PA_ENA_TO_TX2);
        }
-
-
-       r = skge_xm_read16(hw, port, XM_RX_CMD);
-       if (hw->dev[port]->mtu > ETH_DATA_LEN)
-               skge_xm_write16(hw, port, XM_RX_CMD, r | XM_RX_BIG_PK_OK);
-       else
-               skge_xm_write16(hw, port, XM_RX_CMD, r & ~(XM_RX_BIG_PK_OK));
-
-       switch (hw->phy_type) {
-       case SK_PHY_XMAC:
-               if (skge->autoneg == AUTONEG_ENABLE) {
-                       ctrl1 = PHY_X_AN_FD | PHY_X_AN_HD;
-
-                       switch (skge->flow_control) {
-                       case FLOW_MODE_NONE:
-                               ctrl1 |= PHY_X_P_NO_PAUSE;
-                               break;
-                       case FLOW_MODE_LOC_SEND:
-                               ctrl1 |= PHY_X_P_ASYM_MD;
-                               break;
-                       case FLOW_MODE_SYMMETRIC:
-                               ctrl1 |= PHY_X_P_SYM_MD;
-                               break;
-                       case FLOW_MODE_REM_SEND:
-                               ctrl1 |= PHY_X_P_BOTH_MD;
-                               break;
-                       }
-
-                       skge_xm_phy_write(hw, port, PHY_XMAC_AUNE_ADV, ctrl1);
-                       ctrl2 = PHY_CT_ANE | PHY_CT_RE_CFG;
-               } else {
-                       ctrl2 = 0;
-                       if (skge->duplex == DUPLEX_FULL)
-                               ctrl2 |= PHY_CT_DUP_MD;
-               }
-
-               skge_xm_phy_write(hw, port, PHY_XMAC_CTRL, ctrl2);
-               break;
-
-       case SK_PHY_BCOM:
-               ctrl1 = PHY_CT_SP1000;
-               ctrl2 = 0;
-               ctrl3 = PHY_SEL_TYPE;
-               ctrl4 = PHY_B_PEC_EN_LTR;
-               ctrl5 = PHY_B_AC_TX_TST;
-
-               if (skge->autoneg == AUTONEG_ENABLE) {
-                       /*
-                        * Workaround BCOM Errata #1 for the C5 type.
-                        * 1000Base-T Link Acquisition Failure in Slave Mode
-                        * Set Repeater/DTE bit 10 of the 1000Base-T Control Register
-                        */
-                       ctrl2 |= PHY_B_1000C_RD;
-                       if (skge->advertising & ADVERTISED_1000baseT_Half)
-                               ctrl2 |= PHY_B_1000C_AHD;
-                       if (skge->advertising & ADVERTISED_1000baseT_Full)
-                               ctrl2 |= PHY_B_1000C_AFD;
-
-                       /* Set Flow-control capabilities */
-                       switch (skge->flow_control) {
-                       case FLOW_MODE_NONE:
-                               ctrl3 |= PHY_B_P_NO_PAUSE;
-                               break;
-                       case FLOW_MODE_LOC_SEND:
-                               ctrl3 |= PHY_B_P_ASYM_MD;
-                               break;
-                       case FLOW_MODE_SYMMETRIC:
-                               ctrl3 |= PHY_B_P_SYM_MD;
-                               break;
-                       case FLOW_MODE_REM_SEND:
-                               ctrl3 |= PHY_B_P_BOTH_MD;
-                               break;
-                       }
-
-                       /* Restart Auto-negotiation */
-                       ctrl1 |= PHY_CT_ANE | PHY_CT_RE_CFG;
-               } else {
-                       if (skge->duplex == DUPLEX_FULL)
-                               ctrl1 |= PHY_CT_DUP_MD;
-
-                       ctrl2 |= PHY_B_1000C_MSE;       /* set it to Slave */
-               }
-
-               skge_xm_phy_write(hw, port, PHY_BCOM_1000T_CTRL, ctrl2);
-               skge_xm_phy_write(hw, port, PHY_BCOM_AUNE_ADV, ctrl3);
-
-               if (skge->netdev->mtu > ETH_DATA_LEN) {
-                       ctrl4 |= PHY_B_PEC_HIGH_LA;
-                       ctrl5 |= PHY_B_AC_LONG_PACK;
-
-                       skge_xm_phy_write(hw, port,PHY_BCOM_AUX_CTRL, ctrl5);
-               }
-
-               skge_xm_phy_write(hw, port, PHY_BCOM_P_EXT_CTRL, ctrl4);
-               skge_xm_phy_write(hw, port, PHY_BCOM_CTRL, ctrl1);
-               break;
-       }
-       spin_unlock_bh(&hw->phy_lock);
-
-       /* Clear MIB counters */
-       skge_xm_write16(hw, port, XM_STAT_CMD,
-                       XM_SC_CLR_RXC | XM_SC_CLR_TXC);
-       /* Clear two times according to Errata #3 */
-       skge_xm_write16(hw, port, XM_STAT_CMD,
-                       XM_SC_CLR_RXC | XM_SC_CLR_TXC);
-
-       /* Start polling for link status */
-       mod_timer(&skge->link_check, jiffies + LINK_POLL_HZ);
 }
 
 static void genesis_stop(struct skge_port *skge)
 {
        struct skge_hw *hw = skge->hw;
        int port = skge->port;
+       u32 reg;
 
        /* Clear Tx packet arbiter timeout IRQ */
        skge_write16(hw, B3_PA_CTRL,
@@ -1304,33 +1340,30 @@ static void genesis_stop(struct skge_port *skge)
         * If the transfer stucks at the MAC the STOP command will not
         * terminate if we don't flush the XMAC's transmit FIFO !
         */
-       skge_xm_write32(hw, port, XM_MODE,
-                       skge_xm_read32(hw, port, XM_MODE)|XM_MD_FTF);
+       xm_write32(hw, port, XM_MODE,
+                       xm_read32(hw, port, XM_MODE)|XM_MD_FTF);
 
 
        /* Reset the MAC */
-       skge_write16(hw, SKGEMAC_REG(port, TX_MFF_CTRL1), MFF_SET_MAC_RST);
+       skge_write16(hw, SK_REG(port, TX_MFF_CTRL1), MFF_SET_MAC_RST);
 
        /* For external PHYs there must be special handling */
-       if (hw->phy_type != SK_PHY_XMAC) {
-               u32 reg = skge_read32(hw, B2_GP_IO);
-
-               if (port == 0) {
-                       reg |= GP_DIR_0;
-                       reg &= ~GP_IO_0;
-               } else {
-                       reg |= GP_DIR_2;
-                       reg &= ~GP_IO_2;
-               }
-               skge_write32(hw, B2_GP_IO, reg);
-               skge_read32(hw, B2_GP_IO);
+       reg = skge_read32(hw, B2_GP_IO);
+       if (port == 0) {
+               reg |= GP_DIR_0;
+               reg &= ~GP_IO_0;
+       } else {
+               reg |= GP_DIR_2;
+               reg &= ~GP_IO_2;
        }
+       skge_write32(hw, B2_GP_IO, reg);
+       skge_read32(hw, B2_GP_IO);
 
-       skge_xm_write16(hw, port, XM_MMU_CMD,
-                       skge_xm_read16(hw, port, XM_MMU_CMD)
+       xm_write16(hw, port, XM_MMU_CMD,
+                       xm_read16(hw, port, XM_MMU_CMD)
                        & ~(XM_MMU_ENA_RX | XM_MMU_ENA_TX));
 
-       skge_xm_read16(hw, port, XM_MMU_CMD);
+       xm_read16(hw, port, XM_MMU_CMD);
 }
 
 
@@ -1341,11 +1374,11 @@ static void genesis_get_stats(struct skge_port *skge, u64 *data)
        int i;
        unsigned long timeout = jiffies + HZ;
 
-       skge_xm_write16(hw, port,
+       xm_write16(hw, port,
                        XM_STAT_CMD, XM_SC_SNP_TXC | XM_SC_SNP_RXC);
 
        /* wait for update to complete */
-       while (skge_xm_read16(hw, port, XM_STAT_CMD)
+       while (xm_read16(hw, port, XM_STAT_CMD)
               & (XM_SC_SNP_TXC | XM_SC_SNP_RXC)) {
                if (time_after(jiffies, timeout))
                        break;
@@ -1353,68 +1386,60 @@ static void genesis_get_stats(struct skge_port *skge, u64 *data)
        }
 
        /* special case for 64 bit octet counter */
-       data[0] = (u64) skge_xm_read32(hw, port, XM_TXO_OK_HI) << 32
-               | skge_xm_read32(hw, port, XM_TXO_OK_LO);
-       data[1] = (u64) skge_xm_read32(hw, port, XM_RXO_OK_HI) << 32
-               | skge_xm_read32(hw, port, XM_RXO_OK_LO);
+       data[0] = (u64) xm_read32(hw, port, XM_TXO_OK_HI) << 32
+               | xm_read32(hw, port, XM_TXO_OK_LO);
+       data[1] = (u64) xm_read32(hw, port, XM_RXO_OK_HI) << 32
+               | xm_read32(hw, port, XM_RXO_OK_LO);
 
        for (i = 2; i < ARRAY_SIZE(skge_stats); i++)
-               data[i] = skge_xm_read32(hw, port, skge_stats[i].xmac_offset);
+               data[i] = xm_read32(hw, port, skge_stats[i].xmac_offset);
 }
 
 static void genesis_mac_intr(struct skge_hw *hw, int port)
 {
        struct skge_port *skge = netdev_priv(hw->dev[port]);
-       u16 status = skge_xm_read16(hw, port, XM_ISRC);
-
-       pr_debug("genesis_intr status %x\n", status);
-       if (hw->phy_type == SK_PHY_XMAC) {
-               /* LInk down, start polling for state change */
-               if (status & XM_IS_INP_ASS) {
-                       skge_xm_write16(hw, port, XM_IMSK,
-                                       skge_xm_read16(hw, port, XM_IMSK) | XM_IS_INP_ASS);
-                       mod_timer(&skge->link_check, jiffies + LINK_POLL_HZ);
-               }
-               else if (status & XM_IS_AND)
-                       mod_timer(&skge->link_check, jiffies + LINK_POLL_HZ);
-       }
+       u16 status = xm_read16(hw, port, XM_ISRC);
+
+       if (netif_msg_intr(skge))
+               printk(KERN_DEBUG PFX "%s: mac interrupt status 0x%x\n",
+                      skge->netdev->name, status);
 
        if (status & XM_IS_TXF_UR) {
-               skge_xm_write32(hw, port, XM_MODE, XM_MD_FTF);
+               xm_write32(hw, port, XM_MODE, XM_MD_FTF);
                ++skge->net_stats.tx_fifo_errors;
        }
        if (status & XM_IS_RXF_OV) {
-               skge_xm_write32(hw, port, XM_MODE, XM_MD_FRF);
+               xm_write32(hw, port, XM_MODE, XM_MD_FRF);
                ++skge->net_stats.rx_fifo_errors;
        }
 }
 
-static void skge_gm_phy_write(struct skge_hw *hw, int port, u16 reg, u16 val)
+static void gm_phy_write(struct skge_hw *hw, int port, u16 reg, u16 val)
 {
        int i;
 
-       skge_gma_write16(hw, port, GM_SMI_DATA, val);
-       skge_gma_write16(hw, port, GM_SMI_CTRL,
+       gma_write16(hw, port, GM_SMI_DATA, val);
+       gma_write16(hw, port, GM_SMI_CTRL,
                         GM_SMI_CT_PHY_AD(hw->phy_addr) | GM_SMI_CT_REG_AD(reg));
        for (i = 0; i < PHY_RETRIES; i++) {
                udelay(1);
 
-               if (!(skge_gma_read16(hw, port, GM_SMI_CTRL) & GM_SMI_CT_BUSY))
+               if (!(gma_read16(hw, port, GM_SMI_CTRL) & GM_SMI_CT_BUSY))
                        break;
        }
 }
 
-static u16 skge_gm_phy_read(struct skge_hw *hw, int port, u16 reg)
+static u16 gm_phy_read(struct skge_hw *hw, int port, u16 reg)
 {
        int i;
 
-       skge_gma_write16(hw, port, GM_SMI_CTRL,
+       gma_write16(hw, port, GM_SMI_CTRL,
                         GM_SMI_CT_PHY_AD(hw->phy_addr)
                         | GM_SMI_CT_REG_AD(reg) | GM_SMI_CT_OP_RD);
 
        for (i = 0; i < PHY_RETRIES; i++) {
                udelay(1);
-               if (skge_gma_read16(hw, port, GM_SMI_CTRL) & GM_SMI_CT_RD_VAL)
+               if (gma_read16(hw, port, GM_SMI_CTRL) & GM_SMI_CT_RD_VAL)
                        goto ready;
        }
 
@@ -1422,24 +1447,7 @@ static u16 skge_gm_phy_read(struct skge_hw *hw, int port, u16 reg)
               hw->dev[port]->name);
        return 0;
  ready:
-       return skge_gma_read16(hw, port, GM_SMI_DATA);
-}
-
-static void genesis_link_down(struct skge_port *skge)
-{
-       struct skge_hw *hw = skge->hw;
-       int port = skge->port;
-
-       pr_debug("genesis_link_down\n");
-
-       skge_xm_write16(hw, port, XM_MMU_CMD,
-                       skge_xm_read16(hw, port, XM_MMU_CMD)
-                       & ~(XM_MMU_ENA_RX | XM_MMU_ENA_TX));
-
-       /* dummy read to ensure writing */
-       (void) skge_xm_read16(hw, port, XM_MMU_CMD);
-
-       skge_link_down(skge);
+       return gma_read16(hw, port, GM_SMI_DATA);
 }
 
 static void genesis_link_up(struct skge_port *skge)
@@ -1450,7 +1458,7 @@ static void genesis_link_up(struct skge_port *skge)
        u32 mode, msk;
 
        pr_debug("genesis_link_up\n");
-       cmd = skge_xm_read16(hw, port, XM_MMU_CMD);
+       cmd = xm_read16(hw, port, XM_MMU_CMD);
 
        /*
         * enabling pause frame reception is required for 1000BT
@@ -1458,14 +1466,15 @@ static void genesis_link_up(struct skge_port *skge)
         */
        if (skge->flow_control == FLOW_MODE_NONE ||
            skge->flow_control == FLOW_MODE_LOC_SEND)
+               /* Disable Pause Frame Reception */
                cmd |= XM_MMU_IGN_PF;
        else
                /* Enable Pause Frame Reception */
                cmd &= ~XM_MMU_IGN_PF;
 
-       skge_xm_write16(hw, port, XM_MMU_CMD, cmd);
+       xm_write16(hw, port, XM_MMU_CMD, cmd);
 
-       mode = skge_xm_read32(hw, port, XM_MODE);
+       mode = xm_read32(hw, port, XM_MODE);
        if (skge->flow_control == FLOW_MODE_SYMMETRIC ||
            skge->flow_control == FLOW_MODE_LOC_SEND) {
                /*
@@ -1479,10 +1488,10 @@ static void genesis_link_up(struct skge_port *skge)
                /* XM_PAUSE_DA = '010000C28001' (default) */
                /* XM_MAC_PTIME = 0xffff (maximum) */
                /* remember this value is defined in big endian (!) */
-               skge_xm_write16(hw, port, XM_MAC_PTIME, 0xffff);
+               xm_write16(hw, port, XM_MAC_PTIME, 0xffff);
 
                mode |= XM_PAUSE_MODE;
-               skge_write16(hw, SKGEMAC_REG(port, RX_MFF_CTRL1), MFF_ENA_PAUSE);
+               skge_write16(hw, SK_REG(port, RX_MFF_CTRL1), MFF_ENA_PAUSE);
        } else {
                /*
                 * disable pause frame generation is required for 1000BT
@@ -1491,125 +1500,68 @@ static void genesis_link_up(struct skge_port *skge)
                /* Disable Pause Mode in Mode Register */
                mode &= ~XM_PAUSE_MODE;
 
-               skge_write16(hw, SKGEMAC_REG(port, RX_MFF_CTRL1), MFF_DIS_PAUSE);
+               skge_write16(hw, SK_REG(port, RX_MFF_CTRL1), MFF_DIS_PAUSE);
        }
 
-       skge_xm_write32(hw, port, XM_MODE, mode);
+       xm_write32(hw, port, XM_MODE, mode);
 
        msk = XM_DEF_MSK;
-       if (hw->phy_type != SK_PHY_XMAC)
-               msk |= XM_IS_INP_ASS;   /* disable GP0 interrupt bit */
+       /* disable GP0 interrupt bit for external Phy */
+       msk |= XM_IS_INP_ASS;
 
-       skge_xm_write16(hw, port, XM_IMSK, msk);
-       skge_xm_read16(hw, port, XM_ISRC);
+       xm_write16(hw, port, XM_IMSK, msk);
+       xm_read16(hw, port, XM_ISRC);
 
        /* get MMU Command Reg. */
-       cmd = skge_xm_read16(hw, port, XM_MMU_CMD);
-       if (hw->phy_type != SK_PHY_XMAC && skge->duplex == DUPLEX_FULL)
+       cmd = xm_read16(hw, port, XM_MMU_CMD);
+       if (skge->duplex == DUPLEX_FULL)
                cmd |= XM_MMU_GMII_FD;
 
-       if (hw->phy_type == SK_PHY_BCOM) {
-               /*
-                * Workaround BCOM Errata (#10523) for all BCom Phys
-                * Enable Power Management after link up
-                */
-               skge_xm_phy_write(hw, port, PHY_BCOM_AUX_CTRL,
-                                 skge_xm_phy_read(hw, port, PHY_BCOM_AUX_CTRL)
-                                 & ~PHY_B_AC_DIS_PM);
-               skge_xm_phy_write(hw, port, PHY_BCOM_INT_MASK,
-                                 PHY_B_DEF_MSK);
-       }
+       /*
+        * Workaround BCOM Errata (#10523) for all BCom Phys
+        * Enable Power Management after link up
+        */
+       xm_phy_write(hw, port, PHY_BCOM_AUX_CTRL,
+                    xm_phy_read(hw, port, PHY_BCOM_AUX_CTRL)
+                    & ~PHY_B_AC_DIS_PM);
+       xm_phy_write(hw, port, PHY_BCOM_INT_MASK, PHY_B_DEF_MSK);
 
        /* enable Rx/Tx */
-       skge_xm_write16(hw, port, XM_MMU_CMD,
+       xm_write16(hw, port, XM_MMU_CMD,
                        cmd | XM_MMU_ENA_RX | XM_MMU_ENA_TX);
        skge_link_up(skge);
 }
 
 
-static void genesis_bcom_intr(struct skge_port *skge)
+static inline void bcom_phy_intr(struct skge_port *skge)
 {
        struct skge_hw *hw = skge->hw;
        int port = skge->port;
-       u16 stat = skge_xm_phy_read(hw, port, PHY_BCOM_INT_STAT);
+       u16 isrc;
+
+       isrc = xm_phy_read(hw, port, PHY_BCOM_INT_STAT);
+       if (netif_msg_intr(skge))
+               printk(KERN_DEBUG PFX "%s: phy interrupt status 0x%x\n",
+                      skge->netdev->name, isrc);
 
-       pr_debug("genesis_bcom intr stat=%x\n", stat);
+       if (isrc & PHY_B_IS_PSE)
+               printk(KERN_ERR PFX "%s: uncorrectable pair swap error\n",
+                      hw->dev[port]->name);
 
        /* Workaround BCom Errata:
         *      enable and disable loopback mode if "NO HCD" occurs.
         */
-       if (stat & PHY_B_IS_NO_HDCL) {
-               u16 ctrl = skge_xm_phy_read(hw, port, PHY_BCOM_CTRL);
-               skge_xm_phy_write(hw, port, PHY_BCOM_CTRL,
+       if (isrc & PHY_B_IS_NO_HDCL) {
+               u16 ctrl = xm_phy_read(hw, port, PHY_BCOM_CTRL);
+               xm_phy_write(hw, port, PHY_BCOM_CTRL,
                                  ctrl | PHY_CT_LOOP);
-               skge_xm_phy_write(hw, port, PHY_BCOM_CTRL,
+               xm_phy_write(hw, port, PHY_BCOM_CTRL,
                                  ctrl & ~PHY_CT_LOOP);
        }
 
-       stat = skge_xm_phy_read(hw, port, PHY_BCOM_STAT);
-       if (stat & (PHY_B_IS_AN_PR | PHY_B_IS_LST_CHANGE)) {
-               u16 aux = skge_xm_phy_read(hw, port, PHY_BCOM_AUX_STAT);
-               if ( !(aux & PHY_B_AS_LS) && netif_carrier_ok(skge->netdev))
-                       genesis_link_down(skge);
-
-               else if (stat & PHY_B_IS_LST_CHANGE) {
-                       if (aux & PHY_B_AS_AN_C) {
-                               switch (aux & PHY_B_AS_AN_RES_MSK) {
-                               case PHY_B_RES_1000FD:
-                                       skge->duplex = DUPLEX_FULL;
-                                       break;
-                               case PHY_B_RES_1000HD:
-                                       skge->duplex = DUPLEX_HALF;
-                                       break;
-                               }
-
-                               switch (aux & PHY_B_AS_PAUSE_MSK) {
-                               case PHY_B_AS_PAUSE_MSK:
-                                       skge->flow_control = FLOW_MODE_SYMMETRIC;
-                                       break;
-                               case PHY_B_AS_PRR:
-                                       skge->flow_control = FLOW_MODE_REM_SEND;
-                                       break;
-                               case PHY_B_AS_PRT:
-                                       skge->flow_control = FLOW_MODE_LOC_SEND;
-                                       break;
-                               default:
-                                       skge->flow_control = FLOW_MODE_NONE;
-                               }
-                               skge->speed = SPEED_1000;
-                       }
-                       genesis_link_up(skge);
-               }
-               else
-                       mod_timer(&skge->link_check, jiffies + LINK_POLL_HZ);
-       }
-}
+       if (isrc & (PHY_B_IS_AN_PR | PHY_B_IS_LST_CHANGE))
+               bcom_check_link(hw, port);
 
-/* Perodic poll of phy status to check for link transistion  */
-static void skge_link_timer(unsigned long __arg)
-{
-       struct skge_port *skge = (struct skge_port *) __arg;
-       struct skge_hw *hw = skge->hw;
-       int port = skge->port;
-
-       if (hw->chip_id != CHIP_ID_GENESIS || !netif_running(skge->netdev))
-               return;
-
-       spin_lock_bh(&hw->phy_lock);
-       if (hw->phy_type == SK_PHY_BCOM)
-               genesis_bcom_intr(skge);
-       else {
-               int i;
-               for (i = 0; i < 3; i++)
-                       if (skge_xm_read16(hw, port, XM_ISRC) & XM_IS_INP_ASS)
-                               break;
-
-               if (i == 3)
-                       mod_timer(&skge->link_check, jiffies + LINK_POLL_HZ);
-               else
-                       genesis_link_up(skge);
-       }
-       spin_unlock_bh(&hw->phy_lock);
 }
 
 /* Marvell Phy Initailization */
@@ -1621,31 +1573,27 @@ static void yukon_init(struct skge_hw *hw, int port)
 
        pr_debug("yukon_init\n");
        if (skge->autoneg == AUTONEG_ENABLE) {
-               u16 ectrl = skge_gm_phy_read(hw, port, PHY_MARV_EXT_CTRL);
+               u16 ectrl = gm_phy_read(hw, port, PHY_MARV_EXT_CTRL);
 
                ectrl &= ~(PHY_M_EC_M_DSC_MSK | PHY_M_EC_S_DSC_MSK |
                          PHY_M_EC_MAC_S_MSK);
                ectrl |= PHY_M_EC_MAC_S(MAC_TX_CLK_25_MHZ);
 
-               /* on PHY 88E1111 there is a change for downshift control */
-               if (hw->chip_id == CHIP_ID_YUKON_EC)
-                       ectrl |= PHY_M_EC_M_DSC_2(0) | PHY_M_EC_DOWN_S_ENA;
-               else
-                       ectrl |= PHY_M_EC_M_DSC(0) | PHY_M_EC_S_DSC(1);
+               ectrl |= PHY_M_EC_M_DSC(0) | PHY_M_EC_S_DSC(1);
 
-               skge_gm_phy_write(hw, port, PHY_MARV_EXT_CTRL, ectrl);
+               gm_phy_write(hw, port, PHY_MARV_EXT_CTRL, ectrl);
        }
 
-       ctrl = skge_gm_phy_read(hw, port, PHY_MARV_CTRL);
+       ctrl = gm_phy_read(hw, port, PHY_MARV_CTRL);
        if (skge->autoneg == AUTONEG_DISABLE)
                ctrl &= ~PHY_CT_ANE;
 
        ctrl |= PHY_CT_RESET;
-       skge_gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl);
+       gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl);
 
        ctrl = 0;
        ct1000 = 0;
-       adv = PHY_SEL_TYPE;
+       adv = PHY_AN_CSMA;
 
        if (skge->autoneg == AUTONEG_ENABLE) {
                if (iscopper(hw)) {
@@ -1661,41 +1609,12 @@ static void yukon_init(struct skge_hw *hw, int port)
                                adv |= PHY_M_AN_10_FD;
                        if (skge->advertising & ADVERTISED_10baseT_Half)
                                adv |= PHY_M_AN_10_HD;
-
-                       /* Set Flow-control capabilities */
-                       switch (skge->flow_control) {
-                       case FLOW_MODE_NONE:
-                               adv |= PHY_B_P_NO_PAUSE;
-                               break;
-                       case FLOW_MODE_LOC_SEND:
-                               adv |= PHY_B_P_ASYM_MD;
-                               break;
-                       case FLOW_MODE_SYMMETRIC:
-                               adv |= PHY_B_P_SYM_MD;
-                               break;
-                       case FLOW_MODE_REM_SEND:
-                               adv |= PHY_B_P_BOTH_MD;
-                               break;
-                       }
-               } else {        /* special defines for FIBER (88E1011S only) */
+               } else  /* special defines for FIBER (88E1011S only) */
                        adv |= PHY_M_AN_1000X_AHD | PHY_M_AN_1000X_AFD;
 
-                       /* Set Flow-control capabilities */
-                       switch (skge->flow_control) {
-                       case FLOW_MODE_NONE:
-                               adv |= PHY_M_P_NO_PAUSE_X;
-                               break;
-                       case FLOW_MODE_LOC_SEND:
-                               adv |= PHY_M_P_ASYM_MD_X;
-                               break;
-                       case FLOW_MODE_SYMMETRIC:
-                               adv |= PHY_M_P_SYM_MD_X;
-                               break;
-                       case FLOW_MODE_REM_SEND:
-                               adv |= PHY_M_P_BOTH_MD_X;
-                               break;
-                       }
-               }
+               /* Set Flow-control capabilities */
+               adv |= phy_pause_map[skge->flow_control];
+
                /* Restart Auto-negotiation */
                ctrl |= PHY_CT_ANE | PHY_CT_RE_CFG;
        } else {
@@ -1717,36 +1636,23 @@ static void yukon_init(struct skge_hw *hw, int port)
                ctrl |= PHY_CT_RESET;
        }
 
-       if (hw->chip_id != CHIP_ID_YUKON_FE)
-               skge_gm_phy_write(hw, port, PHY_MARV_1000T_CTRL, ct1000);
+       gm_phy_write(hw, port, PHY_MARV_1000T_CTRL, ct1000);
 
-       skge_gm_phy_write(hw, port, PHY_MARV_AUNE_ADV, adv);
-       skge_gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl);
+       gm_phy_write(hw, port, PHY_MARV_AUNE_ADV, adv);
+       gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl);
 
        /* Setup Phy LED's */
        ledctrl = PHY_M_LED_PULS_DUR(PULS_170MS);
        ledover = 0;
 
-       if (hw->chip_id == CHIP_ID_YUKON_FE) {
-               /* on 88E3082 these bits are at 11..9 (shifted left) */
-               ledctrl |= PHY_M_LED_BLINK_RT(BLINK_84MS) << 1;
-
-               skge_gm_phy_write(hw, port, PHY_MARV_FE_LED_PAR,
-                                 ((skge_gm_phy_read(hw, port, PHY_MARV_FE_LED_PAR)
-
-                                   & ~PHY_M_FELP_LED1_MSK)
-                                  | PHY_M_FELP_LED1_CTRL(LED_PAR_CTRL_ACT_BL)));
-       } else {
-               /* set Tx LED (LED_TX) to blink mode on Rx OR Tx activity */
-               ledctrl |= PHY_M_LED_BLINK_RT(BLINK_84MS) | PHY_M_LEDC_TX_CTRL;
+       ledctrl |= PHY_M_LED_BLINK_RT(BLINK_84MS) | PHY_M_LEDC_TX_CTRL;
 
-               /* turn off the Rx LED (LED_RX) */
-               ledover |= PHY_M_LED_MO_RX(MO_LED_OFF);
-       }
+       /* turn off the Rx LED (LED_RX) */
+       ledover |= PHY_M_LED_MO_RX(MO_LED_OFF);
 
        /* disable blink mode (LED_DUPLEX) on collisions */
        ctrl |= PHY_M_LEDC_DP_CTRL;
-       skge_gm_phy_write(hw, port, PHY_MARV_LED_CTRL, ledctrl);
+       gm_phy_write(hw, port, PHY_MARV_LED_CTRL, ledctrl);
 
        if (skge->autoneg == AUTONEG_DISABLE || skge->speed == SPEED_100) {
                /* turn on 100 Mbps LED (LED_LINK100) */
@@ -1754,25 +1660,25 @@ static void yukon_init(struct skge_hw *hw, int port)
        }
 
        if (ledover)
-               skge_gm_phy_write(hw, port, PHY_MARV_LED_OVER, ledover);
+               gm_phy_write(hw, port, PHY_MARV_LED_OVER, ledover);
 
        /* Enable phy interrupt on autonegotiation complete (or link up) */
        if (skge->autoneg == AUTONEG_ENABLE)
-               skge_gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_IS_AN_COMPL);
+               gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_IS_AN_COMPL);
        else
-               skge_gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_DEF_MSK);
+               gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_DEF_MSK);
 }
 
 static void yukon_reset(struct skge_hw *hw, int port)
 {
-       skge_gm_phy_write(hw, port, PHY_MARV_INT_MASK, 0);/* disable PHY IRQs */
-       skge_gma_write16(hw, port, GM_MC_ADDR_H1, 0);   /* clear MC hash */
-       skge_gma_write16(hw, port, GM_MC_ADDR_H2, 0);
-       skge_gma_write16(hw, port, GM_MC_ADDR_H3, 0);
-       skge_gma_write16(hw, port, GM_MC_ADDR_H4, 0);
+       gm_phy_write(hw, port, PHY_MARV_INT_MASK, 0);/* disable PHY IRQs */
+       gma_write16(hw, port, GM_MC_ADDR_H1, 0);        /* clear MC hash */
+       gma_write16(hw, port, GM_MC_ADDR_H2, 0);
+       gma_write16(hw, port, GM_MC_ADDR_H3, 0);
+       gma_write16(hw, port, GM_MC_ADDR_H4, 0);
 
-       skge_gma_write16(hw, port, GM_RX_CTRL,
-                        skge_gma_read16(hw, port, GM_RX_CTRL)
+       gma_write16(hw, port, GM_RX_CTRL,
+                        gma_read16(hw, port, GM_RX_CTRL)
                         | GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA);
 }
 
@@ -1785,17 +1691,17 @@ static void yukon_mac_init(struct skge_hw *hw, int port)
 
        /* WA code for COMA mode -- set PHY reset */
        if (hw->chip_id == CHIP_ID_YUKON_LITE &&
-           chip_rev(hw) == CHIP_REV_YU_LITE_A3)
+           hw->chip_rev == CHIP_REV_YU_LITE_A3)
                skge_write32(hw, B2_GP_IO,
                             (skge_read32(hw, B2_GP_IO) | GP_DIR_9 | GP_IO_9));
 
        /* hard reset */
-       skge_write32(hw, SKGEMAC_REG(port, GPHY_CTRL), GPC_RST_SET);
-       skge_write32(hw, SKGEMAC_REG(port, GMAC_CTRL), GMC_RST_SET);
+       skge_write32(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET);
+       skge_write32(hw, SK_REG(port, GMAC_CTRL), GMC_RST_SET);
 
        /* WA code for COMA mode -- clear PHY reset */
        if (hw->chip_id == CHIP_ID_YUKON_LITE &&
-           chip_rev(hw) == CHIP_REV_YU_LITE_A3)
+           hw->chip_rev == CHIP_REV_YU_LITE_A3)
                skge_write32(hw, B2_GP_IO,
                             (skge_read32(hw, B2_GP_IO) | GP_DIR_9)
                             & ~GP_IO_9);
@@ -1806,13 +1712,13 @@ static void yukon_mac_init(struct skge_hw *hw, int port)
        reg |= iscopper(hw) ? GPC_HWCFG_GMII_COP : GPC_HWCFG_GMII_FIB;
 
        /* Clear GMC reset */
-       skge_write32(hw, SKGEMAC_REG(port, GPHY_CTRL), reg | GPC_RST_SET);
-       skge_write32(hw, SKGEMAC_REG(port, GPHY_CTRL), reg | GPC_RST_CLR);
-       skge_write32(hw, SKGEMAC_REG(port, GMAC_CTRL), GMC_PAUSE_ON | GMC_RST_CLR);
+       skge_write32(hw, SK_REG(port, GPHY_CTRL), reg | GPC_RST_SET);
+       skge_write32(hw, SK_REG(port, GPHY_CTRL), reg | GPC_RST_CLR);
+       skge_write32(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_ON | GMC_RST_CLR);
        if (skge->autoneg == AUTONEG_DISABLE) {
                reg = GM_GPCR_AU_ALL_DIS;
-               skge_gma_write16(hw, port, GM_GP_CTRL,
-                                skge_gma_read16(hw, port, GM_GP_CTRL) | reg);
+               gma_write16(hw, port, GM_GP_CTRL,
+                                gma_read16(hw, port, GM_GP_CTRL) | reg);
 
                switch (skge->speed) {
                case SPEED_1000:
@@ -1828,7 +1734,7 @@ static void yukon_mac_init(struct skge_hw *hw, int port)
                reg = GM_GPCR_SPEED_1000 | GM_GPCR_SPEED_100 | GM_GPCR_DUP_FULL;
        switch (skge->flow_control) {
        case FLOW_MODE_NONE:
-               skge_write32(hw, SKGEMAC_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);
+               skge_write32(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);
                reg |= GM_GPCR_FC_TX_DIS | GM_GPCR_FC_RX_DIS | GM_GPCR_AU_FCT_DIS;
                break;
        case FLOW_MODE_LOC_SEND:
@@ -1836,7 +1742,7 @@ static void yukon_mac_init(struct skge_hw *hw, int port)
                reg |= GM_GPCR_FC_RX_DIS | GM_GPCR_AU_FCT_DIS;
        }
 
-       skge_gma_write16(hw, port, GM_GP_CTRL, reg);
+       gma_write16(hw, port, GM_GP_CTRL, reg);
        skge_read16(hw, GMAC_IRQ_SRC);
 
        spin_lock_bh(&hw->phy_lock);
@@ -1844,25 +1750,25 @@ static void yukon_mac_init(struct skge_hw *hw, int port)
        spin_unlock_bh(&hw->phy_lock);
 
        /* MIB clear */
-       reg = skge_gma_read16(hw, port, GM_PHY_ADDR);
-       skge_gma_write16(hw, port, GM_PHY_ADDR, reg | GM_PAR_MIB_CLR);
+       reg = gma_read16(hw, port, GM_PHY_ADDR);
+       gma_write16(hw, port, GM_PHY_ADDR, reg | GM_PAR_MIB_CLR);
 
        for (i = 0; i < GM_MIB_CNT_SIZE; i++)
-               skge_gma_read16(hw, port, GM_MIB_CNT_BASE + 8*i);
-       skge_gma_write16(hw, port, GM_PHY_ADDR, reg);
+               gma_read16(hw, port, GM_MIB_CNT_BASE + 8*i);
+       gma_write16(hw, port, GM_PHY_ADDR, reg);
 
        /* transmit control */
-       skge_gma_write16(hw, port, GM_TX_CTRL, TX_COL_THR(TX_COL_DEF));
+       gma_write16(hw, port, GM_TX_CTRL, TX_COL_THR(TX_COL_DEF));
 
        /* receive control reg: unicast + multicast + no FCS  */
-       skge_gma_write16(hw, port, GM_RX_CTRL,
+       gma_write16(hw, port, GM_RX_CTRL,
                         GM_RXCR_UCF_ENA | GM_RXCR_CRC_DIS | GM_RXCR_MCF_ENA);
 
        /* transmit flow control */
-       skge_gma_write16(hw, port, GM_TX_FLOW_CTRL, 0xffff);
+       gma_write16(hw, port, GM_TX_FLOW_CTRL, 0xffff);
 
        /* transmit parameter */
-       skge_gma_write16(hw, port, GM_TX_PARAM,
+       gma_write16(hw, port, GM_TX_PARAM,
                         TX_JAM_LEN_VAL(TX_JAM_LEN_DEF) |
                         TX_JAM_IPG_VAL(TX_JAM_IPG_DEF) |
                         TX_IPG_JAM_DATA(TX_IPG_JAM_DEF));
@@ -1872,33 +1778,33 @@ static void yukon_mac_init(struct skge_hw *hw, int port)
        if (hw->dev[port]->mtu > 1500)
                reg |= GM_SMOD_JUMBO_ENA;
 
-       skge_gma_write16(hw, port, GM_SERIAL_MODE, reg);
+       gma_write16(hw, port, GM_SERIAL_MODE, reg);
 
        /* physical address: used for pause frames */
-       skge_gm_set_addr(hw, port, GM_SRC_ADDR_1L, addr);
+       gma_set_addr(hw, port, GM_SRC_ADDR_1L, addr);
        /* virtual address for data */
-       skge_gm_set_addr(hw, port, GM_SRC_ADDR_2L, addr);
+       gma_set_addr(hw, port, GM_SRC_ADDR_2L, addr);
 
        /* enable interrupt mask for counter overflows */
-       skge_gma_write16(hw, port, GM_TX_IRQ_MSK, 0);
-       skge_gma_write16(hw, port, GM_RX_IRQ_MSK, 0);
-       skge_gma_write16(hw, port, GM_TR_IRQ_MSK, 0);
+       gma_write16(hw, port, GM_TX_IRQ_MSK, 0);
+       gma_write16(hw, port, GM_RX_IRQ_MSK, 0);
+       gma_write16(hw, port, GM_TR_IRQ_MSK, 0);
 
        /* Initialize Mac Fifo */
 
        /* Configure Rx MAC FIFO */
-       skge_write16(hw, SKGEMAC_REG(port, RX_GMF_FL_MSK), RX_FF_FL_DEF_MSK);
+       skge_write16(hw, SK_REG(port, RX_GMF_FL_MSK), RX_FF_FL_DEF_MSK);
        reg = GMF_OPER_ON | GMF_RX_F_FL_ON;
        if (hw->chip_id == CHIP_ID_YUKON_LITE &&
-           chip_rev(hw) == CHIP_REV_YU_LITE_A3)
+           hw->chip_rev == CHIP_REV_YU_LITE_A3)
                reg &= ~GMF_RX_F_FL_ON;
-       skge_write8(hw, SKGEMAC_REG(port, RX_GMF_CTRL_T), GMF_RST_CLR);
-       skge_write16(hw, SKGEMAC_REG(port, RX_GMF_CTRL_T), reg);
-       skge_write16(hw, SKGEMAC_REG(port, RX_GMF_FL_THR), RX_GMF_FL_THR_DEF);
+       skge_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_CLR);
+       skge_write16(hw, SK_REG(port, RX_GMF_CTRL_T), reg);
+       skge_write16(hw, SK_REG(port, RX_GMF_FL_THR), RX_GMF_FL_THR_DEF);
 
        /* Configure Tx MAC FIFO */
-       skge_write8(hw, SKGEMAC_REG(port, TX_GMF_CTRL_T), GMF_RST_CLR);
-       skge_write16(hw, SKGEMAC_REG(port, TX_GMF_CTRL_T), GMF_OPER_ON);
+       skge_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_CLR);
+       skge_write16(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_OPER_ON);
 }
 
 static void yukon_stop(struct skge_port *skge)
@@ -1907,19 +1813,19 @@ static void yukon_stop(struct skge_port *skge)
        int port = skge->port;
 
        if (hw->chip_id == CHIP_ID_YUKON_LITE &&
-           chip_rev(hw) == CHIP_REV_YU_LITE_A3) {
+           hw->chip_rev == CHIP_REV_YU_LITE_A3) {
                skge_write32(hw, B2_GP_IO,
                             skge_read32(hw, B2_GP_IO) | GP_DIR_9 | GP_IO_9);
        }
 
-       skge_gma_write16(hw, port, GM_GP_CTRL,
-                        skge_gma_read16(hw, port, GM_GP_CTRL)
+       gma_write16(hw, port, GM_GP_CTRL,
+                        gma_read16(hw, port, GM_GP_CTRL)
                         & ~(GM_GPCR_RX_ENA|GM_GPCR_RX_ENA));
-       skge_gma_read16(hw, port, GM_GP_CTRL);
+       gma_read16(hw, port, GM_GP_CTRL);
 
        /* set GPHY Control reset */
-       skge_gma_write32(hw, port, GPHY_CTRL, GPC_RST_SET);
-       skge_gma_write32(hw, port, GMAC_CTRL, GMC_RST_SET);
+       gma_write32(hw, port, GPHY_CTRL, GPC_RST_SET);
+       gma_write32(hw, port, GMAC_CTRL, GMC_RST_SET);
 }
 
 static void yukon_get_stats(struct skge_port *skge, u64 *data)
@@ -1928,39 +1834,40 @@ static void yukon_get_stats(struct skge_port *skge, u64 *data)
        int port = skge->port;
        int i;
 
-       data[0] = (u64) skge_gma_read32(hw, port, GM_TXO_OK_HI) << 32
-               | skge_gma_read32(hw, port, GM_TXO_OK_LO);
-       data[1] = (u64) skge_gma_read32(hw, port, GM_RXO_OK_HI) << 32
-               | skge_gma_read32(hw, port, GM_RXO_OK_LO);
+       data[0] = (u64) gma_read32(hw, port, GM_TXO_OK_HI) << 32
+               | gma_read32(hw, port, GM_TXO_OK_LO);
+       data[1] = (u64) gma_read32(hw, port, GM_RXO_OK_HI) << 32
+               | gma_read32(hw, port, GM_RXO_OK_LO);
 
        for (i = 2; i < ARRAY_SIZE(skge_stats); i++)
-               data[i] = skge_gma_read32(hw, port,
+               data[i] = gma_read32(hw, port,
                                          skge_stats[i].gma_offset);
 }
 
 static void yukon_mac_intr(struct skge_hw *hw, int port)
 {
-       struct skge_port *skge = netdev_priv(hw->dev[port]);
-       u8 status = skge_read8(hw, SKGEMAC_REG(port, GMAC_IRQ_SRC));
+       struct net_device *dev = hw->dev[port];
+       struct skge_port *skge = netdev_priv(dev);
+       u8 status = skge_read8(hw, SK_REG(port, GMAC_IRQ_SRC));
+
+       if (netif_msg_intr(skge))
+               printk(KERN_DEBUG PFX "%s: mac interrupt status 0x%x\n",
+                      dev->name, status);
 
-       pr_debug("yukon_intr status %x\n", status);
        if (status & GM_IS_RX_FF_OR) {
                ++skge->net_stats.rx_fifo_errors;
-               skge_gma_write8(hw, port, RX_GMF_CTRL_T, GMF_CLI_RX_FO);
+               gma_write8(hw, port, RX_GMF_CTRL_T, GMF_CLI_RX_FO);
        }
        if (status & GM_IS_TX_FF_UR) {
                ++skge->net_stats.tx_fifo_errors;
-               skge_gma_write8(hw, port, TX_GMF_CTRL_T, GMF_CLI_TX_FU);
+               gma_write8(hw, port, TX_GMF_CTRL_T, GMF_CLI_TX_FU);
        }
 
 }
 
 static u16 yukon_speed(const struct skge_hw *hw, u16 aux)
 {
-       if (hw->chip_id == CHIP_ID_YUKON_FE)
-               return (aux & PHY_M_PS_SPEED_100) ? SPEED_100 : SPEED_10;
-
-       switch(aux & PHY_M_PS_SPEED_MSK) {
+       switch (aux & PHY_M_PS_SPEED_MSK) {
        case PHY_M_PS_SPEED_1000:
                return SPEED_1000;
        case PHY_M_PS_SPEED_100:
@@ -1981,15 +1888,15 @@ static void yukon_link_up(struct skge_port *skge)
        /* Enable Transmit FIFO Underrun */
        skge_write8(hw, GMAC_IRQ_MSK, GMAC_DEF_MSK);
 
-       reg = skge_gma_read16(hw, port, GM_GP_CTRL);
+       reg = gma_read16(hw, port, GM_GP_CTRL);
        if (skge->duplex == DUPLEX_FULL || skge->autoneg == AUTONEG_ENABLE)
                reg |= GM_GPCR_DUP_FULL;
 
        /* enable Rx/Tx */
        reg |= GM_GPCR_RX_ENA | GM_GPCR_TX_ENA;
-       skge_gma_write16(hw, port, GM_GP_CTRL, reg);
+       gma_write16(hw, port, GM_GP_CTRL, reg);
 
-       skge_gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_DEF_MSK);
+       gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_DEF_MSK);
        skge_link_up(skge);
 }
 
@@ -1999,16 +1906,15 @@ static void yukon_link_down(struct skge_port *skge)
        int port = skge->port;
 
        pr_debug("yukon_link_down\n");
-       skge_gm_phy_write(hw, port, PHY_MARV_INT_MASK, 0);
-       skge_gm_phy_write(hw, port, GM_GP_CTRL,
-                         skge_gm_phy_read(hw, port, GM_GP_CTRL)
+       gm_phy_write(hw, port, PHY_MARV_INT_MASK, 0);
+       gm_phy_write(hw, port, GM_GP_CTRL,
+                         gm_phy_read(hw, port, GM_GP_CTRL)
                          & ~(GM_GPCR_RX_ENA | GM_GPCR_TX_ENA));
 
-       if (hw->chip_id != CHIP_ID_YUKON_FE &&
-           skge->flow_control == FLOW_MODE_REM_SEND) {
+       if (skge->flow_control == FLOW_MODE_REM_SEND) {
                /* restore Asymmetric Pause bit */
-               skge_gm_phy_write(hw, port, PHY_MARV_AUNE_ADV,
-                                 skge_gm_phy_read(hw, port,
+               gm_phy_write(hw, port, PHY_MARV_AUNE_ADV,
+                                 gm_phy_read(hw, port,
                                                   PHY_MARV_AUNE_ADV)
                                  | PHY_M_AN_ASP);
 
@@ -2027,20 +1933,21 @@ static void yukon_phy_intr(struct skge_port *skge)
        const char *reason = NULL;
        u16 istatus, phystat;
 
-       istatus = skge_gm_phy_read(hw, port, PHY_MARV_INT_STAT);
-       phystat = skge_gm_phy_read(hw, port, PHY_MARV_PHY_STAT);
-       pr_debug("yukon phy intr istat=%x phy_stat=%x\n", istatus, phystat);
+       istatus = gm_phy_read(hw, port, PHY_MARV_INT_STAT);
+       phystat = gm_phy_read(hw, port, PHY_MARV_PHY_STAT);
+
+       if (netif_msg_intr(skge))
+               printk(KERN_DEBUG PFX "%s: phy interrupt status 0x%x 0x%x\n",
+                      skge->netdev->name, istatus, phystat);
 
        if (istatus & PHY_M_IS_AN_COMPL) {
-               if (skge_gm_phy_read(hw, port, PHY_MARV_AUNE_LP)
+               if (gm_phy_read(hw, port, PHY_MARV_AUNE_LP)
                    & PHY_M_AN_RF) {
                        reason = "remote fault";
                        goto failed;
                }
 
-               if (!(hw->chip_id == CHIP_ID_YUKON_FE || hw->chip_id == CHIP_ID_YUKON_EC)
-                   && (skge_gm_phy_read(hw, port, PHY_MARV_1000T_STAT)
-                       & PHY_B_1000S_MSF)) {
+               if (gm_phy_read(hw, port, PHY_MARV_1000T_STAT) & PHY_B_1000S_MSF) {
                        reason = "master/slave fault";
                        goto failed;
                }
@@ -2054,10 +1961,6 @@ static void yukon_phy_intr(struct skge_port *skge)
                        ? DUPLEX_FULL : DUPLEX_HALF;
                skge->speed = yukon_speed(hw, phystat);
 
-               /* Tx & Rx Pause Enabled bits are at 9..8 */
-               if (hw->chip_id == CHIP_ID_YUKON_XL)
-                       phystat >>= 6;
-
                /* We are using IEEE 802.3z/D5.0 Table 37-4 */
                switch (phystat & PHY_M_PS_PAUSE_MSK) {
                case PHY_M_PS_PAUSE_MSK:
@@ -2075,9 +1978,9 @@ static void yukon_phy_intr(struct skge_port *skge)
 
                if (skge->flow_control == FLOW_MODE_NONE ||
                    (skge->speed < SPEED_1000 && skge->duplex == DUPLEX_HALF))
-                       skge_write8(hw, SKGEMAC_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);
+                       skge_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);
                else
-                       skge_write8(hw, SKGEMAC_REG(port, GMAC_CTRL), GMC_PAUSE_ON);
+                       skge_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_ON);
                yukon_link_up(skge);
                return;
        }
@@ -2161,6 +2064,12 @@ static int skge_up(struct net_device *dev)
        if (netif_msg_ifup(skge))
                printk(KERN_INFO PFX "%s: enabling interface\n", dev->name);
 
+       if (dev->mtu > RX_BUF_SIZE)
+               skge->rx_buf_size = dev->mtu + ETH_HLEN + NET_IP_ALIGN;
+       else
+               skge->rx_buf_size = RX_BUF_SIZE;
+
+
        rx_size = skge->rx_ring.count * sizeof(struct skge_rx_desc);
        tx_size = skge->tx_ring.count * sizeof(struct skge_tx_desc);
        skge->mem_size = tx_size + rx_size;
@@ -2173,7 +2082,8 @@ static int skge_up(struct net_device *dev)
        if ((err = skge_ring_alloc(&skge->rx_ring, skge->mem, skge->dma)))
                goto free_pci_mem;
 
-       if (skge_rx_fill(skge))
+       err = skge_rx_fill(skge);
+       if (err)
                goto free_rx_ring;
 
        if ((err = skge_ring_alloc(&skge->tx_ring, skge->mem + rx_size,
@@ -2182,6 +2092,10 @@ static int skge_up(struct net_device *dev)
 
        skge->tx_avail = skge->tx_ring.count - 1;
 
+       /* Enable IRQ from port */
+       hw->intr_mask |= portirqmask[port];
+       skge_write32(hw, B0_IMSK, hw->intr_mask);
+
        /* Initialze MAC */
        if (hw->chip_id == CHIP_ID_GENESIS)
                genesis_mac_init(hw, port);
@@ -2189,7 +2103,7 @@ static int skge_up(struct net_device *dev)
                yukon_mac_init(hw, port);
 
        /* Configure RAMbuffers */
-       chunk = hw->ram_size / (isdualport(hw) ? 4 : 2);
+       chunk = hw->ram_size / ((hw->ports + 1)*2);
        ram_addr = hw->ram_offset + 2 * chunk * port;
 
        skge_ramset(hw, rxqaddr[port], ram_addr, chunk);
@@ -2227,7 +2141,6 @@ static int skge_down(struct net_device *dev)
        netif_stop_queue(dev);
 
        del_timer_sync(&skge->led_blink);
-       del_timer_sync(&skge->link_check);
 
        /* Stop transmitter */
        skge_write8(hw, Q_ADDR(txqaddr[port], Q_CSR), CSR_STOP);
@@ -2240,12 +2153,12 @@ static int skge_down(struct net_device *dev)
                yukon_stop(skge);
 
        /* Disable Force Sync bit and Enable Alloc bit */
-       skge_write8(hw, SKGEMAC_REG(port, TXA_CTRL),
+       skge_write8(hw, SK_REG(port, TXA_CTRL),
                    TXA_DIS_FSYNC | TXA_DIS_ALLOC | TXA_STOP_RC);
 
        /* Stop Interval Timer and Limit Counter of Tx Arbiter */
-       skge_write32(hw, SKGEMAC_REG(port, TXA_ITI_INI), 0L);
-       skge_write32(hw, SKGEMAC_REG(port, TXA_LIM_INI), 0L);
+       skge_write32(hw, SK_REG(port, TXA_ITI_INI), 0L);
+       skge_write32(hw, SK_REG(port, TXA_LIM_INI), 0L);
 
        /* Reset PCI FIFO */
        skge_write32(hw, Q_ADDR(txqaddr[port], Q_CSR), CSR_SET_RESET);
@@ -2260,13 +2173,13 @@ static int skge_down(struct net_device *dev)
        skge_write32(hw, Q_ADDR(rxqaddr[port], Q_CSR), CSR_SET_RESET);
 
        if (hw->chip_id == CHIP_ID_GENESIS) {
-               skge_write8(hw, SKGEMAC_REG(port, TX_MFF_CTRL2), MFF_RST_SET);
-               skge_write8(hw, SKGEMAC_REG(port, RX_MFF_CTRL2), MFF_RST_SET);
-               skge_write8(hw, SKGEMAC_REG(port, TX_LED_CTRL), LED_STOP);
-               skge_write8(hw, SKGEMAC_REG(port, RX_LED_CTRL), LED_STOP);
+               skge_write8(hw, SK_REG(port, TX_MFF_CTRL2), MFF_RST_SET);
+               skge_write8(hw, SK_REG(port, RX_MFF_CTRL2), MFF_RST_SET);
+               skge_write8(hw, SK_REG(port, TX_LED_CTRL), LED_STOP);
+               skge_write8(hw, SK_REG(port, RX_LED_CTRL), LED_STOP);
        } else {
-               skge_write8(hw, SKGEMAC_REG(port, RX_GMF_CTRL_T), GMF_RST_SET);
-               skge_write8(hw, SKGEMAC_REG(port, TX_GMF_CTRL_T), GMF_RST_SET);
+               skge_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_SET);
+               skge_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_SET);
        }
 
        /* turn off led's */
@@ -2299,10 +2212,10 @@ static int skge_xmit_frame(struct sk_buff *skb, struct net_device *dev)
 
        local_irq_save(flags);
        if (!spin_trylock(&skge->tx_lock)) {
-               /* Collision - tell upper layer to requeue */ 
-               local_irq_restore(flags); 
-               return NETDEV_TX_LOCKED; 
-       } 
+               /* Collision - tell upper layer to requeue */
+               local_irq_restore(flags);
+               return NETDEV_TX_LOCKED;
+       }
 
        if (unlikely(skge->tx_avail < skb_shinfo(skb)->nr_frags +1)) {
                netif_stop_queue(dev);
@@ -2333,7 +2246,7 @@ static int skge_xmit_frame(struct sk_buff *skb, struct net_device *dev)
                 * does.  Looks like hardware is wrong?
                 */
                if (ip->protocol == IPPROTO_UDP
-                   && chip_rev(hw) == 0 && hw->chip_id == CHIP_ID_YUKON)
+                   && hw->chip_rev == 0 && hw->chip_id == CHIP_ID_YUKON)
                        control = BMU_TCP_CHECK;
                else
                        control = BMU_UDP_CHECK;
@@ -2394,6 +2307,7 @@ static int skge_xmit_frame(struct sk_buff *skb, struct net_device *dev)
 
 static inline void skge_tx_free(struct skge_hw *hw, struct skge_element *e)
 {
+       /* This ring element can be skb or fragment */
        if (e->skb) {
                pci_unmap_single(hw->pdev,
                               pci_unmap_addr(e, mapaddr),
@@ -2438,16 +2352,17 @@ static void skge_tx_timeout(struct net_device *dev)
 static int skge_change_mtu(struct net_device *dev, int new_mtu)
 {
        int err = 0;
+       int running = netif_running(dev);
 
-       if(new_mtu < ETH_ZLEN || new_mtu > ETH_JUMBO_MTU)
+       if (new_mtu < ETH_ZLEN || new_mtu > ETH_JUMBO_MTU)
                return -EINVAL;
 
-       dev->mtu = new_mtu;
 
-       if (netif_running(dev)) {
+       if (running)
                skge_down(dev);
+       dev->mtu = new_mtu;
+       if (running)
                skge_up(dev);
-       }
 
        return err;
 }
@@ -2462,7 +2377,9 @@ static void genesis_set_multicast(struct net_device *dev)
        u32 mode;
        u8 filter[8];
 
-       mode = skge_xm_read32(hw, port, XM_MODE);
+       pr_debug("genesis_set_multicast flags=%x count=%d\n", dev->flags, dev->mc_count);
+
+       mode = xm_read32(hw, port, XM_MODE);
        mode |= XM_MD_ENA_HASH;
        if (dev->flags & IFF_PROMISC)
                mode |= XM_MD_ENA_PROM;
@@ -2473,17 +2390,16 @@ static void genesis_set_multicast(struct net_device *dev)
                memset(filter, 0xff, sizeof(filter));
        else {
                memset(filter, 0, sizeof(filter));
-               for(i = 0; list && i < count; i++, list = list->next) {
-                       u32 crc = crc32_le(~0, list->dmi_addr, ETH_ALEN);
-                       u8 bit = 63 - (crc & 63);
-
+               for (i = 0; list && i < count; i++, list = list->next) {
+                       u32 crc, bit;
+                       crc = ether_crc_le(ETH_ALEN, list->dmi_addr);
+                       bit = ~crc & 0x3f;
                        filter[bit/8] |= 1 << (bit%8);
                }
        }
 
-       skge_xm_outhash(hw, port, XM_HSM, filter);
-
-       skge_xm_write32(hw, port, XM_MODE, mode);
+       xm_write32(hw, port, XM_MODE, mode);
+       xm_outhash(hw, port, XM_HSM, filter);
 }
 
 static void yukon_set_multicast(struct net_device *dev)
@@ -2497,7 +2413,7 @@ static void yukon_set_multicast(struct net_device *dev)
 
        memset(filter, 0, sizeof(filter));
 
-       reg = skge_gma_read16(hw, port, GM_RX_CTRL);
+       reg = gma_read16(hw, port, GM_RX_CTRL);
        reg |= GM_RXCR_UCF_ENA;
 
        if (dev->flags & IFF_PROMISC)           /* promiscious */
@@ -2510,23 +2426,23 @@ static void yukon_set_multicast(struct net_device *dev)
                int i;
                reg |= GM_RXCR_MCF_ENA;
 
-               for(i = 0; list && i < dev->mc_count; i++, list = list->next) {
+               for (i = 0; list && i < dev->mc_count; i++, list = list->next) {
                        u32 bit = ether_crc(ETH_ALEN, list->dmi_addr) & 0x3f;
                        filter[bit/8] |= 1 << (bit%8);
                }
        }
 
 
-       skge_gma_write16(hw, port, GM_MC_ADDR_H1,
+       gma_write16(hw, port, GM_MC_ADDR_H1,
                         (u16)filter[0] | ((u16)filter[1] << 8));
-       skge_gma_write16(hw, port, GM_MC_ADDR_H2,
+       gma_write16(hw, port, GM_MC_ADDR_H2,
                         (u16)filter[2] | ((u16)filter[3] << 8));
-       skge_gma_write16(hw, port, GM_MC_ADDR_H3,
+       gma_write16(hw, port, GM_MC_ADDR_H3,
                         (u16)filter[4] | ((u16)filter[5] << 8));
-       skge_gma_write16(hw, port, GM_MC_ADDR_H4,
+       gma_write16(hw, port, GM_MC_ADDR_H4,
                         (u16)filter[6] | ((u16)filter[7] << 8));
 
-       skge_gma_write16(hw, port, GM_RX_CTRL, reg);
+       gma_write16(hw, port, GM_RX_CTRL, reg);
 }
 
 static inline int bad_phy_status(const struct skge_hw *hw, u32 status)
@@ -2545,28 +2461,76 @@ static void skge_rx_error(struct skge_port *skge, int slot,
                printk(KERN_DEBUG PFX "%s: rx err, slot %d control 0x%x status 0x%x\n",
                       skge->netdev->name, slot, control, status);
 
-       if ((control & (BMU_EOF|BMU_STF)) != (BMU_STF|BMU_EOF)
-           || (control & BMU_BBC) > skge->netdev->mtu + VLAN_ETH_HLEN)
+       if ((control & (BMU_EOF|BMU_STF)) != (BMU_STF|BMU_EOF))
                skge->net_stats.rx_length_errors++;
-       else {
-               if (skge->hw->chip_id == CHIP_ID_GENESIS) {
-                       if (status & (XMR_FS_RUNT|XMR_FS_LNG_ERR))
-                               skge->net_stats.rx_length_errors++;
-                       if (status & XMR_FS_FRA_ERR)
-                               skge->net_stats.rx_frame_errors++;
-                       if (status & XMR_FS_FCS_ERR)
-                               skge->net_stats.rx_crc_errors++;
-               } else {
-                       if (status & (GMR_FS_LONG_ERR|GMR_FS_UN_SIZE))
-                               skge->net_stats.rx_length_errors++;
-                       if (status & GMR_FS_FRAGMENT)
-                               skge->net_stats.rx_frame_errors++;
-                       if (status & GMR_FS_CRC_ERR)
-                               skge->net_stats.rx_crc_errors++;
+       else if (skge->hw->chip_id == CHIP_ID_GENESIS) {
+               if (status & (XMR_FS_RUNT|XMR_FS_LNG_ERR))
+                       skge->net_stats.rx_length_errors++;
+               if (status & XMR_FS_FRA_ERR)
+                       skge->net_stats.rx_frame_errors++;
+               if (status & XMR_FS_FCS_ERR)
+                       skge->net_stats.rx_crc_errors++;
+       } else {
+               if (status & (GMR_FS_LONG_ERR|GMR_FS_UN_SIZE))
+                       skge->net_stats.rx_length_errors++;
+               if (status & GMR_FS_FRAGMENT)
+                       skge->net_stats.rx_frame_errors++;
+               if (status & GMR_FS_CRC_ERR)
+                       skge->net_stats.rx_crc_errors++;
+       }
+}
+
+/* Get receive buffer from descriptor.
+ * Handles copy of small buffers and reallocation failures
+ */
+static inline struct sk_buff *skge_rx_get(struct skge_port *skge,
+                                         struct skge_element *e,
+                                         unsigned int len)
+{
+       struct sk_buff *nskb, *skb;
+
+       if (len < RX_COPY_THRESHOLD) {
+               nskb = skge_rx_alloc(skge->netdev, len + NET_IP_ALIGN);
+               if (unlikely(!nskb))
+                       return NULL;
+
+               pci_dma_sync_single_for_cpu(skge->hw->pdev,
+                                           pci_unmap_addr(e, mapaddr),
+                                           len, PCI_DMA_FROMDEVICE);
+               memcpy(nskb->data, e->skb->data, len);
+               pci_dma_sync_single_for_device(skge->hw->pdev,
+                                              pci_unmap_addr(e, mapaddr),
+                                              len, PCI_DMA_FROMDEVICE);
+
+               if (skge->rx_csum) {
+                       struct skge_rx_desc *rd = e->desc;
+                       nskb->csum = le16_to_cpu(rd->csum2);
+                       nskb->ip_summed = CHECKSUM_HW;
                }
+               skge_rx_reuse(e, skge->rx_buf_size);
+               return nskb;
+       } else {
+               nskb = skge_rx_alloc(skge->netdev, skge->rx_buf_size);
+               if (unlikely(!nskb))
+                       return NULL;
+
+               pci_unmap_single(skge->hw->pdev,
+                                pci_unmap_addr(e, mapaddr),
+                                pci_unmap_len(e, maplen),
+                                PCI_DMA_FROMDEVICE);
+               skb = e->skb;
+               if (skge->rx_csum) {
+                       struct skge_rx_desc *rd = e->desc;
+                       skb->csum = le16_to_cpu(rd->csum2);
+                       skb->ip_summed = CHECKSUM_HW;
+               }
+
+               skge_rx_setup(skge, e, nskb, skge->rx_buf_size);
+               return skb;
        }
 }
 
+
 static int skge_poll(struct net_device *dev, int *budget)
 {
        struct skge_port *skge = netdev_priv(dev);
@@ -2575,13 +2539,12 @@ static int skge_poll(struct net_device *dev, int *budget)
        struct skge_element *e;
        unsigned int to_do = min(dev->quota, *budget);
        unsigned int work_done = 0;
-       int done;
-       static const u32 irqmask[] = { IS_PORT_1, IS_PORT_2 };
 
-       for (e = ring->to_clean; e != ring->to_use && work_done < to_do;
-            e = e->next) {
+       pr_debug("skge_poll\n");
+
+       for (e = ring->to_clean; work_done < to_do; e = e->next) {
                struct skge_rx_desc *rd = e->desc;
-               struct sk_buff *skb = e->skb;
+               struct sk_buff *skb;
                u32 control, len, status;
 
                rmb();
@@ -2590,19 +2553,12 @@ static int skge_poll(struct net_device *dev, int *budget)
                        break;
 
                len = control & BMU_BBC;
-               e->skb = NULL;
-
-               pci_unmap_single(hw->pdev,
-                                pci_unmap_addr(e, mapaddr),
-                                pci_unmap_len(e, maplen),
-                                PCI_DMA_FROMDEVICE);
-
                status = rd->status;
-               if ((control & (BMU_EOF|BMU_STF)) != (BMU_STF|BMU_EOF)
-                    || len > dev->mtu + VLAN_ETH_HLEN
-                    || bad_phy_status(hw, status)) {
+
+               if (unlikely((control & (BMU_EOF|BMU_STF)) != (BMU_STF|BMU_EOF)
+                            || bad_phy_status(hw, status))) {
                        skge_rx_error(skge, e - ring->start, control, status);
-                       dev_kfree_skb(skb);
+                       skge_rx_reuse(e, skge->rx_buf_size);
                        continue;
                }
 
@@ -2610,43 +2566,37 @@ static int skge_poll(struct net_device *dev, int *budget)
                    printk(KERN_DEBUG PFX "%s: rx slot %td status 0x%x len %d\n",
                           dev->name, e - ring->start, rd->status, len);
 
-               skb_put(skb, len);
-               skb->protocol = eth_type_trans(skb, dev);
-
-               if (skge->rx_csum) {
-                       skb->csum = le16_to_cpu(rd->csum2);
-                       skb->ip_summed = CHECKSUM_HW;
-               }
+               skb = skge_rx_get(skge, e, len);
+               if (likely(skb)) {
+                       skb_put(skb, len);
+                       skb->protocol = eth_type_trans(skb, dev);
 
-               dev->last_rx = jiffies;
-               netif_receive_skb(skb);
+                       dev->last_rx = jiffies;
+                       netif_receive_skb(skb);
 
-               ++work_done;
+                       ++work_done;
+               } else
+                       skge_rx_reuse(e, skge->rx_buf_size);
        }
        ring->to_clean = e;
 
-       *budget -= work_done;
-       dev->quota -= work_done;
-       done = work_done < to_do;
-
-       if (skge_rx_fill(skge))
-               done = 0;
-
        /* restart receiver */
        wmb();
        skge_write8(hw, Q_ADDR(rxqaddr[skge->port], Q_CSR),
                    CSR_START | CSR_IRQ_CL_F);
 
-       if (done) {
-               local_irq_disable();
-               hw->intr_mask |= irqmask[skge->port];
-               /* Order is important since data can get interrupted */
-               skge_write32(hw, B0_IMSK, hw->intr_mask);
-               __netif_rx_complete(dev);
-               local_irq_enable();
-       }
+       *budget -= work_done;
+       dev->quota -= work_done;
 
-       return !done;
+       if (work_done >=  to_do)
+               return 1; /* not done */
+
+       local_irq_disable();
+       __netif_rx_complete(dev);
+       hw->intr_mask |= portirqmask[skge->port];
+       skge_write32(hw, B0_IMSK, hw->intr_mask);
+       local_irq_enable();
+       return 0;
 }
 
 static inline void skge_tx_intr(struct net_device *dev)
@@ -2657,7 +2607,7 @@ static inline void skge_tx_intr(struct net_device *dev)
        struct skge_element *e;
 
        spin_lock(&skge->tx_lock);
-       for(e = ring->to_clean; e != ring->to_use; e = e->next) {
+       for (e = ring->to_clean; e != ring->to_use; e = e->next) {
                struct skge_tx_desc *td = e->desc;
                u32 control;
 
@@ -2690,12 +2640,12 @@ static void skge_mac_parity(struct skge_hw *hw, int port)
               : (port == 0 ? "(port A)": "(port B"));
 
        if (hw->chip_id == CHIP_ID_GENESIS)
-               skge_write16(hw, SKGEMAC_REG(port, TX_MFF_CTRL1),
+               skge_write16(hw, SK_REG(port, TX_MFF_CTRL1),
                             MFF_CLR_PERR);
        else
                /* HW-Bug #8: cleared by GMF_CLI_TX_FC instead of GMF_CLI_TX_PE */
-               skge_write8(hw, SKGEMAC_REG(port, TX_GMF_CTRL_T),
-                           (hw->chip_id == CHIP_ID_YUKON && chip_rev(hw) == 0)
+               skge_write8(hw, SK_REG(port, TX_GMF_CTRL_T),
+                           (hw->chip_id == CHIP_ID_YUKON && hw->chip_rev == 0)
                            ? GMF_CLI_TX_FC : GMF_CLI_TX_PE);
 }
 
@@ -2703,16 +2653,16 @@ static void skge_pci_clear(struct skge_hw *hw)
 {
        u16 status;
 
-       status = skge_read16(hw, SKGEPCI_REG(PCI_STATUS));
+       pci_read_config_word(hw->pdev, PCI_STATUS, &status);
        skge_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
-       skge_write16(hw, SKGEPCI_REG(PCI_STATUS),
-                    status | PCI_STATUS_ERROR_BITS);
+       pci_write_config_word(hw->pdev, PCI_STATUS,
+                             status | PCI_STATUS_ERROR_BITS);
        skge_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
 }
 
 static void skge_mac_intr(struct skge_hw *hw, int port)
 {
-       if (hw->chip_id == CHIP_ID_GENESIS) 
+       if (hw->chip_id == CHIP_ID_GENESIS)
                genesis_mac_intr(hw, port);
        else
                yukon_mac_intr(hw, port);
@@ -2726,9 +2676,9 @@ static void skge_error_irq(struct skge_hw *hw)
        if (hw->chip_id == CHIP_ID_GENESIS) {
                /* clear xmac errors */
                if (hwstatus & (IS_NO_STAT_M1|IS_NO_TIST_M1))
-                       skge_write16(hw, SKGEMAC_REG(0, RX_MFF_CTRL1), MFF_CLR_INSTAT);
+                       skge_write16(hw, SK_REG(0, RX_MFF_CTRL1), MFF_CLR_INSTAT);
                if (hwstatus & (IS_NO_STAT_M2|IS_NO_TIST_M2))
-                       skge_write16(hw, SKGEMAC_REG(0, RX_MFF_CTRL2), MFF_CLR_INSTAT);
+                       skge_write16(hw, SK_REG(0, RX_MFF_CTRL2), MFF_CLR_INSTAT);
        } else {
                /* Timestamp (unused) overflow */
                if (hwstatus & IS_IRQ_TIST_OV)
@@ -2803,8 +2753,8 @@ static void skge_extirq(unsigned long data)
 
                        if (hw->chip_id != CHIP_ID_GENESIS)
                                yukon_phy_intr(skge);
-                       else if (hw->phy_type == SK_PHY_BCOM)
-                               genesis_bcom_intr(skge);
+                       else
+                               bcom_phy_intr(skge);
                }
        }
        spin_unlock(&hw->phy_lock);
@@ -2824,19 +2774,14 @@ static irqreturn_t skge_intr(int irq, void *dev_id, struct pt_regs *regs)
                return IRQ_NONE;
 
        status &= hw->intr_mask;
-
-       if ((status & IS_R1_F) && netif_rx_schedule_prep(hw->dev[0])) {
-               status &= ~IS_R1_F;
+       if (status & IS_R1_F) {
                hw->intr_mask &= ~IS_R1_F;
-               skge_write32(hw, B0_IMSK, hw->intr_mask);
-               __netif_rx_schedule(hw->dev[0]);
+               netif_rx_schedule(hw->dev[0]);
        }
 
-       if ((status & IS_R2_F) && netif_rx_schedule_prep(hw->dev[1])) {
-               status &= ~IS_R2_F;
+       if (status & IS_R2_F) {
                hw->intr_mask &= ~IS_R2_F;
-               skge_write32(hw, B0_IMSK, hw->intr_mask);
-               __netif_rx_schedule(hw->dev[1]);
+               netif_rx_schedule(hw->dev[1]);
        }
 
        if (status & IS_XA1_F)
@@ -2845,9 +2790,27 @@ static irqreturn_t skge_intr(int irq, void *dev_id, struct pt_regs *regs)
        if (status & IS_XA2_F)
                skge_tx_intr(hw->dev[1]);
 
+       if (status & IS_PA_TO_RX1) {
+               struct skge_port *skge = netdev_priv(hw->dev[0]);
+               ++skge->net_stats.rx_over_errors;
+               skge_write16(hw, B3_PA_CTRL, PA_CLR_TO_RX1);
+       }
+
+       if (status & IS_PA_TO_RX2) {
+               struct skge_port *skge = netdev_priv(hw->dev[1]);
+               ++skge->net_stats.rx_over_errors;
+               skge_write16(hw, B3_PA_CTRL, PA_CLR_TO_RX2);
+       }
+
+       if (status & IS_PA_TO_TX1)
+               skge_write16(hw, B3_PA_CTRL, PA_CLR_TO_TX1);
+
+       if (status & IS_PA_TO_TX2)
+               skge_write16(hw, B3_PA_CTRL, PA_CLR_TO_TX2);
+
        if (status & IS_MAC1)
                skge_mac_intr(hw, 0);
-       
+
        if (status & IS_MAC2)
                skge_mac_intr(hw, 1);
 
@@ -2859,8 +2822,7 @@ static irqreturn_t skge_intr(int irq, void *dev_id, struct pt_regs *regs)
                tasklet_schedule(&hw->ext_tasklet);
        }
 
-       if (status)
-               skge_write32(hw, B0_IMSK, hw->intr_mask);
+       skge_write32(hw, B0_IMSK, hw->intr_mask);
 
        return IRQ_HANDLED;
 }
@@ -2904,9 +2866,6 @@ static const struct {
        { CHIP_ID_YUKON,         "Yukon" },
        { CHIP_ID_YUKON_LITE,    "Yukon-Lite"},
        { CHIP_ID_YUKON_LP,      "Yukon-LP"},
-       { CHIP_ID_YUKON_XL,      "Yukon-2 XL"},
-       { CHIP_ID_YUKON_EC,      "YUKON-2 EC"},
-       { CHIP_ID_YUKON_FE,      "YUKON-2 FE"},
 };
 
 static const char *skge_board_name(const struct skge_hw *hw)
@@ -2930,8 +2889,8 @@ static const char *skge_board_name(const struct skge_hw *hw)
 static int skge_reset(struct skge_hw *hw)
 {
        u16 ctst;
-       u8 t8;
-       int i, ports;
+       u8 t8, mac_cfg;
+       int i;
 
        ctst = skge_read16(hw, B0_CTST);
 
@@ -2952,12 +2911,9 @@ static int skge_reset(struct skge_hw *hw)
        hw->phy_type = skge_read8(hw, B2_E_1) & 0xf;
        hw->pmd_type = skge_read8(hw, B2_PMD_TYP);
 
-       switch(hw->chip_id) {
+       switch (hw->chip_id) {
        case CHIP_ID_GENESIS:
                switch (hw->phy_type) {
-               case SK_PHY_XMAC:
-                       hw->phy_addr = PHY_ADDR_XMAC;
-                       break;
                case SK_PHY_BCOM:
                        hw->phy_addr = PHY_ADDR_BCOM;
                        break;
@@ -2986,8 +2942,9 @@ static int skge_reset(struct skge_hw *hw)
                return -EOPNOTSUPP;
        }
 
-       hw->mac_cfg = skge_read8(hw, B2_MAC_CFG);
-       ports = isdualport(hw) ? 2 : 1;
+       mac_cfg = skge_read8(hw, B2_MAC_CFG);
+       hw->ports = (mac_cfg & CFG_SNG_MAC) ? 1 : 2;
+       hw->chip_rev = (mac_cfg & CFG_CHIP_R_MSK) >> 4;
 
        /* read the adapters RAM size */
        t8 = skge_read8(hw, B2_E_0);
@@ -3010,9 +2967,9 @@ static int skge_reset(struct skge_hw *hw)
                /* switch power to VCC (WA for VAUX problem) */
                skge_write8(hw, B0_POWER_CTRL,
                            PC_VAUX_ENA | PC_VCC_ENA | PC_VAUX_OFF | PC_VCC_ON);
-               for (i = 0; i < ports; i++) {
-                       skge_write16(hw, SKGEMAC_REG(i, GMAC_LINK_CTRL), GMLC_RST_SET);
-                       skge_write16(hw, SKGEMAC_REG(i, GMAC_LINK_CTRL), GMLC_RST_CLR);
+               for (i = 0; i < hw->ports; i++) {
+                       skge_write16(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_SET);
+                       skge_write16(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_CLR);
                }
        }
 
@@ -3022,8 +2979,8 @@ static int skge_reset(struct skge_hw *hw)
        skge_write8(hw, B0_LED, LED_STAT_ON);
 
        /* enable the Tx Arbiters */
-       for (i = 0; i < ports; i++)
-               skge_write8(hw, SKGEMAC_REG(i, TXA_CTRL), TXA_ENA_ARB);
+       for (i = 0; i < hw->ports; i++)
+               skge_write8(hw, SK_REG(i, TXA_CTRL), TXA_ENA_ARB);
 
        /* Initialize ram interface */
        skge_write16(hw, B3_RI_CTRL, RI_RST_CLR);
@@ -3050,16 +3007,14 @@ static int skge_reset(struct skge_hw *hw)
        skge_write32(hw, B2_IRQM_INI, skge_usecs2clk(hw, 100));
        skge_write32(hw, B2_IRQM_CTRL, TIM_START);
 
-       hw->intr_mask = IS_HW_ERR | IS_EXT_REG | IS_PORT_1;
-       if (isdualport(hw))
-               hw->intr_mask |= IS_PORT_2;
+       hw->intr_mask = IS_HW_ERR | IS_EXT_REG;
        skge_write32(hw, B0_IMSK, hw->intr_mask);
 
        if (hw->chip_id != CHIP_ID_GENESIS)
                skge_write8(hw, GMAC_IRQ_MSK, 0);
 
        spin_lock_bh(&hw->phy_lock);
-       for (i = 0; i < ports; i++) {
+       for (i = 0; i < hw->ports; i++) {
                if (hw->chip_id == CHIP_ID_GENESIS)
                        genesis_reset(hw, i);
                else
@@ -3071,7 +3026,8 @@ static int skge_reset(struct skge_hw *hw)
 }
 
 /* Initialize network device */
-static struct net_device *skge_devinit(struct skge_hw *hw, int port)
+static struct net_device *skge_devinit(struct skge_hw *hw, int port,
+                                      int highmem)
 {
        struct skge_port *skge;
        struct net_device *dev = alloc_etherdev(sizeof(*skge));
@@ -3104,6 +3060,8 @@ static struct net_device *skge_devinit(struct skge_hw *hw, int port)
 #endif
        dev->irq = hw->pdev->irq;
        dev->features = NETIF_F_LLTX;
+       if (highmem)
+               dev->features |= NETIF_F_HIGHDMA;
 
        skge = netdev_priv(dev);
        skge->netdev = dev;
@@ -3117,7 +3075,7 @@ static struct net_device *skge_devinit(struct skge_hw *hw, int port)
        skge->flow_control = FLOW_MODE_SYMMETRIC;
        skge->duplex = -1;
        skge->speed = -1;
-       skge->advertising = skge_modes(hw);
+       skge->advertising = skge_supported_modes(hw);
 
        hw->dev[port] = dev;
 
@@ -3125,10 +3083,6 @@ static struct net_device *skge_devinit(struct skge_hw *hw, int port)
 
        spin_lock_init(&skge->tx_lock);
 
-       init_timer(&skge->link_check);
-       skge->link_check.function = skge_link_timer;
-       skge->link_check.data = (unsigned long) skge;
-
        init_timer(&skge->led_blink);
        skge->led_blink.function = skge_blink_timer;
        skge->led_blink.data = (unsigned long) skge;
@@ -3232,14 +3186,11 @@ static int __devinit skge_probe(struct pci_dev *pdev,
 
        printk(KERN_INFO PFX "addr 0x%lx irq %d chip %s rev %d\n",
               pci_resource_start(pdev, 0), pdev->irq,
-              skge_board_name(hw), chip_rev(hw));
+              skge_board_name(hw), hw->chip_rev);
 
-       if ((dev = skge_devinit(hw, 0)) == NULL)
+       if ((dev = skge_devinit(hw, 0, using_dac)) == NULL)
                goto err_out_led_off;
 
-       if (using_dac)
-               dev->features |= NETIF_F_HIGHDMA;
-
        if ((err = register_netdev(dev))) {
                printk(KERN_ERR PFX "%s: cannot register net device\n",
                       pci_name(pdev));
@@ -3248,10 +3199,7 @@ static int __devinit skge_probe(struct pci_dev *pdev,
 
        skge_show_addr(dev);
 
-       if (isdualport(hw) && (dev1 = skge_devinit(hw, 1))) {
-               if (using_dac)
-                       dev1->features |= NETIF_F_HIGHDMA;
-
+       if (hw->ports > 1 && (dev1 = skge_devinit(hw, 1, using_dac))) {
                if (register_netdev(dev1) == 0)
                        skge_show_addr(dev1);
                else {
@@ -3288,7 +3236,7 @@ static void __devexit skge_remove(struct pci_dev *pdev)
        struct skge_hw *hw  = pci_get_drvdata(pdev);
        struct net_device *dev0, *dev1;
 
-       if(!hw)
+       if (!hw)
                return;
 
        if ((dev1 = hw->dev[1]))
@@ -3316,7 +3264,7 @@ static int skge_suspend(struct pci_dev *pdev, u32 state)
        struct skge_hw *hw  = pci_get_drvdata(pdev);
        int i, wol = 0;
 
-       for(i = 0; i < 2; i++) {
+       for (i = 0; i < 2; i++) {
                struct net_device *dev = hw->dev[i];
 
                if (dev) {
@@ -3349,11 +3297,11 @@ static int skge_resume(struct pci_dev *pdev)
 
        skge_reset(hw);
 
-       for(i = 0; i < 2; i++) {
+       for (i = 0; i < 2; i++) {
                struct net_device *dev = hw->dev[i];
                if (dev) {
                        netif_device_attach(dev);
-                       if(netif_running(dev))
+                       if (netif_running(dev))
                                skge_up(dev);
                }
        }
index 36c62b68fab4f8a5185ccb8eb4ef2a5fa0d91122..14d0cc01fb9a7ee90abae1648ee7a79746928f0a 100644 (file)
@@ -7,31 +7,6 @@
 /* PCI config registers */
 #define PCI_DEV_REG1   0x40
 #define PCI_DEV_REG2   0x44
-#ifndef PCI_VPD
-#define PCI_VPD                0x50
-#endif
-
-/*     PCI_OUR_REG_2           32 bit  Our Register 2 */
-enum {
-       PCI_VPD_WR_THR  = 0xff<<24, /* Bit 31..24:      VPD Write Threshold */
-       PCI_DEV_SEL     = 0x7f<<17, /* Bit 23..17:      EEPROM Device Select */
-       PCI_VPD_ROM_SZ  = 7   <<14, /* Bit 16..14:      VPD ROM Size    */
-                                   /* Bit 13..12:      reserved        */
-       PCI_EN_DUMMY_RD = 1<<3, /* Enable Dummy Read */
-       PCI_REV_DESC    = 1<<2, /* Reverse Desc. Bytes */
-       PCI_USEDATA64   = 1<<0, /* Use 64Bit Data bus ext */
-};
-
-/*     PCI_VPD_ADR_REG         16 bit  VPD Address Register */
-enum {
-       PCI_VPD_FLAG    = 1<<15,  /* starts VPD rd/wr cycle */
-       PCI_VPD_ADR_MSK =0x7fffL, /* Bit 14.. 0:        VPD Address Mask */
-       VPD_RES_ID      = 0x82,
-       VPD_RES_READ    = 0x90,
-       VPD_RES_WRITE   = 0x81,
-       VPD_RES_END     = 0x78,
-};
-
 
 #define PCI_STATUS_ERROR_BITS (PCI_STATUS_DETECTED_PARITY | \
                               PCI_STATUS_SIG_SYSTEM_ERROR | \
@@ -39,7 +14,6 @@ enum {
                               PCI_STATUS_REC_TARGET_ABORT | \
                               PCI_STATUS_PARITY)
 
-
 enum csr_regs {
        B0_RAP  = 0x0000,
        B0_CTST = 0x0004,
@@ -229,8 +203,11 @@ enum {
        IS_XA2_F        = 1<<1,         /* Q_XA2 End of Frame */
        IS_XA2_C        = 1<<0,         /* Q_XA2 Encoding Error */
 
-       IS_PORT_1       = IS_XA1_F| IS_R1_F| IS_MAC1,
-       IS_PORT_2       = IS_XA2_F| IS_R2_F| IS_MAC2,
+       IS_TO_PORT1     = IS_PA_TO_RX1 | IS_PA_TO_TX1,
+       IS_TO_PORT2     = IS_PA_TO_RX2 | IS_PA_TO_TX2,
+
+       IS_PORT_1       = IS_XA1_F| IS_R1_F | IS_TO_PORT1 | IS_MAC1,
+       IS_PORT_2       = IS_XA2_F| IS_R2_F | IS_TO_PORT2 | IS_MAC2,
 };
 
 
@@ -288,14 +265,6 @@ enum {
        CHIP_REV_YU_LITE_A3  = 7,       /* Chip Rev. for YUKON-Lite A3 */
 };
 
-/*     B2_LD_TEST               8 bit  EPROM loader test register */
-enum {
-       LD_T_ON         = 1<<3, /* Loader Test mode on */
-       LD_T_OFF        = 1<<2, /* Loader Test mode off */
-       LD_T_STEP       = 1<<1, /* Decrement FPROM addr. Counter */
-       LD_START        = 1<<0, /* Start loading FPROM */
-};
-
 /*     B2_TI_CTRL               8 bit  Timer control */
 /*     B2_IRQM_CTRL     8 bit  IRQ Moderation Timer Control */
 enum {
@@ -313,16 +282,6 @@ enum {
        TIM_T_STEP      = 1<<0, /* Test step */
 };
 
-/*     B28_DPT_INI     32 bit  Descriptor Poll Timer Init Val */
-/*     B28_DPT_VAL     32 bit  Descriptor Poll Timer Curr Val */
-/*     B28_DPT_CTRL     8 bit  Descriptor Poll Timer Ctrl Reg */
-enum {
-       DPT_MSK = 0x00ffffffL,  /* Bit 23.. 0:  Desc Poll Timer Bits */
-
-       DPT_START       = 1<<1, /* Start Descriptor Poll Timer */
-       DPT_STOP        = 1<<0, /* Stop  Descriptor Poll Timer */
-};
-
 /*     B2_GP_IO                32 bit  General Purpose I/O Register */
 enum {
        GP_DIR_9 = 1<<25, /* IO_9 direct, 0=In/1=Out */
@@ -348,30 +307,6 @@ enum {
        GP_IO_0 = 1<<0, /* IO_0 pin */
 };
 
-/* Rx/Tx Path related Arbiter Test Registers */
-/*     B3_MA_TO_TEST   16 bit  MAC Arbiter Timeout Test Reg */
-/*     B3_MA_RC_TEST   16 bit  MAC Arbiter Recovery Test Reg */
-/*     B3_PA_TEST              16 bit  Packet Arbiter Test Register */
-/*                     Bit 15, 11, 7, and 3 are reserved in B3_PA_TEST */
-enum {
-       TX2_T_EV        = 1<<15,/* TX2 Timeout/Recv Event occured */
-       TX2_T_ON        = 1<<14,/* TX2 Timeout/Recv Timer Test On */
-       TX2_T_OFF       = 1<<13,/* TX2 Timeout/Recv Timer Tst Off */
-       TX2_T_STEP      = 1<<12,/* TX2 Timeout/Recv Timer Step */
-       TX1_T_EV        = 1<<11,/* TX1 Timeout/Recv Event occured */
-       TX1_T_ON        = 1<<10,/* TX1 Timeout/Recv Timer Test On */
-       TX1_T_OFF       = 1<<9, /* TX1 Timeout/Recv Timer Tst Off */
-       TX1_T_STEP      = 1<<8, /* TX1 Timeout/Recv Timer Step */
-       RX2_T_EV        = 1<<7, /* RX2 Timeout/Recv Event occured */
-       RX2_T_ON        = 1<<6, /* RX2 Timeout/Recv Timer Test On */
-       RX2_T_OFF       = 1<<5, /* RX2 Timeout/Recv Timer Tst Off */
-       RX2_T_STEP      = 1<<4, /* RX2 Timeout/Recv Timer Step */
-       RX1_T_EV        = 1<<3, /* RX1 Timeout/Recv Event occured */
-       RX1_T_ON        = 1<<2, /* RX1 Timeout/Recv Timer Test On */
-       RX1_T_OFF       = 1<<1, /* RX1 Timeout/Recv Timer Tst Off */
-       RX1_T_STEP      = 1<<0, /* RX1 Timeout/Recv Timer Step */
-};
-
 /* Descriptor Bit Definition */
 /*     TxCtrl          Transmit Buffer Control Field */
 /*     RxCtrl          Receive  Buffer Control Field */
@@ -428,14 +363,6 @@ enum {
        RI_RST_SET      = 1<<0, /* Set   RAM Interface Reset */
 };
 
-/*     B3_RI_TEST               8 bit  RAM Iface Test Register */
-enum {
-       RI_T_EV = 1<<3, /* Timeout Event occured */
-       RI_T_ON = 1<<2, /* Timeout Timer Test On */
-       RI_T_OFF        = 1<<1, /* Timeout Timer Test Off */
-       RI_T_STEP       = 1<<0, /* Timeout Timer Step */
-};
-
 /* MAC Arbiter Registers */
 /*     B3_MA_TO_CTRL   16 bit  MAC Arbiter Timeout Ctrl Reg */
 enum {
@@ -452,19 +379,6 @@ enum {
 #define SK_PKT_TO_MAX  0xffff          /* Maximum value */
 #define SK_RI_TO_53    36              /* RAM interface timeout */
 
-
-/*     B3_MA_RC_CTRL   16 bit  MAC Arbiter Recovery Ctrl Reg */
-enum {
-       MA_ENA_REC_TX2  = 1<<7, /* Enable  Recovery Timer TX2 */
-       MA_DIS_REC_TX2  = 1<<6, /* Disable Recovery Timer TX2 */
-       MA_ENA_REC_TX1  = 1<<5, /* Enable  Recovery Timer TX1 */
-       MA_DIS_REC_TX1  = 1<<4, /* Disable Recovery Timer TX1 */
-       MA_ENA_REC_RX2  = 1<<3, /* Enable  Recovery Timer RX2 */
-       MA_DIS_REC_RX2  = 1<<2, /* Disable Recovery Timer RX2 */
-       MA_ENA_REC_RX1  = 1<<1, /* Enable  Recovery Timer RX1 */
-       MA_DIS_REC_RX1  = 1<<0, /* Disable Recovery Timer RX1 */
-};
-
 /* Packet Arbiter Registers */
 /*     B3_PA_CTRL              16 bit  Packet Arbiter Ctrl Register */
 enum {
@@ -488,7 +402,7 @@ enum {
                                                PA_ENA_TO_TX1 | PA_ENA_TO_TX2)
 
 
-/* Transmit Arbiter Registers MAC 1 and 2, use MR_ADDR() to access */
+/* Transmit Arbiter Registers MAC 1 and 2, use SK_REG() to access */
 /*     TXA_ITI_INI             32 bit  Tx Arb Interval Timer Init Val */
 /*     TXA_ITI_VAL             32 bit  Tx Arb Interval Timer Value */
 /*     TXA_LIM_INI             32 bit  Tx Arb Limit Counter Init Val */
@@ -511,7 +425,7 @@ enum {
 /*
  *     Bank 4 - 5
  */
-/* Transmit Arbiter Registers MAC 1 and 2, use MR_ADDR() to access */
+/* Transmit Arbiter Registers MAC 1 and 2, use SK_REG() to access */
 enum {
        TXA_ITI_INI     = 0x0200,/* 32 bit      Tx Arb Interval Timer Init Val*/
        TXA_ITI_VAL     = 0x0204,/* 32 bit      Tx Arb Interval Timer Value */
@@ -537,7 +451,7 @@ enum {
 
 /* Queue Register Offsets, use Q_ADDR() to access */
 enum {
-       B8_Q_REGS = 0x0400, /* base of Queue registers */       
+       B8_Q_REGS = 0x0400, /* base of Queue registers */
        Q_D     = 0x00, /* 8*32 bit     Current Descriptor */
        Q_DA_L  = 0x20, /* 32 bit       Current Descriptor Address Low dWord */
        Q_DA_H  = 0x24, /* 32 bit       Current Descriptor Address High dWord */
@@ -618,8 +532,7 @@ enum {
 enum {
        PHY_ADDR_XMAC   = 0<<8,
        PHY_ADDR_BCOM   = 1<<8,
-       PHY_ADDR_LONE   = 3<<8,
-       PHY_ADDR_NAT    = 0<<8,
+
 /* GPHY address (bits 15..11 of SMI control reg) */
        PHY_ADDR_MARV   = 0,
 };
@@ -986,7 +899,7 @@ enum {
        LINKLED_BLINK_OFF    = 0x10,
        LINKLED_BLINK_ON     = 0x20,
 };
-       
+
 /* GMAC and GPHY Control Registers (YUKON only) */
 enum {
        GMAC_CTRL       = 0x0f00,/* 32 bit      GMAC Control Reg */
@@ -1151,54 +1064,6 @@ enum {
        PHY_MARV_FE_SPEC_2      = 0x1c,/* 16 bit r/w    Specific Control Reg. 2 */
 };
 
-/* Level One-PHY Registers, indirect addressed over XMAC */
-enum {
-       PHY_LONE_CTRL           = 0x00,/* 16 bit r/w    PHY Control Register */
-       PHY_LONE_STAT           = 0x01,/* 16 bit r/o    PHY Status Register */
-       PHY_LONE_ID0            = 0x02,/* 16 bit r/o    PHY ID0 Register */
-       PHY_LONE_ID1            = 0x03,/* 16 bit r/o    PHY ID1 Register */
-       PHY_LONE_AUNE_ADV       = 0x04,/* 16 bit r/w    Auto-Neg. Advertisement */
-       PHY_LONE_AUNE_LP        = 0x05,/* 16 bit r/o    Link Part Ability Reg */
-       PHY_LONE_AUNE_EXP       = 0x06,/* 16 bit r/o    Auto-Neg. Expansion Reg */
-       PHY_LONE_NEPG           = 0x07,/* 16 bit r/w    Next Page Register */
-       PHY_LONE_NEPG_LP        = 0x08,/* 16 bit r/o    Next Page Link Partner */
-       /* Level One-specific registers */
-       PHY_LONE_1000T_CTRL     = 0x09,/* 16 bit r/w    1000Base-T Control Reg */
-       PHY_LONE_1000T_STAT     = 0x0a,/* 16 bit r/o    1000Base-T Status Reg */
-       PHY_LONE_EXT_STAT       = 0x0f,/* 16 bit r/o    Extended Status Reg */
-       PHY_LONE_PORT_CFG       = 0x10,/* 16 bit r/w    Port Configuration Reg*/
-       PHY_LONE_Q_STAT         = 0x11,/* 16 bit r/o    Quick Status Reg */
-       PHY_LONE_INT_ENAB       = 0x12,/* 16 bit r/w    Interrupt Enable Reg */
-       PHY_LONE_INT_STAT       = 0x13,/* 16 bit r/o    Interrupt Status Reg */
-       PHY_LONE_LED_CFG        = 0x14,/* 16 bit r/w    LED Configuration Reg */
-       PHY_LONE_PORT_CTRL      = 0x15,/* 16 bit r/w    Port Control Reg */
-       PHY_LONE_CIM            = 0x16,/* 16 bit r/o    CIM Reg */
-};
-
-/* National-PHY Registers, indirect addressed over XMAC */
-enum {
-       PHY_NAT_CTRL            = 0x00,/* 16 bit r/w    PHY Control Register */
-       PHY_NAT_STAT            = 0x01,/* 16 bit r/w    PHY Status Register */
-       PHY_NAT_ID0             = 0x02,/* 16 bit r/o    PHY ID0 Register */
-       PHY_NAT_ID1             = 0x03,/* 16 bit r/o    PHY ID1 Register */
-       PHY_NAT_AUNE_ADV        = 0x04,/* 16 bit r/w    Auto-Neg. Advertisement */
-       PHY_NAT_AUNE_LP         = 0x05,/* 16 bit r/o    Link Partner Ability Reg */
-       PHY_NAT_AUNE_EXP        = 0x06,/* 16 bit r/o    Auto-Neg. Expansion Reg */
-       PHY_NAT_NEPG            = 0x07,/* 16 bit r/w    Next Page Register */
-       PHY_NAT_NEPG_LP         = 0x08,/* 16 bit r/o    Next Page Link Partner Reg */
-       /* National-specific registers */
-       PHY_NAT_1000T_CTRL      = 0x09,/* 16 bit r/w    1000Base-T Control Reg */
-       PHY_NAT_1000T_STAT      = 0x0a,/* 16 bit r/o    1000Base-T Status Reg */
-       PHY_NAT_EXT_STAT        = 0x0f,/* 16 bit r/o    Extended Status Register */
-       PHY_NAT_EXT_CTRL1       = 0x10,/* 16 bit r/o    Extended Control Reg1 */
-       PHY_NAT_Q_STAT1         = 0x11,/* 16 bit r/o    Quick Status Reg1 */
-       PHY_NAT_10B_OP          = 0x12,/* 16 bit r/o    10Base-T Operations Reg */
-       PHY_NAT_EXT_CTRL2       = 0x13,/* 16 bit r/o    Extended Control Reg1 */
-       PHY_NAT_Q_STAT2         = 0x14,/* 16 bit r/o    Quick Status Reg2 */
-
-       PHY_NAT_PHY_ADDR        = 0x19,/* 16 bit r/o    PHY Address Register */
-};
-
 enum {
        PHY_CT_RESET    = 1<<15, /* Bit 15: (sc)        clear all PHY related regs */
        PHY_CT_LOOP     = 1<<14, /* Bit 14:     enable Loopback over PHY */
@@ -1253,8 +1118,29 @@ enum {
        PHY_MARV_ID1_Y2 = 0x0C91, /* Yukon-2 (PHY 88E1112) */
 };
 
+/* Advertisement register bits */
 enum {
        PHY_AN_NXT_PG   = 1<<15, /* Bit 15:     Request Next Page */
+       PHY_AN_ACK      = 1<<14, /* Bit 14:     (ro) Acknowledge Received */
+       PHY_AN_RF       = 1<<13, /* Bit 13:     Remote Fault Bits */
+
+       PHY_AN_PAUSE_ASYM = 1<<11,/* Bit 11:    Try for asymmetric */
+       PHY_AN_PAUSE_CAP = 1<<10, /* Bit 10:    Try for pause */
+       PHY_AN_100BASE4 = 1<<9, /* Bit 9:       Try for 100mbps 4k packets */
+       PHY_AN_100FULL  = 1<<8, /* Bit 8:       Try for 100mbps full-duplex */
+       PHY_AN_100HALF  = 1<<7, /* Bit 7:       Try for 100mbps half-duplex */
+       PHY_AN_10FULL   = 1<<6, /* Bit 6:       Try for 10mbps full-duplex */
+       PHY_AN_10HALF   = 1<<5, /* Bit 5:       Try for 10mbps half-duplex */
+       PHY_AN_CSMA     = 1<<0, /* Bit 0:       Only selector supported */
+       PHY_AN_SEL      = 0x1f, /* Bit 4..0:    Selector Field, 00001=Ethernet*/
+       PHY_AN_FULL     = PHY_AN_100FULL | PHY_AN_10FULL | PHY_AN_CSMA,
+       PHY_AN_ALL      = PHY_AN_10HALF | PHY_AN_10FULL |
+                         PHY_AN_100HALF | PHY_AN_100FULL,
+};
+
+/* Xmac Specific */
+enum {
+       PHY_X_AN_NXT_PG = 1<<15, /* Bit 15:     Request Next Page */
        PHY_X_AN_ACK    = 1<<14, /* Bit 14:     (ro) Acknowledge Received */
        PHY_X_AN_RFB    = 3<<12,/* Bit 13..12:  Remote Fault Bits */
 
@@ -1263,82 +1149,6 @@ enum {
        PHY_X_AN_FD     = 1<<5, /* Bit  5:      Full Duplex */
 };
 
-enum {
-       PHY_B_AN_RF     = 1<<13, /* Bit 13:     Remote Fault */
-
-       PHY_B_AN_ASP    = 1<<11, /* Bit 11:     Asymmetric Pause */
-       PHY_B_AN_PC     = 1<<10, /* Bit 10:     Pause Capable */
-       PHY_B_AN_SEL    = 0x1f, /* Bit 4..0:    Selector Field, 00001=Ethernet*/
-};
-
-enum {
-       PHY_L_AN_RF     = 1<<13, /* Bit 13:     Remote Fault */
-                                                               /* Bit 12:      reserved */
-       PHY_L_AN_ASP    = 1<<11, /* Bit 11:     Asymmetric Pause */
-       PHY_L_AN_PC     = 1<<10, /* Bit 10:     Pause Capable */
-
-       PHY_L_AN_SEL    = 0x1f, /* Bit 4..0:    Selector Field, 00001=Ethernet*/
-};
-
-/*  PHY_NAT_AUNE_ADV   16 bit r/w      Auto-Negotiation Advertisement */
-/*  PHY_NAT_AUNE_LP    16 bit r/o      Link Partner Ability Reg *****/
-/*  PHY_AN_NXT_PG      (see XMAC) Bit 15:      Request Next Page */
-enum {
-       PHY_N_AN_RF     = 1<<13, /* Bit 13:     Remote Fault */
-
-       PHY_N_AN_100F   = 1<<11, /* Bit 11:     100Base-T2 FD Support */
-       PHY_N_AN_100H   = 1<<10, /* Bit 10:     100Base-T2 HD Support */
-
-       PHY_N_AN_SEL    = 0x1f, /* Bit 4..0:    Selector Field, 00001=Ethernet*/
-};
-
-/* field type definition for PHY_x_AN_SEL */
-enum {
-       PHY_SEL_TYPE     = 1,   /* 00001 = Ethernet */
-};
-
-enum {
-       PHY_ANE_LP_NP   = 1<<3, /* Bit  3:      Link Partner can Next Page */
-       PHY_ANE_LOC_NP  = 1<<2, /* Bit  2:      Local PHY can Next Page */
-       PHY_ANE_RX_PG   = 1<<1, /* Bit  1:      Page Received */
-};
-
-enum {
-       PHY_ANE_PAR_DF  = 1<<4, /* Bit  4:      Parallel Detection Fault */
-
-       PHY_ANE_LP_CAP  = 1<<0, /* Bit  0:      Link Partner Auto-Neg. Cap. */  
-};
-
-enum {
-       PHY_NP_MORE     = 1<<15, /* Bit 15:     More, Next Pages to follow */
-       PHY_NP_ACK1     = 1<<14, /* Bit 14: (ro)        Ack1, for receiving a message */
-       PHY_NP_MSG_VAL  = 1<<13, /* Bit 13:     Message Page valid */
-       PHY_NP_ACK2     = 1<<12, /* Bit 12:     Ack2, comply with msg content */
-       PHY_NP_TOG      = 1<<11, /* Bit 11:     Toggle Bit, ensure sync */
-       PHY_NP_MSG      = 0x07ff, /* Bit 10..0: Message from/to Link Partner */
-};
-
-enum {
-       PHY_X_EX_FD     = 1<<15, /* Bit 15:     Device Supports Full Duplex */
-       PHY_X_EX_HD     = 1<<14, /* Bit 14:     Device Supports Half Duplex */
-};
-
-enum {
-       PHY_X_RS_PAUSE  = 3<<7,/* Bit  8..7:    selected Pause Mode */
-       PHY_X_RS_HD     = 1<<6, /* Bit  6:      Half Duplex Mode selected */
-       PHY_X_RS_FD     = 1<<5, /* Bit  5:      Full Duplex Mode selected */
-       PHY_X_RS_ABLMIS = 1<<4, /* Bit  4:      duplex or pause cap mismatch */
-       PHY_X_RS_PAUMIS = 1<<3, /* Bit  3:      pause capability mismatch */
-};
-
-/** Remote Fault Bits (PHY_X_AN_RFB) encoding  */
-enum {
-       X_RFB_OK        = 0<<12,/* Bit 13..12   No errors, Link OK */
-       X_RFB_LF        = 1<<12, /* Bit 13..12  Link Failure */
-       X_RFB_OFF       = 2<<12,/* Bit 13..12   Offline */
-       X_RFB_AN_ERR    = 3<<12,/* Bit 13..12   Auto-Negotiation Error */
-};
-
 /* Pause Bits (PHY_X_AN_PAUSE and PHY_X_RS_PAUSE) encoding */
 enum {
        PHY_X_P_NO_PAUSE        = 0<<7,/* Bit  8..7:    no Pause Mode */
@@ -1418,6 +1228,16 @@ enum {
        PHY_B_PES_MLT3_ER       = 1<<0, /* Bit  0:      MLT3 code Error */
 };
 
+/*  PHY_BCOM_AUNE_ADV  16 bit r/w      Auto-Negotiation Advertisement *****/
+/*  PHY_BCOM_AUNE_LP   16 bit r/o      Link Partner Ability Reg *****/
+enum {
+       PHY_B_AN_RF     = 1<<13, /* Bit 13:     Remote Fault */
+
+       PHY_B_AN_ASP    = 1<<11, /* Bit 11:     Asymmetric Pause */
+       PHY_B_AN_PC     = 1<<10, /* Bit 10:     Pause Capable */
+};
+
+
 /*****  PHY_BCOM_FC_CTR                16 bit r/w      False Carrier Counter *****/
 enum {
        PHY_B_FC_CTR    = 0xff, /* Bit  7..0:   False Carrier Counter */
@@ -1478,7 +1298,9 @@ enum {
        PHY_B_IS_LST_CHANGE     = 1<<1, /* Bit  1:      Link Status Changed */
        PHY_B_IS_CRC_ER = 1<<0, /* Bit  0:      CRC Error */
 };
-#define PHY_B_DEF_MSK  (~(PHY_B_IS_AN_PR | PHY_B_IS_LST_CHANGE))
+#define PHY_B_DEF_MSK  \
+       (~(PHY_B_IS_PSE | PHY_B_IS_AN_PR | PHY_B_IS_DUP_CHANGE | \
+           PHY_B_IS_LSP_CHANGE | PHY_B_IS_LST_CHANGE))
 
 /* Pause Bits (PHY_B_AN_ASP and PHY_B_AN_PC) encoding */
 enum {
@@ -1495,166 +1317,6 @@ enum {
        PHY_B_RES_1000HD        = 6<<8,/* Bit 10..8:    1000Base-T Half Dup. */
 };
 
-/*
- * Level One-Specific
- */
-/*****  PHY_LONE_1000T_CTRL    16 bit r/w      1000Base-T Control Reg *****/
-enum {
-       PHY_L_1000C_TEST        = 7<<13,/* Bit 15..13:  Test Modes */
-       PHY_L_1000C_MSE = 1<<12, /* Bit 12:     Master/Slave Enable */
-       PHY_L_1000C_MSC = 1<<11, /* Bit 11:     M/S Configuration */
-       PHY_L_1000C_RD  = 1<<10, /* Bit 10:     Repeater/DTE */
-       PHY_L_1000C_AFD = 1<<9, /* Bit  9:      Advertise Full Duplex */
-       PHY_L_1000C_AHD = 1<<8, /* Bit  8:      Advertise Half Duplex */
-};
-
-/*****  PHY_LONE_1000T_STAT    16 bit r/o      1000Base-T Status Reg *****/
-enum {
-       PHY_L_1000S_MSF = 1<<15, /* Bit 15:     Master/Slave Fault */
-       PHY_L_1000S_MSR = 1<<14, /* Bit 14:     Master/Slave Result */
-       PHY_L_1000S_LRS = 1<<13, /* Bit 13:     Local Receiver Status */
-       PHY_L_1000S_RRS = 1<<12, /* Bit 12:     Remote Receiver Status */
-       PHY_L_1000S_LP_FD = 1<<11, /* Bit 11:   Link Partner can FD */
-       PHY_L_1000S_LP_HD = 1<<10, /* Bit 10:   Link Partner can HD */
-
-       PHY_L_1000S_IEC  = 0xff, /* Bit  7..0:  Idle Error Count */
-
-/*****  PHY_LONE_EXT_STAT      16 bit r/o      Extended Status Register *****/
-       PHY_L_ES_X_FD_CAP = 1<<15, /* Bit 15:   1000Base-X FD capable */
-       PHY_L_ES_X_HD_CAP = 1<<14, /* Bit 14:   1000Base-X HD capable */
-       PHY_L_ES_T_FD_CAP = 1<<13, /* Bit 13:   1000Base-T FD capable */
-       PHY_L_ES_T_HD_CAP = 1<<12, /* Bit 12:   1000Base-T HD capable */
-};
-
-/*****  PHY_LONE_PORT_CFG      16 bit r/w      Port Configuration Reg *****/
-enum {
-       PHY_L_PC_REP_MODE       = 1<<15, /* Bit 15:     Repeater Mode */
-
-       PHY_L_PC_TX_DIS = 1<<13, /* Bit 13:     Tx output Disabled */
-       PHY_L_PC_BY_SCR = 1<<12, /* Bit 12:     Bypass Scrambler */
-       PHY_L_PC_BY_45  = 1<<11, /* Bit 11:     Bypass 4B5B-Decoder */
-       PHY_L_PC_JAB_DIS        = 1<<10, /* Bit 10:     Jabber Disabled */
-       PHY_L_PC_SQE    = 1<<9, /* Bit  9:      Enable Heartbeat */
-       PHY_L_PC_TP_LOOP        = 1<<8, /* Bit  8:      TP Loopback */
-       PHY_L_PC_SSS    = 1<<7, /* Bit  7:      Smart Speed Selection */
-       PHY_L_PC_FIFO_SIZE      = 1<<6, /* Bit  6:      FIFO Size */
-       PHY_L_PC_PRE_EN = 1<<5, /* Bit  5:      Preamble Enable */
-       PHY_L_PC_CIM    = 1<<4, /* Bit  4:      Carrier Integrity Mon */
-       PHY_L_PC_10_SER = 1<<3, /* Bit  3:      Use Serial Output */
-       PHY_L_PC_ANISOL = 1<<2, /* Bit  2:      Unisolate Port */
-       PHY_L_PC_TEN_BIT        = 1<<1, /* Bit  1:      10bit iface mode on */
-       PHY_L_PC_ALTCLOCK       = 1<<0, /* Bit  0: (ro) ALTCLOCK Mode on */
-};
-
-/*****  PHY_LONE_Q_STAT                16 bit r/o      Quick Status Reg *****/
-enum {
-       PHY_L_QS_D_RATE = 3<<14,/* Bit 15..14:  Data Rate */
-       PHY_L_QS_TX_STAT        = 1<<13, /* Bit 13:     Transmitting */
-       PHY_L_QS_RX_STAT        = 1<<12, /* Bit 12:     Receiving */
-       PHY_L_QS_COL_STAT       = 1<<11, /* Bit 11:     Collision */
-       PHY_L_QS_L_STAT = 1<<10, /* Bit 10:     Link is up */
-       PHY_L_QS_DUP_MOD        = 1<<9, /* Bit  9:      Full/Half Duplex */
-       PHY_L_QS_AN     = 1<<8, /* Bit  8:      AutoNeg is On */
-       PHY_L_QS_AN_C   = 1<<7, /* Bit  7:      AN is Complete */
-       PHY_L_QS_LLE    = 7<<4,/* Bit  6..4:    Line Length Estim. */
-       PHY_L_QS_PAUSE  = 1<<3, /* Bit  3:      LP advertised Pause */
-       PHY_L_QS_AS_PAUSE       = 1<<2, /* Bit  2:      LP adv. asym. Pause */
-       PHY_L_QS_ISOLATE        = 1<<1, /* Bit  1:      CIM Isolated */
-       PHY_L_QS_EVENT  = 1<<0, /* Bit  0:      Event has occurred */
-};
-
-/*****  PHY_LONE_INT_ENAB      16 bit r/w      Interrupt Enable Reg *****/
-/*****  PHY_LONE_INT_STAT      16 bit r/o      Interrupt Status Reg *****/
-enum {
-       PHY_L_IS_AN_F   = 1<<13, /* Bit 13:     Auto-Negotiation fault */
-       PHY_L_IS_CROSS  = 1<<11, /* Bit 11:     Crossover used */
-       PHY_L_IS_POL    = 1<<10, /* Bit 10:     Polarity correct. used */
-       PHY_L_IS_SS     = 1<<9, /* Bit  9:      Smart Speed Downgrade */
-       PHY_L_IS_CFULL  = 1<<8, /* Bit  8:      Counter Full */
-       PHY_L_IS_AN_C   = 1<<7, /* Bit  7:      AutoNeg Complete */
-       PHY_L_IS_SPEED  = 1<<6, /* Bit  6:      Speed Changed */
-       PHY_L_IS_DUP    = 1<<5, /* Bit  5:      Duplex Changed */
-       PHY_L_IS_LS     = 1<<4, /* Bit  4:      Link Status Changed */
-       PHY_L_IS_ISOL   = 1<<3, /* Bit  3:      Isolate Occured */
-       PHY_L_IS_MDINT  = 1<<2, /* Bit  2: (ro) STAT: MII Int Pending */
-       PHY_L_IS_INTEN  = 1<<1, /* Bit  1:      ENAB: Enable IRQs */
-       PHY_L_IS_FORCE  = 1<<0, /* Bit  0:      ENAB: Force Interrupt */
-};
-
-/* int. mask */
-#define PHY_L_DEF_MSK  (PHY_L_IS_LS | PHY_L_IS_ISOL | PHY_L_IS_INTEN)
-
-/*****  PHY_LONE_LED_CFG       16 bit r/w      LED Configuration Reg *****/
-enum {
-       PHY_L_LC_LEDC   = 3<<14,/* Bit 15..14:  Col/Blink/On/Off */
-       PHY_L_LC_LEDR   = 3<<12,/* Bit 13..12:  Rx/Blink/On/Off */
-       PHY_L_LC_LEDT   = 3<<10,/* Bit 11..10:  Tx/Blink/On/Off */
-       PHY_L_LC_LEDG   = 3<<8,/* Bit  9..8:    Giga/Blink/On/Off */
-       PHY_L_LC_LEDS   = 3<<6,/* Bit  7..6:    10-100/Blink/On/Off */
-       PHY_L_LC_LEDL   = 3<<4,/* Bit  5..4:    Link/Blink/On/Off */
-       PHY_L_LC_LEDF   = 3<<2,/* Bit  3..2:    Duplex/Blink/On/Off */
-       PHY_L_LC_PSTRECH= 1<<1, /* Bit  1:      Strech LED Pulses */
-       PHY_L_LC_FREQ   = 1<<0, /* Bit  0:      30/100 ms */
-};
-
-/*****  PHY_LONE_PORT_CTRL     16 bit r/w      Port Control Reg *****/
-enum {
-       PHY_L_PC_TX_TCLK = 1<<15, /* Bit 15:    Enable TX_TCLK */
-       PHY_L_PC_ALT_NP  = 1<<13, /* Bit 14:    Alternate Next Page */
-       PHY_L_PC_GMII_ALT= 1<<12, /* Bit 13:    Alternate GMII driver */
-       PHY_L_PC_TEN_CRS = 1<<10, /* Bit 10:    Extend CRS*/
-};
-
-/*****  PHY_LONE_CIM           16 bit r/o      CIM Reg *****/
-enum {
-       PHY_L_CIM_ISOL      = 0xff<<8,/* Bit 15..8:     Isolate Count */
-       PHY_L_CIM_FALSE_CAR = 0xff,   /* Bit  7..0:     False Carrier Count */
-};
-
-/*
- * Pause Bits (PHY_L_AN_ASP and PHY_L_AN_PC) encoding
- */
-enum {
-       PHY_L_P_NO_PAUSE= 0<<10,/* Bit 11..10:  no Pause Mode */
-       PHY_L_P_SYM_MD  = 1<<10, /* Bit 11..10: symmetric Pause Mode */
-       PHY_L_P_ASYM_MD = 2<<10,/* Bit 11..10:  asymmetric Pause Mode */
-       PHY_L_P_BOTH_MD = 3<<10,/* Bit 11..10:  both Pause Mode */
-};
-
-/*
- * National-Specific
- */
-/*****  PHY_NAT_1000T_CTRL     16 bit r/w      1000Base-T Control Reg *****/
-enum {
-       PHY_N_1000C_TEST= 7<<13,/* Bit 15..13:  Test Modes */
-       PHY_N_1000C_MSE = 1<<12, /* Bit 12:     Master/Slave Enable */
-       PHY_N_1000C_MSC = 1<<11, /* Bit 11:     M/S Configuration */
-       PHY_N_1000C_RD  = 1<<10, /* Bit 10:     Repeater/DTE */
-       PHY_N_1000C_AFD = 1<<9, /* Bit  9:      Advertise Full Duplex */
-       PHY_N_1000C_AHD = 1<<8, /* Bit  8:      Advertise Half Duplex */
-       PHY_N_1000C_APC = 1<<7, /* Bit  7:      Asymmetric Pause Cap. */};
-
-
-/*****  PHY_NAT_1000T_STAT     16 bit r/o      1000Base-T Status Reg *****/
-enum {
-       PHY_N_1000S_MSF = 1<<15, /* Bit 15:     Master/Slave Fault */
-       PHY_N_1000S_MSR = 1<<14, /* Bit 14:     Master/Slave Result */
-       PHY_N_1000S_LRS = 1<<13, /* Bit 13:     Local Receiver Status */
-       PHY_N_1000S_RRS = 1<<12, /* Bit 12:     Remote Receiver Status*/
-       PHY_N_1000S_LP_FD= 1<<11, /* Bit 11:    Link Partner can FD */
-       PHY_N_1000S_LP_HD= 1<<10, /* Bit 10:    Link Partner can HD */
-       PHY_N_1000C_LP_APC= 1<<9, /* Bit  9:    LP Asym. Pause Cap. */
-       PHY_N_1000S_IEC = 0xff, /* Bit  7..0:   Idle Error Count */
-};
-
-/*****  PHY_NAT_EXT_STAT       16 bit r/o      Extended Status Register *****/
-enum {
-       PHY_N_ES_X_FD_CAP= 1<<15, /* Bit 15:    1000Base-X FD capable */
-       PHY_N_ES_X_HD_CAP= 1<<14, /* Bit 14:    1000Base-X HD capable */
-       PHY_N_ES_T_FD_CAP= 1<<13, /* Bit 13:    1000Base-T FD capable */
-       PHY_N_ES_T_HD_CAP= 1<<12, /* Bit 12:    1000Base-T HD capable */
-};
-
 /** Marvell-Specific */
 enum {
        PHY_M_AN_NXT_PG = 1<<15, /* Request Next Page */
@@ -1718,7 +1380,7 @@ enum {
        PHY_M_PC_EN_DET_PLUS    = 3<<8, /* Energy Detect Plus (Mode 2) */
 };
 
-#define PHY_M_PC_MDI_XMODE(x)  (((x)<<5) & PHY_M_PC_MDIX_MSK)  
+#define PHY_M_PC_MDI_XMODE(x)  (((x)<<5) & PHY_M_PC_MDIX_MSK)
 
 enum {
        PHY_M_PC_MAN_MDI        = 0, /* 00 = Manual MDI configuration */
@@ -2105,7 +1767,7 @@ enum {
        GM_GPSR_FC_RX_DIS       = 1<<2, /* Bit  2:      Rx Flow-Control Mode Disabled */
        GM_GPSR_PROM_EN         = 1<<1, /* Bit  1:      Promiscuous Mode Enabled */
 };
-       
+
 /*     GM_GP_CTRL      16 bit r/w      General Purpose Control Register */
 enum {
        GM_GPCR_PROM_ENA        = 1<<14,        /* Bit 14:      Enable Promiscuous Mode */
@@ -2127,7 +1789,7 @@ enum {
 
 #define GM_GPCR_SPEED_1000     (GM_GPCR_GIGS_ENA | GM_GPCR_SPEED_100)
 #define GM_GPCR_AU_ALL_DIS     (GM_GPCR_AU_DUP_DIS | GM_GPCR_AU_FCT_DIS|GM_GPCR_AU_SPD_DIS)
-       
+
 /*     GM_TX_CTRL                      16 bit r/w      Transmit Control Register */
 enum {
        GM_TXCR_FORCE_JAM       = 1<<15, /* Bit 15:     Force Jam / Flow-Control */
@@ -2138,7 +1800,7 @@ enum {
 
 #define TX_COL_THR(x)          (((x)<<10) & GM_TXCR_COL_THR_MSK)
 #define TX_COL_DEF             0x04
-       
+
 /*     GM_RX_CTRL                      16 bit r/w      Receive Control Register */
 enum {
        GM_RXCR_UCF_ENA = 1<<15, /* Bit 15:     Enable Unicast filtering */
@@ -2146,7 +1808,7 @@ enum {
        GM_RXCR_CRC_DIS = 1<<13, /* Bit 13:     Remove 4-byte CRC */
        GM_RXCR_PASS_FC = 1<<12, /* Bit 12:     Pass FC packets to FIFO */
 };
-       
+
 /*     GM_TX_PARAM             16 bit r/w      Transmit Parameter Register */
 enum {
        GM_TXPA_JAMLEN_MSK      = 0x03<<14,     /* Bit 15..14:  Jam Length */
@@ -2171,7 +1833,7 @@ enum {
        GM_SMOD_JUMBO_ENA       = 1<<8, /* Bit  8:      Enable Jumbo (Max. Frame Len) */
         GM_SMOD_IPG_MSK        = 0x1f  /* Bit 4..0:    Inter-Packet Gap (IPG) */
 };
-       
+
 #define DATA_BLIND_VAL(x)      (((x)<<11) & GM_SMOD_DATABL_MSK)
 #define DATA_BLIND_DEF         0x04
 
@@ -2186,7 +1848,7 @@ enum {
        GM_SMI_CT_RD_VAL        = 1<<4, /* Bit  4:      Read Valid (Read completed) */
        GM_SMI_CT_BUSY          = 1<<3, /* Bit  3:      Busy (Operation in progress) */
 };
-       
+
 #define GM_SMI_CT_PHY_AD(x)    (((x)<<11) & GM_SMI_CT_PHY_A_MSK)
 #define GM_SMI_CT_REG_AD(x)    (((x)<<6) & GM_SMI_CT_REG_A_MSK)
 
@@ -2195,7 +1857,7 @@ enum {
        GM_PAR_MIB_CLR  = 1<<5, /* Bit  5:      Set MIB Clear Counter Mode */
        GM_PAR_MIB_TST  = 1<<4, /* Bit  4:      MIB Load Counter (Test Mode) */
 };
-       
+
 /* Receive Frame Status Encoding */
 enum {
        GMR_FS_LEN      = 0xffff<<16, /* Bit 31..16:    Rx Frame Length */
@@ -2217,12 +1879,12 @@ enum {
 /*
  * GMR_FS_ANY_ERR (analogous to XMR_FS_ANY_ERR)
  */
-       GMR_FS_ANY_ERR  = GMR_FS_CRC_ERR | GMR_FS_LONG_ERR | 
-                         GMR_FS_MII_ERR | GMR_FS_BAD_FC | GMR_FS_GOOD_FC | 
+       GMR_FS_ANY_ERR  = GMR_FS_CRC_ERR | GMR_FS_LONG_ERR |
+                         GMR_FS_MII_ERR | GMR_FS_BAD_FC | GMR_FS_GOOD_FC |
                          GMR_FS_JABBER,
 /* Rx GMAC FIFO Flush Mask (default) */
        RX_FF_FL_DEF_MSK = GMR_FS_CRC_ERR | GMR_FS_RX_FF_OV |GMR_FS_MII_ERR |
-                          GMR_FS_BAD_FC | GMR_FS_GOOD_FC | GMR_FS_UN_SIZE | 
+                          GMR_FS_BAD_FC | GMR_FS_GOOD_FC | GMR_FS_UN_SIZE |
                           GMR_FS_JABBER,
 };
 
@@ -2540,10 +2202,6 @@ enum {
 };
 
 
-/*     XM_PHY_ADDR     16 bit r/w      PHY Address Register */
-#define XM_PHY_ADDR_SZ 0x1f    /* Bit  4..0:   PHY Address bits */
-
-
 /*     XM_GP_PORT      32 bit r/w      General Purpose Port Register */
 enum {
        XM_GP_ANIP      = 1<<6, /* Bit  6: (ro) Auto-Neg. in progress */
@@ -2662,8 +2320,8 @@ enum {
 };
 
 #define XM_PAUSE_MODE  (XM_MD_SPOE_E | XM_MD_SPOL_I | XM_MD_SPOH_I)
-#define XM_DEF_MODE            (XM_MD_RX_RUNT | XM_MD_RX_IRLE | XM_MD_RX_LONG |\
-                               XM_MD_RX_CRCE | XM_MD_RX_ERR | XM_MD_CSA | XM_MD_CAA)
+#define XM_DEF_MODE    (XM_MD_RX_RUNT | XM_MD_RX_IRLE | XM_MD_RX_LONG |\
+                        XM_MD_RX_CRCE | XM_MD_RX_ERR | XM_MD_CSA)
 
 /*     XM_STAT_CMD     16 bit r/w      Statistics Command Register */
 enum {
@@ -2793,28 +2451,20 @@ struct skge_hw {
        u32                  intr_mask;
        struct net_device    *dev[2];
 
-       u8                   mac_cfg;
        u8                   chip_id;
+       u8                   chip_rev;
        u8                   phy_type;
        u8                   pmd_type;
        u16                  phy_addr;
+       u8                   ports;
 
        u32                  ram_size;
        u32                  ram_offset;
-       
+
        struct tasklet_struct ext_tasklet;
        spinlock_t           phy_lock;
 };
 
-static inline int isdualport(const struct skge_hw *hw)
-{
-       return !(hw->mac_cfg & CFG_SNG_MAC);
-}
-
-static inline u8 chip_rev(const struct skge_hw *hw)
-{
-       return (hw->mac_cfg & CFG_CHIP_R_MSK) >> 4;
-}
 
 static inline int iscopper(const struct skge_hw *hw)
 {
@@ -2827,7 +2477,7 @@ enum {
        FLOW_MODE_REM_SEND      = 2, /* Symmetric or just remote */
        FLOW_MODE_SYMMETRIC     = 3, /* Both stations may send PAUSE */
 };
-       
+
 struct skge_port {
        u32                  msg_enable;
        struct skge_hw       *hw;
@@ -2853,8 +2503,8 @@ struct skge_port {
        void                 *mem;      /* PCI memory for rings */
        dma_addr_t           dma;
        unsigned long        mem_size;
+       unsigned int         rx_buf_size;
 
-       struct timer_list    link_check;
        struct timer_list    led_blink;
 };
 
@@ -2863,7 +2513,6 @@ struct skge_port {
 static inline u32 skge_read32(const struct skge_hw *hw, int reg)
 {
        return readl(hw->regs + reg);
-
 }
 
 static inline u16 skge_read16(const struct skge_hw *hw, int reg)
@@ -2892,114 +2541,87 @@ static inline void skge_write8(const struct skge_hw *hw, int reg, u8 val)
 }
 
 /* MAC Related Registers inside the device. */
-#define SKGEMAC_REG(port,reg)  (((port)<<7)+(reg))
-
-/* PCI config space can be accessed via memory mapped space */
-#define SKGEPCI_REG(reg) ((reg)+ 0x380)
-
-#define SKGEXM_REG(port, reg) \
+#define SK_REG(port,reg)       (((port)<<7)+(reg))
+#define SK_XMAC_REG(port, reg) \
        ((BASE_XMAC_1 + (port) * (BASE_XMAC_2 - BASE_XMAC_1)) | (reg) << 1)
 
-static inline u32 skge_xm_read32(const struct skge_hw *hw, int port, int reg)
-{
-       return skge_read32(hw, SKGEXM_REG(port,reg));
-}
-
-static inline u16 skge_xm_read16(const struct skge_hw *hw, int port, int reg)
+static inline u32 xm_read32(const struct skge_hw *hw, int port, int reg)
 {
-       return skge_read16(hw, SKGEXM_REG(port,reg));
+       u32 v;
+       v = skge_read16(hw, SK_XMAC_REG(port, reg));
+       v |= (u32)skge_read16(hw, SK_XMAC_REG(port, reg+2)) << 16;
+       return v;
 }
 
-static inline u8 skge_xm_read8(const struct skge_hw *hw, int port, int reg)
+static inline u16 xm_read16(const struct skge_hw *hw, int port, int reg)
 {
-       return skge_read8(hw, SKGEXM_REG(port,reg));
+       return skge_read16(hw, SK_XMAC_REG(port,reg));
 }
 
-static inline void skge_xm_write32(const struct skge_hw *hw, int port, int r, u32 v)
+static inline void xm_write32(const struct skge_hw *hw, int port, int r, u32 v)
 {
-       skge_write32(hw, SKGEXM_REG(port,r), v);
+       skge_write16(hw, SK_XMAC_REG(port,r), v & 0xffff);
+       skge_write16(hw, SK_XMAC_REG(port,r+2), v >> 16);
 }
 
-static inline void skge_xm_write16(const struct skge_hw *hw, int port, int r, u16 v)
+static inline void xm_write16(const struct skge_hw *hw, int port, int r, u16 v)
 {
-       skge_write16(hw, SKGEXM_REG(port,r), v);
+       skge_write16(hw, SK_XMAC_REG(port,r), v);
 }
 
-static inline void skge_xm_write8(const struct skge_hw *hw, int port, int r, u8 v)
-{
-       skge_write8(hw, SKGEXM_REG(port,r), v);
-}
-
-static inline void skge_xm_outhash(const struct skge_hw *hw, int port, int reg,
+static inline void xm_outhash(const struct skge_hw *hw, int port, int reg,
                                   const u8 *hash)
 {
-       skge_xm_write16(hw, port, reg, 
-                       (u16)hash[0] | ((u16)hash[1] << 8));
-       skge_xm_write16(hw, port, reg+2, 
-                       (u16)hash[2] | ((u16)hash[3] << 8));
-       skge_xm_write16(hw, port, reg+4, 
-                       (u16)hash[4] | ((u16)hash[5] << 8));
-       skge_xm_write16(hw, port, reg+6, 
-                       (u16)hash[6] | ((u16)hash[7] << 8));
+       xm_write16(hw, port, reg,   (u16)hash[0] | ((u16)hash[1] << 8));
+       xm_write16(hw, port, reg+2, (u16)hash[2] | ((u16)hash[3] << 8));
+       xm_write16(hw, port, reg+4, (u16)hash[4] | ((u16)hash[5] << 8));
+       xm_write16(hw, port, reg+6, (u16)hash[6] | ((u16)hash[7] << 8));
 }
 
-static inline void skge_xm_outaddr(const struct skge_hw *hw, int port, int reg,
+static inline void xm_outaddr(const struct skge_hw *hw, int port, int reg,
                                   const u8 *addr)
 {
-       skge_xm_write16(hw, port, reg, 
-                       (u16)addr[0] | ((u16)addr[1] << 8));
-       skge_xm_write16(hw, port, reg, 
-                       (u16)addr[2] | ((u16)addr[3] << 8));
-       skge_xm_write16(hw, port, reg, 
-                       (u16)addr[4] | ((u16)addr[5] << 8));
+       xm_write16(hw, port, reg,   (u16)addr[0] | ((u16)addr[1] << 8));
+       xm_write16(hw, port, reg+2, (u16)addr[2] | ((u16)addr[3] << 8));
+       xm_write16(hw, port, reg+4, (u16)addr[4] | ((u16)addr[5] << 8));
 }
 
+#define SK_GMAC_REG(port,reg) \
+       (BASE_GMAC_1 + (port) * (BASE_GMAC_2-BASE_GMAC_1) + (reg))
 
-#define SKGEGMA_REG(port,reg) \
-       ((reg) + BASE_GMAC_1 + \
-        (port) * (BASE_GMAC_2-BASE_GMAC_1))
-
-static inline u16 skge_gma_read16(const struct skge_hw *hw, int port, int reg)
+static inline u16 gma_read16(const struct skge_hw *hw, int port, int reg)
 {
-       return skge_read16(hw, SKGEGMA_REG(port,reg));
+       return skge_read16(hw, SK_GMAC_REG(port,reg));
 }
 
-static inline u32 skge_gma_read32(const struct skge_hw *hw, int port, int reg)
+static inline u32 gma_read32(const struct skge_hw *hw, int port, int reg)
 {
-       return (u32) skge_read16(hw, SKGEGMA_REG(port,reg))
-               | ((u32)skge_read16(hw, SKGEGMA_REG(port,reg+4)) << 16);
+       return (u32) skge_read16(hw, SK_GMAC_REG(port,reg))
+               | ((u32)skge_read16(hw, SK_GMAC_REG(port,reg+4)) << 16);
 }
 
-static inline u8 skge_gma_read8(const struct skge_hw *hw, int port, int reg)
+static inline void gma_write16(const struct skge_hw *hw, int port, int r, u16 v)
 {
-       return skge_read8(hw, SKGEGMA_REG(port,reg));
+       skge_write16(hw, SK_GMAC_REG(port,r), v);
 }
 
-static inline void skge_gma_write16(const struct skge_hw *hw, int port, int r, u16 v)
+static inline void gma_write32(const struct skge_hw *hw, int port, int r, u32 v)
 {
-       skge_write16(hw, SKGEGMA_REG(port,r), v);
+       skge_write16(hw, SK_GMAC_REG(port, r), (u16) v);
+       skge_write32(hw, SK_GMAC_REG(port, r+4), (u16)(v >> 16));
 }
 
-static inline void skge_gma_write32(const struct skge_hw *hw, int port, int r, u32 v)
+static inline void gma_write8(const struct skge_hw *hw, int port, int r, u8 v)
 {
-       skge_write16(hw, SKGEGMA_REG(port, r), (u16) v);
-       skge_write32(hw, SKGEGMA_REG(port, r+4), (u16)(v >> 16));
+       skge_write8(hw, SK_GMAC_REG(port,r), v);
 }
 
-static inline void skge_gma_write8(const struct skge_hw *hw, int port, int r, u8 v)
-{
-       skge_write8(hw, SKGEGMA_REG(port,r), v);
-}
-
-static inline void skge_gm_set_addr(struct skge_hw *hw, int port, int reg,
+static inline void gma_set_addr(struct skge_hw *hw, int port, int reg,
                                    const u8 *addr)
 {
-       skge_gma_write16(hw, port, reg,
-                        (u16) addr[0] | ((u16) addr[1] << 8));
-       skge_gma_write16(hw, port, reg+4,
-                        (u16) addr[2] | ((u16) addr[3] << 8));
-       skge_gma_write16(hw, port, reg+8,
-                        (u16) addr[4] | ((u16) addr[5] << 8));
+       gma_write16(hw, port, reg,  (u16) addr[0] | ((u16) addr[1] << 8));
+       gma_write16(hw, port, reg+4,(u16) addr[2] | ((u16) addr[3] << 8));
+       gma_write16(hw, port, reg+8,(u16) addr[4] | ((u16) addr[5] << 8));
 }
-               
+
 #endif
index 1d3231cc471acff346ef9dd6425d66c1b96c4276..d20e0da05a26eab996841f5c678f11d54a8fb460 100644 (file)
@@ -137,6 +137,110 @@ config PCMCIA_RAYCS
 comment "Wireless 802.11b ISA/PCI cards support"
        depends on NET_RADIO && (ISA || PCI || PPC_PMAC || PCMCIA)
 
+config IPW2100
+       tristate "Intel PRO/Wireless 2100 Network Connection"
+       depends on NET_RADIO && PCI && IEEE80211
+       select FW_LOADER
+       ---help---
+          A driver for the Intel PRO/Wireless 2100 Network 
+         Connection 802.11b wireless network adapter.
+
+          See <file:Documentation/networking/README.ipw2100> for information on
+          the capabilities currently enabled in this driver and for tips
+          for debugging issues and problems.
+
+         In order to use this driver, you will need a firmware image for it.
+          You can obtain the firmware from
+         <http://ipw2100.sf.net/>.  Once you have the firmware image, you 
+         will need to place it in /etc/firmware.
+
+          You will also very likely need the Wireless Tools in order to
+          configure your card:
+
+          <http://www.hpl.hp.com/personal/Jean_Tourrilhes/Linux/Tools.html>.
+          If you want to compile the driver as a module ( = code which can be
+          inserted in and remvoed from the running kernel whenever you want),
+          say M here and read <file:Documentation/modules.txt>.  The module
+          will be called ipw2100.ko.
+       
+config IPW2100_PROMISC
+        bool "Enable promiscuous mode"
+        depends on IPW2100
+        ---help---
+         Enables promiscuous/monitor mode support for the ipw2100 driver.
+         With this feature compiled into the driver, you can switch to 
+         promiscuous mode via the Wireless Tool's Monitor mode.  While in this
+         mode, no packets can be sent.
+
+config IPW_DEBUG
+       bool "Enable full debugging output in IPW2100 module."
+       depends on IPW2100
+       ---help---
+         This option will enable debug tracing output for the IPW2100.  
+
+         This will result in the kernel module being ~60k larger.  You can 
+         control which debug output is sent to the kernel log by setting the 
+         value in 
+
+         /sys/bus/pci/drivers/ipw2100/debug_level
+
+         This entry will only exist if this option is enabled.
+
+         If you are not trying to debug or develop the IPW2100 driver, you 
+         most likely want to say N here.
+
+config IPW2200
+       tristate "Intel PRO/Wireless 2200BG and 2915ABG Network Connection"
+       depends on IEEE80211 && PCI
+       select FW_LOADER
+       ---help---
+          A driver for the Intel PRO/Wireless 2200BG and 2915ABG Network
+         Connection adapters. 
+
+          See <file:Documentation/networking/README.ipw2200> for 
+         information on the capabilities currently enabled in this 
+         driver and for tips for debugging issues and problems.
+
+         In order to use this driver, you will need a firmware image for it.
+          You can obtain the firmware from
+         <http://ipw2200.sf.net/>.  See the above referenced README.ipw2200 
+         for information on where to install the firmare images.
+
+          You will also very likely need the Wireless Tools in order to
+          configure your card:
+
+          <http://www.hpl.hp.com/personal/Jean_Tourrilhes/Linux/Tools.html>.
+          If you want to compile the driver as a module ( = code which can be
+          inserted in and remvoed from the running kernel whenever you want),
+          say M here and read <file:Documentation/modules.txt>.  The module
+          will be called ipw2200.ko.
+
+config IPW_DEBUG
+       bool "Enable full debugging output in IPW2200 module."
+       depends on IPW2200
+       ---help---
+         This option will enable debug tracing output for the IPW2200.  
+
+         This will result in the kernel module being ~100k larger.  You can 
+         control which debug output is sent to the kernel log by setting the 
+         value in 
+
+         /sys/bus/pci/drivers/ipw2200/debug_level
+
+         This entry will only exist if this option is enabled.
+
+         To set a value, simply echo an 8-byte hex value to the same file:
+
+         % echo 0x00000FFO > /sys/bus/pci/drivers/ipw2200/debug_level
+
+         You can find the list of debug mask values in 
+         drivers/net/wireless/ipw2200.h
+
+         If you are not trying to debug or develop the IPW2200 driver, you 
+         most likely want to say N here.
+
 config AIRO
        tristate "Cisco/Aironet 34X/35X/4500/4800 ISA and PCI cards"
        depends on NET_RADIO && ISA && (PCI || BROKEN)
index 2b87841322cc8f7d27fac0a36bdb063d204d7420..0859787581bb0c084cf5b0aa4c2987d5be442dfd 100644 (file)
@@ -2,6 +2,10 @@
 # Makefile for the Linux Wireless network device drivers.
 #
 
+obj-$(CONFIG_IPW2100) += ipw2100.o
+
+obj-$(CONFIG_IPW2200) += ipw2200.o
+
 obj-$(CONFIG_STRIP) += strip.o
 obj-$(CONFIG_ARLAN) += arlan.o 
 
index 18a7d38d2a1301f833dd36eb4ed587d73390e109..bed160a25cabc71689b839f5603bd24a18d9a107 100644 (file)
@@ -68,7 +68,7 @@
 #include <linux/device.h>
 #include <linux/moduleparam.h>
 #include <linux/firmware.h>
-#include "ieee802_11.h"
+#include <net/ieee80211.h>
 #include "atmel.h"
 
 #define DRIVER_MAJOR 0
@@ -618,12 +618,12 @@ static int atmel_lock_mac(struct atmel_private *priv);
 static void atmel_wmem32(struct atmel_private *priv, u16 pos, u32 data);
 static void atmel_command_irq(struct atmel_private *priv);
 static int atmel_validate_channel(struct atmel_private *priv, int channel);
-static void atmel_management_frame(struct atmel_private *priv, struct ieee802_11_hdr *header, 
+static void atmel_management_frame(struct atmel_private *priv, struct ieee80211_hdr *header, 
                                   u16 frame_len, u8 rssi);
 static void atmel_management_timer(u_long a);
 static void atmel_send_command(struct atmel_private *priv, int command, void *cmd, int cmd_size);
 static int atmel_send_command_wait(struct atmel_private *priv, int command, void *cmd, int cmd_size);
-static void atmel_transmit_management_frame(struct atmel_private *priv, struct ieee802_11_hdr *header,
+static void atmel_transmit_management_frame(struct atmel_private *priv, struct ieee80211_hdr *header,
                                            u8 *body, int body_len);
 
 static u8 atmel_get_mib8(struct atmel_private *priv, u8 type, u8 index);
@@ -827,7 +827,7 @@ static void tx_update_descriptor(struct atmel_private *priv, int is_bcast, u16 l
 static int start_tx (struct sk_buff *skb, struct net_device *dev)
 {
        struct atmel_private *priv = netdev_priv(dev);
-       struct ieee802_11_hdr header;
+       struct ieee80211_hdr header;
        unsigned long flags;
        u16 buff, frame_ctl, len = (ETH_ZLEN < skb->len) ? skb->len : ETH_ZLEN;
        u8 SNAP_RFC1024[6] = {0xaa, 0xaa, 0x03, 0x00, 0x00, 0x00};
@@ -863,17 +863,17 @@ static int start_tx (struct sk_buff *skb, struct net_device *dev)
                return 1;
        }
        
-       frame_ctl = IEEE802_11_FTYPE_DATA;
+       frame_ctl = IEEE80211_FTYPE_DATA;
        header.duration_id = 0;
        header.seq_ctl = 0;
        if (priv->wep_is_on)
-               frame_ctl |= IEEE802_11_FCTL_WEP;
+               frame_ctl |= IEEE80211_FCTL_WEP;
        if (priv->operating_mode == IW_MODE_ADHOC) {
                memcpy(&header.addr1, skb->data, 6);
                memcpy(&header.addr2, dev->dev_addr, 6);
                memcpy(&header.addr3, priv->BSSID, 6);
        } else {
-               frame_ctl |= IEEE802_11_FCTL_TODS;
+               frame_ctl |= IEEE80211_FCTL_TODS;
                memcpy(&header.addr1, priv->CurrentBSSID, 6);
                memcpy(&header.addr2, dev->dev_addr, 6);
                memcpy(&header.addr3, skb->data, 6);
@@ -902,7 +902,7 @@ static int start_tx (struct sk_buff *skb, struct net_device *dev)
 }
 
 static void atmel_transmit_management_frame(struct atmel_private *priv, 
-                                           struct ieee802_11_hdr *header,
+                                           struct ieee80211_hdr *header,
                                            u8 *body, int body_len)
 {
        u16 buff;
@@ -917,7 +917,7 @@ static void atmel_transmit_management_frame(struct atmel_private *priv,
        tx_update_descriptor(priv, header->addr1[0] & 0x01, len, buff, TX_PACKET_TYPE_MGMT);
 }
        
-static void fast_rx_path(struct atmel_private *priv, struct ieee802_11_hdr *header, 
+static void fast_rx_path(struct atmel_private *priv, struct ieee80211_hdr *header, 
                         u16 msdu_size, u16 rx_packet_loc, u32 crc)
 {
        /* fast path: unfragmented packet copy directly into skbuf */
@@ -955,7 +955,7 @@ static void fast_rx_path(struct atmel_private *priv, struct ieee802_11_hdr *head
        }
        
        memcpy(skbp, header->addr1, 6); /* destination address */
-       if (le16_to_cpu(header->frame_ctl) & IEEE802_11_FCTL_FROMDS) 
+       if (le16_to_cpu(header->frame_ctl) & IEEE80211_FCTL_FROMDS) 
                memcpy(&skbp[6], header->addr3, 6);
        else
                memcpy(&skbp[6], header->addr2, 6); /* source address */
@@ -990,14 +990,14 @@ static int probe_crc(struct atmel_private *priv, u16 packet_loc, u16 msdu_size)
        return (crc ^ 0xffffffff) == netcrc;
 }
 
-static void frag_rx_path(struct atmel_private *priv, struct ieee802_11_hdr *header, 
+static void frag_rx_path(struct atmel_private *priv, struct ieee80211_hdr *header, 
                         u16 msdu_size, u16 rx_packet_loc, u32 crc, u16 seq_no, u8 frag_no, int more_frags)
 {
        u8 mac4[6]; 
        u8 source[6];
        struct sk_buff *skb;
 
-       if (le16_to_cpu(header->frame_ctl) & IEEE802_11_FCTL_FROMDS) 
+       if (le16_to_cpu(header->frame_ctl) & IEEE80211_FCTL_FROMDS) 
                memcpy(source, header->addr3, 6);
        else
                memcpy(source, header->addr2, 6); 
@@ -1082,7 +1082,7 @@ static void frag_rx_path(struct atmel_private *priv, struct ieee802_11_hdr *head
 static void rx_done_irq(struct atmel_private *priv)
 {
        int i;
-       struct ieee802_11_hdr header;
+       struct ieee80211_hdr header;
        
        for (i = 0; 
             atmel_rmem8(priv, atmel_rx(priv, RX_DESC_FLAGS_OFFSET, priv->rx_desc_head)) == RX_DESC_FLAG_VALID &&
@@ -1117,7 +1117,7 @@ static void rx_done_irq(struct atmel_private *priv)
                /* probe for CRC use here if needed  once five packets have arrived with
                   the same crc status, we assume we know what's happening and stop probing */
                if (priv->probe_crc) {
-                       if (!priv->wep_is_on || !(frame_ctl & IEEE802_11_FCTL_WEP)) {
+                       if (!priv->wep_is_on || !(frame_ctl & IEEE80211_FCTL_WEP)) {
                                priv->do_rx_crc = probe_crc(priv, rx_packet_loc, msdu_size);
                        } else {
                                priv->do_rx_crc = probe_crc(priv, rx_packet_loc + 24, msdu_size - 24);
@@ -1132,16 +1132,16 @@ static void rx_done_irq(struct atmel_private *priv)
                }
                    
                /* don't CRC header when WEP in use */
-               if (priv->do_rx_crc && (!priv->wep_is_on || !(frame_ctl & IEEE802_11_FCTL_WEP))) {
+               if (priv->do_rx_crc && (!priv->wep_is_on || !(frame_ctl & IEEE80211_FCTL_WEP))) {
                        crc = crc32_le(0xffffffff, (unsigned char *)&header, 24);
                }
                msdu_size -= 24; /* header */
 
-               if ((frame_ctl & IEEE802_11_FCTL_FTYPE) == IEEE802_11_FTYPE_DATA) { 
+               if ((frame_ctl & IEEE80211_FCTL_FTYPE) == IEEE80211_FTYPE_DATA) { 
                        
-                       int more_fragments = frame_ctl & IEEE802_11_FCTL_MOREFRAGS;
-                       u8 packet_fragment_no = seq_control & IEEE802_11_SCTL_FRAG;
-                       u16 packet_sequence_no = (seq_control & IEEE802_11_SCTL_SEQ) >> 4;
+                       int more_fragments = frame_ctl & IEEE80211_FCTL_MOREFRAGS;
+                       u8 packet_fragment_no = seq_control & IEEE80211_SCTL_FRAG;
+                       u16 packet_sequence_no = (seq_control & IEEE80211_SCTL_SEQ) >> 4;
                        
                        if (!more_fragments && packet_fragment_no == 0 ) {
                                fast_rx_path(priv, &header, msdu_size, rx_packet_loc, crc);
@@ -1151,7 +1151,7 @@ static void rx_done_irq(struct atmel_private *priv)
                        }
                }
                
-               if ((frame_ctl & IEEE802_11_FCTL_FTYPE) == IEEE802_11_FTYPE_MGMT) {
+               if ((frame_ctl & IEEE80211_FCTL_FTYPE) == IEEE80211_FTYPE_MGMT) {
                        /* copy rest of packet into buffer */
                        atmel_copy_to_host(priv->dev, (unsigned char *)&priv->rx_buf, rx_packet_loc + 24, msdu_size);
                        
@@ -2663,10 +2663,10 @@ static void handle_beacon_probe(struct atmel_private *priv, u16 capability, u8 c
  
 static void send_authentication_request(struct atmel_private *priv, u8 *challenge, int challenge_len)
 {
-       struct ieee802_11_hdr header;
+       struct ieee80211_hdr header;
        struct auth_body auth;
        
-       header.frame_ctl = cpu_to_le16(IEEE802_11_FTYPE_MGMT | IEEE802_11_STYPE_AUTH); 
+       header.frame_ctl = cpu_to_le16(IEEE80211_FTYPE_MGMT | IEEE80211_STYPE_AUTH); 
        header.duration_id      = cpu_to_le16(0x8000);  
        header.seq_ctl = 0;
        memcpy(header.addr1, priv->CurrentBSSID, 6);
@@ -2677,7 +2677,7 @@ static void send_authentication_request(struct atmel_private *priv, u8 *challeng
                auth.alg = cpu_to_le16(C80211_MGMT_AAN_SHAREDKEY); 
                /* no WEP for authentication frames with TrSeqNo 1 */
                if (priv->CurrentAuthentTransactionSeqNum != 1)
-                       header.frame_ctl |=  cpu_to_le16(IEEE802_11_FCTL_WEP); 
+                       header.frame_ctl |=  cpu_to_le16(IEEE80211_FCTL_WEP); 
        } else {
                auth.alg = cpu_to_le16(C80211_MGMT_AAN_OPENSYSTEM);
        }
@@ -2701,7 +2701,7 @@ static void send_association_request(struct atmel_private *priv, int is_reassoc)
 {
        u8 *ssid_el_p;
        int bodysize;
-       struct ieee802_11_hdr header;
+       struct ieee80211_hdr header;
        struct ass_req_format {
                u16 capability;
                u16 listen_interval; 
@@ -2714,8 +2714,8 @@ static void send_association_request(struct atmel_private *priv, int is_reassoc)
                u8 rates[4];
        } body;
                
-       header.frame_ctl = cpu_to_le16(IEEE802_11_FTYPE_MGMT | 
-               (is_reassoc ? IEEE802_11_STYPE_REASSOC_REQ : IEEE802_11_STYPE_ASSOC_REQ));
+       header.frame_ctl = cpu_to_le16(IEEE80211_FTYPE_MGMT | 
+               (is_reassoc ? IEEE80211_STYPE_REASSOC_REQ : IEEE80211_STYPE_ASSOC_REQ));
        header.duration_id = cpu_to_le16(0x8000);
        header.seq_ctl = 0;
 
@@ -2751,9 +2751,9 @@ static void send_association_request(struct atmel_private *priv, int is_reassoc)
        atmel_transmit_management_frame(priv, &header, (void *)&body, bodysize);
 }
 
-static int is_frame_from_current_bss(struct atmel_private *priv, struct ieee802_11_hdr *header)
+static int is_frame_from_current_bss(struct atmel_private *priv, struct ieee80211_hdr *header)
 {
-       if (le16_to_cpu(header->frame_ctl) & IEEE802_11_FCTL_FROMDS)
+       if (le16_to_cpu(header->frame_ctl) & IEEE80211_FCTL_FROMDS)
                return memcmp(header->addr3, priv->CurrentBSSID, 6) == 0;
        else
                return memcmp(header->addr2, priv->CurrentBSSID, 6) == 0;
@@ -2801,7 +2801,7 @@ static int retrieve_bss(struct atmel_private *priv)
 }
 
 
-static void store_bss_info(struct atmel_private *priv, struct ieee802_11_hdr *header,
+static void store_bss_info(struct atmel_private *priv, struct ieee80211_hdr *header,
                           u16 capability, u16 beacon_period, u8 channel, u8 rssi, 
                           u8 ssid_len, u8 *ssid, int is_beacon)
 {
@@ -3085,12 +3085,12 @@ static void atmel_smooth_qual(struct atmel_private *priv)
 }
 
 /* deals with incoming managment frames. */
-static void atmel_management_frame(struct atmel_private *priv, struct ieee802_11_hdr *header, 
+static void atmel_management_frame(struct atmel_private *priv, struct ieee80211_hdr *header, 
                      u16 frame_len, u8 rssi)
 {
        u16 subtype;
        
-       switch (subtype = le16_to_cpu(header->frame_ctl) & IEEE802_11_FCTL_STYPE) {
+       switch (subtype = le16_to_cpu(header->frame_ctl) & IEEE80211_FCTL_STYPE) {
        case C80211_SUBTYPE_MGMT_BEACON :
        case C80211_SUBTYPE_MGMT_ProbeResponse:
                
diff --git a/drivers/net/wireless/ieee802_11.h b/drivers/net/wireless/ieee802_11.h
deleted file mode 100644 (file)
index 53dd524..0000000
+++ /dev/null
@@ -1,78 +0,0 @@
-#ifndef _IEEE802_11_H
-#define _IEEE802_11_H
-
-#define IEEE802_11_DATA_LEN            2304
-/* Maximum size for the MA-UNITDATA primitive, 802.11 standard section
-   6.2.1.1.2.
-
-   The figure in section 7.1.2 suggests a body size of up to 2312
-   bytes is allowed, which is a bit confusing, I suspect this
-   represents the 2304 bytes of real data, plus a possible 8 bytes of
-   WEP IV and ICV. (this interpretation suggested by Ramiro Barreiro) */
-
-
-#define IEEE802_11_HLEN                        30
-#define IEEE802_11_FRAME_LEN           (IEEE802_11_DATA_LEN + IEEE802_11_HLEN)
-
-struct ieee802_11_hdr {
-       u16 frame_ctl;
-       u16 duration_id;
-       u8 addr1[ETH_ALEN];
-       u8 addr2[ETH_ALEN];
-       u8 addr3[ETH_ALEN];
-       u16 seq_ctl;
-       u8 addr4[ETH_ALEN];
-} __attribute__ ((packed));
-
-/* Frame control field constants */
-#define IEEE802_11_FCTL_VERS           0x0002
-#define IEEE802_11_FCTL_FTYPE          0x000c
-#define IEEE802_11_FCTL_STYPE          0x00f0
-#define IEEE802_11_FCTL_TODS           0x0100
-#define IEEE802_11_FCTL_FROMDS         0x0200
-#define IEEE802_11_FCTL_MOREFRAGS      0x0400
-#define IEEE802_11_FCTL_RETRY          0x0800
-#define IEEE802_11_FCTL_PM             0x1000
-#define IEEE802_11_FCTL_MOREDATA       0x2000
-#define IEEE802_11_FCTL_WEP            0x4000
-#define IEEE802_11_FCTL_ORDER          0x8000
-
-#define IEEE802_11_FTYPE_MGMT          0x0000
-#define IEEE802_11_FTYPE_CTL           0x0004
-#define IEEE802_11_FTYPE_DATA          0x0008
-
-/* management */
-#define IEEE802_11_STYPE_ASSOC_REQ     0x0000
-#define IEEE802_11_STYPE_ASSOC_RESP    0x0010
-#define IEEE802_11_STYPE_REASSOC_REQ   0x0020
-#define IEEE802_11_STYPE_REASSOC_RESP  0x0030
-#define IEEE802_11_STYPE_PROBE_REQ     0x0040
-#define IEEE802_11_STYPE_PROBE_RESP    0x0050
-#define IEEE802_11_STYPE_BEACON                0x0080
-#define IEEE802_11_STYPE_ATIM          0x0090
-#define IEEE802_11_STYPE_DISASSOC      0x00A0
-#define IEEE802_11_STYPE_AUTH          0x00B0
-#define IEEE802_11_STYPE_DEAUTH                0x00C0
-
-/* control */
-#define IEEE802_11_STYPE_PSPOLL                0x00A0
-#define IEEE802_11_STYPE_RTS           0x00B0
-#define IEEE802_11_STYPE_CTS           0x00C0
-#define IEEE802_11_STYPE_ACK           0x00D0
-#define IEEE802_11_STYPE_CFEND         0x00E0
-#define IEEE802_11_STYPE_CFENDACK      0x00F0
-
-/* data */
-#define IEEE802_11_STYPE_DATA          0x0000
-#define IEEE802_11_STYPE_DATA_CFACK    0x0010
-#define IEEE802_11_STYPE_DATA_CFPOLL   0x0020
-#define IEEE802_11_STYPE_DATA_CFACKPOLL        0x0030
-#define IEEE802_11_STYPE_NULLFUNC      0x0040
-#define IEEE802_11_STYPE_CFACK         0x0050
-#define IEEE802_11_STYPE_CFPOLL                0x0060
-#define IEEE802_11_STYPE_CFACKPOLL     0x0070
-
-#define IEEE802_11_SCTL_FRAG           0x000F
-#define IEEE802_11_SCTL_SEQ            0xFFF0
-
-#endif /* _IEEE802_11_H */
diff --git a/drivers/net/wireless/ipw2100.c b/drivers/net/wireless/ipw2100.c
new file mode 100644 (file)
index 0000000..189ad7b
--- /dev/null
@@ -0,0 +1,8641 @@
+/******************************************************************************
+
+  Copyright(c) 2003 - 2005 Intel Corporation. All rights reserved.
+
+  This program is free software; you can redistribute it and/or modify it
+  under the terms of version 2 of the GNU General Public License as
+  published by the Free Software Foundation.
+
+  This program is distributed in the hope that it will be useful, but WITHOUT
+  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+  more details.
+
+  You should have received a copy of the GNU General Public License along with
+  this program; if not, write to the Free Software Foundation, Inc., 59
+  Temple Place - Suite 330, Boston, MA  02111-1307, USA.
+
+  The full GNU General Public License is included in this distribution in the
+  file called LICENSE.
+
+  Contact Information:
+  James P. Ketrenos <ipw2100-admin@linux.intel.com>
+  Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
+
+  Portions of this file are based on the sample_* files provided by Wireless
+  Extensions 0.26 package and copyright (c) 1997-2003 Jean Tourrilhes
+  <jt@hpl.hp.com>
+
+  Portions of this file are based on the Host AP project,
+  Copyright (c) 2001-2002, SSH Communications Security Corp and Jouni Malinen
+    <jkmaline@cc.hut.fi>
+  Copyright (c) 2002-2003, Jouni Malinen <jkmaline@cc.hut.fi>
+
+  Portions of ipw2100_mod_firmware_load, ipw2100_do_mod_firmware_load, and
+  ipw2100_fw_load are loosely based on drivers/sound/sound_firmware.c
+  available in the 2.4.25 kernel sources, and are copyright (c) Alan Cox
+
+******************************************************************************/
+/*
+
+ Initial driver on which this is based was developed by Janusz Gorycki,
+ Maciej Urbaniak, and Maciej Sosnowski.
+
+ Promiscuous mode support added by Jacek Wysoczynski and Maciej Urbaniak.
+
+Theory of Operation
+
+Tx - Commands and Data
+
+Firmware and host share a circular queue of Transmit Buffer Descriptors (TBDs)
+Each TBD contains a pointer to the physical (dma_addr_t) address of data being
+sent to the firmware as well as the length of the data.
+
+The host writes to the TBD queue at the WRITE index.  The WRITE index points
+to the _next_ packet to be written and is advanced when after the TBD has been
+filled.
+
+The firmware pulls from the TBD queue at the READ index.  The READ index points
+to the currently being read entry, and is advanced once the firmware is
+done with a packet.
+
+When data is sent to the firmware, the first TBD is used to indicate to the
+firmware if a Command or Data is being sent.  If it is Command, all of the
+command information is contained within the physical address referred to by the
+TBD.  If it is Data, the first TBD indicates the type of data packet, number
+of fragments, etc.  The next TBD then referrs to the actual packet location.
+
+The Tx flow cycle is as follows:
+
+1) ipw2100_tx() is called by kernel with SKB to transmit
+2) Packet is move from the tx_free_list and appended to the transmit pending
+   list (tx_pend_list)
+3) work is scheduled to move pending packets into the shared circular queue.
+4) when placing packet in the circular queue, the incoming SKB is DMA mapped
+   to a physical address.  That address is entered into a TBD.  Two TBDs are
+   filled out.  The first indicating a data packet, the second referring to the
+   actual payload data.
+5) the packet is removed from tx_pend_list and placed on the end of the
+   firmware pending list (fw_pend_list)
+6) firmware is notified that the WRITE index has
+7) Once the firmware has processed the TBD, INTA is triggered.
+8) For each Tx interrupt received from the firmware, the READ index is checked
+   to see which TBDs are done being processed.
+9) For each TBD that has been processed, the ISR pulls the oldest packet
+   from the fw_pend_list.
+10)The packet structure contained in the fw_pend_list is then used
+   to unmap the DMA address and to free the SKB originally passed to the driver
+   from the kernel.
+11)The packet structure is placed onto the tx_free_list
+
+The above steps are the same for commands, only the msg_free_list/msg_pend_list
+are used instead of tx_free_list/tx_pend_list
+
+...
+
+Critical Sections / Locking :
+
+There are two locks utilized.  The first is the low level lock (priv->low_lock)
+that protects the following:
+
+- Access to the Tx/Rx queue lists via priv->low_lock. The lists are as follows:
+
+  tx_free_list : Holds pre-allocated Tx buffers.
+    TAIL modified in __ipw2100_tx_process()
+    HEAD modified in ipw2100_tx()
+
+  tx_pend_list : Holds used Tx buffers waiting to go into the TBD ring
+    TAIL modified ipw2100_tx()
+    HEAD modified by X__ipw2100_tx_send_data()
+
+  msg_free_list : Holds pre-allocated Msg (Command) buffers
+    TAIL modified in __ipw2100_tx_process()
+    HEAD modified in ipw2100_hw_send_command()
+
+  msg_pend_list : Holds used Msg buffers waiting to go into the TBD ring
+    TAIL modified in ipw2100_hw_send_command()
+    HEAD modified in X__ipw2100_tx_send_commands()
+
+  The flow of data on the TX side is as follows:
+
+  MSG_FREE_LIST + COMMAND => MSG_PEND_LIST => TBD => MSG_FREE_LIST
+  TX_FREE_LIST + DATA => TX_PEND_LIST => TBD => TX_FREE_LIST
+
+  The methods that work on the TBD ring are protected via priv->low_lock.
+
+- The internal data state of the device itself
+- Access to the firmware read/write indexes for the BD queues
+  and associated logic
+
+All external entry functions are locked with the priv->action_lock to ensure
+that only one external action is invoked at a time.
+
+
+*/
+
+#include <linux/compiler.h>
+#include <linux/config.h>
+#include <linux/errno.h>
+#include <linux/if_arp.h>
+#include <linux/in6.h>
+#include <linux/in.h>
+#include <linux/ip.h>
+#include <linux/kernel.h>
+#include <linux/kmod.h>
+#include <linux/module.h>
+#include <linux/netdevice.h>
+#include <linux/ethtool.h>
+#include <linux/pci.h>
+#include <linux/dma-mapping.h>
+#include <linux/proc_fs.h>
+#include <linux/skbuff.h>
+#include <asm/uaccess.h>
+#include <asm/io.h>
+#define __KERNEL_SYSCALLS__
+#include <linux/fs.h>
+#include <linux/mm.h>
+#include <linux/slab.h>
+#include <linux/unistd.h>
+#include <linux/stringify.h>
+#include <linux/tcp.h>
+#include <linux/types.h>
+#include <linux/version.h>
+#include <linux/time.h>
+#include <linux/firmware.h>
+#include <linux/acpi.h>
+#include <linux/ctype.h>
+
+#include "ipw2100.h"
+
+#define IPW2100_VERSION "1.1.0"
+
+#define DRV_NAME       "ipw2100"
+#define DRV_VERSION    IPW2100_VERSION
+#define DRV_DESCRIPTION        "Intel(R) PRO/Wireless 2100 Network Driver"
+#define DRV_COPYRIGHT  "Copyright(c) 2003-2004 Intel Corporation"
+
+
+/* Debugging stuff */
+#ifdef CONFIG_IPW_DEBUG
+#define CONFIG_IPW2100_RX_DEBUG   /* Reception debugging */
+#endif
+
+MODULE_DESCRIPTION(DRV_DESCRIPTION);
+MODULE_VERSION(DRV_VERSION);
+MODULE_AUTHOR(DRV_COPYRIGHT);
+MODULE_LICENSE("GPL");
+
+static int debug = 0;
+static int mode = 0;
+static int channel = 0;
+static int associate = 1;
+static int disable = 0;
+#ifdef CONFIG_PM
+static struct ipw2100_fw ipw2100_firmware;
+#endif
+
+#include <linux/moduleparam.h>
+module_param(debug, int, 0444);
+module_param(mode, int, 0444);
+module_param(channel, int, 0444);
+module_param(associate, int, 0444);
+module_param(disable, int, 0444);
+
+MODULE_PARM_DESC(debug, "debug level");
+MODULE_PARM_DESC(mode, "network mode (0=BSS,1=IBSS,2=Monitor)");
+MODULE_PARM_DESC(channel, "channel");
+MODULE_PARM_DESC(associate, "auto associate when scanning (default on)");
+MODULE_PARM_DESC(disable, "manually disable the radio (default 0 [radio on])");
+
+u32 ipw2100_debug_level = IPW_DL_NONE;
+
+#ifdef CONFIG_IPW_DEBUG
+static const char *command_types[] = {
+       "undefined",
+       "unused", /* HOST_ATTENTION */
+       "HOST_COMPLETE",
+       "unused", /* SLEEP */
+       "unused", /* HOST_POWER_DOWN */
+       "unused",
+       "SYSTEM_CONFIG",
+       "unused", /* SET_IMR */
+       "SSID",
+       "MANDATORY_BSSID",
+       "AUTHENTICATION_TYPE",
+       "ADAPTER_ADDRESS",
+       "PORT_TYPE",
+       "INTERNATIONAL_MODE",
+       "CHANNEL",
+       "RTS_THRESHOLD",
+       "FRAG_THRESHOLD",
+       "POWER_MODE",
+       "TX_RATES",
+       "BASIC_TX_RATES",
+       "WEP_KEY_INFO",
+       "unused",
+       "unused",
+       "unused",
+       "unused",
+       "WEP_KEY_INDEX",
+       "WEP_FLAGS",
+       "ADD_MULTICAST",
+       "CLEAR_ALL_MULTICAST",
+       "BEACON_INTERVAL",
+       "ATIM_WINDOW",
+       "CLEAR_STATISTICS",
+       "undefined",
+       "undefined",
+       "undefined",
+       "undefined",
+       "TX_POWER_INDEX",
+       "undefined",
+       "undefined",
+       "undefined",
+       "undefined",
+       "undefined",
+       "undefined",
+       "BROADCAST_SCAN",
+       "CARD_DISABLE",
+       "PREFERRED_BSSID",
+       "SET_SCAN_OPTIONS",
+       "SCAN_DWELL_TIME",
+       "SWEEP_TABLE",
+       "AP_OR_STATION_TABLE",
+       "GROUP_ORDINALS",
+       "SHORT_RETRY_LIMIT",
+       "LONG_RETRY_LIMIT",
+       "unused", /* SAVE_CALIBRATION */
+       "unused", /* RESTORE_CALIBRATION */
+       "undefined",
+       "undefined",
+       "undefined",
+       "HOST_PRE_POWER_DOWN",
+       "unused", /* HOST_INTERRUPT_COALESCING */
+       "undefined",
+       "CARD_DISABLE_PHY_OFF",
+       "MSDU_TX_RATES"
+       "undefined",
+       "undefined",
+       "SET_STATION_STAT_BITS",
+       "CLEAR_STATIONS_STAT_BITS",
+       "LEAP_ROGUE_MODE",
+       "SET_SECURITY_INFORMATION",
+       "DISASSOCIATION_BSSID",
+       "SET_WPA_ASS_IE"
+};
+#endif
+
+
+/* Pre-decl until we get the code solid and then we can clean it up */
+static void X__ipw2100_tx_send_commands(struct ipw2100_priv *priv);
+static void X__ipw2100_tx_send_data(struct ipw2100_priv *priv);
+static int ipw2100_adapter_setup(struct ipw2100_priv *priv);
+
+static void ipw2100_queues_initialize(struct ipw2100_priv *priv);
+static void ipw2100_queues_free(struct ipw2100_priv *priv);
+static int ipw2100_queues_allocate(struct ipw2100_priv *priv);
+
+
+static inline void read_register(struct net_device *dev, u32 reg, u32 *val)
+{
+       *val = readl((void *)(dev->base_addr + reg));
+       IPW_DEBUG_IO("r: 0x%08X => 0x%08X\n", reg, *val);
+}
+
+static inline void write_register(struct net_device *dev, u32 reg, u32 val)
+{
+       writel(val, (void *)(dev->base_addr + reg));
+       IPW_DEBUG_IO("w: 0x%08X <= 0x%08X\n", reg, val);
+}
+
+static inline void read_register_word(struct net_device *dev, u32 reg, u16 *val)
+{
+       *val = readw((void *)(dev->base_addr + reg));
+       IPW_DEBUG_IO("r: 0x%08X => %04X\n", reg, *val);
+}
+
+static inline void read_register_byte(struct net_device *dev, u32 reg, u8 *val)
+{
+       *val = readb((void *)(dev->base_addr + reg));
+       IPW_DEBUG_IO("r: 0x%08X => %02X\n", reg, *val);
+}
+
+static inline void write_register_word(struct net_device *dev, u32 reg, u16 val)
+{
+       writew(val, (void *)(dev->base_addr + reg));
+       IPW_DEBUG_IO("w: 0x%08X <= %04X\n", reg, val);
+}
+
+
+static inline void write_register_byte(struct net_device *dev, u32 reg, u8 val)
+{
+       writeb(val, (void *)(dev->base_addr + reg));
+       IPW_DEBUG_IO("w: 0x%08X =< %02X\n", reg, val);
+}
+
+static inline void read_nic_dword(struct net_device *dev, u32 addr, u32 *val)
+{
+       write_register(dev, IPW_REG_INDIRECT_ACCESS_ADDRESS,
+                      addr & IPW_REG_INDIRECT_ADDR_MASK);
+       read_register(dev, IPW_REG_INDIRECT_ACCESS_DATA, val);
+}
+
+static inline void write_nic_dword(struct net_device *dev, u32 addr, u32 val)
+{
+       write_register(dev, IPW_REG_INDIRECT_ACCESS_ADDRESS,
+                      addr & IPW_REG_INDIRECT_ADDR_MASK);
+       write_register(dev, IPW_REG_INDIRECT_ACCESS_DATA, val);
+}
+
+static inline void read_nic_word(struct net_device *dev, u32 addr, u16 *val)
+{
+       write_register(dev, IPW_REG_INDIRECT_ACCESS_ADDRESS,
+                      addr & IPW_REG_INDIRECT_ADDR_MASK);
+       read_register_word(dev, IPW_REG_INDIRECT_ACCESS_DATA, val);
+}
+
+static inline void write_nic_word(struct net_device *dev, u32 addr, u16 val)
+{
+       write_register(dev, IPW_REG_INDIRECT_ACCESS_ADDRESS,
+                      addr & IPW_REG_INDIRECT_ADDR_MASK);
+       write_register_word(dev, IPW_REG_INDIRECT_ACCESS_DATA, val);
+}
+
+static inline void read_nic_byte(struct net_device *dev, u32 addr, u8 *val)
+{
+       write_register(dev, IPW_REG_INDIRECT_ACCESS_ADDRESS,
+                      addr & IPW_REG_INDIRECT_ADDR_MASK);
+       read_register_byte(dev, IPW_REG_INDIRECT_ACCESS_DATA, val);
+}
+
+static inline void write_nic_byte(struct net_device *dev, u32 addr, u8 val)
+{
+       write_register(dev, IPW_REG_INDIRECT_ACCESS_ADDRESS,
+                      addr & IPW_REG_INDIRECT_ADDR_MASK);
+       write_register_byte(dev, IPW_REG_INDIRECT_ACCESS_DATA, val);
+}
+
+static inline void write_nic_auto_inc_address(struct net_device *dev, u32 addr)
+{
+       write_register(dev, IPW_REG_AUTOINCREMENT_ADDRESS,
+                      addr & IPW_REG_INDIRECT_ADDR_MASK);
+}
+
+static inline void write_nic_dword_auto_inc(struct net_device *dev, u32 val)
+{
+       write_register(dev, IPW_REG_AUTOINCREMENT_DATA, val);
+}
+
+static inline void write_nic_memory(struct net_device *dev, u32 addr, u32 len,
+                                   const u8 *buf)
+{
+       u32 aligned_addr;
+       u32 aligned_len;
+       u32 dif_len;
+       u32 i;
+
+       /* read first nibble byte by byte */
+       aligned_addr = addr & (~0x3);
+       dif_len = addr - aligned_addr;
+       if (dif_len) {
+               /* Start reading at aligned_addr + dif_len */
+               write_register(dev, IPW_REG_INDIRECT_ACCESS_ADDRESS,
+                              aligned_addr);
+               for (i = dif_len; i < 4; i++, buf++)
+                       write_register_byte(
+                               dev, IPW_REG_INDIRECT_ACCESS_DATA + i,
+                               *buf);
+
+               len -= dif_len;
+               aligned_addr += 4;
+       }
+
+       /* read DWs through autoincrement registers */
+       write_register(dev, IPW_REG_AUTOINCREMENT_ADDRESS,
+                      aligned_addr);
+       aligned_len = len & (~0x3);
+       for (i = 0; i < aligned_len; i += 4, buf += 4, aligned_addr += 4)
+               write_register(
+                       dev, IPW_REG_AUTOINCREMENT_DATA, *(u32 *)buf);
+
+       /* copy the last nibble */
+       dif_len = len - aligned_len;
+       write_register(dev, IPW_REG_INDIRECT_ACCESS_ADDRESS, aligned_addr);
+       for (i = 0; i < dif_len; i++, buf++)
+               write_register_byte(
+                       dev, IPW_REG_INDIRECT_ACCESS_DATA + i, *buf);
+}
+
+static inline void read_nic_memory(struct net_device *dev, u32 addr, u32 len,
+                                  u8 *buf)
+{
+       u32 aligned_addr;
+       u32 aligned_len;
+       u32 dif_len;
+       u32 i;
+
+       /* read first nibble byte by byte */
+       aligned_addr = addr & (~0x3);
+       dif_len = addr - aligned_addr;
+       if (dif_len) {
+               /* Start reading at aligned_addr + dif_len */
+               write_register(dev, IPW_REG_INDIRECT_ACCESS_ADDRESS,
+                              aligned_addr);
+               for (i = dif_len; i < 4; i++, buf++)
+                       read_register_byte(
+                               dev, IPW_REG_INDIRECT_ACCESS_DATA + i, buf);
+
+               len -= dif_len;
+               aligned_addr += 4;
+       }
+
+       /* read DWs through autoincrement registers */
+       write_register(dev, IPW_REG_AUTOINCREMENT_ADDRESS,
+                      aligned_addr);
+       aligned_len = len & (~0x3);
+       for (i = 0; i < aligned_len; i += 4, buf += 4, aligned_addr += 4)
+               read_register(dev, IPW_REG_AUTOINCREMENT_DATA,
+                             (u32 *)buf);
+
+       /* copy the last nibble */
+       dif_len = len - aligned_len;
+       write_register(dev, IPW_REG_INDIRECT_ACCESS_ADDRESS,
+                      aligned_addr);
+       for (i = 0; i < dif_len; i++, buf++)
+               read_register_byte(dev, IPW_REG_INDIRECT_ACCESS_DATA +
+                                  i, buf);
+}
+
+static inline int ipw2100_hw_is_adapter_in_system(struct net_device *dev)
+{
+       return (dev->base_addr &&
+               (readl((void *)(dev->base_addr + IPW_REG_DOA_DEBUG_AREA_START))
+                == IPW_DATA_DOA_DEBUG_VALUE));
+}
+
+int ipw2100_get_ordinal(struct ipw2100_priv *priv, u32 ord,
+                       void *val, u32 *len)
+{
+       struct ipw2100_ordinals *ordinals = &priv->ordinals;
+       u32 addr;
+       u32 field_info;
+       u16 field_len;
+       u16 field_count;
+       u32 total_length;
+
+       if (ordinals->table1_addr == 0) {
+               IPW_DEBUG_WARNING(DRV_NAME ": attempt to use fw ordinals "
+                      "before they have been loaded.\n");
+               return -EINVAL;
+       }
+
+       if (IS_ORDINAL_TABLE_ONE(ordinals, ord)) {
+               if (*len < IPW_ORD_TAB_1_ENTRY_SIZE) {
+                       *len = IPW_ORD_TAB_1_ENTRY_SIZE;
+
+                       IPW_DEBUG_WARNING(DRV_NAME
+                              ": ordinal buffer length too small, need %zd\n",
+                              IPW_ORD_TAB_1_ENTRY_SIZE);
+
+                       return -EINVAL;
+               }
+
+               read_nic_dword(priv->net_dev, ordinals->table1_addr + (ord << 2),
+                              &addr);
+               read_nic_dword(priv->net_dev, addr, val);
+
+               *len = IPW_ORD_TAB_1_ENTRY_SIZE;
+
+               return 0;
+       }
+
+       if (IS_ORDINAL_TABLE_TWO(ordinals, ord)) {
+
+               ord -= IPW_START_ORD_TAB_2;
+
+               /* get the address of statistic */
+               read_nic_dword(priv->net_dev, ordinals->table2_addr + (ord << 3),
+                              &addr);
+
+               /* get the second DW of statistics ;
+                * two 16-bit words - first is length, second is count */
+               read_nic_dword(priv->net_dev,
+                              ordinals->table2_addr + (ord << 3) + sizeof(u32),
+                              &field_info);
+
+               /* get each entry length */
+               field_len = *((u16 *)&field_info);
+
+               /* get number of entries */
+               field_count = *(((u16 *)&field_info) + 1);
+
+               /* abort if no enought memory */
+               total_length = field_len * field_count;
+               if (total_length > *len) {
+                       *len = total_length;
+                       return -EINVAL;
+               }
+
+               *len = total_length;
+               if (!total_length)
+                       return 0;
+
+               /* read the ordinal data from the SRAM */
+               read_nic_memory(priv->net_dev, addr, total_length, val);
+
+               return 0;
+       }
+
+       IPW_DEBUG_WARNING(DRV_NAME ": ordinal %d neither in table 1 nor "
+              "in table 2\n", ord);
+
+       return -EINVAL;
+}
+
+static int ipw2100_set_ordinal(struct ipw2100_priv *priv, u32 ord, u32 *val,
+                              u32 *len)
+{
+       struct ipw2100_ordinals *ordinals = &priv->ordinals;
+       u32 addr;
+
+       if (IS_ORDINAL_TABLE_ONE(ordinals, ord)) {
+               if (*len != IPW_ORD_TAB_1_ENTRY_SIZE) {
+                       *len = IPW_ORD_TAB_1_ENTRY_SIZE;
+                       IPW_DEBUG_INFO("wrong size\n");
+                       return -EINVAL;
+               }
+
+               read_nic_dword(priv->net_dev, ordinals->table1_addr + (ord << 2),
+                              &addr);
+
+               write_nic_dword(priv->net_dev, addr, *val);
+
+               *len = IPW_ORD_TAB_1_ENTRY_SIZE;
+
+               return 0;
+       }
+
+       IPW_DEBUG_INFO("wrong table\n");
+       if (IS_ORDINAL_TABLE_TWO(ordinals, ord))
+               return -EINVAL;
+
+       return -EINVAL;
+}
+
+static char *snprint_line(char *buf, size_t count,
+                         const u8 *data, u32 len, u32 ofs)
+{
+       int out, i, j, l;
+       char c;
+
+       out = snprintf(buf, count, "%08X", ofs);
+
+       for (l = 0, i = 0; i < 2; i++) {
+               out += snprintf(buf + out, count - out, " ");
+               for (j = 0; j < 8 && l < len; j++, l++)
+                       out += snprintf(buf + out, count - out, "%02X ",
+                                       data[(i * 8 + j)]);
+               for (; j < 8; j++)
+                       out += snprintf(buf + out, count - out, "   ");
+       }
+
+       out += snprintf(buf + out, count - out, " ");
+       for (l = 0, i = 0; i < 2; i++) {
+               out += snprintf(buf + out, count - out, " ");
+               for (j = 0; j < 8 && l < len; j++, l++) {
+                       c = data[(i * 8 + j)];
+                       if (!isascii(c) || !isprint(c))
+                               c = '.';
+
+                       out += snprintf(buf + out, count - out, "%c", c);
+               }
+
+               for (; j < 8; j++)
+                       out += snprintf(buf + out, count - out, " ");
+       }
+
+       return buf;
+}
+
+static void printk_buf(int level, const u8 *data, u32 len)
+{
+       char line[81];
+       u32 ofs = 0;
+       if (!(ipw2100_debug_level & level))
+               return;
+
+       while (len) {
+               printk(KERN_DEBUG "%s\n",
+                      snprint_line(line, sizeof(line), &data[ofs],
+                                   min(len, 16U), ofs));
+               ofs += 16;
+               len -= min(len, 16U);
+       }
+}
+
+
+
+#define MAX_RESET_BACKOFF 10
+
+static inline void schedule_reset(struct ipw2100_priv *priv)
+{
+       unsigned long now = get_seconds();
+
+       /* If we haven't received a reset request within the backoff period,
+        * then we can reset the backoff interval so this reset occurs
+        * immediately */
+       if (priv->reset_backoff &&
+           (now - priv->last_reset > priv->reset_backoff))
+               priv->reset_backoff = 0;
+
+       priv->last_reset = get_seconds();
+
+       if (!(priv->status & STATUS_RESET_PENDING)) {
+               IPW_DEBUG_INFO("%s: Scheduling firmware restart (%ds).\n",
+                              priv->net_dev->name, priv->reset_backoff);
+               netif_carrier_off(priv->net_dev);
+               netif_stop_queue(priv->net_dev);
+               priv->status |= STATUS_RESET_PENDING;
+               if (priv->reset_backoff)
+                       queue_delayed_work(priv->workqueue, &priv->reset_work,
+                                          priv->reset_backoff * HZ);
+               else
+                       queue_work(priv->workqueue, &priv->reset_work);
+
+               if (priv->reset_backoff < MAX_RESET_BACKOFF)
+                       priv->reset_backoff++;
+
+               wake_up_interruptible(&priv->wait_command_queue);
+       } else
+               IPW_DEBUG_INFO("%s: Firmware restart already in progress.\n",
+                              priv->net_dev->name);
+
+}
+
+#define HOST_COMPLETE_TIMEOUT (2 * HZ)
+static int ipw2100_hw_send_command(struct ipw2100_priv *priv,
+                                  struct host_command * cmd)
+{
+       struct list_head *element;
+       struct ipw2100_tx_packet *packet;
+       unsigned long flags;
+       int err = 0;
+
+       IPW_DEBUG_HC("Sending %s command (#%d), %d bytes\n",
+                    command_types[cmd->host_command], cmd->host_command,
+                    cmd->host_command_length);
+       printk_buf(IPW_DL_HC, (u8*)cmd->host_command_parameters,
+                  cmd->host_command_length);
+
+       spin_lock_irqsave(&priv->low_lock, flags);
+
+       if (priv->fatal_error) {
+               IPW_DEBUG_INFO("Attempt to send command while hardware in fatal error condition.\n");
+               err = -EIO;
+               goto fail_unlock;
+       }
+
+       if (!(priv->status & STATUS_RUNNING)) {
+               IPW_DEBUG_INFO("Attempt to send command while hardware is not running.\n");
+               err = -EIO;
+               goto fail_unlock;
+       }
+
+       if (priv->status & STATUS_CMD_ACTIVE) {
+               IPW_DEBUG_INFO("Attempt to send command while another command is pending.\n");
+               err = -EBUSY;
+               goto fail_unlock;
+       }
+
+       if (list_empty(&priv->msg_free_list)) {
+               IPW_DEBUG_INFO("no available msg buffers\n");
+               goto fail_unlock;
+       }
+
+       priv->status |= STATUS_CMD_ACTIVE;
+       priv->messages_sent++;
+
+       element = priv->msg_free_list.next;
+
+       packet = list_entry(element, struct ipw2100_tx_packet, list);
+       packet->jiffy_start = jiffies;
+
+       /* initialize the firmware command packet */
+       packet->info.c_struct.cmd->host_command_reg = cmd->host_command;
+       packet->info.c_struct.cmd->host_command_reg1 = cmd->host_command1;
+       packet->info.c_struct.cmd->host_command_len_reg = cmd->host_command_length;
+       packet->info.c_struct.cmd->sequence = cmd->host_command_sequence;
+
+       memcpy(packet->info.c_struct.cmd->host_command_params_reg,
+              cmd->host_command_parameters,
+              sizeof(packet->info.c_struct.cmd->host_command_params_reg));
+
+       list_del(element);
+       DEC_STAT(&priv->msg_free_stat);
+
+       list_add_tail(element, &priv->msg_pend_list);
+       INC_STAT(&priv->msg_pend_stat);
+
+       X__ipw2100_tx_send_commands(priv);
+       X__ipw2100_tx_send_data(priv);
+
+       spin_unlock_irqrestore(&priv->low_lock, flags);
+
+       /*
+        * We must wait for this command to complete before another
+        * command can be sent...  but if we wait more than 3 seconds
+        * then there is a problem.
+        */
+
+       err = wait_event_interruptible_timeout(
+               priv->wait_command_queue, !(priv->status & STATUS_CMD_ACTIVE),
+               HOST_COMPLETE_TIMEOUT);
+
+       if (err == 0) {
+               IPW_DEBUG_INFO("Command completion failed out after %dms.\n",
+                              HOST_COMPLETE_TIMEOUT / (HZ / 100));
+               priv->fatal_error = IPW2100_ERR_MSG_TIMEOUT;
+               priv->status &= ~STATUS_CMD_ACTIVE;
+               schedule_reset(priv);
+               return -EIO;
+       }
+
+       if (priv->fatal_error) {
+               IPW_DEBUG_WARNING("%s: firmware fatal error\n",
+                      priv->net_dev->name);
+               return -EIO;
+       }
+
+       /* !!!!! HACK TEST !!!!!
+        * When lots of debug trace statements are enabled, the driver
+        * doesn't seem to have as many firmware restart cycles...
+        *
+        * As a test, we're sticking in a 1/100s delay here */
+       set_current_state(TASK_UNINTERRUPTIBLE);
+       schedule_timeout(HZ / 100);
+
+       return 0;
+
+ fail_unlock:
+       spin_unlock_irqrestore(&priv->low_lock, flags);
+
+       return err;
+}
+
+
+/*
+ * Verify the values and data access of the hardware
+ * No locks needed or used.  No functions called.
+ */
+static int ipw2100_verify(struct ipw2100_priv *priv)
+{
+       u32 data1, data2;
+       u32 address;
+
+       u32 val1 = 0x76543210;
+       u32 val2 = 0xFEDCBA98;
+
+       /* Domain 0 check - all values should be DOA_DEBUG */
+       for (address = IPW_REG_DOA_DEBUG_AREA_START;
+            address < IPW_REG_DOA_DEBUG_AREA_END;
+            address += sizeof(u32)) {
+               read_register(priv->net_dev, address, &data1);
+               if (data1 != IPW_DATA_DOA_DEBUG_VALUE)
+                       return -EIO;
+       }
+
+       /* Domain 1 check - use arbitrary read/write compare  */
+       for (address = 0; address < 5; address++) {
+               /* The memory area is not used now */
+               write_register(priv->net_dev, IPW_REG_DOMAIN_1_OFFSET + 0x32,
+                              val1);
+               write_register(priv->net_dev, IPW_REG_DOMAIN_1_OFFSET + 0x36,
+                              val2);
+               read_register(priv->net_dev, IPW_REG_DOMAIN_1_OFFSET + 0x32,
+                             &data1);
+               read_register(priv->net_dev, IPW_REG_DOMAIN_1_OFFSET + 0x36,
+                             &data2);
+               if (val1 == data1 && val2 == data2)
+                       return 0;
+       }
+
+       return -EIO;
+}
+
+/*
+ *
+ * Loop until the CARD_DISABLED bit is the same value as the
+ * supplied parameter
+ *
+ * TODO: See if it would be more efficient to do a wait/wake
+ *       cycle and have the completion event trigger the wakeup
+ *
+ */
+#define IPW_CARD_DISABLE_COMPLETE_WAIT             100 // 100 milli
+static int ipw2100_wait_for_card_state(struct ipw2100_priv *priv, int state)
+{
+       int i;
+       u32 card_state;
+       u32 len = sizeof(card_state);
+       int err;
+
+       for (i = 0; i <= IPW_CARD_DISABLE_COMPLETE_WAIT * 1000; i += 50) {
+               err = ipw2100_get_ordinal(priv, IPW_ORD_CARD_DISABLED,
+                                         &card_state, &len);
+               if (err) {
+                       IPW_DEBUG_INFO("Query of CARD_DISABLED ordinal "
+                                      "failed.\n");
+                       return 0;
+               }
+
+               /* We'll break out if either the HW state says it is
+                * in the state we want, or if HOST_COMPLETE command
+                * finishes */
+               if ((card_state == state) ||
+                   ((priv->status & STATUS_ENABLED) ?
+                    IPW_HW_STATE_ENABLED : IPW_HW_STATE_DISABLED) == state) {
+                       if (state == IPW_HW_STATE_ENABLED)
+                               priv->status |= STATUS_ENABLED;
+                       else
+                               priv->status &= ~STATUS_ENABLED;
+
+                       return 0;
+               }
+
+               udelay(50);
+       }
+
+       IPW_DEBUG_INFO("ipw2100_wait_for_card_state to %s state timed out\n",
+                      state ? "DISABLED" : "ENABLED");
+       return -EIO;
+}
+
+
+/*********************************************************************
+    Procedure   :   sw_reset_and_clock
+    Purpose     :   Asserts s/w reset, asserts clock initialization
+                    and waits for clock stabilization
+ ********************************************************************/
+static int sw_reset_and_clock(struct ipw2100_priv *priv)
+{
+       int i;
+       u32 r;
+
+       // assert s/w reset
+       write_register(priv->net_dev, IPW_REG_RESET_REG,
+                      IPW_AUX_HOST_RESET_REG_SW_RESET);
+
+       // wait for clock stabilization
+       for (i = 0; i < 1000; i++) {
+               udelay(IPW_WAIT_RESET_ARC_COMPLETE_DELAY);
+
+               // check clock ready bit
+               read_register(priv->net_dev, IPW_REG_RESET_REG, &r);
+               if (r & IPW_AUX_HOST_RESET_REG_PRINCETON_RESET)
+                       break;
+       }
+
+       if (i == 1000)
+               return -EIO;    // TODO: better error value
+
+       /* set "initialization complete" bit to move adapter to
+        * D0 state */
+       write_register(priv->net_dev, IPW_REG_GP_CNTRL,
+                      IPW_AUX_HOST_GP_CNTRL_BIT_INIT_DONE);
+
+       /* wait for clock stabilization */
+       for (i = 0; i < 10000; i++) {
+               udelay(IPW_WAIT_CLOCK_STABILIZATION_DELAY * 4);
+
+               /* check clock ready bit */
+               read_register(priv->net_dev, IPW_REG_GP_CNTRL, &r);
+               if (r & IPW_AUX_HOST_GP_CNTRL_BIT_CLOCK_READY)
+                       break;
+       }
+
+       if (i == 10000)
+               return -EIO;    /* TODO: better error value */
+
+       /* set D0 standby bit */
+       read_register(priv->net_dev, IPW_REG_GP_CNTRL, &r);
+       write_register(priv->net_dev, IPW_REG_GP_CNTRL,
+                      r | IPW_AUX_HOST_GP_CNTRL_BIT_HOST_ALLOWS_STANDBY);
+
+       return 0;
+}
+
+/*********************************************************************
+    Procedure   :   ipw2100_download_firmware
+    Purpose     :   Initiaze adapter after power on.
+                    The sequence is:
+                    1. assert s/w reset first!
+                    2. awake clocks & wait for clock stabilization
+                    3. hold ARC (don't ask me why...)
+                    4. load Dino ucode and reset/clock init again
+                    5. zero-out shared mem
+                    6. download f/w
+ *******************************************************************/
+static int ipw2100_download_firmware(struct ipw2100_priv *priv)
+{
+       u32 address;
+       int err;
+
+#ifndef CONFIG_PM
+       /* Fetch the firmware and microcode */
+       struct ipw2100_fw ipw2100_firmware;
+#endif
+
+       if (priv->fatal_error) {
+               IPW_DEBUG_ERROR("%s: ipw2100_download_firmware called after "
+                      "fatal error %d.  Interface must be brought down.\n",
+                      priv->net_dev->name, priv->fatal_error);
+               return -EINVAL;
+       }
+
+#ifdef CONFIG_PM
+       if (!ipw2100_firmware.version) {
+               err = ipw2100_get_firmware(priv, &ipw2100_firmware);
+               if (err) {
+                       IPW_DEBUG_ERROR("%s: ipw2100_get_firmware failed: %d\n",
+                              priv->net_dev->name, err);
+                       priv->fatal_error = IPW2100_ERR_FW_LOAD;
+                       goto fail;
+               }
+       }
+#else
+       err = ipw2100_get_firmware(priv, &ipw2100_firmware);
+       if (err) {
+               IPW_DEBUG_ERROR("%s: ipw2100_get_firmware failed: %d\n",
+                      priv->net_dev->name, err);
+               priv->fatal_error = IPW2100_ERR_FW_LOAD;
+               goto fail;
+       }
+#endif
+       priv->firmware_version = ipw2100_firmware.version;
+
+       /* s/w reset and clock stabilization */
+       err = sw_reset_and_clock(priv);
+       if (err) {
+               IPW_DEBUG_ERROR("%s: sw_reset_and_clock failed: %d\n",
+                      priv->net_dev->name, err);
+               goto fail;
+       }
+
+       err = ipw2100_verify(priv);
+       if (err) {
+               IPW_DEBUG_ERROR("%s: ipw2100_verify failed: %d\n",
+                      priv->net_dev->name, err);
+               goto fail;
+       }
+
+       /* Hold ARC */
+       write_nic_dword(priv->net_dev,
+                       IPW_INTERNAL_REGISTER_HALT_AND_RESET,
+                       0x80000000);
+
+       /* allow ARC to run */
+       write_register(priv->net_dev, IPW_REG_RESET_REG, 0);
+
+       /* load microcode */
+       err = ipw2100_ucode_download(priv, &ipw2100_firmware);
+       if (err) {
+               IPW_DEBUG_ERROR("%s: Error loading microcode: %d\n",
+                      priv->net_dev->name, err);
+               goto fail;
+       }
+
+       /* release ARC */
+       write_nic_dword(priv->net_dev,
+                       IPW_INTERNAL_REGISTER_HALT_AND_RESET,
+                       0x00000000);
+
+       /* s/w reset and clock stabilization (again!!!) */
+       err = sw_reset_and_clock(priv);
+       if (err) {
+               IPW_DEBUG_ERROR("%s: sw_reset_and_clock failed: %d\n",
+                      priv->net_dev->name, err);
+               goto fail;
+       }
+
+       /* load f/w */
+       err = ipw2100_fw_download(priv, &ipw2100_firmware);
+       if (err) {
+               IPW_DEBUG_ERROR("%s: Error loading firmware: %d\n",
+                      priv->net_dev->name, err);
+               goto fail;
+       }
+
+#ifndef CONFIG_PM
+       /*
+        * When the .resume method of the driver is called, the other
+        * part of the system, i.e. the ide driver could still stay in
+        * the suspend stage. This prevents us from loading the firmware
+        * from the disk.  --YZ
+        */
+
+       /* free any storage allocated for firmware image */
+       ipw2100_release_firmware(priv, &ipw2100_firmware);
+#endif
+
+       /* zero out Domain 1 area indirectly (Si requirement) */
+       for (address = IPW_HOST_FW_SHARED_AREA0;
+            address < IPW_HOST_FW_SHARED_AREA0_END; address += 4)
+               write_nic_dword(priv->net_dev, address, 0);
+       for (address = IPW_HOST_FW_SHARED_AREA1;
+            address < IPW_HOST_FW_SHARED_AREA1_END; address += 4)
+               write_nic_dword(priv->net_dev, address, 0);
+       for (address = IPW_HOST_FW_SHARED_AREA2;
+            address < IPW_HOST_FW_SHARED_AREA2_END; address += 4)
+               write_nic_dword(priv->net_dev, address, 0);
+       for (address = IPW_HOST_FW_SHARED_AREA3;
+            address < IPW_HOST_FW_SHARED_AREA3_END; address += 4)
+               write_nic_dword(priv->net_dev, address, 0);
+       for (address = IPW_HOST_FW_INTERRUPT_AREA;
+            address < IPW_HOST_FW_INTERRUPT_AREA_END; address += 4)
+               write_nic_dword(priv->net_dev, address, 0);
+
+       return 0;
+
+ fail:
+       ipw2100_release_firmware(priv, &ipw2100_firmware);
+       return err;
+}
+
+static inline void ipw2100_enable_interrupts(struct ipw2100_priv *priv)
+{
+       if (priv->status & STATUS_INT_ENABLED)
+               return;
+       priv->status |= STATUS_INT_ENABLED;
+       write_register(priv->net_dev, IPW_REG_INTA_MASK, IPW_INTERRUPT_MASK);
+}
+
+static inline void ipw2100_disable_interrupts(struct ipw2100_priv *priv)
+{
+       if (!(priv->status & STATUS_INT_ENABLED))
+               return;
+       priv->status &= ~STATUS_INT_ENABLED;
+       write_register(priv->net_dev, IPW_REG_INTA_MASK, 0x0);
+}
+
+
+static void ipw2100_initialize_ordinals(struct ipw2100_priv *priv)
+{
+       struct ipw2100_ordinals *ord = &priv->ordinals;
+
+       IPW_DEBUG_INFO("enter\n");
+
+       read_register(priv->net_dev, IPW_MEM_HOST_SHARED_ORDINALS_TABLE_1,
+                     &ord->table1_addr);
+
+       read_register(priv->net_dev, IPW_MEM_HOST_SHARED_ORDINALS_TABLE_2,
+                     &ord->table2_addr);
+
+       read_nic_dword(priv->net_dev, ord->table1_addr, &ord->table1_size);
+       read_nic_dword(priv->net_dev, ord->table2_addr, &ord->table2_size);
+
+       ord->table2_size &= 0x0000FFFF;
+
+       IPW_DEBUG_INFO("table 1 size: %d\n", ord->table1_size);
+       IPW_DEBUG_INFO("table 2 size: %d\n", ord->table2_size);
+       IPW_DEBUG_INFO("exit\n");
+}
+
+static inline void ipw2100_hw_set_gpio(struct ipw2100_priv *priv)
+{
+       u32 reg = 0;
+       /*
+        * Set GPIO 3 writable by FW; GPIO 1 writable
+        * by driver and enable clock
+        */
+       reg = (IPW_BIT_GPIO_GPIO3_MASK | IPW_BIT_GPIO_GPIO1_ENABLE |
+              IPW_BIT_GPIO_LED_OFF);
+       write_register(priv->net_dev, IPW_REG_GPIO, reg);
+}
+
+static inline int rf_kill_active(struct ipw2100_priv *priv)
+{
+#define MAX_RF_KILL_CHECKS 5
+#define RF_KILL_CHECK_DELAY 40
+
+       unsigned short value = 0;
+       u32 reg = 0;
+       int i;
+
+       if (!(priv->hw_features & HW_FEATURE_RFKILL)) {
+               priv->status &= ~STATUS_RF_KILL_HW;
+               return 0;
+       }
+
+       for (i = 0; i < MAX_RF_KILL_CHECKS; i++) {
+               udelay(RF_KILL_CHECK_DELAY);
+               read_register(priv->net_dev, IPW_REG_GPIO, &reg);
+               value = (value << 1) | ((reg & IPW_BIT_GPIO_RF_KILL) ? 0 : 1);
+       }
+
+       if (value == 0)
+               priv->status |= STATUS_RF_KILL_HW;
+       else
+               priv->status &= ~STATUS_RF_KILL_HW;
+
+       return (value == 0);
+}
+
+static int ipw2100_get_hw_features(struct ipw2100_priv *priv)
+{
+       u32 addr, len;
+       u32 val;
+
+       /*
+        * EEPROM_SRAM_DB_START_ADDRESS using ordinal in ordinal table 1
+        */
+       len = sizeof(addr);
+       if (ipw2100_get_ordinal(
+                   priv, IPW_ORD_EEPROM_SRAM_DB_BLOCK_START_ADDRESS,
+                   &addr, &len)) {
+               IPW_DEBUG_INFO("failed querying ordinals at line %d\n",
+                      __LINE__);
+               return -EIO;
+       }
+
+       IPW_DEBUG_INFO("EEPROM address: %08X\n", addr);
+
+       /*
+        * EEPROM version is the byte at offset 0xfd in firmware
+        * We read 4 bytes, then shift out the byte we actually want */
+       read_nic_dword(priv->net_dev, addr + 0xFC, &val);
+       priv->eeprom_version = (val >> 24) & 0xFF;
+       IPW_DEBUG_INFO("EEPROM version: %d\n", priv->eeprom_version);
+
+        /*
+        *  HW RF Kill enable is bit 0 in byte at offset 0x21 in firmware
+        *
+        *  notice that the EEPROM bit is reverse polarity, i.e.
+        *     bit = 0  signifies HW RF kill switch is supported
+        *     bit = 1  signifies HW RF kill switch is NOT supported
+        */
+       read_nic_dword(priv->net_dev, addr + 0x20, &val);
+       if (!((val >> 24) & 0x01))
+               priv->hw_features |= HW_FEATURE_RFKILL;
+
+       IPW_DEBUG_INFO("HW RF Kill: %ssupported.\n",
+                          (priv->hw_features & HW_FEATURE_RFKILL) ?
+                          "" : "not ");
+
+       return 0;
+}
+
+/*
+ * Start firmware execution after power on and intialization
+ * The sequence is:
+ *  1. Release ARC
+ *  2. Wait for f/w initialization completes;
+ */
+static int ipw2100_start_adapter(struct ipw2100_priv *priv)
+{
+       int i;
+       u32 inta, inta_mask, gpio;
+
+       IPW_DEBUG_INFO("enter\n");
+
+       if (priv->status & STATUS_RUNNING)
+               return 0;
+
+       /*
+        * Initialize the hw - drive adapter to DO state by setting
+        * init_done bit. Wait for clk_ready bit and Download
+        * fw & dino ucode
+        */
+       if (ipw2100_download_firmware(priv)) {
+               IPW_DEBUG_ERROR("%s: Failed to power on the adapter.\n",
+                      priv->net_dev->name);
+               return -EIO;
+       }
+
+       /* Clear the Tx, Rx and Msg queues and the r/w indexes
+        * in the firmware RBD and TBD ring queue */
+       ipw2100_queues_initialize(priv);
+
+       ipw2100_hw_set_gpio(priv);
+
+       /* TODO -- Look at disabling interrupts here to make sure none
+        * get fired during FW initialization */
+
+       /* Release ARC - clear reset bit */
+       write_register(priv->net_dev, IPW_REG_RESET_REG, 0);
+
+       /* wait for f/w intialization complete */
+       IPW_DEBUG_FW("Waiting for f/w initialization to complete...\n");
+       i = 5000;
+       do {
+               set_current_state(TASK_UNINTERRUPTIBLE);
+               schedule_timeout(40 * HZ / 1000);
+               /* Todo... wait for sync command ... */
+
+               read_register(priv->net_dev, IPW_REG_INTA, &inta);
+
+               /* check "init done" bit */
+               if (inta & IPW2100_INTA_FW_INIT_DONE) {
+                       /* reset "init done" bit */
+                       write_register(priv->net_dev, IPW_REG_INTA,
+                                      IPW2100_INTA_FW_INIT_DONE);
+                       break;
+               }
+
+               /* check error conditions : we check these after the firmware
+                * check so that if there is an error, the interrupt handler
+                * will see it and the adapter will be reset */
+               if (inta &
+                   (IPW2100_INTA_FATAL_ERROR | IPW2100_INTA_PARITY_ERROR)) {
+                       /* clear error conditions */
+                       write_register(priv->net_dev, IPW_REG_INTA,
+                                      IPW2100_INTA_FATAL_ERROR |
+                                      IPW2100_INTA_PARITY_ERROR);
+               }
+       } while (i--);
+
+       /* Clear out any pending INTAs since we aren't supposed to have
+        * interrupts enabled at this point... */
+       read_register(priv->net_dev, IPW_REG_INTA, &inta);
+       read_register(priv->net_dev, IPW_REG_INTA_MASK, &inta_mask);
+       inta &= IPW_INTERRUPT_MASK;
+       /* Clear out any pending interrupts */
+       if (inta & inta_mask)
+               write_register(priv->net_dev, IPW_REG_INTA, inta);
+
+       IPW_DEBUG_FW("f/w initialization complete: %s\n",
+                    i ? "SUCCESS" : "FAILED");
+
+       if (!i) {
+               IPW_DEBUG_WARNING("%s: Firmware did not initialize.\n",
+                      priv->net_dev->name);
+               return -EIO;
+       }
+
+       /* allow firmware to write to GPIO1 & GPIO3 */
+       read_register(priv->net_dev, IPW_REG_GPIO, &gpio);
+
+       gpio |= (IPW_BIT_GPIO_GPIO1_MASK | IPW_BIT_GPIO_GPIO3_MASK);
+
+       write_register(priv->net_dev, IPW_REG_GPIO, gpio);
+
+       /* Ready to receive commands */
+       priv->status |= STATUS_RUNNING;
+
+       /* The adapter has been reset; we are not associated */
+       priv->status &= ~(STATUS_ASSOCIATING | STATUS_ASSOCIATED);
+
+       IPW_DEBUG_INFO("exit\n");
+
+       return 0;
+}
+
+static inline void ipw2100_reset_fatalerror(struct ipw2100_priv *priv)
+{
+       if (!priv->fatal_error)
+               return;
+
+       priv->fatal_errors[priv->fatal_index++] = priv->fatal_error;
+       priv->fatal_index %= IPW2100_ERROR_QUEUE;
+       priv->fatal_error = 0;
+}
+
+
+/* NOTE: Our interrupt is disabled when this method is called */
+static int ipw2100_power_cycle_adapter(struct ipw2100_priv *priv)
+{
+       u32 reg;
+       int i;
+
+       IPW_DEBUG_INFO("Power cycling the hardware.\n");
+
+       ipw2100_hw_set_gpio(priv);
+
+       /* Step 1. Stop Master Assert */
+       write_register(priv->net_dev, IPW_REG_RESET_REG,
+                      IPW_AUX_HOST_RESET_REG_STOP_MASTER);
+
+       /* Step 2. Wait for stop Master Assert
+        *         (not more then 50us, otherwise ret error */
+       i = 5;
+       do {
+               udelay(IPW_WAIT_RESET_MASTER_ASSERT_COMPLETE_DELAY);
+               read_register(priv->net_dev, IPW_REG_RESET_REG, &reg);
+
+               if (reg & IPW_AUX_HOST_RESET_REG_MASTER_DISABLED)
+                       break;
+       }  while(i--);
+
+       priv->status &= ~STATUS_RESET_PENDING;
+
+       if (!i) {
+               IPW_DEBUG_INFO("exit - waited too long for master assert stop\n");
+               return -EIO;
+       }
+
+       write_register(priv->net_dev, IPW_REG_RESET_REG,
+                      IPW_AUX_HOST_RESET_REG_SW_RESET);
+
+
+       /* Reset any fatal_error conditions */
+       ipw2100_reset_fatalerror(priv);
+
+       /* At this point, the adapter is now stopped and disabled */
+       priv->status &= ~(STATUS_RUNNING | STATUS_ASSOCIATING |
+                         STATUS_ASSOCIATED | STATUS_ENABLED);
+
+       return 0;
+}
+
+/*
+ * Send the CARD_DISABLE_PHY_OFF comamnd to the card to disable it
+ *
+ * After disabling, if the card was associated, a STATUS_ASSN_LOST will be sent.
+ *
+ * STATUS_CARD_DISABLE_NOTIFICATION will be sent regardless of
+ * if STATUS_ASSN_LOST is sent.
+ */
+static int ipw2100_hw_phy_off(struct ipw2100_priv *priv)
+{
+
+#define HW_PHY_OFF_LOOP_DELAY (HZ / 5000)
+
+       struct host_command cmd = {
+               .host_command = CARD_DISABLE_PHY_OFF,
+               .host_command_sequence = 0,
+               .host_command_length = 0,
+       };
+       int err, i;
+       u32 val1, val2;
+
+       IPW_DEBUG_HC("CARD_DISABLE_PHY_OFF\n");
+
+       /* Turn off the radio */
+       err = ipw2100_hw_send_command(priv, &cmd);
+       if (err)
+               return err;
+
+       for (i = 0; i < 2500; i++) {
+               read_nic_dword(priv->net_dev, IPW2100_CONTROL_REG, &val1);
+               read_nic_dword(priv->net_dev, IPW2100_COMMAND, &val2);
+
+               if ((val1 & IPW2100_CONTROL_PHY_OFF) &&
+                   (val2 & IPW2100_COMMAND_PHY_OFF))
+                       return 0;
+
+               set_current_state(TASK_UNINTERRUPTIBLE);
+               schedule_timeout(HW_PHY_OFF_LOOP_DELAY);
+       }
+
+       return -EIO;
+}
+
+
+static int ipw2100_enable_adapter(struct ipw2100_priv *priv)
+{
+       struct host_command cmd = {
+               .host_command = HOST_COMPLETE,
+               .host_command_sequence = 0,
+               .host_command_length = 0
+       };
+       int err = 0;
+
+       IPW_DEBUG_HC("HOST_COMPLETE\n");
+
+       if (priv->status & STATUS_ENABLED)
+               return 0;
+
+       down(&priv->adapter_sem);
+
+       if (rf_kill_active(priv)) {
+               IPW_DEBUG_HC("Command aborted due to RF kill active.\n");
+               goto fail_up;
+       }
+
+       err = ipw2100_hw_send_command(priv, &cmd);
+       if (err) {
+               IPW_DEBUG_INFO("Failed to send HOST_COMPLETE command\n");
+               goto fail_up;
+       }
+
+       err = ipw2100_wait_for_card_state(priv, IPW_HW_STATE_ENABLED);
+       if (err) {
+               IPW_DEBUG_INFO(
+                      "%s: card not responding to init command.\n",
+                      priv->net_dev->name);
+               goto fail_up;
+       }
+
+       if (priv->stop_hang_check) {
+               priv->stop_hang_check = 0;
+               queue_delayed_work(priv->workqueue, &priv->hang_check, HZ / 2);
+       }
+
+fail_up:
+       up(&priv->adapter_sem);
+       return err;
+}
+
+static int ipw2100_hw_stop_adapter(struct ipw2100_priv *priv)
+{
+#define HW_POWER_DOWN_DELAY (HZ / 10)
+
+       struct host_command cmd = {
+               .host_command = HOST_PRE_POWER_DOWN,
+               .host_command_sequence = 0,
+               .host_command_length = 0,
+       };
+       int err, i;
+       u32 reg;
+
+       if (!(priv->status & STATUS_RUNNING))
+               return 0;
+
+       priv->status |= STATUS_STOPPING;
+
+       /* We can only shut down the card if the firmware is operational.  So,
+        * if we haven't reset since a fatal_error, then we can not send the
+        * shutdown commands. */
+       if (!priv->fatal_error) {
+               /* First, make sure the adapter is enabled so that the PHY_OFF
+                * command can shut it down */
+               ipw2100_enable_adapter(priv);
+
+               err = ipw2100_hw_phy_off(priv);
+               if (err)
+                       IPW_DEBUG_WARNING("Error disabling radio %d\n", err);
+
+               /*
+                * If in D0-standby mode going directly to D3 may cause a
+                * PCI bus violation.  Therefore we must change out of the D0
+                * state.
+                *
+                * Sending the PREPARE_FOR_POWER_DOWN will restrict the
+                * hardware from going into standby mode and will transition
+                * out of D0-standy if it is already in that state.
+                *
+                * STATUS_PREPARE_POWER_DOWN_COMPLETE will be sent by the
+                * driver upon completion.  Once received, the driver can
+                * proceed to the D3 state.
+                *
+                * Prepare for power down command to fw.  This command would
+                * take HW out of D0-standby and prepare it for D3 state.
+                *
+                * Currently FW does not support event notification for this
+                * event. Therefore, skip waiting for it.  Just wait a fixed
+                * 100ms
+                */
+               IPW_DEBUG_HC("HOST_PRE_POWER_DOWN\n");
+
+               err = ipw2100_hw_send_command(priv, &cmd);
+               if (err)
+                       IPW_DEBUG_WARNING(
+                              "%s: Power down command failed: Error %d\n",
+                              priv->net_dev->name, err);
+               else {
+                       set_current_state(TASK_UNINTERRUPTIBLE);
+                       schedule_timeout(HW_POWER_DOWN_DELAY);
+               }
+       }
+
+       priv->status &= ~STATUS_ENABLED;
+
+       /*
+        * Set GPIO 3 writable by FW; GPIO 1 writable
+        * by driver and enable clock
+        */
+       ipw2100_hw_set_gpio(priv);
+
+       /*
+        * Power down adapter.  Sequence:
+        * 1. Stop master assert (RESET_REG[9]=1)
+        * 2. Wait for stop master (RESET_REG[8]==1)
+        * 3. S/w reset assert (RESET_REG[7] = 1)
+        */
+
+       /* Stop master assert */
+       write_register(priv->net_dev, IPW_REG_RESET_REG,
+                      IPW_AUX_HOST_RESET_REG_STOP_MASTER);
+
+       /* wait stop master not more than 50 usec.
+        * Otherwise return error. */
+       for (i = 5; i > 0; i--) {
+               udelay(10);
+
+               /* Check master stop bit */
+               read_register(priv->net_dev, IPW_REG_RESET_REG, &reg);
+
+               if (reg & IPW_AUX_HOST_RESET_REG_MASTER_DISABLED)
+                       break;
+       }
+
+       if (i == 0)
+               IPW_DEBUG_WARNING(DRV_NAME
+                      ": %s: Could now power down adapter.\n",
+                      priv->net_dev->name);
+
+       /* assert s/w reset */
+       write_register(priv->net_dev, IPW_REG_RESET_REG,
+                      IPW_AUX_HOST_RESET_REG_SW_RESET);
+
+       priv->status &= ~(STATUS_RUNNING | STATUS_STOPPING);
+
+       return 0;
+}
+
+
+static int ipw2100_disable_adapter(struct ipw2100_priv *priv)
+{
+       struct host_command cmd = {
+               .host_command = CARD_DISABLE,
+               .host_command_sequence = 0,
+               .host_command_length = 0
+       };
+       int err = 0;
+
+       IPW_DEBUG_HC("CARD_DISABLE\n");
+
+       if (!(priv->status & STATUS_ENABLED))
+               return 0;
+
+       /* Make sure we clear the associated state */
+       priv->status &= ~(STATUS_ASSOCIATED | STATUS_ASSOCIATING);
+
+       if (!priv->stop_hang_check) {
+               priv->stop_hang_check = 1;
+               cancel_delayed_work(&priv->hang_check);
+       }
+
+       down(&priv->adapter_sem);
+
+       err = ipw2100_hw_send_command(priv, &cmd);
+       if (err) {
+               IPW_DEBUG_WARNING("exit - failed to send CARD_DISABLE command\n");
+               goto fail_up;
+       }
+
+       err = ipw2100_wait_for_card_state(priv, IPW_HW_STATE_DISABLED);
+       if (err) {
+               IPW_DEBUG_WARNING("exit - card failed to change to DISABLED\n");
+               goto fail_up;
+       }
+
+       IPW_DEBUG_INFO("TODO: implement scan state machine\n");
+
+fail_up:
+       up(&priv->adapter_sem);
+       return err;
+}
+
+int ipw2100_set_scan_options(struct ipw2100_priv *priv)
+{
+       struct host_command cmd = {
+               .host_command = SET_SCAN_OPTIONS,
+               .host_command_sequence = 0,
+               .host_command_length = 8
+       };
+       int err;
+
+       IPW_DEBUG_INFO("enter\n");
+
+       IPW_DEBUG_SCAN("setting scan options\n");
+
+       cmd.host_command_parameters[0] = 0;
+
+       if (!(priv->config & CFG_ASSOCIATE))
+               cmd.host_command_parameters[0] |= IPW_SCAN_NOASSOCIATE;
+       if ((priv->sec.flags & SEC_ENABLED) && priv->sec.enabled)
+               cmd.host_command_parameters[0] |= IPW_SCAN_MIXED_CELL;
+       if (priv->config & CFG_PASSIVE_SCAN)
+               cmd.host_command_parameters[0] |= IPW_SCAN_PASSIVE;
+
+       cmd.host_command_parameters[1] = priv->channel_mask;
+
+       err = ipw2100_hw_send_command(priv, &cmd);
+
+       IPW_DEBUG_HC("SET_SCAN_OPTIONS 0x%04X\n",
+                    cmd.host_command_parameters[0]);
+
+       return err;
+}
+
+int ipw2100_start_scan(struct ipw2100_priv *priv)
+{
+       struct host_command cmd = {
+               .host_command = BROADCAST_SCAN,
+               .host_command_sequence = 0,
+               .host_command_length = 4
+       };
+       int err;
+
+       IPW_DEBUG_HC("START_SCAN\n");
+
+       cmd.host_command_parameters[0] = 0;
+
+       /* No scanning if in monitor mode */
+       if (priv->ieee->iw_mode == IW_MODE_MONITOR)
+               return 1;
+
+       if (priv->status & STATUS_SCANNING) {
+               IPW_DEBUG_SCAN("Scan requested while already in scan...\n");
+               return 0;
+       }
+
+       IPW_DEBUG_INFO("enter\n");
+
+       /* Not clearing here; doing so makes iwlist always return nothing...
+        *
+        * We should modify the table logic to use aging tables vs. clearing
+        * the table on each scan start.
+        */
+       IPW_DEBUG_SCAN("starting scan\n");
+
+       priv->status |= STATUS_SCANNING;
+       err = ipw2100_hw_send_command(priv, &cmd);
+       if (err)
+               priv->status &= ~STATUS_SCANNING;
+
+       IPW_DEBUG_INFO("exit\n");
+
+       return err;
+}
+
+static int ipw2100_up(struct ipw2100_priv *priv, int deferred)
+{
+       unsigned long flags;
+       int rc = 0;
+       u32 lock;
+       u32 ord_len = sizeof(lock);
+
+       /* Quite if manually disabled. */
+       if (priv->status & STATUS_RF_KILL_SW) {
+               IPW_DEBUG_INFO("%s: Radio is disabled by Manual Disable "
+                              "switch\n", priv->net_dev->name);
+               return 0;
+       }
+
+       /* If the interrupt is enabled, turn it off... */
+       spin_lock_irqsave(&priv->low_lock, flags);
+       ipw2100_disable_interrupts(priv);
+
+       /* Reset any fatal_error conditions */
+       ipw2100_reset_fatalerror(priv);
+       spin_unlock_irqrestore(&priv->low_lock, flags);
+
+       if (priv->status & STATUS_POWERED ||
+           (priv->status & STATUS_RESET_PENDING)) {
+               /* Power cycle the card ... */
+               if (ipw2100_power_cycle_adapter(priv)) {
+                       IPW_DEBUG_WARNING("%s: Could not cycle adapter.\n",
+                                         priv->net_dev->name);
+                       rc = 1;
+                       goto exit;
+               }
+       } else
+               priv->status |= STATUS_POWERED;
+
+       /* Load the firmware, start the clocks, etc. */
+       if (ipw2100_start_adapter(priv)) {
+               IPW_DEBUG_ERROR("%s: Failed to start the firmware.\n",
+                               priv->net_dev->name);
+               rc = 1;
+               goto exit;
+       }
+
+       ipw2100_initialize_ordinals(priv);
+
+       /* Determine capabilities of this particular HW configuration */
+       if (ipw2100_get_hw_features(priv)) {
+               IPW_DEBUG_ERROR("%s: Failed to determine HW features.\n",
+                               priv->net_dev->name);
+               rc = 1;
+               goto exit;
+       }
+
+       lock = LOCK_NONE;
+       if (ipw2100_set_ordinal(priv, IPW_ORD_PERS_DB_LOCK, &lock, &ord_len)) {
+               IPW_DEBUG_ERROR("%s: Failed to clear ordinal lock.\n",
+                               priv->net_dev->name);
+               rc = 1;
+               goto exit;
+       }
+
+       priv->status &= ~STATUS_SCANNING;
+
+       if (rf_kill_active(priv)) {
+               printk(KERN_INFO "%s: Radio is disabled by RF switch.\n",
+                      priv->net_dev->name);
+
+               if (priv->stop_rf_kill) {
+                       priv->stop_rf_kill = 0;
+                       queue_delayed_work(priv->workqueue, &priv->rf_kill, HZ);
+               }
+
+               deferred = 1;
+       }
+
+       /* Turn on the interrupt so that commands can be processed */
+       ipw2100_enable_interrupts(priv);
+
+       /* Send all of the commands that must be sent prior to
+        * HOST_COMPLETE */
+       if (ipw2100_adapter_setup(priv)) {
+               IPW_DEBUG_ERROR("%s: Failed to start the card.\n",
+                               priv->net_dev->name);
+               rc = 1;
+               goto exit;
+       }
+
+       if (!deferred) {
+               /* Enable the adapter - sends HOST_COMPLETE */
+               if (ipw2100_enable_adapter(priv)) {
+                       IPW_DEBUG_ERROR(
+                               "%s: failed in call to enable adapter.\n",
+                               priv->net_dev->name);
+                       ipw2100_hw_stop_adapter(priv);
+                       rc = 1;
+                       goto exit;
+               }
+
+
+               /* Start a scan . . . */
+               ipw2100_set_scan_options(priv);
+               ipw2100_start_scan(priv);
+       }
+
+ exit:
+       return rc;
+}
+
+/* Called by register_netdev() */
+static int ipw2100_net_init(struct net_device *dev)
+{
+       struct ipw2100_priv *priv = ieee80211_priv(dev);
+       return ipw2100_up(priv, 1);
+}
+
+static void ipw2100_down(struct ipw2100_priv *priv)
+{
+       unsigned long flags;
+       union iwreq_data wrqu = {
+               .ap_addr = {
+                       .sa_family = ARPHRD_ETHER
+               }
+       };
+       int associated = priv->status & STATUS_ASSOCIATED;
+
+       /* Kill the RF switch timer */
+       if (!priv->stop_rf_kill) {
+               priv->stop_rf_kill = 1;
+               cancel_delayed_work(&priv->rf_kill);
+       }
+
+       /* Kill the firmare hang check timer */
+       if (!priv->stop_hang_check) {
+               priv->stop_hang_check = 1;
+               cancel_delayed_work(&priv->hang_check);
+       }
+
+       /* Kill any pending resets */
+       if (priv->status & STATUS_RESET_PENDING)
+               cancel_delayed_work(&priv->reset_work);
+
+       /* Make sure the interrupt is on so that FW commands will be
+        * processed correctly */
+       spin_lock_irqsave(&priv->low_lock, flags);
+       ipw2100_enable_interrupts(priv);
+       spin_unlock_irqrestore(&priv->low_lock, flags);
+
+       if (ipw2100_hw_stop_adapter(priv))
+               IPW_DEBUG_ERROR("%s: Error stopping adapter.\n",
+                      priv->net_dev->name);
+
+       /* Do not disable the interrupt until _after_ we disable
+        * the adaptor.  Otherwise the CARD_DISABLE command will never
+        * be ack'd by the firmware */
+       spin_lock_irqsave(&priv->low_lock, flags);
+       ipw2100_disable_interrupts(priv);
+       spin_unlock_irqrestore(&priv->low_lock, flags);
+
+#ifdef ACPI_CSTATE_LIMIT_DEFINED
+       if (priv->config & CFG_C3_DISABLED) {
+               IPW_DEBUG_INFO(DRV_NAME ": Resetting C3 transitions.\n");
+               acpi_set_cstate_limit(priv->cstate_limit);
+               priv->config &= ~CFG_C3_DISABLED;
+       }
+#endif
+
+       /* We have to signal any supplicant if we are disassociating */
+       if (associated)
+               wireless_send_event(priv->net_dev, SIOCGIWAP, &wrqu, NULL);
+
+       priv->status &= ~(STATUS_ASSOCIATED | STATUS_ASSOCIATING);
+       netif_carrier_off(priv->net_dev);
+       netif_stop_queue(priv->net_dev);
+}
+
+void ipw2100_reset_adapter(struct ipw2100_priv *priv)
+{
+       unsigned long flags;
+       union iwreq_data wrqu = {
+               .ap_addr = {
+                       .sa_family = ARPHRD_ETHER
+               }
+       };
+       int associated = priv->status & STATUS_ASSOCIATED;
+
+       spin_lock_irqsave(&priv->low_lock, flags);
+       IPW_DEBUG_INFO(DRV_NAME ": %s: Restarting adapter.\n",
+                      priv->net_dev->name);
+       priv->resets++;
+       priv->status &= ~(STATUS_ASSOCIATED | STATUS_ASSOCIATING);
+       priv->status |= STATUS_SECURITY_UPDATED;
+
+       /* Force a power cycle even if interface hasn't been opened
+        * yet */
+       cancel_delayed_work(&priv->reset_work);
+       priv->status |= STATUS_RESET_PENDING;
+       spin_unlock_irqrestore(&priv->low_lock, flags);
+
+       down(&priv->action_sem);
+       /* stop timed checks so that they don't interfere with reset */
+       priv->stop_hang_check = 1;
+       cancel_delayed_work(&priv->hang_check);
+
+       /* We have to signal any supplicant if we are disassociating */
+       if (associated)
+               wireless_send_event(priv->net_dev, SIOCGIWAP, &wrqu, NULL);
+
+       ipw2100_up(priv, 0);
+       up(&priv->action_sem);
+
+}
+
+
+static void isr_indicate_associated(struct ipw2100_priv *priv, u32 status)
+{
+
+#define MAC_ASSOCIATION_READ_DELAY (HZ)
+       int ret, len, essid_len;
+       char essid[IW_ESSID_MAX_SIZE];
+       u32 txrate;
+       u32 chan;
+       char *txratename;
+       u8 bssid[ETH_ALEN];
+
+       /*
+        * TBD: BSSID is usually 00:00:00:00:00:00 here and not
+        *      an actual MAC of the AP. Seems like FW sets this
+        *      address too late. Read it later and expose through
+        *      /proc or schedule a later task to query and update
+        */
+
+       essid_len = IW_ESSID_MAX_SIZE;
+       ret = ipw2100_get_ordinal(priv, IPW_ORD_STAT_ASSN_SSID,
+                                 essid, &essid_len);
+       if (ret) {
+               IPW_DEBUG_INFO("failed querying ordinals at line %d\n",
+                                  __LINE__);
+               return;
+       }
+
+       len = sizeof(u32);
+       ret = ipw2100_get_ordinal(priv, IPW_ORD_CURRENT_TX_RATE,
+                                 &txrate, &len);
+       if (ret) {
+               IPW_DEBUG_INFO("failed querying ordinals at line %d\n",
+                                  __LINE__);
+               return;
+       }
+
+       len = sizeof(u32);
+       ret = ipw2100_get_ordinal(priv, IPW_ORD_OUR_FREQ, &chan, &len);
+       if (ret) {
+               IPW_DEBUG_INFO("failed querying ordinals at line %d\n",
+                                  __LINE__);
+               return;
+       }
+       len = ETH_ALEN;
+        ipw2100_get_ordinal(priv, IPW_ORD_STAT_ASSN_AP_BSSID, &bssid,  &len);
+       if (ret) {
+               IPW_DEBUG_INFO("failed querying ordinals at line %d\n",
+                                  __LINE__);
+               return;
+       }
+       memcpy(priv->ieee->bssid, bssid, ETH_ALEN);
+
+
+       switch (txrate) {
+       case TX_RATE_1_MBIT:
+               txratename = "1Mbps";
+               break;
+       case TX_RATE_2_MBIT:
+               txratename = "2Mbsp";
+               break;
+       case TX_RATE_5_5_MBIT:
+               txratename = "5.5Mbps";
+               break;
+       case TX_RATE_11_MBIT:
+               txratename = "11Mbps";
+               break;
+       default:
+               IPW_DEBUG_INFO("Unknown rate: %d\n", txrate);
+               txratename = "unknown rate";
+               break;
+       }
+
+       IPW_DEBUG_INFO("%s: Associated with '%s' at %s, channel %d (BSSID="
+                      MAC_FMT ")\n",
+                      priv->net_dev->name, escape_essid(essid, essid_len),
+                      txratename, chan, MAC_ARG(bssid));
+
+       /* now we copy read ssid into dev */
+       if (!(priv->config & CFG_STATIC_ESSID)) {
+               priv->essid_len = min((u8)essid_len, (u8)IW_ESSID_MAX_SIZE);
+               memcpy(priv->essid, essid, priv->essid_len);
+       }
+       priv->channel = chan;
+       memcpy(priv->bssid, bssid, ETH_ALEN);
+
+       priv->status |= STATUS_ASSOCIATING;
+       priv->connect_start = get_seconds();
+
+       queue_delayed_work(priv->workqueue, &priv->wx_event_work, HZ / 10);
+}
+
+
+int ipw2100_set_essid(struct ipw2100_priv *priv, char *essid,
+                     int length, int batch_mode)
+{
+       int ssid_len = min(length, IW_ESSID_MAX_SIZE);
+       struct host_command cmd = {
+               .host_command = SSID,
+               .host_command_sequence = 0,
+               .host_command_length = ssid_len
+       };
+       int err;
+
+       IPW_DEBUG_HC("SSID: '%s'\n", escape_essid(essid, ssid_len));
+
+       if (ssid_len)
+               memcpy((char*)cmd.host_command_parameters,
+                      essid, ssid_len);
+
+       if (!batch_mode) {
+               err = ipw2100_disable_adapter(priv);
+               if (err)
+                       return err;
+       }
+
+       /* Bug in FW currently doesn't honor bit 0 in SET_SCAN_OPTIONS to
+        * disable auto association -- so we cheat by setting a bogus SSID */
+       if (!ssid_len && !(priv->config & CFG_ASSOCIATE)) {
+               int i;
+               u8 *bogus = (u8*)cmd.host_command_parameters;
+               for (i = 0; i < IW_ESSID_MAX_SIZE; i++)
+                       bogus[i] = 0x18 + i;
+               cmd.host_command_length = IW_ESSID_MAX_SIZE;
+       }
+
+       /* NOTE:  We always send the SSID command even if the provided ESSID is
+        * the same as what we currently think is set. */
+
+       err = ipw2100_hw_send_command(priv, &cmd);
+       if (!err) {
+               memset(priv->essid + ssid_len, 0,
+                      IW_ESSID_MAX_SIZE - ssid_len);
+               memcpy(priv->essid, essid, ssid_len);
+               priv->essid_len = ssid_len;
+       }
+
+       if (!batch_mode) {
+               if (ipw2100_enable_adapter(priv))
+                       err = -EIO;
+       }
+
+       return err;
+}
+
+static void isr_indicate_association_lost(struct ipw2100_priv *priv, u32 status)
+{
+       IPW_DEBUG(IPW_DL_NOTIF | IPW_DL_STATE | IPW_DL_ASSOC,
+                 "disassociated: '%s' " MAC_FMT " \n",
+                 escape_essid(priv->essid, priv->essid_len),
+                 MAC_ARG(priv->bssid));
+
+       priv->status &= ~(STATUS_ASSOCIATED | STATUS_ASSOCIATING);
+
+       if (priv->status & STATUS_STOPPING) {
+               IPW_DEBUG_INFO("Card is stopping itself, discard ASSN_LOST.\n");
+               return;
+       }
+
+       memset(priv->bssid, 0, ETH_ALEN);
+       memset(priv->ieee->bssid, 0, ETH_ALEN);
+
+       netif_carrier_off(priv->net_dev);
+       netif_stop_queue(priv->net_dev);
+
+       if (!(priv->status & STATUS_RUNNING))
+               return;
+
+       if (priv->status & STATUS_SECURITY_UPDATED)
+               queue_work(priv->workqueue, &priv->security_work);
+
+       queue_work(priv->workqueue, &priv->wx_event_work);
+}
+
+static void isr_indicate_rf_kill(struct ipw2100_priv *priv, u32 status)
+{
+       IPW_DEBUG_INFO("%s: RF Kill state changed to radio OFF.\n",
+              priv->net_dev->name);
+
+       /* RF_KILL is now enabled (else we wouldn't be here) */
+       priv->status |= STATUS_RF_KILL_HW;
+
+#ifdef ACPI_CSTATE_LIMIT_DEFINED
+       if (priv->config & CFG_C3_DISABLED) {
+               IPW_DEBUG_INFO(DRV_NAME ": Resetting C3 transitions.\n");
+               acpi_set_cstate_limit(priv->cstate_limit);
+               priv->config &= ~CFG_C3_DISABLED;
+       }
+#endif
+
+       /* Make sure the RF Kill check timer is running */
+       priv->stop_rf_kill = 0;
+       cancel_delayed_work(&priv->rf_kill);
+       queue_delayed_work(priv->workqueue, &priv->rf_kill, HZ);
+}
+
+static void isr_scan_complete(struct ipw2100_priv *priv, u32 status)
+{
+       IPW_DEBUG_SCAN("scan complete\n");
+       /* Age the scan results... */
+       priv->ieee->scans++;
+       priv->status &= ~STATUS_SCANNING;
+}
+
+#ifdef CONFIG_IPW_DEBUG
+#define IPW2100_HANDLER(v, f) { v, f, # v }
+struct ipw2100_status_indicator {
+       int status;
+       void (*cb)(struct ipw2100_priv *priv, u32 status);
+       char *name;
+};
+#else
+#define IPW2100_HANDLER(v, f) { v, f }
+struct ipw2100_status_indicator {
+       int status;
+       void (*cb)(struct ipw2100_priv *priv, u32 status);
+};
+#endif /* CONFIG_IPW_DEBUG */
+
+static void isr_indicate_scanning(struct ipw2100_priv *priv, u32 status)
+{
+       IPW_DEBUG_SCAN("Scanning...\n");
+       priv->status |= STATUS_SCANNING;
+}
+
+const struct ipw2100_status_indicator status_handlers[] = {
+       IPW2100_HANDLER(IPW_STATE_INITIALIZED, 0),
+       IPW2100_HANDLER(IPW_STATE_COUNTRY_FOUND, 0),
+       IPW2100_HANDLER(IPW_STATE_ASSOCIATED, isr_indicate_associated),
+       IPW2100_HANDLER(IPW_STATE_ASSN_LOST, isr_indicate_association_lost),
+       IPW2100_HANDLER(IPW_STATE_ASSN_CHANGED, 0),
+       IPW2100_HANDLER(IPW_STATE_SCAN_COMPLETE, isr_scan_complete),
+       IPW2100_HANDLER(IPW_STATE_ENTERED_PSP, 0),
+       IPW2100_HANDLER(IPW_STATE_LEFT_PSP, 0),
+       IPW2100_HANDLER(IPW_STATE_RF_KILL, isr_indicate_rf_kill),
+       IPW2100_HANDLER(IPW_STATE_DISABLED, 0),
+       IPW2100_HANDLER(IPW_STATE_POWER_DOWN, 0),
+       IPW2100_HANDLER(IPW_STATE_SCANNING, isr_indicate_scanning),
+       IPW2100_HANDLER(-1, 0)
+};
+
+
+static void isr_status_change(struct ipw2100_priv *priv, int status)
+{
+       int i;
+
+       if (status == IPW_STATE_SCANNING &&
+           priv->status & STATUS_ASSOCIATED &&
+           !(priv->status & STATUS_SCANNING)) {
+               IPW_DEBUG_INFO("Scan detected while associated, with "
+                              "no scan request.  Restarting firmware.\n");
+
+               /* Wake up any sleeping jobs */
+               schedule_reset(priv);
+       }
+
+       for (i = 0; status_handlers[i].status != -1; i++) {
+               if (status == status_handlers[i].status) {
+                       IPW_DEBUG_NOTIF("Status change: %s\n",
+                                        status_handlers[i].name);
+                       if (status_handlers[i].cb)
+                               status_handlers[i].cb(priv, status);
+                       priv->wstats.status = status;
+                       return;
+               }
+       }
+
+       IPW_DEBUG_NOTIF("unknown status received: %04x\n", status);
+}
+
+static void isr_rx_complete_command(
+       struct ipw2100_priv *priv,
+       struct ipw2100_cmd_header *cmd)
+{
+#ifdef CONFIG_IPW_DEBUG
+       if (cmd->host_command_reg < ARRAY_SIZE(command_types)) {
+               IPW_DEBUG_HC("Command completed '%s (%d)'\n",
+                            command_types[cmd->host_command_reg],
+                            cmd->host_command_reg);
+       }
+#endif
+       if (cmd->host_command_reg == HOST_COMPLETE)
+               priv->status |= STATUS_ENABLED;
+
+       if (cmd->host_command_reg == CARD_DISABLE)
+               priv->status &= ~STATUS_ENABLED;
+
+       priv->status &= ~STATUS_CMD_ACTIVE;
+
+       wake_up_interruptible(&priv->wait_command_queue);
+}
+
+#ifdef CONFIG_IPW_DEBUG
+const char *frame_types[] = {
+       "COMMAND_STATUS_VAL",
+       "STATUS_CHANGE_VAL",
+       "P80211_DATA_VAL",
+       "P8023_DATA_VAL",
+       "HOST_NOTIFICATION_VAL"
+};
+#endif
+
+
+static inline int ipw2100_alloc_skb(
+       struct ipw2100_priv *priv,
+       struct ipw2100_rx_packet *packet)
+{
+       packet->skb = dev_alloc_skb(sizeof(struct ipw2100_rx));
+       if (!packet->skb)
+               return -ENOMEM;
+
+       packet->rxp = (struct ipw2100_rx *)packet->skb->data;
+       packet->dma_addr = pci_map_single(priv->pci_dev, packet->skb->data,
+                                         sizeof(struct ipw2100_rx),
+                                         PCI_DMA_FROMDEVICE);
+       /* NOTE: pci_map_single does not return an error code, and 0 is a valid
+        *       dma_addr */
+
+       return 0;
+}
+
+
+#define SEARCH_ERROR   0xffffffff
+#define SEARCH_FAIL    0xfffffffe
+#define SEARCH_SUCCESS 0xfffffff0
+#define SEARCH_DISCARD 0
+#define SEARCH_SNAPSHOT 1
+
+#define SNAPSHOT_ADDR(ofs) (priv->snapshot[((ofs) >> 12) & 0xff] + ((ofs) & 0xfff))
+static inline int ipw2100_snapshot_alloc(struct ipw2100_priv *priv)
+{
+       int i;
+       if (priv->snapshot[0])
+               return 1;
+       for (i = 0; i < 0x30; i++) {
+               priv->snapshot[i] = (u8*)kmalloc(0x1000, GFP_ATOMIC);
+               if (!priv->snapshot[i]) {
+                       IPW_DEBUG_INFO("%s: Error allocating snapshot "
+                              "buffer %d\n", priv->net_dev->name, i);
+                       while (i > 0)
+                               kfree(priv->snapshot[--i]);
+                       priv->snapshot[0] = NULL;
+                       return 0;
+               }
+       }
+
+       return 1;
+}
+
+static inline void ipw2100_snapshot_free(struct ipw2100_priv *priv)
+{
+       int i;
+       if (!priv->snapshot[0])
+               return;
+       for (i = 0; i < 0x30; i++)
+               kfree(priv->snapshot[i]);
+       priv->snapshot[0] = NULL;
+}
+
+static inline u32 ipw2100_match_buf(struct ipw2100_priv *priv, u8 *in_buf,
+                                   size_t len, int mode)
+{
+       u32 i, j;
+       u32 tmp;
+       u8 *s, *d;
+       u32 ret;
+
+       s = in_buf;
+       if (mode == SEARCH_SNAPSHOT) {
+               if (!ipw2100_snapshot_alloc(priv))
+                       mode = SEARCH_DISCARD;
+       }
+
+       for (ret = SEARCH_FAIL, i = 0; i < 0x30000; i += 4) {
+               read_nic_dword(priv->net_dev, i, &tmp);
+               if (mode == SEARCH_SNAPSHOT)
+                       *(u32 *)SNAPSHOT_ADDR(i) = tmp;
+               if (ret == SEARCH_FAIL) {
+                       d = (u8*)&tmp;
+                       for (j = 0; j < 4; j++) {
+                               if (*s != *d) {
+                                       s = in_buf;
+                                       continue;
+                               }
+
+                               s++;
+                               d++;
+
+                               if ((s - in_buf) == len)
+                                       ret = (i + j) - len + 1;
+                       }
+               } else if (mode == SEARCH_DISCARD)
+                       return ret;
+       }
+
+       return ret;
+}
+
+/*
+ *
+ * 0) Disconnect the SKB from the firmware (just unmap)
+ * 1) Pack the ETH header into the SKB
+ * 2) Pass the SKB to the network stack
+ *
+ * When packet is provided by the firmware, it contains the following:
+ *
+ * .  ieee80211_hdr
+ * .  ieee80211_snap_hdr
+ *
+ * The size of the constructed ethernet
+ *
+ */
+#ifdef CONFIG_IPW2100_RX_DEBUG
+u8 packet_data[IPW_RX_NIC_BUFFER_LENGTH];
+#endif
+
+static inline void ipw2100_corruption_detected(struct ipw2100_priv *priv,
+                                              int i)
+{
+#ifdef CONFIG_IPW_DEBUG_C3
+       struct ipw2100_status *status = &priv->status_queue.drv[i];
+       u32 match, reg;
+       int j;
+#endif
+#ifdef ACPI_CSTATE_LIMIT_DEFINED
+       int limit;
+#endif
+
+       IPW_DEBUG_INFO(DRV_NAME ": PCI latency error detected at "
+                      "0x%04zX.\n", i * sizeof(struct ipw2100_status));
+
+#ifdef ACPI_CSTATE_LIMIT_DEFINED
+       IPW_DEBUG_INFO(DRV_NAME ": Disabling C3 transitions.\n");
+       limit = acpi_get_cstate_limit();
+       if (limit > 2) {
+               priv->cstate_limit = limit;
+               acpi_set_cstate_limit(2);
+               priv->config |= CFG_C3_DISABLED;
+       }
+#endif
+
+#ifdef CONFIG_IPW_DEBUG_C3
+       /* Halt the fimrware so we can get a good image */
+       write_register(priv->net_dev, IPW_REG_RESET_REG,
+                      IPW_AUX_HOST_RESET_REG_STOP_MASTER);
+       j = 5;
+       do {
+               udelay(IPW_WAIT_RESET_MASTER_ASSERT_COMPLETE_DELAY);
+               read_register(priv->net_dev, IPW_REG_RESET_REG, &reg);
+
+               if (reg & IPW_AUX_HOST_RESET_REG_MASTER_DISABLED)
+                       break;
+       }  while (j--);
+
+       match = ipw2100_match_buf(priv, (u8*)status,
+                                 sizeof(struct ipw2100_status),
+                                 SEARCH_SNAPSHOT);
+       if (match < SEARCH_SUCCESS)
+               IPW_DEBUG_INFO("%s: DMA status match in Firmware at "
+                              "offset 0x%06X, length %d:\n",
+                              priv->net_dev->name, match,
+                              sizeof(struct ipw2100_status));
+       else
+               IPW_DEBUG_INFO("%s: No DMA status match in "
+                              "Firmware.\n", priv->net_dev->name);
+
+       printk_buf((u8*)priv->status_queue.drv,
+                  sizeof(struct ipw2100_status) * RX_QUEUE_LENGTH);
+#endif
+
+       priv->fatal_error = IPW2100_ERR_C3_CORRUPTION;
+       priv->ieee->stats.rx_errors++;
+       schedule_reset(priv);
+}
+
+static inline void isr_rx(struct ipw2100_priv *priv, int i,
+                         struct ieee80211_rx_stats *stats)
+{
+       struct ipw2100_status *status = &priv->status_queue.drv[i];
+       struct ipw2100_rx_packet *packet = &priv->rx_buffers[i];
+
+       IPW_DEBUG_RX("Handler...\n");
+
+       if (unlikely(status->frame_size > skb_tailroom(packet->skb))) {
+               IPW_DEBUG_INFO("%s: frame_size (%u) > skb_tailroom (%u)!"
+                              "  Dropping.\n",
+                              priv->net_dev->name,
+                              status->frame_size, skb_tailroom(packet->skb));
+               priv->ieee->stats.rx_errors++;
+               return;
+       }
+
+       if (unlikely(!netif_running(priv->net_dev))) {
+               priv->ieee->stats.rx_errors++;
+               priv->wstats.discard.misc++;
+               IPW_DEBUG_DROP("Dropping packet while interface is not up.\n");
+               return;
+       }
+
+       if (unlikely(priv->ieee->iw_mode == IW_MODE_MONITOR &&
+                    status->flags & IPW_STATUS_FLAG_CRC_ERROR)) {
+               IPW_DEBUG_RX("CRC error in packet.  Dropping.\n");
+               priv->ieee->stats.rx_errors++;
+               return;
+       }
+
+       if (unlikely(priv->ieee->iw_mode != IW_MODE_MONITOR &&
+               !(priv->status & STATUS_ASSOCIATED))) {
+               IPW_DEBUG_DROP("Dropping packet while not associated.\n");
+               priv->wstats.discard.misc++;
+               return;
+       }
+
+
+       pci_unmap_single(priv->pci_dev,
+                        packet->dma_addr,
+                        sizeof(struct ipw2100_rx),
+                        PCI_DMA_FROMDEVICE);
+
+       skb_put(packet->skb, status->frame_size);
+
+#ifdef CONFIG_IPW2100_RX_DEBUG
+       /* Make a copy of the frame so we can dump it to the logs if
+        * ieee80211_rx fails */
+       memcpy(packet_data, packet->skb->data,
+              min_t(u32, status->frame_size, IPW_RX_NIC_BUFFER_LENGTH));
+#endif
+
+       if (!ieee80211_rx(priv->ieee, packet->skb, stats)) {
+#ifdef CONFIG_IPW2100_RX_DEBUG
+               IPW_DEBUG_DROP("%s: Non consumed packet:\n",
+                              priv->net_dev->name);
+               printk_buf(IPW_DL_DROP, packet_data, status->frame_size);
+#endif
+               priv->ieee->stats.rx_errors++;
+
+               /* ieee80211_rx failed, so it didn't free the SKB */
+               dev_kfree_skb_any(packet->skb);
+               packet->skb = NULL;
+       }
+
+       /* We need to allocate a new SKB and attach it to the RDB. */
+       if (unlikely(ipw2100_alloc_skb(priv, packet))) {
+               IPW_DEBUG_WARNING(
+                       "%s: Unable to allocate SKB onto RBD ring - disabling "
+                       "adapter.\n", priv->net_dev->name);
+               /* TODO: schedule adapter shutdown */
+               IPW_DEBUG_INFO("TODO: Shutdown adapter...\n");
+       }
+
+       /* Update the RDB entry */
+       priv->rx_queue.drv[i].host_addr = packet->dma_addr;
+}
+
+static inline int ipw2100_corruption_check(struct ipw2100_priv *priv, int i)
+{
+       struct ipw2100_status *status = &priv->status_queue.drv[i];
+       struct ipw2100_rx *u = priv->rx_buffers[i].rxp;
+       u16 frame_type = status->status_fields & STATUS_TYPE_MASK;
+
+       switch (frame_type) {
+       case COMMAND_STATUS_VAL:
+               return (status->frame_size != sizeof(u->rx_data.command));
+       case STATUS_CHANGE_VAL:
+               return (status->frame_size != sizeof(u->rx_data.status));
+       case HOST_NOTIFICATION_VAL:
+               return (status->frame_size < sizeof(u->rx_data.notification));
+       case P80211_DATA_VAL:
+       case P8023_DATA_VAL:
+#ifdef CONFIG_IPW2100_MONITOR
+               return 0;
+#else
+               switch (WLAN_FC_GET_TYPE(u->rx_data.header.frame_ctl)) {
+               case IEEE80211_FTYPE_MGMT:
+               case IEEE80211_FTYPE_CTL:
+                       return 0;
+               case IEEE80211_FTYPE_DATA:
+                       return (status->frame_size >
+                               IPW_MAX_802_11_PAYLOAD_LENGTH);
+               }
+#endif
+       }
+
+       return 1;
+}
+
+/*
+ * ipw2100 interrupts are disabled at this point, and the ISR
+ * is the only code that calls this method.  So, we do not need
+ * to play with any locks.
+ *
+ * RX Queue works as follows:
+ *
+ * Read index - firmware places packet in entry identified by the
+ *              Read index and advances Read index.  In this manner,
+ *              Read index will always point to the next packet to
+ *              be filled--but not yet valid.
+ *
+ * Write index - driver fills this entry with an unused RBD entry.
+ *               This entry has not filled by the firmware yet.
+ *
+ * In between the W and R indexes are the RBDs that have been received
+ * but not yet processed.
+ *
+ * The process of handling packets will start at WRITE + 1 and advance
+ * until it reaches the READ index.
+ *
+ * The WRITE index is cached in the variable 'priv->rx_queue.next'.
+ *
+ */
+static inline void __ipw2100_rx_process(struct ipw2100_priv *priv)
+{
+       struct ipw2100_bd_queue *rxq = &priv->rx_queue;
+       struct ipw2100_status_queue *sq = &priv->status_queue;
+       struct ipw2100_rx_packet *packet;
+       u16 frame_type;
+       u32 r, w, i, s;
+       struct ipw2100_rx *u;
+       struct ieee80211_rx_stats stats = {
+               .mac_time = jiffies,
+       };
+
+       read_register(priv->net_dev, IPW_MEM_HOST_SHARED_RX_READ_INDEX, &r);
+       read_register(priv->net_dev, IPW_MEM_HOST_SHARED_RX_WRITE_INDEX, &w);
+
+       if (r >= rxq->entries) {
+               IPW_DEBUG_RX("exit - bad read index\n");
+               return;
+       }
+
+       i = (rxq->next + 1) % rxq->entries;
+       s = i;
+       while (i != r) {
+               /* IPW_DEBUG_RX("r = %d : w = %d : processing = %d\n",
+                  r, rxq->next, i); */
+
+               packet = &priv->rx_buffers[i];
+
+               /* Sync the DMA for the STATUS buffer so CPU is sure to get
+                * the correct values */
+               pci_dma_sync_single_for_cpu(
+                       priv->pci_dev,
+                       sq->nic + sizeof(struct ipw2100_status) * i,
+                       sizeof(struct ipw2100_status),
+                       PCI_DMA_FROMDEVICE);
+
+               /* Sync the DMA for the RX buffer so CPU is sure to get
+                * the correct values */
+               pci_dma_sync_single_for_cpu(priv->pci_dev, packet->dma_addr,
+                                           sizeof(struct ipw2100_rx),
+                                           PCI_DMA_FROMDEVICE);
+
+               if (unlikely(ipw2100_corruption_check(priv, i))) {
+                       ipw2100_corruption_detected(priv, i);
+                       goto increment;
+               }
+
+               u = packet->rxp;
+               frame_type = sq->drv[i].status_fields &
+                       STATUS_TYPE_MASK;
+               stats.rssi = sq->drv[i].rssi + IPW2100_RSSI_TO_DBM;
+               stats.len = sq->drv[i].frame_size;
+
+               stats.mask = 0;
+               if (stats.rssi != 0)
+                       stats.mask |= IEEE80211_STATMASK_RSSI;
+               stats.freq = IEEE80211_24GHZ_BAND;
+
+               IPW_DEBUG_RX(
+                       "%s: '%s' frame type received (%d).\n",
+                       priv->net_dev->name, frame_types[frame_type],
+                       stats.len);
+
+               switch (frame_type) {
+               case COMMAND_STATUS_VAL:
+                       /* Reset Rx watchdog */
+                       isr_rx_complete_command(
+                               priv, &u->rx_data.command);
+                       break;
+
+               case STATUS_CHANGE_VAL:
+                       isr_status_change(priv, u->rx_data.status);
+                       break;
+
+               case P80211_DATA_VAL:
+               case P8023_DATA_VAL:
+#ifdef CONFIG_IPW2100_MONITOR
+                       if (priv->ieee->iw_mode == IW_MODE_MONITOR) {
+                               isr_rx(priv, i, &stats);
+                               break;
+                       }
+#endif
+                       if (stats.len < sizeof(u->rx_data.header))
+                               break;
+                       switch (WLAN_FC_GET_TYPE(u->rx_data.header.
+                                                frame_ctl)) {
+                       case IEEE80211_FTYPE_MGMT:
+                               ieee80211_rx_mgt(priv->ieee,
+                                                &u->rx_data.header,
+                                                &stats);
+                               break;
+
+                       case IEEE80211_FTYPE_CTL:
+                               break;
+
+                       case IEEE80211_FTYPE_DATA:
+                               isr_rx(priv, i, &stats);
+                               break;
+
+                       }
+                       break;
+               }
+
+       increment:
+               /* clear status field associated with this RBD */
+               rxq->drv[i].status.info.field = 0;
+
+               i = (i + 1) % rxq->entries;
+       }
+
+       if (i != s) {
+               /* backtrack one entry, wrapping to end if at 0 */
+               rxq->next = (i ? i : rxq->entries) - 1;
+
+               write_register(priv->net_dev,
+                              IPW_MEM_HOST_SHARED_RX_WRITE_INDEX,
+                              rxq->next);
+       }
+}
+
+
+/*
+ * __ipw2100_tx_process
+ *
+ * This routine will determine whether the next packet on
+ * the fw_pend_list has been processed by the firmware yet.
+ *
+ * If not, then it does nothing and returns.
+ *
+ * If so, then it removes the item from the fw_pend_list, frees
+ * any associated storage, and places the item back on the
+ * free list of its source (either msg_free_list or tx_free_list)
+ *
+ * TX Queue works as follows:
+ *
+ * Read index - points to the next TBD that the firmware will
+ *              process.  The firmware will read the data, and once
+ *              done processing, it will advance the Read index.
+ *
+ * Write index - driver fills this entry with an constructed TBD
+ *               entry.  The Write index is not advanced until the
+ *               packet has been configured.
+ *
+ * In between the W and R indexes are the TBDs that have NOT been
+ * processed.  Lagging behind the R index are packets that have
+ * been processed but have not been freed by the driver.
+ *
+ * In order to free old storage, an internal index will be maintained
+ * that points to the next packet to be freed.  When all used
+ * packets have been freed, the oldest index will be the same as the
+ * firmware's read index.
+ *
+ * The OLDEST index is cached in the variable 'priv->tx_queue.oldest'
+ *
+ * Because the TBD structure can not contain arbitrary data, the
+ * driver must keep an internal queue of cached allocations such that
+ * it can put that data back into the tx_free_list and msg_free_list
+ * for use by future command and data packets.
+ *
+ */
+static inline int __ipw2100_tx_process(struct ipw2100_priv *priv)
+{
+       struct ipw2100_bd_queue *txq = &priv->tx_queue;
+        struct ipw2100_bd *tbd;
+       struct list_head *element;
+       struct ipw2100_tx_packet *packet;
+       int descriptors_used;
+       int e, i;
+       u32 r, w, frag_num = 0;
+
+       if (list_empty(&priv->fw_pend_list))
+               return 0;
+
+       element = priv->fw_pend_list.next;
+
+       packet = list_entry(element, struct ipw2100_tx_packet, list);
+        tbd = &txq->drv[packet->index];
+
+       /* Determine how many TBD entries must be finished... */
+       switch (packet->type) {
+       case COMMAND:
+               /* COMMAND uses only one slot; don't advance */
+               descriptors_used = 1;
+               e = txq->oldest;
+               break;
+
+       case DATA:
+               /* DATA uses two slots; advance and loop position. */
+               descriptors_used = tbd->num_fragments;
+                frag_num = tbd->num_fragments - 1;
+               e = txq->oldest + frag_num;
+               e %= txq->entries;
+               break;
+
+       default:
+               IPW_DEBUG_WARNING("%s: Bad fw_pend_list entry!\n",
+                                  priv->net_dev->name);
+               return 0;
+       }
+
+       /* if the last TBD is not done by NIC yet, then packet is
+        * not ready to be released.
+        *
+        */
+       read_register(priv->net_dev, IPW_MEM_HOST_SHARED_TX_QUEUE_READ_INDEX,
+                     &r);
+       read_register(priv->net_dev, IPW_MEM_HOST_SHARED_TX_QUEUE_WRITE_INDEX,
+                     &w);
+       if (w != txq->next)
+               IPW_DEBUG_WARNING("%s: write index mismatch\n",
+                      priv->net_dev->name);
+
+        /*
+        * txq->next is the index of the last packet written txq->oldest is
+        * the index of the r is the index of the next packet to be read by
+        * firmware
+        */
+
+
+       /*
+        * Quick graphic to help you visualize the following
+        * if / else statement
+        *
+        * ===>|                     s---->|===============
+        *                               e>|
+        * | a | b | c | d | e | f | g | h | i | j | k | l
+        *       r---->|
+        *               w
+        *
+        * w - updated by driver
+        * r - updated by firmware
+        * s - start of oldest BD entry (txq->oldest)
+        * e - end of oldest BD entry
+        *
+        */
+       if (!((r <= w && (e < r || e >= w)) || (e < r && e >= w))) {
+               IPW_DEBUG_TX("exit - no processed packets ready to release.\n");
+               return 0;
+       }
+
+       list_del(element);
+       DEC_STAT(&priv->fw_pend_stat);
+
+#ifdef CONFIG_IPW_DEBUG
+       {
+               int i = txq->oldest;
+               IPW_DEBUG_TX(
+                       "TX%d V=%p P=%04X T=%04X L=%d\n", i,
+                       &txq->drv[i],
+                       (u32)(txq->nic + i * sizeof(struct ipw2100_bd)),
+                       txq->drv[i].host_addr,
+                       txq->drv[i].buf_length);
+
+               if (packet->type == DATA) {
+                       i = (i + 1) % txq->entries;
+
+                       IPW_DEBUG_TX(
+                               "TX%d V=%p P=%04X T=%04X L=%d\n", i,
+                               &txq->drv[i],
+                               (u32)(txq->nic + i *
+                               sizeof(struct ipw2100_bd)),
+                               (u32)txq->drv[i].host_addr,
+                               txq->drv[i].buf_length);
+               }
+       }
+#endif
+
+       switch (packet->type) {
+       case DATA:
+               if (txq->drv[txq->oldest].status.info.fields.txType != 0)
+                       IPW_DEBUG_WARNING("%s: Queue mismatch.  "
+                              "Expecting DATA TBD but pulled "
+                              "something else: ids %d=%d.\n",
+                              priv->net_dev->name, txq->oldest, packet->index);
+
+               /* DATA packet; we have to unmap and free the SKB */
+               priv->ieee->stats.tx_packets++;
+               for (i = 0; i < frag_num; i++) {
+                       tbd = &txq->drv[(packet->index + 1 + i) %
+                                       txq->entries];
+
+                       IPW_DEBUG_TX(
+                               "TX%d P=%08x L=%d\n",
+                               (packet->index + 1 + i) % txq->entries,
+                               tbd->host_addr, tbd->buf_length);
+
+                       pci_unmap_single(priv->pci_dev,
+                                        tbd->host_addr,
+                                        tbd->buf_length,
+                                        PCI_DMA_TODEVICE);
+               }
+
+               priv->ieee->stats.tx_bytes += packet->info.d_struct.txb->payload_size;
+               ieee80211_txb_free(packet->info.d_struct.txb);
+               packet->info.d_struct.txb = NULL;
+
+               list_add_tail(element, &priv->tx_free_list);
+               INC_STAT(&priv->tx_free_stat);
+
+               /* We have a free slot in the Tx queue, so wake up the
+                * transmit layer if it is stopped. */
+               if (priv->status & STATUS_ASSOCIATED &&
+                   netif_queue_stopped(priv->net_dev)) {
+                       IPW_DEBUG_INFO(KERN_INFO
+                                          "%s: Waking net queue.\n",
+                                          priv->net_dev->name);
+                       netif_wake_queue(priv->net_dev);
+               }
+
+               /* A packet was processed by the hardware, so update the
+                * watchdog */
+               priv->net_dev->trans_start = jiffies;
+
+          &