]> nv-tegra.nvidia Code Review - linux-2.6.git/commitdiff
sh: Add 32-bit opcode feature CPU flag.
authorPaul Mundt <lethal@linux-sh.org>
Tue, 8 May 2007 06:45:33 +0000 (15:45 +0900)
committerPaul Mundt <lethal@hera.kernel.org>
Wed, 9 May 2007 01:35:01 +0000 (01:35 +0000)
Add a CPU flag for the CPUs that support 32-bit opcodes, which
gets passed down to userspace.

Signed-off-by: Paul Mundt <lethal@linux-sh.org>
arch/sh/kernel/cpu/sh2a/probe.c
arch/sh/kernel/setup.c
include/asm-sh/cpu-features.h

index 426f6db01fc69d117621398e5be60f29a09f261a..f455c3509789b8ba5b4943e758b31b27d9626695 100644 (file)
@@ -18,6 +18,7 @@ int __init detect_cpu_and_cache_system(void)
 {
        /* Just SH7206 for now .. */
        current_cpu_data.type                   = CPU_SH7206;
 {
        /* Just SH7206 for now .. */
        current_cpu_data.type                   = CPU_SH7206;
+       current_cpu_data.flags                  |= CPU_HAS_OP32;
 
        current_cpu_data.dcache.ways            = 4;
        current_cpu_data.dcache.way_incr        = (1 << 11);
 
        current_cpu_data.dcache.ways            = 4;
        current_cpu_data.dcache.way_incr        = (1 << 11);
index 477d2a854fc4e4a59d0f83cec2341b8648b10fd1..c27729135935d77a8a4387fdb562e3bb86158357 100644 (file)
@@ -431,7 +431,7 @@ const char *get_cpu_subtype(struct sh_cpuinfo *c)
 /* Symbolic CPU flags, keep in sync with asm/cpu-features.h */
 static const char *cpu_flags[] = {
        "none", "fpu", "p2flush", "mmuassoc", "dsp", "perfctr",
 /* Symbolic CPU flags, keep in sync with asm/cpu-features.h */
 static const char *cpu_flags[] = {
        "none", "fpu", "p2flush", "mmuassoc", "dsp", "perfctr",
-       "ptea", "llsc", "l2", NULL
+       "ptea", "llsc", "l2", "op32", NULL
 };
 
 static void show_cpuflags(struct seq_file *m, struct sh_cpuinfo *c)
 };
 
 static void show_cpuflags(struct seq_file *m, struct sh_cpuinfo *c)
index 4bccd7c032f9c3d2320c8c7735b7fb5a0d02937b..86308aa3973180867a7b30a2f95e43f6137e54c2 100644 (file)
@@ -20,5 +20,6 @@
 #define CPU_HAS_PTEA           0x0020  /* PTEA register */
 #define CPU_HAS_LLSC           0x0040  /* movli.l/movco.l */
 #define CPU_HAS_L2_CACHE       0x0080  /* Secondary cache / URAM */
 #define CPU_HAS_PTEA           0x0020  /* PTEA register */
 #define CPU_HAS_LLSC           0x0040  /* movli.l/movco.l */
 #define CPU_HAS_L2_CACHE       0x0080  /* Secondary cache / URAM */
+#define CPU_HAS_OP32           0x0100  /* 32-bit instruction support */
 
 #endif /* __ASM_SH_CPU_FEATURES_H */
 
 #endif /* __ASM_SH_CPU_FEATURES_H */