]> nv-tegra.nvidia Code Review - linux-2.6.git/commit
i.MX31: Image Processing Unit DMA and IRQ drivers
authorGuennadi Liakhovetski <lg@denx.de>
Mon, 19 Jan 2009 22:36:21 +0000 (15:36 -0700)
committerDan Williams <dan.j.williams@intel.com>
Mon, 19 Jan 2009 22:36:21 +0000 (15:36 -0700)
commit5296b56d1b2000b60fb966be161c1f8fb629786b
tree18277748caa9ba43610f76a310d34a3b2155e1a5
parentef560682a97491f62ef538931a4861b57d66c52c
i.MX31: Image Processing Unit DMA and IRQ drivers

i.MX3x SoCs contain an Image Processing Unit, consisting of a Control
Module (CM), Display Interface (DI), Synchronous Display Controller (SDC),
Asynchronous Display Controller (ADC), Image Converter (IC), Post-Filter
(PF), Camera Sensor Interface (CSI), and an Image DMA Controller (IDMAC).
CM contains, among other blocks, an Interrupt Generator (IG) and a Clock
and Reset Control Unit (CRCU). This driver serves IDMAC and IG. They are
supported over dmaengine and irq-chip APIs respectively.

IDMAC is a specialised DMA controller, its DMA channels cannot be used for
general-purpose operations, even though it might be possible to configure
a memory-to-memory channel for memcpy operation. This driver will not work
with generic dmaengine clients, clients, wishing to use it must use
respective wrapper structures, they also must specify which channels they
require, as channels are hard-wired to specific IPU functions.

Acked-by: Sascha Hauer <s.hauer@pengutronix.de>
Signed-off-by: Guennadi Liakhovetski <lg@denx.de>
Signed-off-by: Dan Williams <dan.j.williams@intel.com>
arch/arm/plat-mxc/include/mach/ipu.h [new file with mode: 0644]
arch/arm/plat-mxc/include/mach/irqs.h
drivers/dma/Kconfig
drivers/dma/Makefile
drivers/dma/ipu/Makefile [new file with mode: 0644]
drivers/dma/ipu/ipu_idmac.c [new file with mode: 0644]
drivers/dma/ipu/ipu_intern.h [new file with mode: 0644]
drivers/dma/ipu/ipu_irq.c [new file with mode: 0644]