[XTENSA] Add support for cache-aliasing
[linux-2.6.git] / include / asm-xtensa / tlb.h
index 4562b2dcfbc068d25cd3021ee5267eedbf5a14ca..4830232017aff0766c99b83a7cc185acf473f919 100644 (file)
 #ifndef _XTENSA_TLB_H
 #define _XTENSA_TLB_H
 
-#define tlb_start_vma(tlb,vma)                 do { } while (0)
-#define tlb_end_vma(tlb,vma)                   do { } while (0)
-#define __tlb_remove_tlb_entry(tlb,pte,addr)   do { } while (0)
+#include <asm/cache.h>
+#include <asm/page.h>
+
+#if (DCACHE_WAY_SIZE <= PAGE_SIZE)
+
+/* Note, read http://lkml.org/lkml/2004/1/15/6 */
+
+# define tlb_start_vma(tlb,vma)                        do { } while (0)
+# define tlb_end_vma(tlb,vma)                  do { } while (0)
+
+#else
 
+# define tlb_start_vma(tlb, vma)                                             \
+       do {                                                                  \
+               if (!tlb->fullmm)                                             \
+                       flush_cache_range(vma, vma->vm_start, vma->vm_end);   \
+       } while(0)
+
+# define tlb_end_vma(tlb, vma)                                               \
+       do {                                                                  \
+               if (!tlb->fullmm)                                             \
+                       flush_tlb_range(vma, vma->vm_start, vma->vm_end);     \
+       } while(0)
+
+#endif
+
+#define __tlb_remove_tlb_entry(tlb,pte,addr)   do { } while (0)
 #define tlb_flush(tlb)                         flush_tlb_mm((tlb)->mm)
 
 #include <asm-generic/tlb.h>
-#include <asm/page.h>
 
 #define __pte_free_tlb(tlb,pte)                        pte_free(pte)