x86: remove pointless comments

[linux-2.6.git] / arch / ia64 / pci / pci.c

diff --git a/arch/ia64/pci/pci.c b/arch/ia64/pci/pci.c
index 07d0e92742c8ee604585a526668fd0f0baac8d60..53d0a8ee35d75cbdd252d4899403713db1846767 100644 (file)
--- a/arch/ia64/pci/pci.c
+++ b/arch/ia64/pci/pci.c
@@ -43,8 +43,7 @@
 #define PCI_SAL_EXT_ADDRESS(seg, bus, devfn, reg)      \
        (((u64) seg << 28) | (bus << 20) | (devfn << 12) | (reg))
 
-static int
-pci_sal_read (unsigned int seg, unsigned int bus, unsigned int devfn,
+int raw_pci_read(unsigned int seg, unsigned int bus, unsigned int devfn,
              int reg, int len, u32 *value)
 {
        u64 addr, data = 0;
@@ -68,8 +67,7 @@ pci_sal_read (unsigned int seg, unsigned int bus, unsigned int devfn,
        return 0;
 }
 
-static int
-pci_sal_write (unsigned int seg, unsigned int bus, unsigned int devfn,
+int raw_pci_write(unsigned int seg, unsigned int bus, unsigned int devfn,
               int reg, int len, u32 value)
 {
        u64 addr;
@@ -91,24 +89,17 @@ pci_sal_write (unsigned int seg, unsigned int bus, unsigned int devfn,
        return 0;
 }
 
-static struct pci_raw_ops pci_sal_ops = {
-       .read =         pci_sal_read,
-       .write =        pci_sal_write
-};
-
-struct pci_raw_ops *raw_pci_ops = &pci_sal_ops;
-
-static int
-pci_read (struct pci_bus *bus, unsigned int devfn, int where, int size, u32 *value)
+static int pci_read(struct pci_bus *bus, unsigned int devfn, int where,
+                                                       int size, u32 *value)
 {
-       return raw_pci_ops->read(pci_domain_nr(bus), bus->number,
+       return raw_pci_read(pci_domain_nr(bus), bus->number,
                                 devfn, where, size, value);
 }
 
-static int
-pci_write (struct pci_bus *bus, unsigned int devfn, int where, int size, u32 value)
+static int pci_write(struct pci_bus *bus, unsigned int devfn, int where,
+                                                       int size, u32 value)
 {
-       return raw_pci_ops->write(pci_domain_nr(bus), bus->number,
+       return raw_pci_write(pci_domain_nr(bus), bus->number,
                                  devfn, where, size, value);
 }
 
@@ -371,7 +362,12 @@ pci_acpi_scan_root(struct acpi_device *device, int domain, int bus)
        info.name = name;
        acpi_walk_resources(device->handle, METHOD_NAME__CRS, add_window,
                        &info);
-
+       /*
+        * See arch/x86/pci/acpi.c.
+        * The desired pci bus might already be scanned in a quirk. We
+        * should handle the case here, but it appears that IA64 hasn't
+        * such quirk. So we just ignore the case now.
+        */
        pbus = pci_scan_bus_parented(NULL, bus, &pci_root_ops, controller);
        if (pbus)
                pcibios_setup_root_windows(pbus, controller);
@@ -581,7 +577,7 @@ pcibios_align_resource (void *data, struct resource *res,
 /*
  * PCI BIOS setup, always defaults to SAL interface
  */
-char * __init
+char * __devinit
 pcibios_setup (char *str)
 {
        return str;
@@ -774,7 +770,7 @@ static void __init set_pci_cacheline_size(void)
        status = ia64_pal_cache_summary(&levels, &unique_caches);
        if (status != 0) {
                printk(KERN_ERR "%s: ia64_pal_cache_summary() failed "
-                       "(status=%ld)\n", __FUNCTION__, status);
+                       "(status=%ld)\n", __func__, status);
                return;
        }
 
@@ -782,7 +778,7 @@ static void __init set_pci_cacheline_size(void)
                                /* cache_type (data_or_unified)= */ 2, &cci);
        if (status != 0) {
                printk(KERN_ERR "%s: ia64_pal_cache_config_info() failed "
-                       "(status=%ld)\n", __FUNCTION__, status);
+                       "(status=%ld)\n", __func__, status);
                return;
        }
        pci_cache_line_size = (1 << cci.pcci_line_size) / 4;