Blackfin arch: push bf561 PERIPHERAL_MAP oddity into bf561-specific code

[linux-2.6.git] / arch / blackfin / mach-bf561 / include / mach / cdefBF561.h

diff --git a/arch/blackfin/mach-bf561/include/mach/cdefBF561.h b/arch/blackfin/mach-bf561/include/mach/cdefBF561.h
index c14d63402e70cc1d4851cea13a492873ae95c0eb..b16875d735b3405df77257399321d4c307ca737f 100644 (file)
--- a/arch/blackfin/mach-bf561/include/mach/cdefBF561.h
+++ b/arch/blackfin/mach-bf561/include/mach/cdefBF561.h
@@ -39,65 +39,15 @@
 /*include core specific register pointer definitions*/
 #include <asm/cdef_LPBlackfin.h>
 
-#include <asm/system.h>
-
 /*********************************************************************************** */
 /* System MMR Register Map */
 /*********************************************************************************** */
 
 /* Clock and System Control (0xFFC00000 - 0xFFC000FF) */
 #define bfin_read_PLL_CTL()                  bfin_read16(PLL_CTL)
-/* Writing to PLL_CTL initiates a PLL relock sequence. */
-static __inline__ void bfin_write_PLL_CTL(unsigned int val)
-{
-       unsigned long flags, iwr0, iwr1;
-
-       if (val == bfin_read_PLL_CTL())
-               return;
-
-       local_irq_save(flags);
-       /* Enable the PLL Wakeup bit in SIC IWR */
-       iwr0 = bfin_read32(SICA_IWR0);
-       iwr1 = bfin_read32(SICA_IWR1);
-       /* Only allow PPL Wakeup) */
-       bfin_write32(SICA_IWR0, IWR_ENABLE(0));
-       bfin_write32(SICA_IWR1, 0);
-
-       bfin_write16(PLL_CTL, val);
-       SSYNC();
-       asm("IDLE;");
-
-       bfin_write32(SICA_IWR0, iwr0);
-       bfin_write32(SICA_IWR1, iwr1);
-       local_irq_restore(flags);
-}
 #define bfin_read_PLL_DIV()                  bfin_read16(PLL_DIV)
 #define bfin_write_PLL_DIV(val)              bfin_write16(PLL_DIV,val)
 #define bfin_read_VR_CTL()                   bfin_read16(VR_CTL)
-/* Writing to VR_CTL initiates a PLL relock sequence. */
-static __inline__ void bfin_write_VR_CTL(unsigned int val)
-{
-       unsigned long flags, iwr0, iwr1;
-
-       if (val == bfin_read_VR_CTL())
-               return;
-
-       local_irq_save(flags);
-       /* Enable the PLL Wakeup bit in SIC IWR */
-       iwr0 = bfin_read32(SICA_IWR0);
-       iwr1 = bfin_read32(SICA_IWR1);
-       /* Only allow PPL Wakeup) */
-       bfin_write32(SICA_IWR0, IWR_ENABLE(0));
-       bfin_write32(SICA_IWR1, 0);
-
-       bfin_write16(VR_CTL, val);
-       SSYNC();
-       asm("IDLE;");
-
-       bfin_write32(SICA_IWR0, iwr0);
-       bfin_write32(SICA_IWR1, iwr1);
-       local_irq_restore(flags);
-}
 #define bfin_read_PLL_STAT()                 bfin_read16(PLL_STAT)
 #define bfin_write_PLL_STAT(val)             bfin_write16(PLL_STAT,val)
 #define bfin_read_PLL_LOCKCNT()              bfin_read16(PLL_LOCKCNT)
@@ -1576,4 +1526,57 @@ static __inline__ void bfin_write_VR_CTL(unsigned int val)
 #define bfin_read_MDMA_D0_START_ADDR()  bfin_read_MDMA1_D0_START_ADDR()
 #define bfin_write_MDMA_D0_START_ADDR(val) bfin_write_MDMA1_D0_START_ADDR(val)
 
+/* These need to be last due to the cdef/linux inter-dependencies */
+#include <asm/irq.h>
+
+/* Writing to PLL_CTL initiates a PLL relock sequence. */
+static __inline__ void bfin_write_PLL_CTL(unsigned int val)
+{
+       unsigned long flags, iwr0, iwr1;
+
+       if (val == bfin_read_PLL_CTL())
+               return;
+
+       local_irq_save(flags);
+       /* Enable the PLL Wakeup bit in SIC IWR */
+       iwr0 = bfin_read32(SICA_IWR0);
+       iwr1 = bfin_read32(SICA_IWR1);
+       /* Only allow PPL Wakeup) */
+       bfin_write32(SICA_IWR0, IWR_ENABLE(0));
+       bfin_write32(SICA_IWR1, 0);
+
+       bfin_write16(PLL_CTL, val);
+       SSYNC();
+       asm("IDLE;");
+
+       bfin_write32(SICA_IWR0, iwr0);
+       bfin_write32(SICA_IWR1, iwr1);
+       local_irq_restore(flags);
+}
+
+/* Writing to VR_CTL initiates a PLL relock sequence. */
+static __inline__ void bfin_write_VR_CTL(unsigned int val)
+{
+       unsigned long flags, iwr0, iwr1;
+
+       if (val == bfin_read_VR_CTL())
+               return;
+
+       local_irq_save(flags);
+       /* Enable the PLL Wakeup bit in SIC IWR */
+       iwr0 = bfin_read32(SICA_IWR0);
+       iwr1 = bfin_read32(SICA_IWR1);
+       /* Only allow PPL Wakeup) */
+       bfin_write32(SICA_IWR0, IWR_ENABLE(0));
+       bfin_write32(SICA_IWR1, 0);
+
+       bfin_write16(VR_CTL, val);
+       SSYNC();
+       asm("IDLE;");
+
+       bfin_write32(SICA_IWR0, iwr0);
+       bfin_write32(SICA_IWR1, iwr1);
+       local_irq_restore(flags);
+}
+
 #endif                         /* _CDEF_BF561_H */