KVM: bit ops for deliver_bitmap
[linux-2.6.git] / virt / kvm / ioapic.c
1 /*
2  *  Copyright (C) 2001  MandrakeSoft S.A.
3  *
4  *    MandrakeSoft S.A.
5  *    43, rue d'Aboukir
6  *    75002 Paris - France
7  *    http://www.linux-mandrake.com/
8  *    http://www.mandrakesoft.com/
9  *
10  *  This library is free software; you can redistribute it and/or
11  *  modify it under the terms of the GNU Lesser General Public
12  *  License as published by the Free Software Foundation; either
13  *  version 2 of the License, or (at your option) any later version.
14  *
15  *  This library is distributed in the hope that it will be useful,
16  *  but WITHOUT ANY WARRANTY; without even the implied warranty of
17  *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
18  *  Lesser General Public License for more details.
19  *
20  *  You should have received a copy of the GNU Lesser General Public
21  *  License along with this library; if not, write to the Free Software
22  *  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307 USA
23  *
24  *  Yunhong Jiang <yunhong.jiang@intel.com>
25  *  Yaozu (Eddie) Dong <eddie.dong@intel.com>
26  *  Based on Xen 3.1 code.
27  */
28
29 #include <linux/kvm_host.h>
30 #include <linux/kvm.h>
31 #include <linux/mm.h>
32 #include <linux/highmem.h>
33 #include <linux/smp.h>
34 #include <linux/hrtimer.h>
35 #include <linux/io.h>
36 #include <asm/processor.h>
37 #include <asm/page.h>
38 #include <asm/current.h>
39
40 #include "ioapic.h"
41 #include "lapic.h"
42 #include "irq.h"
43
44 #if 0
45 #define ioapic_debug(fmt,arg...) printk(KERN_WARNING fmt,##arg)
46 #else
47 #define ioapic_debug(fmt, arg...)
48 #endif
49 static int ioapic_deliver(struct kvm_ioapic *vioapic, int irq);
50
51 static unsigned long ioapic_read_indirect(struct kvm_ioapic *ioapic,
52                                           unsigned long addr,
53                                           unsigned long length)
54 {
55         unsigned long result = 0;
56
57         switch (ioapic->ioregsel) {
58         case IOAPIC_REG_VERSION:
59                 result = ((((IOAPIC_NUM_PINS - 1) & 0xff) << 16)
60                           | (IOAPIC_VERSION_ID & 0xff));
61                 break;
62
63         case IOAPIC_REG_APIC_ID:
64         case IOAPIC_REG_ARB_ID:
65                 result = ((ioapic->id & 0xf) << 24);
66                 break;
67
68         default:
69                 {
70                         u32 redir_index = (ioapic->ioregsel - 0x10) >> 1;
71                         u64 redir_content;
72
73                         ASSERT(redir_index < IOAPIC_NUM_PINS);
74
75                         redir_content = ioapic->redirtbl[redir_index].bits;
76                         result = (ioapic->ioregsel & 0x1) ?
77                             (redir_content >> 32) & 0xffffffff :
78                             redir_content & 0xffffffff;
79                         break;
80                 }
81         }
82
83         return result;
84 }
85
86 static int ioapic_service(struct kvm_ioapic *ioapic, unsigned int idx)
87 {
88         union kvm_ioapic_redirect_entry *pent;
89         int injected = -1;
90
91         pent = &ioapic->redirtbl[idx];
92
93         if (!pent->fields.mask) {
94                 injected = ioapic_deliver(ioapic, idx);
95                 if (injected && pent->fields.trig_mode == IOAPIC_LEVEL_TRIG)
96                         pent->fields.remote_irr = 1;
97         }
98         if (!pent->fields.trig_mode)
99                 ioapic->irr &= ~(1 << idx);
100
101         return injected;
102 }
103
104 static void ioapic_write_indirect(struct kvm_ioapic *ioapic, u32 val)
105 {
106         unsigned index;
107         bool mask_before, mask_after;
108
109         switch (ioapic->ioregsel) {
110         case IOAPIC_REG_VERSION:
111                 /* Writes are ignored. */
112                 break;
113
114         case IOAPIC_REG_APIC_ID:
115                 ioapic->id = (val >> 24) & 0xf;
116                 break;
117
118         case IOAPIC_REG_ARB_ID:
119                 break;
120
121         default:
122                 index = (ioapic->ioregsel - 0x10) >> 1;
123
124                 ioapic_debug("change redir index %x val %x\n", index, val);
125                 if (index >= IOAPIC_NUM_PINS)
126                         return;
127                 mask_before = ioapic->redirtbl[index].fields.mask;
128                 if (ioapic->ioregsel & 1) {
129                         ioapic->redirtbl[index].bits &= 0xffffffff;
130                         ioapic->redirtbl[index].bits |= (u64) val << 32;
131                 } else {
132                         ioapic->redirtbl[index].bits &= ~0xffffffffULL;
133                         ioapic->redirtbl[index].bits |= (u32) val;
134                         ioapic->redirtbl[index].fields.remote_irr = 0;
135                 }
136                 mask_after = ioapic->redirtbl[index].fields.mask;
137                 if (mask_before != mask_after)
138                         kvm_fire_mask_notifiers(ioapic->kvm, index, mask_after);
139                 if (ioapic->irr & (1 << index))
140                         ioapic_service(ioapic, index);
141                 break;
142         }
143 }
144
145 static int ioapic_inj_irq(struct kvm_ioapic *ioapic,
146                            struct kvm_vcpu *vcpu,
147                            u8 vector, u8 trig_mode, u8 delivery_mode)
148 {
149         ioapic_debug("irq %d trig %d deliv %d\n", vector, trig_mode,
150                      delivery_mode);
151
152         ASSERT((delivery_mode == IOAPIC_FIXED) ||
153                (delivery_mode == IOAPIC_LOWEST_PRIORITY));
154
155         return kvm_apic_set_irq(vcpu, vector, trig_mode);
156 }
157
158 static void ioapic_inj_nmi(struct kvm_vcpu *vcpu)
159 {
160         kvm_inject_nmi(vcpu);
161         kvm_vcpu_kick(vcpu);
162 }
163
164 void kvm_ioapic_get_delivery_bitmask(struct kvm_ioapic *ioapic, u8 dest,
165                                      u8 dest_mode, unsigned long *mask)
166 {
167         int i;
168         struct kvm *kvm = ioapic->kvm;
169         struct kvm_vcpu *vcpu;
170
171         ioapic_debug("dest %d dest_mode %d\n", dest, dest_mode);
172
173         *mask = 0;
174         if (dest_mode == 0) {   /* Physical mode. */
175                 if (dest == 0xFF) {     /* Broadcast. */
176                         for (i = 0; i < KVM_MAX_VCPUS; ++i)
177                                 if (kvm->vcpus[i] && kvm->vcpus[i]->arch.apic)
178                                         *mask |= 1 << i;
179                         return;
180                 }
181                 for (i = 0; i < KVM_MAX_VCPUS; ++i) {
182                         vcpu = kvm->vcpus[i];
183                         if (!vcpu)
184                                 continue;
185                         if (kvm_apic_match_physical_addr(vcpu->arch.apic, dest)) {
186                                 if (vcpu->arch.apic)
187                                         *mask = 1 << i;
188                                 break;
189                         }
190                 }
191         } else if (dest != 0)   /* Logical mode, MDA non-zero. */
192                 for (i = 0; i < KVM_MAX_VCPUS; ++i) {
193                         vcpu = kvm->vcpus[i];
194                         if (!vcpu)
195                                 continue;
196                         if (vcpu->arch.apic &&
197                             kvm_apic_match_logical_addr(vcpu->arch.apic, dest))
198                                 *mask |= 1 << vcpu->vcpu_id;
199                 }
200         ioapic_debug("mask %x\n", *mask);
201 }
202
203 static int ioapic_deliver(struct kvm_ioapic *ioapic, int irq)
204 {
205         union kvm_ioapic_redirect_entry entry = ioapic->redirtbl[irq];
206         DECLARE_BITMAP(deliver_bitmask, KVM_MAX_VCPUS);
207         struct kvm_vcpu *vcpu;
208         int vcpu_id, r = -1;
209
210         ioapic_debug("dest=%x dest_mode=%x delivery_mode=%x "
211                      "vector=%x trig_mode=%x\n",
212                      entry.fields.dest, entry.fields.dest_mode,
213                      entry.fields.delivery_mode, entry.fields.vector,
214                      entry.fields.trig_mode);
215
216         bitmap_zero(deliver_bitmask, KVM_MAX_VCPUS);
217
218         /* Always delivery PIT interrupt to vcpu 0 */
219 #ifdef CONFIG_X86
220         if (irq == 0)
221                 __set_bit(0, deliver_bitmask);
222         else
223 #endif
224                 kvm_get_intr_delivery_bitmask(ioapic, &entry, deliver_bitmask);
225
226         if (find_first_bit(deliver_bitmask, KVM_MAX_VCPUS) >= KVM_MAX_VCPUS) {
227                 ioapic_debug("no target on destination\n");
228                 return 0;
229         }
230
231         while ((vcpu_id = find_first_bit(deliver_bitmask, KVM_MAX_VCPUS))
232                         < KVM_MAX_VCPUS) {
233                 __clear_bit(vcpu_id, deliver_bitmask);
234                 vcpu = ioapic->kvm->vcpus[vcpu_id];
235                 if (vcpu) {
236                         if (entry.fields.delivery_mode ==
237                                         IOAPIC_LOWEST_PRIORITY ||
238                             entry.fields.delivery_mode == IOAPIC_FIXED) {
239                                 if (r < 0)
240                                         r = 0;
241                                 r += ioapic_inj_irq(ioapic, vcpu,
242                                                     entry.fields.vector,
243                                                     entry.fields.trig_mode,
244                                                     entry.fields.delivery_mode);
245                         } else if (entry.fields.delivery_mode == IOAPIC_NMI) {
246                                 r = 1;
247                                 ioapic_inj_nmi(vcpu);
248                         } else
249                                 ioapic_debug("unsupported delivery mode %x!\n",
250                                              entry.fields.delivery_mode);
251                 } else
252                         ioapic_debug("null destination vcpu: "
253                                      "mask=%x vector=%x delivery_mode=%x\n",
254                                      entry.fields.deliver_bitmask,
255                                      entry.fields.vector,
256                                      entry.fields.delivery_mode);
257         }
258         return r;
259 }
260
261 int kvm_ioapic_set_irq(struct kvm_ioapic *ioapic, int irq, int level)
262 {
263         u32 old_irr = ioapic->irr;
264         u32 mask = 1 << irq;
265         union kvm_ioapic_redirect_entry entry;
266         int ret = 1;
267
268         if (irq >= 0 && irq < IOAPIC_NUM_PINS) {
269                 entry = ioapic->redirtbl[irq];
270                 level ^= entry.fields.polarity;
271                 if (!level)
272                         ioapic->irr &= ~mask;
273                 else {
274                         ioapic->irr |= mask;
275                         if ((!entry.fields.trig_mode && old_irr != ioapic->irr)
276                             || !entry.fields.remote_irr)
277                                 ret = ioapic_service(ioapic, irq);
278                 }
279         }
280         return ret;
281 }
282
283 static void __kvm_ioapic_update_eoi(struct kvm_ioapic *ioapic, int pin,
284                                     int trigger_mode)
285 {
286         union kvm_ioapic_redirect_entry *ent;
287
288         ent = &ioapic->redirtbl[pin];
289
290         kvm_notify_acked_irq(ioapic->kvm, KVM_IRQCHIP_IOAPIC, pin);
291
292         if (trigger_mode == IOAPIC_LEVEL_TRIG) {
293                 ASSERT(ent->fields.trig_mode == IOAPIC_LEVEL_TRIG);
294                 ent->fields.remote_irr = 0;
295                 if (!ent->fields.mask && (ioapic->irr & (1 << pin)))
296                         ioapic_service(ioapic, pin);
297         }
298 }
299
300 void kvm_ioapic_update_eoi(struct kvm *kvm, int vector, int trigger_mode)
301 {
302         struct kvm_ioapic *ioapic = kvm->arch.vioapic;
303         int i;
304
305         for (i = 0; i < IOAPIC_NUM_PINS; i++)
306                 if (ioapic->redirtbl[i].fields.vector == vector)
307                         __kvm_ioapic_update_eoi(ioapic, i, trigger_mode);
308 }
309
310 static int ioapic_in_range(struct kvm_io_device *this, gpa_t addr,
311                            int len, int is_write)
312 {
313         struct kvm_ioapic *ioapic = (struct kvm_ioapic *)this->private;
314
315         return ((addr >= ioapic->base_address &&
316                  (addr < ioapic->base_address + IOAPIC_MEM_LENGTH)));
317 }
318
319 static void ioapic_mmio_read(struct kvm_io_device *this, gpa_t addr, int len,
320                              void *val)
321 {
322         struct kvm_ioapic *ioapic = (struct kvm_ioapic *)this->private;
323         u32 result;
324
325         ioapic_debug("addr %lx\n", (unsigned long)addr);
326         ASSERT(!(addr & 0xf));  /* check alignment */
327
328         addr &= 0xff;
329         switch (addr) {
330         case IOAPIC_REG_SELECT:
331                 result = ioapic->ioregsel;
332                 break;
333
334         case IOAPIC_REG_WINDOW:
335                 result = ioapic_read_indirect(ioapic, addr, len);
336                 break;
337
338         default:
339                 result = 0;
340                 break;
341         }
342         switch (len) {
343         case 8:
344                 *(u64 *) val = result;
345                 break;
346         case 1:
347         case 2:
348         case 4:
349                 memcpy(val, (char *)&result, len);
350                 break;
351         default:
352                 printk(KERN_WARNING "ioapic: wrong length %d\n", len);
353         }
354 }
355
356 static void ioapic_mmio_write(struct kvm_io_device *this, gpa_t addr, int len,
357                               const void *val)
358 {
359         struct kvm_ioapic *ioapic = (struct kvm_ioapic *)this->private;
360         u32 data;
361
362         ioapic_debug("ioapic_mmio_write addr=%p len=%d val=%p\n",
363                      (void*)addr, len, val);
364         ASSERT(!(addr & 0xf));  /* check alignment */
365         if (len == 4 || len == 8)
366                 data = *(u32 *) val;
367         else {
368                 printk(KERN_WARNING "ioapic: Unsupported size %d\n", len);
369                 return;
370         }
371
372         addr &= 0xff;
373         switch (addr) {
374         case IOAPIC_REG_SELECT:
375                 ioapic->ioregsel = data;
376                 break;
377
378         case IOAPIC_REG_WINDOW:
379                 ioapic_write_indirect(ioapic, data);
380                 break;
381 #ifdef  CONFIG_IA64
382         case IOAPIC_REG_EOI:
383                 kvm_ioapic_update_eoi(ioapic->kvm, data, IOAPIC_LEVEL_TRIG);
384                 break;
385 #endif
386
387         default:
388                 break;
389         }
390 }
391
392 void kvm_ioapic_reset(struct kvm_ioapic *ioapic)
393 {
394         int i;
395
396         for (i = 0; i < IOAPIC_NUM_PINS; i++)
397                 ioapic->redirtbl[i].fields.mask = 1;
398         ioapic->base_address = IOAPIC_DEFAULT_BASE_ADDRESS;
399         ioapic->ioregsel = 0;
400         ioapic->irr = 0;
401         ioapic->id = 0;
402 }
403
404 int kvm_ioapic_init(struct kvm *kvm)
405 {
406         struct kvm_ioapic *ioapic;
407
408         ioapic = kzalloc(sizeof(struct kvm_ioapic), GFP_KERNEL);
409         if (!ioapic)
410                 return -ENOMEM;
411         kvm->arch.vioapic = ioapic;
412         kvm_ioapic_reset(ioapic);
413         ioapic->dev.read = ioapic_mmio_read;
414         ioapic->dev.write = ioapic_mmio_write;
415         ioapic->dev.in_range = ioapic_in_range;
416         ioapic->dev.private = ioapic;
417         ioapic->kvm = kvm;
418         kvm_io_bus_register_dev(&kvm->mmio_bus, &ioapic->dev);
419         return 0;
420 }
421