ec5e18a78758346b9340946d30c15bbf9e498b39
[linux-2.6.git] / sound / soc / omap / omap-mcbsp.c
1 /*
2  * omap-mcbsp.c  --  OMAP ALSA SoC DAI driver using McBSP port
3  *
4  * Copyright (C) 2008 Nokia Corporation
5  *
6  * Contact: Jarkko Nikula <jarkko.nikula@nokia.com>
7  *
8  * This program is free software; you can redistribute it and/or
9  * modify it under the terms of the GNU General Public License
10  * version 2 as published by the Free Software Foundation.
11  *
12  * This program is distributed in the hope that it will be useful, but
13  * WITHOUT ANY WARRANTY; without even the implied warranty of
14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
15  * General Public License for more details.
16  *
17  * You should have received a copy of the GNU General Public License
18  * along with this program; if not, write to the Free Software
19  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
20  * 02110-1301 USA
21  *
22  */
23
24 #include <linux/init.h>
25 #include <linux/module.h>
26 #include <linux/device.h>
27 #include <sound/core.h>
28 #include <sound/pcm.h>
29 #include <sound/pcm_params.h>
30 #include <sound/initval.h>
31 #include <sound/soc.h>
32
33 #include <mach/control.h>
34 #include <mach/dma.h>
35 #include <mach/mcbsp.h>
36 #include "omap-mcbsp.h"
37 #include "omap-pcm.h"
38
39 #define OMAP_MCBSP_RATES        (SNDRV_PCM_RATE_8000_96000)
40
41 struct omap_mcbsp_data {
42         unsigned int                    bus_id;
43         struct omap_mcbsp_reg_cfg       regs;
44         unsigned int                    fmt;
45         /*
46          * Flags indicating is the bus already activated and configured by
47          * another substream
48          */
49         int                             active;
50         int                             configured;
51 };
52
53 #define to_mcbsp(priv)  container_of((priv), struct omap_mcbsp_data, bus_id)
54
55 static struct omap_mcbsp_data mcbsp_data[NUM_LINKS];
56
57 /*
58  * Stream DMA parameters. DMA request line and port address are set runtime
59  * since they are different between OMAP1 and later OMAPs
60  */
61 static struct omap_pcm_dma_data omap_mcbsp_dai_dma_params[NUM_LINKS][2];
62
63 #if defined(CONFIG_ARCH_OMAP15XX) || defined(CONFIG_ARCH_OMAP16XX)
64 static const int omap1_dma_reqs[][2] = {
65         { OMAP_DMA_MCBSP1_TX, OMAP_DMA_MCBSP1_RX },
66         { OMAP_DMA_MCBSP2_TX, OMAP_DMA_MCBSP2_RX },
67         { OMAP_DMA_MCBSP3_TX, OMAP_DMA_MCBSP3_RX },
68 };
69 static const unsigned long omap1_mcbsp_port[][2] = {
70         { OMAP1510_MCBSP1_BASE + OMAP_MCBSP_REG_DXR1,
71           OMAP1510_MCBSP1_BASE + OMAP_MCBSP_REG_DRR1 },
72         { OMAP1510_MCBSP2_BASE + OMAP_MCBSP_REG_DXR1,
73           OMAP1510_MCBSP2_BASE + OMAP_MCBSP_REG_DRR1 },
74         { OMAP1510_MCBSP3_BASE + OMAP_MCBSP_REG_DXR1,
75           OMAP1510_MCBSP3_BASE + OMAP_MCBSP_REG_DRR1 },
76 };
77 #else
78 static const int omap1_dma_reqs[][2] = {};
79 static const unsigned long omap1_mcbsp_port[][2] = {};
80 #endif
81
82 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
83 static const int omap24xx_dma_reqs[][2] = {
84         { OMAP24XX_DMA_MCBSP1_TX, OMAP24XX_DMA_MCBSP1_RX },
85         { OMAP24XX_DMA_MCBSP2_TX, OMAP24XX_DMA_MCBSP2_RX },
86 #if defined(CONFIG_ARCH_OMAP2430) || defined(CONFIG_ARCH_OMAP34XX)
87         { OMAP24XX_DMA_MCBSP3_TX, OMAP24XX_DMA_MCBSP3_RX },
88         { OMAP24XX_DMA_MCBSP4_TX, OMAP24XX_DMA_MCBSP4_RX },
89         { OMAP24XX_DMA_MCBSP5_TX, OMAP24XX_DMA_MCBSP5_RX },
90 #endif
91 };
92 #else
93 static const int omap24xx_dma_reqs[][2] = {};
94 #endif
95
96 #if defined(CONFIG_ARCH_OMAP2420)
97 static const unsigned long omap2420_mcbsp_port[][2] = {
98         { OMAP24XX_MCBSP1_BASE + OMAP_MCBSP_REG_DXR1,
99           OMAP24XX_MCBSP1_BASE + OMAP_MCBSP_REG_DRR1 },
100         { OMAP24XX_MCBSP2_BASE + OMAP_MCBSP_REG_DXR1,
101           OMAP24XX_MCBSP2_BASE + OMAP_MCBSP_REG_DRR1 },
102 };
103 #else
104 static const unsigned long omap2420_mcbsp_port[][2] = {};
105 #endif
106
107 #if defined(CONFIG_ARCH_OMAP2430)
108 static const unsigned long omap2430_mcbsp_port[][2] = {
109         { OMAP24XX_MCBSP1_BASE + OMAP_MCBSP_REG_DXR,
110           OMAP24XX_MCBSP1_BASE + OMAP_MCBSP_REG_DRR },
111         { OMAP24XX_MCBSP2_BASE + OMAP_MCBSP_REG_DXR,
112           OMAP24XX_MCBSP2_BASE + OMAP_MCBSP_REG_DRR },
113         { OMAP2430_MCBSP3_BASE + OMAP_MCBSP_REG_DXR,
114           OMAP2430_MCBSP3_BASE + OMAP_MCBSP_REG_DRR },
115         { OMAP2430_MCBSP4_BASE + OMAP_MCBSP_REG_DXR,
116           OMAP2430_MCBSP4_BASE + OMAP_MCBSP_REG_DRR },
117         { OMAP2430_MCBSP5_BASE + OMAP_MCBSP_REG_DXR,
118           OMAP2430_MCBSP5_BASE + OMAP_MCBSP_REG_DRR },
119 };
120 #else
121 static const unsigned long omap2430_mcbsp_port[][2] = {};
122 #endif
123
124 #if defined(CONFIG_ARCH_OMAP34XX)
125 static const unsigned long omap34xx_mcbsp_port[][2] = {
126         { OMAP34XX_MCBSP1_BASE + OMAP_MCBSP_REG_DXR,
127           OMAP34XX_MCBSP1_BASE + OMAP_MCBSP_REG_DRR },
128         { OMAP34XX_MCBSP2_BASE + OMAP_MCBSP_REG_DXR,
129           OMAP34XX_MCBSP2_BASE + OMAP_MCBSP_REG_DRR },
130         { OMAP34XX_MCBSP3_BASE + OMAP_MCBSP_REG_DXR,
131           OMAP34XX_MCBSP3_BASE + OMAP_MCBSP_REG_DRR },
132         { OMAP34XX_MCBSP4_BASE + OMAP_MCBSP_REG_DXR,
133           OMAP34XX_MCBSP4_BASE + OMAP_MCBSP_REG_DRR },
134         { OMAP34XX_MCBSP5_BASE + OMAP_MCBSP_REG_DXR,
135           OMAP34XX_MCBSP5_BASE + OMAP_MCBSP_REG_DRR },
136 };
137 #else
138 static const unsigned long omap34xx_mcbsp_port[][2] = {};
139 #endif
140
141 static int omap_mcbsp_dai_startup(struct snd_pcm_substream *substream,
142                                   struct snd_soc_dai *dai)
143 {
144         struct snd_soc_pcm_runtime *rtd = substream->private_data;
145         struct snd_soc_dai *cpu_dai = rtd->dai->cpu_dai;
146         struct omap_mcbsp_data *mcbsp_data = to_mcbsp(cpu_dai->private_data);
147         int err = 0;
148
149         if (!cpu_dai->active)
150                 err = omap_mcbsp_request(mcbsp_data->bus_id);
151
152         return err;
153 }
154
155 static void omap_mcbsp_dai_shutdown(struct snd_pcm_substream *substream,
156                                     struct snd_soc_dai *dai)
157 {
158         struct snd_soc_pcm_runtime *rtd = substream->private_data;
159         struct snd_soc_dai *cpu_dai = rtd->dai->cpu_dai;
160         struct omap_mcbsp_data *mcbsp_data = to_mcbsp(cpu_dai->private_data);
161
162         if (!cpu_dai->active) {
163                 omap_mcbsp_free(mcbsp_data->bus_id);
164                 mcbsp_data->configured = 0;
165         }
166 }
167
168 static int omap_mcbsp_dai_trigger(struct snd_pcm_substream *substream, int cmd,
169                                   struct snd_soc_dai *dai)
170 {
171         struct snd_soc_pcm_runtime *rtd = substream->private_data;
172         struct snd_soc_dai *cpu_dai = rtd->dai->cpu_dai;
173         struct omap_mcbsp_data *mcbsp_data = to_mcbsp(cpu_dai->private_data);
174         int err = 0;
175
176         switch (cmd) {
177         case SNDRV_PCM_TRIGGER_START:
178         case SNDRV_PCM_TRIGGER_RESUME:
179         case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
180                 if (!mcbsp_data->active++)
181                         omap_mcbsp_start(mcbsp_data->bus_id);
182                 break;
183
184         case SNDRV_PCM_TRIGGER_STOP:
185         case SNDRV_PCM_TRIGGER_SUSPEND:
186         case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
187                 if (!--mcbsp_data->active)
188                         omap_mcbsp_stop(mcbsp_data->bus_id);
189                 break;
190         default:
191                 err = -EINVAL;
192         }
193
194         return err;
195 }
196
197 static int omap_mcbsp_dai_hw_params(struct snd_pcm_substream *substream,
198                                     struct snd_pcm_hw_params *params,
199                                     struct snd_soc_dai *dai)
200 {
201         struct snd_soc_pcm_runtime *rtd = substream->private_data;
202         struct snd_soc_dai *cpu_dai = rtd->dai->cpu_dai;
203         struct omap_mcbsp_data *mcbsp_data = to_mcbsp(cpu_dai->private_data);
204         struct omap_mcbsp_reg_cfg *regs = &mcbsp_data->regs;
205         int dma, bus_id = mcbsp_data->bus_id, id = cpu_dai->id;
206         int wlen, channels;
207         unsigned long port;
208
209         if (cpu_class_is_omap1()) {
210                 dma = omap1_dma_reqs[bus_id][substream->stream];
211                 port = omap1_mcbsp_port[bus_id][substream->stream];
212         } else if (cpu_is_omap2420()) {
213                 dma = omap24xx_dma_reqs[bus_id][substream->stream];
214                 port = omap2420_mcbsp_port[bus_id][substream->stream];
215         } else if (cpu_is_omap2430()) {
216                 dma = omap24xx_dma_reqs[bus_id][substream->stream];
217                 port = omap2430_mcbsp_port[bus_id][substream->stream];
218         } else if (cpu_is_omap343x()) {
219                 dma = omap24xx_dma_reqs[bus_id][substream->stream];
220                 port = omap34xx_mcbsp_port[bus_id][substream->stream];
221         } else {
222                 return -ENODEV;
223         }
224         omap_mcbsp_dai_dma_params[id][substream->stream].name =
225                 substream->stream ? "Audio Capture" : "Audio Playback";
226         omap_mcbsp_dai_dma_params[id][substream->stream].dma_req = dma;
227         omap_mcbsp_dai_dma_params[id][substream->stream].port_addr = port;
228         cpu_dai->dma_data = &omap_mcbsp_dai_dma_params[id][substream->stream];
229
230         if (mcbsp_data->configured) {
231                 /* McBSP already configured by another stream */
232                 return 0;
233         }
234
235         channels = params_channels(params);
236         switch (channels) {
237         case 2:
238                 /* Use dual-phase frames */
239                 regs->rcr2      |= RPHASE;
240                 regs->xcr2      |= XPHASE;
241         case 1:
242                 /* Set 1 word per (McBSP) frame */
243                 regs->rcr2      |= RFRLEN2(1 - 1);
244                 regs->rcr1      |= RFRLEN1(1 - 1);
245                 regs->xcr2      |= XFRLEN2(1 - 1);
246                 regs->xcr1      |= XFRLEN1(1 - 1);
247                 break;
248         default:
249                 /* Unsupported number of channels */
250                 return -EINVAL;
251         }
252
253         switch (params_format(params)) {
254         case SNDRV_PCM_FORMAT_S16_LE:
255                 /* Set word lengths */
256                 wlen = 16;
257                 regs->rcr2      |= RWDLEN2(OMAP_MCBSP_WORD_16);
258                 regs->rcr1      |= RWDLEN1(OMAP_MCBSP_WORD_16);
259                 regs->xcr2      |= XWDLEN2(OMAP_MCBSP_WORD_16);
260                 regs->xcr1      |= XWDLEN1(OMAP_MCBSP_WORD_16);
261                 break;
262         default:
263                 /* Unsupported PCM format */
264                 return -EINVAL;
265         }
266
267         /* Set FS period and length in terms of bit clock periods */
268         switch (mcbsp_data->fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
269         case SND_SOC_DAIFMT_I2S:
270                 regs->srgr2     |= FPER(wlen * 2 - 1);
271                 regs->srgr1     |= FWID(wlen - 1);
272                 break;
273         case SND_SOC_DAIFMT_DSP_B:
274                 regs->srgr2     |= FPER(wlen * channels - 1);
275                 regs->srgr1     |= FWID(wlen * channels - 2);
276                 break;
277         }
278
279         omap_mcbsp_config(bus_id, &mcbsp_data->regs);
280         mcbsp_data->configured = 1;
281
282         return 0;
283 }
284
285 /*
286  * This must be called before _set_clkdiv and _set_sysclk since McBSP register
287  * cache is initialized here
288  */
289 static int omap_mcbsp_dai_set_dai_fmt(struct snd_soc_dai *cpu_dai,
290                                       unsigned int fmt)
291 {
292         struct omap_mcbsp_data *mcbsp_data = to_mcbsp(cpu_dai->private_data);
293         struct omap_mcbsp_reg_cfg *regs = &mcbsp_data->regs;
294
295         if (mcbsp_data->configured)
296                 return 0;
297
298         mcbsp_data->fmt = fmt;
299         memset(regs, 0, sizeof(*regs));
300         /* Generic McBSP register settings */
301         regs->spcr2     |= XINTM(3) | FREE;
302         regs->spcr1     |= RINTM(3);
303         regs->rcr2      |= RFIG;
304         regs->xcr2      |= XFIG;
305
306         switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
307         case SND_SOC_DAIFMT_I2S:
308                 /* 1-bit data delay */
309                 regs->rcr2      |= RDATDLY(1);
310                 regs->xcr2      |= XDATDLY(1);
311                 break;
312         case SND_SOC_DAIFMT_DSP_B:
313                 /* 0-bit data delay */
314                 regs->rcr2      |= RDATDLY(0);
315                 regs->xcr2      |= XDATDLY(0);
316                 break;
317         default:
318                 /* Unsupported data format */
319                 return -EINVAL;
320         }
321
322         switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
323         case SND_SOC_DAIFMT_CBS_CFS:
324                 /* McBSP master. Set FS and bit clocks as outputs */
325                 regs->pcr0      |= FSXM | FSRM |
326                                    CLKXM | CLKRM;
327                 /* Sample rate generator drives the FS */
328                 regs->srgr2     |= FSGM;
329                 break;
330         case SND_SOC_DAIFMT_CBM_CFM:
331                 /* McBSP slave */
332                 break;
333         default:
334                 /* Unsupported master/slave configuration */
335                 return -EINVAL;
336         }
337
338         /* Set bit clock (CLKX/CLKR) and FS polarities */
339         switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
340         case SND_SOC_DAIFMT_NB_NF:
341                 /*
342                  * Normal BCLK + FS.
343                  * FS active low. TX data driven on falling edge of bit clock
344                  * and RX data sampled on rising edge of bit clock.
345                  */
346                 regs->pcr0      |= FSXP | FSRP |
347                                    CLKXP | CLKRP;
348                 break;
349         case SND_SOC_DAIFMT_NB_IF:
350                 regs->pcr0      |= CLKXP | CLKRP;
351                 break;
352         case SND_SOC_DAIFMT_IB_NF:
353                 regs->pcr0      |= FSXP | FSRP;
354                 break;
355         case SND_SOC_DAIFMT_IB_IF:
356                 break;
357         default:
358                 return -EINVAL;
359         }
360
361         return 0;
362 }
363
364 static int omap_mcbsp_dai_set_clkdiv(struct snd_soc_dai *cpu_dai,
365                                      int div_id, int div)
366 {
367         struct omap_mcbsp_data *mcbsp_data = to_mcbsp(cpu_dai->private_data);
368         struct omap_mcbsp_reg_cfg *regs = &mcbsp_data->regs;
369
370         if (div_id != OMAP_MCBSP_CLKGDV)
371                 return -ENODEV;
372
373         regs->srgr1     |= CLKGDV(div - 1);
374
375         return 0;
376 }
377
378 static int omap_mcbsp_dai_set_clks_src(struct omap_mcbsp_data *mcbsp_data,
379                                        int clk_id)
380 {
381         int sel_bit;
382         u16 reg, reg_devconf1 = OMAP243X_CONTROL_DEVCONF1;
383
384         if (cpu_class_is_omap1()) {
385                 /* OMAP1's can use only external source clock */
386                 if (unlikely(clk_id == OMAP_MCBSP_SYSCLK_CLKS_FCLK))
387                         return -EINVAL;
388                 else
389                         return 0;
390         }
391
392         if (cpu_is_omap2420() && mcbsp_data->bus_id > 1)
393                 return -EINVAL;
394
395         if (cpu_is_omap343x())
396                 reg_devconf1 = OMAP343X_CONTROL_DEVCONF1;
397
398         switch (mcbsp_data->bus_id) {
399         case 0:
400                 reg = OMAP2_CONTROL_DEVCONF0;
401                 sel_bit = 2;
402                 break;
403         case 1:
404                 reg = OMAP2_CONTROL_DEVCONF0;
405                 sel_bit = 6;
406                 break;
407         case 2:
408                 reg = reg_devconf1;
409                 sel_bit = 0;
410                 break;
411         case 3:
412                 reg = reg_devconf1;
413                 sel_bit = 2;
414                 break;
415         case 4:
416                 reg = reg_devconf1;
417                 sel_bit = 4;
418                 break;
419         default:
420                 return -EINVAL;
421         }
422
423         if (clk_id == OMAP_MCBSP_SYSCLK_CLKS_FCLK)
424                 omap_ctrl_writel(omap_ctrl_readl(reg) & ~(1 << sel_bit), reg);
425         else
426                 omap_ctrl_writel(omap_ctrl_readl(reg) | (1 << sel_bit), reg);
427
428         return 0;
429 }
430
431 static int omap_mcbsp_dai_set_dai_sysclk(struct snd_soc_dai *cpu_dai,
432                                          int clk_id, unsigned int freq,
433                                          int dir)
434 {
435         struct omap_mcbsp_data *mcbsp_data = to_mcbsp(cpu_dai->private_data);
436         struct omap_mcbsp_reg_cfg *regs = &mcbsp_data->regs;
437         int err = 0;
438
439         switch (clk_id) {
440         case OMAP_MCBSP_SYSCLK_CLK:
441                 regs->srgr2     |= CLKSM;
442                 break;
443         case OMAP_MCBSP_SYSCLK_CLKS_FCLK:
444         case OMAP_MCBSP_SYSCLK_CLKS_EXT:
445                 err = omap_mcbsp_dai_set_clks_src(mcbsp_data, clk_id);
446                 break;
447
448         case OMAP_MCBSP_SYSCLK_CLKX_EXT:
449                 regs->srgr2     |= CLKSM;
450         case OMAP_MCBSP_SYSCLK_CLKR_EXT:
451                 regs->pcr0      |= SCLKME;
452                 break;
453         default:
454                 err = -ENODEV;
455         }
456
457         return err;
458 }
459
460 #define OMAP_MCBSP_DAI_BUILDER(link_id)                         \
461 {                                                               \
462         .name = "omap-mcbsp-dai-"#link_id,                      \
463         .id = (link_id),                                        \
464         .playback = {                                           \
465                 .channels_min = 1,                              \
466                 .channels_max = 2,                              \
467                 .rates = OMAP_MCBSP_RATES,                      \
468                 .formats = SNDRV_PCM_FMTBIT_S16_LE,             \
469         },                                                      \
470         .capture = {                                            \
471                 .channels_min = 1,                              \
472                 .channels_max = 2,                              \
473                 .rates = OMAP_MCBSP_RATES,                      \
474                 .formats = SNDRV_PCM_FMTBIT_S16_LE,             \
475         },                                                      \
476         .ops = {                                                \
477                 .startup = omap_mcbsp_dai_startup,              \
478                 .shutdown = omap_mcbsp_dai_shutdown,            \
479                 .trigger = omap_mcbsp_dai_trigger,              \
480                 .hw_params = omap_mcbsp_dai_hw_params,          \
481                 .set_fmt = omap_mcbsp_dai_set_dai_fmt,          \
482                 .set_clkdiv = omap_mcbsp_dai_set_clkdiv,        \
483                 .set_sysclk = omap_mcbsp_dai_set_dai_sysclk,    \
484         },                                                      \
485         .private_data = &mcbsp_data[(link_id)].bus_id,          \
486 }
487
488 struct snd_soc_dai omap_mcbsp_dai[] = {
489         OMAP_MCBSP_DAI_BUILDER(0),
490         OMAP_MCBSP_DAI_BUILDER(1),
491 #if NUM_LINKS >= 3
492         OMAP_MCBSP_DAI_BUILDER(2),
493 #endif
494 #if NUM_LINKS == 5
495         OMAP_MCBSP_DAI_BUILDER(3),
496         OMAP_MCBSP_DAI_BUILDER(4),
497 #endif
498 };
499
500 EXPORT_SYMBOL_GPL(omap_mcbsp_dai);
501
502 static int __init snd_omap_mcbsp_init(void)
503 {
504         return snd_soc_register_dais(omap_mcbsp_dai,
505                                      ARRAY_SIZE(omap_mcbsp_dai));
506 }
507 module_init(snd_omap_mcbsp_init);
508
509 static void __exit snd_omap_mcbsp_exit(void)
510 {
511         snd_soc_unregister_dais(omap_mcbsp_dai, ARRAY_SIZE(omap_mcbsp_dai));
512 }
513 module_exit(snd_omap_mcbsp_exit);
514
515 MODULE_AUTHOR("Jarkko Nikula <jarkko.nikula@nokia.com>");
516 MODULE_DESCRIPTION("OMAP I2S SoC Interface");
517 MODULE_LICENSE("GPL");