d32eb4703cfe533ee6b21a05fc5536084421b665
[linux-2.6.git] / sound / soc / omap / omap-mcbsp.c
1 /*
2  * omap-mcbsp.c  --  OMAP ALSA SoC DAI driver using McBSP port
3  *
4  * Copyright (C) 2008 Nokia Corporation
5  *
6  * Contact: Jarkko Nikula <jarkko.nikula@nokia.com>
7  *
8  * This program is free software; you can redistribute it and/or
9  * modify it under the terms of the GNU General Public License
10  * version 2 as published by the Free Software Foundation.
11  *
12  * This program is distributed in the hope that it will be useful, but
13  * WITHOUT ANY WARRANTY; without even the implied warranty of
14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
15  * General Public License for more details.
16  *
17  * You should have received a copy of the GNU General Public License
18  * along with this program; if not, write to the Free Software
19  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
20  * 02110-1301 USA
21  *
22  */
23
24 #include <linux/init.h>
25 #include <linux/module.h>
26 #include <linux/device.h>
27 #include <sound/core.h>
28 #include <sound/pcm.h>
29 #include <sound/pcm_params.h>
30 #include <sound/initval.h>
31 #include <sound/soc.h>
32
33 #include <mach/control.h>
34 #include <mach/dma.h>
35 #include <mach/mcbsp.h>
36 #include "omap-mcbsp.h"
37 #include "omap-pcm.h"
38
39 #define OMAP_MCBSP_RATES        (SNDRV_PCM_RATE_44100 | \
40                                  SNDRV_PCM_RATE_48000 | \
41                                  SNDRV_PCM_RATE_KNOT)
42
43 struct omap_mcbsp_data {
44         unsigned int                    bus_id;
45         struct omap_mcbsp_reg_cfg       regs;
46         /*
47          * Flags indicating is the bus already activated and configured by
48          * another substream
49          */
50         int                             active;
51         int                             configured;
52 };
53
54 #define to_mcbsp(priv)  container_of((priv), struct omap_mcbsp_data, bus_id)
55
56 static struct omap_mcbsp_data mcbsp_data[NUM_LINKS];
57
58 /*
59  * Stream DMA parameters. DMA request line and port address are set runtime
60  * since they are different between OMAP1 and later OMAPs
61  */
62 static struct omap_pcm_dma_data omap_mcbsp_dai_dma_params[NUM_LINKS][2] = {
63 {
64         { .name         = "I2S PCM Stereo out", },
65         { .name         = "I2S PCM Stereo in", },
66 },
67 };
68
69 #if defined(CONFIG_ARCH_OMAP15XX) || defined(CONFIG_ARCH_OMAP16XX)
70 static const int omap1_dma_reqs[][2] = {
71         { OMAP_DMA_MCBSP1_TX, OMAP_DMA_MCBSP1_RX },
72         { OMAP_DMA_MCBSP2_TX, OMAP_DMA_MCBSP2_RX },
73         { OMAP_DMA_MCBSP3_TX, OMAP_DMA_MCBSP3_RX },
74 };
75 static const unsigned long omap1_mcbsp_port[][2] = {
76         { OMAP1510_MCBSP1_BASE + OMAP_MCBSP_REG_DXR1,
77           OMAP1510_MCBSP1_BASE + OMAP_MCBSP_REG_DRR1 },
78         { OMAP1510_MCBSP2_BASE + OMAP_MCBSP_REG_DXR1,
79           OMAP1510_MCBSP2_BASE + OMAP_MCBSP_REG_DRR1 },
80         { OMAP1510_MCBSP3_BASE + OMAP_MCBSP_REG_DXR1,
81           OMAP1510_MCBSP3_BASE + OMAP_MCBSP_REG_DRR1 },
82 };
83 #else
84 static const int omap1_dma_reqs[][2] = {};
85 static const unsigned long omap1_mcbsp_port[][2] = {};
86 #endif
87 #if defined(CONFIG_ARCH_OMAP2420)
88 static const int omap2420_dma_reqs[][2] = {
89         { OMAP24XX_DMA_MCBSP1_TX, OMAP24XX_DMA_MCBSP1_RX },
90         { OMAP24XX_DMA_MCBSP2_TX, OMAP24XX_DMA_MCBSP2_RX },
91 };
92 static const unsigned long omap2420_mcbsp_port[][2] = {
93         { OMAP24XX_MCBSP1_BASE + OMAP_MCBSP_REG_DXR1,
94           OMAP24XX_MCBSP1_BASE + OMAP_MCBSP_REG_DRR1 },
95         { OMAP24XX_MCBSP2_BASE + OMAP_MCBSP_REG_DXR1,
96           OMAP24XX_MCBSP2_BASE + OMAP_MCBSP_REG_DRR1 },
97 };
98 #else
99 static const int omap2420_dma_reqs[][2] = {};
100 static const unsigned long omap2420_mcbsp_port[][2] = {};
101 #endif
102
103 static int omap_mcbsp_dai_startup(struct snd_pcm_substream *substream)
104 {
105         struct snd_soc_pcm_runtime *rtd = substream->private_data;
106         struct snd_soc_dai *cpu_dai = rtd->dai->cpu_dai;
107         struct omap_mcbsp_data *mcbsp_data = to_mcbsp(cpu_dai->private_data);
108         int err = 0;
109
110         if (!cpu_dai->active)
111                 err = omap_mcbsp_request(mcbsp_data->bus_id);
112
113         return err;
114 }
115
116 static void omap_mcbsp_dai_shutdown(struct snd_pcm_substream *substream)
117 {
118         struct snd_soc_pcm_runtime *rtd = substream->private_data;
119         struct snd_soc_dai *cpu_dai = rtd->dai->cpu_dai;
120         struct omap_mcbsp_data *mcbsp_data = to_mcbsp(cpu_dai->private_data);
121
122         if (!cpu_dai->active) {
123                 omap_mcbsp_free(mcbsp_data->bus_id);
124                 mcbsp_data->configured = 0;
125         }
126 }
127
128 static int omap_mcbsp_dai_trigger(struct snd_pcm_substream *substream, int cmd)
129 {
130         struct snd_soc_pcm_runtime *rtd = substream->private_data;
131         struct snd_soc_dai *cpu_dai = rtd->dai->cpu_dai;
132         struct omap_mcbsp_data *mcbsp_data = to_mcbsp(cpu_dai->private_data);
133         int err = 0;
134
135         switch (cmd) {
136         case SNDRV_PCM_TRIGGER_START:
137         case SNDRV_PCM_TRIGGER_RESUME:
138         case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
139                 if (!mcbsp_data->active++)
140                         omap_mcbsp_start(mcbsp_data->bus_id);
141                 break;
142
143         case SNDRV_PCM_TRIGGER_STOP:
144         case SNDRV_PCM_TRIGGER_SUSPEND:
145         case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
146                 if (!--mcbsp_data->active)
147                         omap_mcbsp_stop(mcbsp_data->bus_id);
148                 break;
149         default:
150                 err = -EINVAL;
151         }
152
153         return err;
154 }
155
156 static int omap_mcbsp_dai_hw_params(struct snd_pcm_substream *substream,
157                                     struct snd_pcm_hw_params *params)
158 {
159         struct snd_soc_pcm_runtime *rtd = substream->private_data;
160         struct snd_soc_dai *cpu_dai = rtd->dai->cpu_dai;
161         struct omap_mcbsp_data *mcbsp_data = to_mcbsp(cpu_dai->private_data);
162         struct omap_mcbsp_reg_cfg *regs = &mcbsp_data->regs;
163         int dma, bus_id = mcbsp_data->bus_id, id = cpu_dai->id;
164         unsigned long port;
165
166         if (cpu_class_is_omap1()) {
167                 dma = omap1_dma_reqs[bus_id][substream->stream];
168                 port = omap1_mcbsp_port[bus_id][substream->stream];
169         } else if (cpu_is_omap2420()) {
170                 dma = omap2420_dma_reqs[bus_id][substream->stream];
171                 port = omap2420_mcbsp_port[bus_id][substream->stream];
172         } else {
173                 /*
174                  * TODO: Add support for 2430 and 3430
175                  */
176                 return -ENODEV;
177         }
178         omap_mcbsp_dai_dma_params[id][substream->stream].dma_req = dma;
179         omap_mcbsp_dai_dma_params[id][substream->stream].port_addr = port;
180         cpu_dai->dma_data = &omap_mcbsp_dai_dma_params[id][substream->stream];
181
182         if (mcbsp_data->configured) {
183                 /* McBSP already configured by another stream */
184                 return 0;
185         }
186
187         switch (params_channels(params)) {
188         case 2:
189                 /* Set 1 word per (McBPSP) frame and use dual-phase frames */
190                 regs->rcr2      |= RFRLEN2(1 - 1) | RPHASE;
191                 regs->rcr1      |= RFRLEN1(1 - 1);
192                 regs->xcr2      |= XFRLEN2(1 - 1) | XPHASE;
193                 regs->xcr1      |= XFRLEN1(1 - 1);
194                 break;
195         default:
196                 /* Unsupported number of channels */
197                 return -EINVAL;
198         }
199
200         switch (params_format(params)) {
201         case SNDRV_PCM_FORMAT_S16_LE:
202                 /* Set word lengths */
203                 regs->rcr2      |= RWDLEN2(OMAP_MCBSP_WORD_16);
204                 regs->rcr1      |= RWDLEN1(OMAP_MCBSP_WORD_16);
205                 regs->xcr2      |= XWDLEN2(OMAP_MCBSP_WORD_16);
206                 regs->xcr1      |= XWDLEN1(OMAP_MCBSP_WORD_16);
207                 /* Set FS period and length in terms of bit clock periods */
208                 regs->srgr2     |= FPER(16 * 2 - 1);
209                 regs->srgr1     |= FWID(16 - 1);
210                 break;
211         default:
212                 /* Unsupported PCM format */
213                 return -EINVAL;
214         }
215
216         omap_mcbsp_config(bus_id, &mcbsp_data->regs);
217         mcbsp_data->configured = 1;
218
219         return 0;
220 }
221
222 /*
223  * This must be called before _set_clkdiv and _set_sysclk since McBSP register
224  * cache is initialized here
225  */
226 static int omap_mcbsp_dai_set_dai_fmt(struct snd_soc_dai *cpu_dai,
227                                       unsigned int fmt)
228 {
229         struct omap_mcbsp_data *mcbsp_data = to_mcbsp(cpu_dai->private_data);
230         struct omap_mcbsp_reg_cfg *regs = &mcbsp_data->regs;
231
232         if (mcbsp_data->configured)
233                 return 0;
234
235         memset(regs, 0, sizeof(*regs));
236         /* Generic McBSP register settings */
237         regs->spcr2     |= XINTM(3) | FREE;
238         regs->spcr1     |= RINTM(3);
239         regs->rcr2      |= RFIG;
240         regs->xcr2      |= XFIG;
241
242         switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
243         case SND_SOC_DAIFMT_I2S:
244                 /* 1-bit data delay */
245                 regs->rcr2      |= RDATDLY(1);
246                 regs->xcr2      |= XDATDLY(1);
247                 break;
248         case SND_SOC_DAIFMT_DSP_A:
249                 /* 0-bit data delay */
250                 regs->rcr2      |= RDATDLY(0);
251                 regs->xcr2      |= XDATDLY(0);
252                 break;
253         default:
254                 /* Unsupported data format */
255                 return -EINVAL;
256         }
257
258         switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
259         case SND_SOC_DAIFMT_CBS_CFS:
260                 /* McBSP master. Set FS and bit clocks as outputs */
261                 regs->pcr0      |= FSXM | FSRM |
262                                    CLKXM | CLKRM;
263                 /* Sample rate generator drives the FS */
264                 regs->srgr2     |= FSGM;
265                 break;
266         case SND_SOC_DAIFMT_CBM_CFM:
267                 /* McBSP slave */
268                 break;
269         default:
270                 /* Unsupported master/slave configuration */
271                 return -EINVAL;
272         }
273
274         /* Set bit clock (CLKX/CLKR) and FS polarities */
275         switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
276         case SND_SOC_DAIFMT_NB_NF:
277                 /*
278                  * Normal BCLK + FS.
279                  * FS active low. TX data driven on falling edge of bit clock
280                  * and RX data sampled on rising edge of bit clock.
281                  */
282                 regs->pcr0      |= FSXP | FSRP |
283                                    CLKXP | CLKRP;
284                 break;
285         case SND_SOC_DAIFMT_NB_IF:
286                 regs->pcr0      |= CLKXP | CLKRP;
287                 break;
288         case SND_SOC_DAIFMT_IB_NF:
289                 regs->pcr0      |= FSXP | FSRP;
290                 break;
291         case SND_SOC_DAIFMT_IB_IF:
292                 break;
293         default:
294                 return -EINVAL;
295         }
296
297         return 0;
298 }
299
300 static int omap_mcbsp_dai_set_clkdiv(struct snd_soc_dai *cpu_dai,
301                                      int div_id, int div)
302 {
303         struct omap_mcbsp_data *mcbsp_data = to_mcbsp(cpu_dai->private_data);
304         struct omap_mcbsp_reg_cfg *regs = &mcbsp_data->regs;
305
306         if (div_id != OMAP_MCBSP_CLKGDV)
307                 return -ENODEV;
308
309         regs->srgr1     |= CLKGDV(div - 1);
310
311         return 0;
312 }
313
314 static int omap_mcbsp_dai_set_clks_src(struct omap_mcbsp_data *mcbsp_data,
315                                        int clk_id)
316 {
317         int sel_bit;
318         u16 reg;
319
320         if (cpu_class_is_omap1()) {
321                 /* OMAP1's can use only external source clock */
322                 if (unlikely(clk_id == OMAP_MCBSP_SYSCLK_CLKS_FCLK))
323                         return -EINVAL;
324                 else
325                         return 0;
326         }
327
328         switch (mcbsp_data->bus_id) {
329         case 0:
330                 reg = OMAP2_CONTROL_DEVCONF0;
331                 sel_bit = 2;
332                 break;
333         case 1:
334                 reg = OMAP2_CONTROL_DEVCONF0;
335                 sel_bit = 6;
336                 break;
337         /* TODO: Support for ports 3 - 5 in OMAP2430 and OMAP34xx */
338         default:
339                 return -EINVAL;
340         }
341
342         if (cpu_class_is_omap2()) {
343                 if (clk_id == OMAP_MCBSP_SYSCLK_CLKS_FCLK) {
344                         omap_ctrl_writel(omap_ctrl_readl(reg) &
345                                          ~(1 << sel_bit), reg);
346                 } else {
347                         omap_ctrl_writel(omap_ctrl_readl(reg) |
348                                          (1 << sel_bit), reg);
349                 }
350         }
351
352         return 0;
353 }
354
355 static int omap_mcbsp_dai_set_dai_sysclk(struct snd_soc_dai *cpu_dai,
356                                          int clk_id, unsigned int freq,
357                                          int dir)
358 {
359         struct omap_mcbsp_data *mcbsp_data = to_mcbsp(cpu_dai->private_data);
360         struct omap_mcbsp_reg_cfg *regs = &mcbsp_data->regs;
361         int err = 0;
362
363         switch (clk_id) {
364         case OMAP_MCBSP_SYSCLK_CLK:
365                 regs->srgr2     |= CLKSM;
366                 break;
367         case OMAP_MCBSP_SYSCLK_CLKS_FCLK:
368         case OMAP_MCBSP_SYSCLK_CLKS_EXT:
369                 err = omap_mcbsp_dai_set_clks_src(mcbsp_data, clk_id);
370                 break;
371
372         case OMAP_MCBSP_SYSCLK_CLKX_EXT:
373                 regs->srgr2     |= CLKSM;
374         case OMAP_MCBSP_SYSCLK_CLKR_EXT:
375                 regs->pcr0      |= SCLKME;
376                 break;
377         default:
378                 err = -ENODEV;
379         }
380
381         return err;
382 }
383
384 #define OMAP_MCBSP_DAI_BUILDER(link_id)                         \
385 {                                                               \
386         .name = "omap-mcbsp-dai-(link_id)",                     \
387         .id = (link_id),                                        \
388         .type = SND_SOC_DAI_I2S,                                \
389         .playback = {                                           \
390                 .channels_min = 2,                              \
391                 .channels_max = 2,                              \
392                 .rates = OMAP_MCBSP_RATES,                      \
393                 .formats = SNDRV_PCM_FMTBIT_S16_LE,             \
394         },                                                      \
395         .capture = {                                            \
396                 .channels_min = 2,                              \
397                 .channels_max = 2,                              \
398                 .rates = OMAP_MCBSP_RATES,                      \
399                 .formats = SNDRV_PCM_FMTBIT_S16_LE,             \
400         },                                                      \
401         .ops = {                                                \
402                 .startup = omap_mcbsp_dai_startup,              \
403                 .shutdown = omap_mcbsp_dai_shutdown,            \
404                 .trigger = omap_mcbsp_dai_trigger,              \
405                 .hw_params = omap_mcbsp_dai_hw_params,          \
406         },                                                      \
407         .dai_ops = {                                            \
408                 .set_fmt = omap_mcbsp_dai_set_dai_fmt,          \
409                 .set_clkdiv = omap_mcbsp_dai_set_clkdiv,        \
410                 .set_sysclk = omap_mcbsp_dai_set_dai_sysclk,    \
411         },                                                      \
412         .private_data = &mcbsp_data[(link_id)].bus_id,          \
413 }
414
415 struct snd_soc_dai omap_mcbsp_dai[] = {
416         OMAP_MCBSP_DAI_BUILDER(0),
417         OMAP_MCBSP_DAI_BUILDER(1),
418 #if NUM_LINKS >= 3
419         OMAP_MCBSP_DAI_BUILDER(2),
420 #endif
421 #if NUM_LINKS == 5
422         OMAP_MCBSP_DAI_BUILDER(3),
423         OMAP_MCBSP_DAI_BUILDER(4),
424 #endif
425 };
426
427 EXPORT_SYMBOL_GPL(omap_mcbsp_dai);
428
429 MODULE_AUTHOR("Jarkko Nikula <jarkko.nikula@nokia.com>");
430 MODULE_DESCRIPTION("OMAP I2S SoC Interface");
431 MODULE_LICENSE("GPL");