Merge branch 'fix/hda' into topic/hda
[linux-2.6.git] / sound / pci / hda / hda_intel.c
1 /*
2  *
3  *  hda_intel.c - Implementation of primary alsa driver code base
4  *                for Intel HD Audio.
5  *
6  *  Copyright(c) 2004 Intel Corporation. All rights reserved.
7  *
8  *  Copyright (c) 2004 Takashi Iwai <tiwai@suse.de>
9  *                     PeiSen Hou <pshou@realtek.com.tw>
10  *
11  *  This program is free software; you can redistribute it and/or modify it
12  *  under the terms of the GNU General Public License as published by the Free
13  *  Software Foundation; either version 2 of the License, or (at your option)
14  *  any later version.
15  *
16  *  This program is distributed in the hope that it will be useful, but WITHOUT
17  *  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
18  *  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
19  *  more details.
20  *
21  *  You should have received a copy of the GNU General Public License along with
22  *  this program; if not, write to the Free Software Foundation, Inc., 59
23  *  Temple Place - Suite 330, Boston, MA  02111-1307, USA.
24  *
25  *  CONTACTS:
26  *
27  *  Matt Jared          matt.jared@intel.com
28  *  Andy Kopp           andy.kopp@intel.com
29  *  Dan Kogan           dan.d.kogan@intel.com
30  *
31  *  CHANGES:
32  *
33  *  2004.12.01  Major rewrite by tiwai, merged the work of pshou
34  * 
35  */
36
37 #include <asm/io.h>
38 #include <linux/delay.h>
39 #include <linux/interrupt.h>
40 #include <linux/kernel.h>
41 #include <linux/module.h>
42 #include <linux/dma-mapping.h>
43 #include <linux/moduleparam.h>
44 #include <linux/init.h>
45 #include <linux/slab.h>
46 #include <linux/pci.h>
47 #include <linux/mutex.h>
48 #include <linux/reboot.h>
49 #include <sound/core.h>
50 #include <sound/initval.h>
51 #include "hda_codec.h"
52
53
54 static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX;
55 static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR;
56 static int enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP;
57 static char *model[SNDRV_CARDS];
58 static int position_fix[SNDRV_CARDS];
59 static int bdl_pos_adj[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1};
60 static int probe_mask[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1};
61 static int single_cmd;
62 static int enable_msi;
63
64 module_param_array(index, int, NULL, 0444);
65 MODULE_PARM_DESC(index, "Index value for Intel HD audio interface.");
66 module_param_array(id, charp, NULL, 0444);
67 MODULE_PARM_DESC(id, "ID string for Intel HD audio interface.");
68 module_param_array(enable, bool, NULL, 0444);
69 MODULE_PARM_DESC(enable, "Enable Intel HD audio interface.");
70 module_param_array(model, charp, NULL, 0444);
71 MODULE_PARM_DESC(model, "Use the given board model.");
72 module_param_array(position_fix, int, NULL, 0444);
73 MODULE_PARM_DESC(position_fix, "Fix DMA pointer "
74                  "(0 = auto, 1 = none, 2 = POSBUF).");
75 module_param_array(bdl_pos_adj, int, NULL, 0644);
76 MODULE_PARM_DESC(bdl_pos_adj, "BDL position adjustment offset.");
77 module_param_array(probe_mask, int, NULL, 0444);
78 MODULE_PARM_DESC(probe_mask, "Bitmask to probe codecs (default = -1).");
79 module_param(single_cmd, bool, 0444);
80 MODULE_PARM_DESC(single_cmd, "Use single command to communicate with codecs "
81                  "(for debugging only).");
82 module_param(enable_msi, int, 0444);
83 MODULE_PARM_DESC(enable_msi, "Enable Message Signaled Interrupt (MSI)");
84
85 #ifdef CONFIG_SND_HDA_POWER_SAVE
86 static int power_save = CONFIG_SND_HDA_POWER_SAVE_DEFAULT;
87 module_param(power_save, int, 0644);
88 MODULE_PARM_DESC(power_save, "Automatic power-saving timeout "
89                  "(in second, 0 = disable).");
90
91 /* reset the HD-audio controller in power save mode.
92  * this may give more power-saving, but will take longer time to
93  * wake up.
94  */
95 static int power_save_controller = 1;
96 module_param(power_save_controller, bool, 0644);
97 MODULE_PARM_DESC(power_save_controller, "Reset controller in power save mode.");
98 #endif
99
100 MODULE_LICENSE("GPL");
101 MODULE_SUPPORTED_DEVICE("{{Intel, ICH6},"
102                          "{Intel, ICH6M},"
103                          "{Intel, ICH7},"
104                          "{Intel, ESB2},"
105                          "{Intel, ICH8},"
106                          "{Intel, ICH9},"
107                          "{Intel, ICH10},"
108                          "{Intel, PCH},"
109                          "{Intel, SCH},"
110                          "{ATI, SB450},"
111                          "{ATI, SB600},"
112                          "{ATI, RS600},"
113                          "{ATI, RS690},"
114                          "{ATI, RS780},"
115                          "{ATI, R600},"
116                          "{ATI, RV630},"
117                          "{ATI, RV610},"
118                          "{ATI, RV670},"
119                          "{ATI, RV635},"
120                          "{ATI, RV620},"
121                          "{ATI, RV770},"
122                          "{VIA, VT8251},"
123                          "{VIA, VT8237A},"
124                          "{SiS, SIS966},"
125                          "{ULI, M5461}}");
126 MODULE_DESCRIPTION("Intel HDA driver");
127
128 #define SFX     "hda-intel: "
129
130
131 /*
132  * registers
133  */
134 #define ICH6_REG_GCAP                   0x00
135 #define ICH6_REG_VMIN                   0x02
136 #define ICH6_REG_VMAJ                   0x03
137 #define ICH6_REG_OUTPAY                 0x04
138 #define ICH6_REG_INPAY                  0x06
139 #define ICH6_REG_GCTL                   0x08
140 #define ICH6_REG_WAKEEN                 0x0c
141 #define ICH6_REG_STATESTS               0x0e
142 #define ICH6_REG_GSTS                   0x10
143 #define ICH6_REG_INTCTL                 0x20
144 #define ICH6_REG_INTSTS                 0x24
145 #define ICH6_REG_WALCLK                 0x30
146 #define ICH6_REG_SYNC                   0x34    
147 #define ICH6_REG_CORBLBASE              0x40
148 #define ICH6_REG_CORBUBASE              0x44
149 #define ICH6_REG_CORBWP                 0x48
150 #define ICH6_REG_CORBRP                 0x4A
151 #define ICH6_REG_CORBCTL                0x4c
152 #define ICH6_REG_CORBSTS                0x4d
153 #define ICH6_REG_CORBSIZE               0x4e
154
155 #define ICH6_REG_RIRBLBASE              0x50
156 #define ICH6_REG_RIRBUBASE              0x54
157 #define ICH6_REG_RIRBWP                 0x58
158 #define ICH6_REG_RINTCNT                0x5a
159 #define ICH6_REG_RIRBCTL                0x5c
160 #define ICH6_REG_RIRBSTS                0x5d
161 #define ICH6_REG_RIRBSIZE               0x5e
162
163 #define ICH6_REG_IC                     0x60
164 #define ICH6_REG_IR                     0x64
165 #define ICH6_REG_IRS                    0x68
166 #define   ICH6_IRS_VALID        (1<<1)
167 #define   ICH6_IRS_BUSY         (1<<0)
168
169 #define ICH6_REG_DPLBASE                0x70
170 #define ICH6_REG_DPUBASE                0x74
171 #define   ICH6_DPLBASE_ENABLE   0x1     /* Enable position buffer */
172
173 /* SD offset: SDI0=0x80, SDI1=0xa0, ... SDO3=0x160 */
174 enum { SDI0, SDI1, SDI2, SDI3, SDO0, SDO1, SDO2, SDO3 };
175
176 /* stream register offsets from stream base */
177 #define ICH6_REG_SD_CTL                 0x00
178 #define ICH6_REG_SD_STS                 0x03
179 #define ICH6_REG_SD_LPIB                0x04
180 #define ICH6_REG_SD_CBL                 0x08
181 #define ICH6_REG_SD_LVI                 0x0c
182 #define ICH6_REG_SD_FIFOW               0x0e
183 #define ICH6_REG_SD_FIFOSIZE            0x10
184 #define ICH6_REG_SD_FORMAT              0x12
185 #define ICH6_REG_SD_BDLPL               0x18
186 #define ICH6_REG_SD_BDLPU               0x1c
187
188 /* PCI space */
189 #define ICH6_PCIREG_TCSEL       0x44
190
191 /*
192  * other constants
193  */
194
195 /* max number of SDs */
196 /* ICH, ATI and VIA have 4 playback and 4 capture */
197 #define ICH6_NUM_CAPTURE        4
198 #define ICH6_NUM_PLAYBACK       4
199
200 /* ULI has 6 playback and 5 capture */
201 #define ULI_NUM_CAPTURE         5
202 #define ULI_NUM_PLAYBACK        6
203
204 /* ATI HDMI has 1 playback and 0 capture */
205 #define ATIHDMI_NUM_CAPTURE     0
206 #define ATIHDMI_NUM_PLAYBACK    1
207
208 /* TERA has 4 playback and 3 capture */
209 #define TERA_NUM_CAPTURE        3
210 #define TERA_NUM_PLAYBACK       4
211
212 /* this number is statically defined for simplicity */
213 #define MAX_AZX_DEV             16
214
215 /* max number of fragments - we may use more if allocating more pages for BDL */
216 #define BDL_SIZE                4096
217 #define AZX_MAX_BDL_ENTRIES     (BDL_SIZE / 16)
218 #define AZX_MAX_FRAG            32
219 /* max buffer size - no h/w limit, you can increase as you like */
220 #define AZX_MAX_BUF_SIZE        (1024*1024*1024)
221 /* max number of PCM devics per card */
222 #define AZX_MAX_PCMS            8
223
224 /* RIRB int mask: overrun[2], response[0] */
225 #define RIRB_INT_RESPONSE       0x01
226 #define RIRB_INT_OVERRUN        0x04
227 #define RIRB_INT_MASK           0x05
228
229 /* STATESTS int mask: S3,SD2,SD1,SD0 */
230 #define AZX_MAX_CODECS          4
231 #define STATESTS_INT_MASK       0x0f
232
233 /* SD_CTL bits */
234 #define SD_CTL_STREAM_RESET     0x01    /* stream reset bit */
235 #define SD_CTL_DMA_START        0x02    /* stream DMA start bit */
236 #define SD_CTL_STRIPE           (3 << 16)       /* stripe control */
237 #define SD_CTL_TRAFFIC_PRIO     (1 << 18)       /* traffic priority */
238 #define SD_CTL_DIR              (1 << 19)       /* bi-directional stream */
239 #define SD_CTL_STREAM_TAG_MASK  (0xf << 20)
240 #define SD_CTL_STREAM_TAG_SHIFT 20
241
242 /* SD_CTL and SD_STS */
243 #define SD_INT_DESC_ERR         0x10    /* descriptor error interrupt */
244 #define SD_INT_FIFO_ERR         0x08    /* FIFO error interrupt */
245 #define SD_INT_COMPLETE         0x04    /* completion interrupt */
246 #define SD_INT_MASK             (SD_INT_DESC_ERR|SD_INT_FIFO_ERR|\
247                                  SD_INT_COMPLETE)
248
249 /* SD_STS */
250 #define SD_STS_FIFO_READY       0x20    /* FIFO ready */
251
252 /* INTCTL and INTSTS */
253 #define ICH6_INT_ALL_STREAM     0xff       /* all stream interrupts */
254 #define ICH6_INT_CTRL_EN        0x40000000 /* controller interrupt enable bit */
255 #define ICH6_INT_GLOBAL_EN      0x80000000 /* global interrupt enable bit */
256
257 /* GCTL unsolicited response enable bit */
258 #define ICH6_GCTL_UREN          (1<<8)
259
260 /* GCTL reset bit */
261 #define ICH6_GCTL_RESET         (1<<0)
262
263 /* CORB/RIRB control, read/write pointer */
264 #define ICH6_RBCTL_DMA_EN       0x02    /* enable DMA */
265 #define ICH6_RBCTL_IRQ_EN       0x01    /* enable IRQ */
266 #define ICH6_RBRWP_CLR          0x8000  /* read/write pointer clear */
267 /* below are so far hardcoded - should read registers in future */
268 #define ICH6_MAX_CORB_ENTRIES   256
269 #define ICH6_MAX_RIRB_ENTRIES   256
270
271 /* position fix mode */
272 enum {
273         POS_FIX_AUTO,
274         POS_FIX_LPIB,
275         POS_FIX_POSBUF,
276 };
277
278 /* Defines for ATI HD Audio support in SB450 south bridge */
279 #define ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR   0x42
280 #define ATI_SB450_HDAUDIO_ENABLE_SNOOP      0x02
281
282 /* Defines for Nvidia HDA support */
283 #define NVIDIA_HDA_TRANSREG_ADDR      0x4e
284 #define NVIDIA_HDA_ENABLE_COHBITS     0x0f
285 #define NVIDIA_HDA_ISTRM_COH          0x4d
286 #define NVIDIA_HDA_OSTRM_COH          0x4c
287 #define NVIDIA_HDA_ENABLE_COHBIT      0x01
288
289 /* Defines for Intel SCH HDA snoop control */
290 #define INTEL_SCH_HDA_DEVC      0x78
291 #define INTEL_SCH_HDA_DEVC_NOSNOOP       (0x1<<11)
292
293 /* Define IN stream 0 FIFO size offset in VIA controller */
294 #define VIA_IN_STREAM0_FIFO_SIZE_OFFSET 0x90
295 /* Define VIA HD Audio Device ID*/
296 #define VIA_HDAC_DEVICE_ID              0x3288
297
298 /* HD Audio class code */
299 #define PCI_CLASS_MULTIMEDIA_HD_AUDIO   0x0403
300
301 /*
302  */
303
304 struct azx_dev {
305         struct snd_dma_buffer bdl; /* BDL buffer */
306         u32 *posbuf;            /* position buffer pointer */
307
308         unsigned int bufsize;   /* size of the play buffer in bytes */
309         unsigned int period_bytes; /* size of the period in bytes */
310         unsigned int frags;     /* number for period in the play buffer */
311         unsigned int fifo_size; /* FIFO size */
312
313         void __iomem *sd_addr;  /* stream descriptor pointer */
314
315         u32 sd_int_sta_mask;    /* stream int status mask */
316
317         /* pcm support */
318         struct snd_pcm_substream *substream;    /* assigned substream,
319                                                  * set in PCM open
320                                                  */
321         unsigned int format_val;        /* format value to be set in the
322                                          * controller and the codec
323                                          */
324         unsigned char stream_tag;       /* assigned stream */
325         unsigned char index;            /* stream index */
326
327         unsigned int opened :1;
328         unsigned int running :1;
329         unsigned int irq_pending :1;
330         unsigned int irq_ignore :1;
331         /*
332          * For VIA:
333          *  A flag to ensure DMA position is 0
334          *  when link position is not greater than FIFO size
335          */
336         unsigned int insufficient :1;
337 };
338
339 /* CORB/RIRB */
340 struct azx_rb {
341         u32 *buf;               /* CORB/RIRB buffer
342                                  * Each CORB entry is 4byte, RIRB is 8byte
343                                  */
344         dma_addr_t addr;        /* physical address of CORB/RIRB buffer */
345         /* for RIRB */
346         unsigned short rp, wp;  /* read/write pointers */
347         int cmds;               /* number of pending requests */
348         u32 res;                /* last read value */
349 };
350
351 struct azx {
352         struct snd_card *card;
353         struct pci_dev *pci;
354         int dev_index;
355
356         /* chip type specific */
357         int driver_type;
358         int playback_streams;
359         int playback_index_offset;
360         int capture_streams;
361         int capture_index_offset;
362         int num_streams;
363
364         /* pci resources */
365         unsigned long addr;
366         void __iomem *remap_addr;
367         int irq;
368
369         /* locks */
370         spinlock_t reg_lock;
371         struct mutex open_mutex;
372
373         /* streams (x num_streams) */
374         struct azx_dev *azx_dev;
375
376         /* PCM */
377         struct snd_pcm *pcm[AZX_MAX_PCMS];
378
379         /* HD codec */
380         unsigned short codec_mask;
381         struct hda_bus *bus;
382
383         /* CORB/RIRB */
384         struct azx_rb corb;
385         struct azx_rb rirb;
386
387         /* CORB/RIRB and position buffers */
388         struct snd_dma_buffer rb;
389         struct snd_dma_buffer posbuf;
390
391         /* flags */
392         int position_fix;
393         unsigned int running :1;
394         unsigned int initialized :1;
395         unsigned int single_cmd :1;
396         unsigned int polling_mode :1;
397         unsigned int msi :1;
398         unsigned int irq_pending_warned :1;
399         unsigned int via_dmapos_patch :1; /* enable DMA-position fix for VIA */
400         unsigned int probing :1; /* codec probing phase */
401
402         /* for debugging */
403         unsigned int last_cmd;  /* last issued command (to sync) */
404
405         /* for pending irqs */
406         struct work_struct irq_pending_work;
407
408         /* reboot notifier (for mysterious hangup problem at power-down) */
409         struct notifier_block reboot_notifier;
410 };
411
412 /* driver types */
413 enum {
414         AZX_DRIVER_ICH,
415         AZX_DRIVER_SCH,
416         AZX_DRIVER_ATI,
417         AZX_DRIVER_ATIHDMI,
418         AZX_DRIVER_VIA,
419         AZX_DRIVER_SIS,
420         AZX_DRIVER_ULI,
421         AZX_DRIVER_NVIDIA,
422         AZX_DRIVER_TERA,
423         AZX_DRIVER_GENERIC,
424         AZX_NUM_DRIVERS, /* keep this as last entry */
425 };
426
427 static char *driver_short_names[] __devinitdata = {
428         [AZX_DRIVER_ICH] = "HDA Intel",
429         [AZX_DRIVER_SCH] = "HDA Intel MID",
430         [AZX_DRIVER_ATI] = "HDA ATI SB",
431         [AZX_DRIVER_ATIHDMI] = "HDA ATI HDMI",
432         [AZX_DRIVER_VIA] = "HDA VIA VT82xx",
433         [AZX_DRIVER_SIS] = "HDA SIS966",
434         [AZX_DRIVER_ULI] = "HDA ULI M5461",
435         [AZX_DRIVER_NVIDIA] = "HDA NVidia",
436         [AZX_DRIVER_TERA] = "HDA Teradici", 
437         [AZX_DRIVER_GENERIC] = "HD-Audio Generic",
438 };
439
440 /*
441  * macros for easy use
442  */
443 #define azx_writel(chip,reg,value) \
444         writel(value, (chip)->remap_addr + ICH6_REG_##reg)
445 #define azx_readl(chip,reg) \
446         readl((chip)->remap_addr + ICH6_REG_##reg)
447 #define azx_writew(chip,reg,value) \
448         writew(value, (chip)->remap_addr + ICH6_REG_##reg)
449 #define azx_readw(chip,reg) \
450         readw((chip)->remap_addr + ICH6_REG_##reg)
451 #define azx_writeb(chip,reg,value) \
452         writeb(value, (chip)->remap_addr + ICH6_REG_##reg)
453 #define azx_readb(chip,reg) \
454         readb((chip)->remap_addr + ICH6_REG_##reg)
455
456 #define azx_sd_writel(dev,reg,value) \
457         writel(value, (dev)->sd_addr + ICH6_REG_##reg)
458 #define azx_sd_readl(dev,reg) \
459         readl((dev)->sd_addr + ICH6_REG_##reg)
460 #define azx_sd_writew(dev,reg,value) \
461         writew(value, (dev)->sd_addr + ICH6_REG_##reg)
462 #define azx_sd_readw(dev,reg) \
463         readw((dev)->sd_addr + ICH6_REG_##reg)
464 #define azx_sd_writeb(dev,reg,value) \
465         writeb(value, (dev)->sd_addr + ICH6_REG_##reg)
466 #define azx_sd_readb(dev,reg) \
467         readb((dev)->sd_addr + ICH6_REG_##reg)
468
469 /* for pcm support */
470 #define get_azx_dev(substream) (substream->runtime->private_data)
471
472 static int azx_acquire_irq(struct azx *chip, int do_disconnect);
473
474 /*
475  * Interface for HD codec
476  */
477
478 /*
479  * CORB / RIRB interface
480  */
481 static int azx_alloc_cmd_io(struct azx *chip)
482 {
483         int err;
484
485         /* single page (at least 4096 bytes) must suffice for both ringbuffes */
486         err = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV,
487                                   snd_dma_pci_data(chip->pci),
488                                   PAGE_SIZE, &chip->rb);
489         if (err < 0) {
490                 snd_printk(KERN_ERR SFX "cannot allocate CORB/RIRB\n");
491                 return err;
492         }
493         return 0;
494 }
495
496 static void azx_init_cmd_io(struct azx *chip)
497 {
498         /* CORB set up */
499         chip->corb.addr = chip->rb.addr;
500         chip->corb.buf = (u32 *)chip->rb.area;
501         azx_writel(chip, CORBLBASE, (u32)chip->corb.addr);
502         azx_writel(chip, CORBUBASE, upper_32_bits(chip->corb.addr));
503
504         /* set the corb size to 256 entries (ULI requires explicitly) */
505         azx_writeb(chip, CORBSIZE, 0x02);
506         /* set the corb write pointer to 0 */
507         azx_writew(chip, CORBWP, 0);
508         /* reset the corb hw read pointer */
509         azx_writew(chip, CORBRP, ICH6_RBRWP_CLR);
510         /* enable corb dma */
511         azx_writeb(chip, CORBCTL, ICH6_RBCTL_DMA_EN);
512
513         /* RIRB set up */
514         chip->rirb.addr = chip->rb.addr + 2048;
515         chip->rirb.buf = (u32 *)(chip->rb.area + 2048);
516         azx_writel(chip, RIRBLBASE, (u32)chip->rirb.addr);
517         azx_writel(chip, RIRBUBASE, upper_32_bits(chip->rirb.addr));
518
519         /* set the rirb size to 256 entries (ULI requires explicitly) */
520         azx_writeb(chip, RIRBSIZE, 0x02);
521         /* reset the rirb hw write pointer */
522         azx_writew(chip, RIRBWP, ICH6_RBRWP_CLR);
523         /* set N=1, get RIRB response interrupt for new entry */
524         azx_writew(chip, RINTCNT, 1);
525         /* enable rirb dma and response irq */
526         azx_writeb(chip, RIRBCTL, ICH6_RBCTL_DMA_EN | ICH6_RBCTL_IRQ_EN);
527         chip->rirb.rp = chip->rirb.cmds = 0;
528 }
529
530 static void azx_free_cmd_io(struct azx *chip)
531 {
532         /* disable ringbuffer DMAs */
533         azx_writeb(chip, RIRBCTL, 0);
534         azx_writeb(chip, CORBCTL, 0);
535 }
536
537 /* send a command */
538 static int azx_corb_send_cmd(struct hda_bus *bus, u32 val)
539 {
540         struct azx *chip = bus->private_data;
541         unsigned int wp;
542
543         /* add command to corb */
544         wp = azx_readb(chip, CORBWP);
545         wp++;
546         wp %= ICH6_MAX_CORB_ENTRIES;
547
548         spin_lock_irq(&chip->reg_lock);
549         chip->rirb.cmds++;
550         chip->corb.buf[wp] = cpu_to_le32(val);
551         azx_writel(chip, CORBWP, wp);
552         spin_unlock_irq(&chip->reg_lock);
553
554         return 0;
555 }
556
557 #define ICH6_RIRB_EX_UNSOL_EV   (1<<4)
558
559 /* retrieve RIRB entry - called from interrupt handler */
560 static void azx_update_rirb(struct azx *chip)
561 {
562         unsigned int rp, wp;
563         u32 res, res_ex;
564
565         wp = azx_readb(chip, RIRBWP);
566         if (wp == chip->rirb.wp)
567                 return;
568         chip->rirb.wp = wp;
569                 
570         while (chip->rirb.rp != wp) {
571                 chip->rirb.rp++;
572                 chip->rirb.rp %= ICH6_MAX_RIRB_ENTRIES;
573
574                 rp = chip->rirb.rp << 1; /* an RIRB entry is 8-bytes */
575                 res_ex = le32_to_cpu(chip->rirb.buf[rp + 1]);
576                 res = le32_to_cpu(chip->rirb.buf[rp]);
577                 if (res_ex & ICH6_RIRB_EX_UNSOL_EV)
578                         snd_hda_queue_unsol_event(chip->bus, res, res_ex);
579                 else if (chip->rirb.cmds) {
580                         chip->rirb.res = res;
581                         smp_wmb();
582                         chip->rirb.cmds--;
583                 }
584         }
585 }
586
587 /* receive a response */
588 static unsigned int azx_rirb_get_response(struct hda_bus *bus)
589 {
590         struct azx *chip = bus->private_data;
591         unsigned long timeout;
592
593  again:
594         timeout = jiffies + msecs_to_jiffies(1000);
595         for (;;) {
596                 if (chip->polling_mode) {
597                         spin_lock_irq(&chip->reg_lock);
598                         azx_update_rirb(chip);
599                         spin_unlock_irq(&chip->reg_lock);
600                 }
601                 if (!chip->rirb.cmds) {
602                         smp_rmb();
603                         return chip->rirb.res; /* the last value */
604                 }
605                 if (time_after(jiffies, timeout))
606                         break;
607                 if (bus->needs_damn_long_delay)
608                         msleep(2); /* temporary workaround */
609                 else {
610                         udelay(10);
611                         cond_resched();
612                 }
613         }
614
615         if (chip->msi) {
616                 snd_printk(KERN_WARNING "hda_intel: No response from codec, "
617                            "disabling MSI: last cmd=0x%08x\n", chip->last_cmd);
618                 free_irq(chip->irq, chip);
619                 chip->irq = -1;
620                 pci_disable_msi(chip->pci);
621                 chip->msi = 0;
622                 if (azx_acquire_irq(chip, 1) < 0)
623                         return -1;
624                 goto again;
625         }
626
627         if (!chip->polling_mode) {
628                 snd_printk(KERN_WARNING "hda_intel: azx_get_response timeout, "
629                            "switching to polling mode: last cmd=0x%08x\n",
630                            chip->last_cmd);
631                 chip->polling_mode = 1;
632                 goto again;
633         }
634
635         if (chip->probing) {
636                 /* If this critical timeout happens during the codec probing
637                  * phase, this is likely an access to a non-existing codec
638                  * slot.  Better to return an error and reset the system.
639                  */
640                 return -1;
641         }
642
643         snd_printk(KERN_ERR "hda_intel: azx_get_response timeout, "
644                    "switching to single_cmd mode: last cmd=0x%08x\n",
645                    chip->last_cmd);
646         chip->rirb.rp = azx_readb(chip, RIRBWP);
647         chip->rirb.cmds = 0;
648         /* switch to single_cmd mode */
649         chip->single_cmd = 1;
650         azx_free_cmd_io(chip);
651         return -1;
652 }
653
654 /*
655  * Use the single immediate command instead of CORB/RIRB for simplicity
656  *
657  * Note: according to Intel, this is not preferred use.  The command was
658  *       intended for the BIOS only, and may get confused with unsolicited
659  *       responses.  So, we shouldn't use it for normal operation from the
660  *       driver.
661  *       I left the codes, however, for debugging/testing purposes.
662  */
663
664 /* send a command */
665 static int azx_single_send_cmd(struct hda_bus *bus, u32 val)
666 {
667         struct azx *chip = bus->private_data;
668         int timeout = 50;
669
670         while (timeout--) {
671                 /* check ICB busy bit */
672                 if (!((azx_readw(chip, IRS) & ICH6_IRS_BUSY))) {
673                         /* Clear IRV valid bit */
674                         azx_writew(chip, IRS, azx_readw(chip, IRS) |
675                                    ICH6_IRS_VALID);
676                         azx_writel(chip, IC, val);
677                         azx_writew(chip, IRS, azx_readw(chip, IRS) |
678                                    ICH6_IRS_BUSY);
679                         return 0;
680                 }
681                 udelay(1);
682         }
683         if (printk_ratelimit())
684                 snd_printd(SFX "send_cmd timeout: IRS=0x%x, val=0x%x\n",
685                            azx_readw(chip, IRS), val);
686         return -EIO;
687 }
688
689 /* receive a response */
690 static unsigned int azx_single_get_response(struct hda_bus *bus)
691 {
692         struct azx *chip = bus->private_data;
693         int timeout = 50;
694
695         while (timeout--) {
696                 /* check IRV busy bit */
697                 if (azx_readw(chip, IRS) & ICH6_IRS_VALID)
698                         return azx_readl(chip, IR);
699                 udelay(1);
700         }
701         if (printk_ratelimit())
702                 snd_printd(SFX "get_response timeout: IRS=0x%x\n",
703                            azx_readw(chip, IRS));
704         return (unsigned int)-1;
705 }
706
707 /*
708  * The below are the main callbacks from hda_codec.
709  *
710  * They are just the skeleton to call sub-callbacks according to the
711  * current setting of chip->single_cmd.
712  */
713
714 /* send a command */
715 static int azx_send_cmd(struct hda_bus *bus, unsigned int val)
716 {
717         struct azx *chip = bus->private_data;
718
719         chip->last_cmd = val;
720         if (chip->single_cmd)
721                 return azx_single_send_cmd(bus, val);
722         else
723                 return azx_corb_send_cmd(bus, val);
724 }
725
726 /* get a response */
727 static unsigned int azx_get_response(struct hda_bus *bus)
728 {
729         struct azx *chip = bus->private_data;
730         if (chip->single_cmd)
731                 return azx_single_get_response(bus);
732         else
733                 return azx_rirb_get_response(bus);
734 }
735
736 #ifdef CONFIG_SND_HDA_POWER_SAVE
737 static void azx_power_notify(struct hda_bus *bus);
738 #endif
739
740 /* reset codec link */
741 static int azx_reset(struct azx *chip)
742 {
743         int count;
744
745         /* clear STATESTS */
746         azx_writeb(chip, STATESTS, STATESTS_INT_MASK);
747
748         /* reset controller */
749         azx_writel(chip, GCTL, azx_readl(chip, GCTL) & ~ICH6_GCTL_RESET);
750
751         count = 50;
752         while (azx_readb(chip, GCTL) && --count)
753                 msleep(1);
754
755         /* delay for >= 100us for codec PLL to settle per spec
756          * Rev 0.9 section 5.5.1
757          */
758         msleep(1);
759
760         /* Bring controller out of reset */
761         azx_writeb(chip, GCTL, azx_readb(chip, GCTL) | ICH6_GCTL_RESET);
762
763         count = 50;
764         while (!azx_readb(chip, GCTL) && --count)
765                 msleep(1);
766
767         /* Brent Chartrand said to wait >= 540us for codecs to initialize */
768         msleep(1);
769
770         /* check to see if controller is ready */
771         if (!azx_readb(chip, GCTL)) {
772                 snd_printd("azx_reset: controller not ready!\n");
773                 return -EBUSY;
774         }
775
776         /* Accept unsolicited responses */
777         azx_writel(chip, GCTL, azx_readl(chip, GCTL) | ICH6_GCTL_UREN);
778
779         /* detect codecs */
780         if (!chip->codec_mask) {
781                 chip->codec_mask = azx_readw(chip, STATESTS);
782                 snd_printdd("codec_mask = 0x%x\n", chip->codec_mask);
783         }
784
785         return 0;
786 }
787
788
789 /*
790  * Lowlevel interface
791  */  
792
793 /* enable interrupts */
794 static void azx_int_enable(struct azx *chip)
795 {
796         /* enable controller CIE and GIE */
797         azx_writel(chip, INTCTL, azx_readl(chip, INTCTL) |
798                    ICH6_INT_CTRL_EN | ICH6_INT_GLOBAL_EN);
799 }
800
801 /* disable interrupts */
802 static void azx_int_disable(struct azx *chip)
803 {
804         int i;
805
806         /* disable interrupts in stream descriptor */
807         for (i = 0; i < chip->num_streams; i++) {
808                 struct azx_dev *azx_dev = &chip->azx_dev[i];
809                 azx_sd_writeb(azx_dev, SD_CTL,
810                               azx_sd_readb(azx_dev, SD_CTL) & ~SD_INT_MASK);
811         }
812
813         /* disable SIE for all streams */
814         azx_writeb(chip, INTCTL, 0);
815
816         /* disable controller CIE and GIE */
817         azx_writel(chip, INTCTL, azx_readl(chip, INTCTL) &
818                    ~(ICH6_INT_CTRL_EN | ICH6_INT_GLOBAL_EN));
819 }
820
821 /* clear interrupts */
822 static void azx_int_clear(struct azx *chip)
823 {
824         int i;
825
826         /* clear stream status */
827         for (i = 0; i < chip->num_streams; i++) {
828                 struct azx_dev *azx_dev = &chip->azx_dev[i];
829                 azx_sd_writeb(azx_dev, SD_STS, SD_INT_MASK);
830         }
831
832         /* clear STATESTS */
833         azx_writeb(chip, STATESTS, STATESTS_INT_MASK);
834
835         /* clear rirb status */
836         azx_writeb(chip, RIRBSTS, RIRB_INT_MASK);
837
838         /* clear int status */
839         azx_writel(chip, INTSTS, ICH6_INT_CTRL_EN | ICH6_INT_ALL_STREAM);
840 }
841
842 /* start a stream */
843 static void azx_stream_start(struct azx *chip, struct azx_dev *azx_dev)
844 {
845         /*
846          * Before stream start, initialize parameter
847          */
848         azx_dev->insufficient = 1;
849
850         /* enable SIE */
851         azx_writeb(chip, INTCTL,
852                    azx_readb(chip, INTCTL) | (1 << azx_dev->index));
853         /* set DMA start and interrupt mask */
854         azx_sd_writeb(azx_dev, SD_CTL, azx_sd_readb(azx_dev, SD_CTL) |
855                       SD_CTL_DMA_START | SD_INT_MASK);
856 }
857
858 /* stop a stream */
859 static void azx_stream_stop(struct azx *chip, struct azx_dev *azx_dev)
860 {
861         /* stop DMA */
862         azx_sd_writeb(azx_dev, SD_CTL, azx_sd_readb(azx_dev, SD_CTL) &
863                       ~(SD_CTL_DMA_START | SD_INT_MASK));
864         azx_sd_writeb(azx_dev, SD_STS, SD_INT_MASK); /* to be sure */
865         /* disable SIE */
866         azx_writeb(chip, INTCTL,
867                    azx_readb(chip, INTCTL) & ~(1 << azx_dev->index));
868 }
869
870
871 /*
872  * reset and start the controller registers
873  */
874 static void azx_init_chip(struct azx *chip)
875 {
876         if (chip->initialized)
877                 return;
878
879         /* reset controller */
880         azx_reset(chip);
881
882         /* initialize interrupts */
883         azx_int_clear(chip);
884         azx_int_enable(chip);
885
886         /* initialize the codec command I/O */
887         if (!chip->single_cmd)
888                 azx_init_cmd_io(chip);
889
890         /* program the position buffer */
891         azx_writel(chip, DPLBASE, (u32)chip->posbuf.addr);
892         azx_writel(chip, DPUBASE, upper_32_bits(chip->posbuf.addr));
893
894         chip->initialized = 1;
895 }
896
897 /*
898  * initialize the PCI registers
899  */
900 /* update bits in a PCI register byte */
901 static void update_pci_byte(struct pci_dev *pci, unsigned int reg,
902                             unsigned char mask, unsigned char val)
903 {
904         unsigned char data;
905
906         pci_read_config_byte(pci, reg, &data);
907         data &= ~mask;
908         data |= (val & mask);
909         pci_write_config_byte(pci, reg, data);
910 }
911
912 static void azx_init_pci(struct azx *chip)
913 {
914         unsigned short snoop;
915
916         /* Clear bits 0-2 of PCI register TCSEL (at offset 0x44)
917          * TCSEL == Traffic Class Select Register, which sets PCI express QOS
918          * Ensuring these bits are 0 clears playback static on some HD Audio
919          * codecs
920          */
921         update_pci_byte(chip->pci, ICH6_PCIREG_TCSEL, 0x07, 0);
922
923         switch (chip->driver_type) {
924         case AZX_DRIVER_ATI:
925                 /* For ATI SB450 azalia HD audio, we need to enable snoop */
926                 update_pci_byte(chip->pci,
927                                 ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR, 
928                                 0x07, ATI_SB450_HDAUDIO_ENABLE_SNOOP);
929                 break;
930         case AZX_DRIVER_NVIDIA:
931                 /* For NVIDIA HDA, enable snoop */
932                 update_pci_byte(chip->pci,
933                                 NVIDIA_HDA_TRANSREG_ADDR,
934                                 0x0f, NVIDIA_HDA_ENABLE_COHBITS);
935                 update_pci_byte(chip->pci,
936                                 NVIDIA_HDA_ISTRM_COH,
937                                 0x01, NVIDIA_HDA_ENABLE_COHBIT);
938                 update_pci_byte(chip->pci,
939                                 NVIDIA_HDA_OSTRM_COH,
940                                 0x01, NVIDIA_HDA_ENABLE_COHBIT);
941                 break;
942         case AZX_DRIVER_SCH:
943                 pci_read_config_word(chip->pci, INTEL_SCH_HDA_DEVC, &snoop);
944                 if (snoop & INTEL_SCH_HDA_DEVC_NOSNOOP) {
945                         pci_write_config_word(chip->pci, INTEL_SCH_HDA_DEVC, \
946                                 snoop & (~INTEL_SCH_HDA_DEVC_NOSNOOP));
947                         pci_read_config_word(chip->pci,
948                                 INTEL_SCH_HDA_DEVC, &snoop);
949                         snd_printdd("HDA snoop disabled, enabling ... %s\n",\
950                                 (snoop & INTEL_SCH_HDA_DEVC_NOSNOOP) \
951                                 ? "Failed" : "OK");
952                 }
953                 break;
954
955         }
956 }
957
958
959 static int azx_position_ok(struct azx *chip, struct azx_dev *azx_dev);
960
961 /*
962  * interrupt handler
963  */
964 static irqreturn_t azx_interrupt(int irq, void *dev_id)
965 {
966         struct azx *chip = dev_id;
967         struct azx_dev *azx_dev;
968         u32 status;
969         int i;
970
971         spin_lock(&chip->reg_lock);
972
973         status = azx_readl(chip, INTSTS);
974         if (status == 0) {
975                 spin_unlock(&chip->reg_lock);
976                 return IRQ_NONE;
977         }
978         
979         for (i = 0; i < chip->num_streams; i++) {
980                 azx_dev = &chip->azx_dev[i];
981                 if (status & azx_dev->sd_int_sta_mask) {
982                         azx_sd_writeb(azx_dev, SD_STS, SD_INT_MASK);
983                         if (!azx_dev->substream || !azx_dev->running)
984                                 continue;
985                         /* ignore the first dummy IRQ (due to pos_adj) */
986                         if (azx_dev->irq_ignore) {
987                                 azx_dev->irq_ignore = 0;
988                                 continue;
989                         }
990                         /* check whether this IRQ is really acceptable */
991                         if (azx_position_ok(chip, azx_dev)) {
992                                 azx_dev->irq_pending = 0;
993                                 spin_unlock(&chip->reg_lock);
994                                 snd_pcm_period_elapsed(azx_dev->substream);
995                                 spin_lock(&chip->reg_lock);
996                         } else {
997                                 /* bogus IRQ, process it later */
998                                 azx_dev->irq_pending = 1;
999                                 schedule_work(&chip->irq_pending_work);
1000                         }
1001                 }
1002         }
1003
1004         /* clear rirb int */
1005         status = azx_readb(chip, RIRBSTS);
1006         if (status & RIRB_INT_MASK) {
1007                 if (!chip->single_cmd && (status & RIRB_INT_RESPONSE))
1008                         azx_update_rirb(chip);
1009                 azx_writeb(chip, RIRBSTS, RIRB_INT_MASK);
1010         }
1011
1012 #if 0
1013         /* clear state status int */
1014         if (azx_readb(chip, STATESTS) & 0x04)
1015                 azx_writeb(chip, STATESTS, 0x04);
1016 #endif
1017         spin_unlock(&chip->reg_lock);
1018         
1019         return IRQ_HANDLED;
1020 }
1021
1022
1023 /*
1024  * set up a BDL entry
1025  */
1026 static int setup_bdle(struct snd_pcm_substream *substream,
1027                       struct azx_dev *azx_dev, u32 **bdlp,
1028                       int ofs, int size, int with_ioc)
1029 {
1030         u32 *bdl = *bdlp;
1031
1032         while (size > 0) {
1033                 dma_addr_t addr;
1034                 int chunk;
1035
1036                 if (azx_dev->frags >= AZX_MAX_BDL_ENTRIES)
1037                         return -EINVAL;
1038
1039                 addr = snd_pcm_sgbuf_get_addr(substream, ofs);
1040                 /* program the address field of the BDL entry */
1041                 bdl[0] = cpu_to_le32((u32)addr);
1042                 bdl[1] = cpu_to_le32(upper_32_bits(addr));
1043                 /* program the size field of the BDL entry */
1044                 chunk = snd_pcm_sgbuf_get_chunk_size(substream, ofs, size);
1045                 bdl[2] = cpu_to_le32(chunk);
1046                 /* program the IOC to enable interrupt
1047                  * only when the whole fragment is processed
1048                  */
1049                 size -= chunk;
1050                 bdl[3] = (size || !with_ioc) ? 0 : cpu_to_le32(0x01);
1051                 bdl += 4;
1052                 azx_dev->frags++;
1053                 ofs += chunk;
1054         }
1055         *bdlp = bdl;
1056         return ofs;
1057 }
1058
1059 /*
1060  * set up BDL entries
1061  */
1062 static int azx_setup_periods(struct azx *chip,
1063                              struct snd_pcm_substream *substream,
1064                              struct azx_dev *azx_dev)
1065 {
1066         u32 *bdl;
1067         int i, ofs, periods, period_bytes;
1068         int pos_adj;
1069
1070         /* reset BDL address */
1071         azx_sd_writel(azx_dev, SD_BDLPL, 0);
1072         azx_sd_writel(azx_dev, SD_BDLPU, 0);
1073
1074         period_bytes = snd_pcm_lib_period_bytes(substream);
1075         azx_dev->period_bytes = period_bytes;
1076         periods = azx_dev->bufsize / period_bytes;
1077
1078         /* program the initial BDL entries */
1079         bdl = (u32 *)azx_dev->bdl.area;
1080         ofs = 0;
1081         azx_dev->frags = 0;
1082         azx_dev->irq_ignore = 0;
1083         pos_adj = bdl_pos_adj[chip->dev_index];
1084         if (pos_adj > 0) {
1085                 struct snd_pcm_runtime *runtime = substream->runtime;
1086                 int pos_align = pos_adj;
1087                 pos_adj = (pos_adj * runtime->rate + 47999) / 48000;
1088                 if (!pos_adj)
1089                         pos_adj = pos_align;
1090                 else
1091                         pos_adj = ((pos_adj + pos_align - 1) / pos_align) *
1092                                 pos_align;
1093                 pos_adj = frames_to_bytes(runtime, pos_adj);
1094                 if (pos_adj >= period_bytes) {
1095                         snd_printk(KERN_WARNING "Too big adjustment %d\n",
1096                                    bdl_pos_adj[chip->dev_index]);
1097                         pos_adj = 0;
1098                 } else {
1099                         ofs = setup_bdle(substream, azx_dev,
1100                                          &bdl, ofs, pos_adj, 1);
1101                         if (ofs < 0)
1102                                 goto error;
1103                         azx_dev->irq_ignore = 1;
1104                 }
1105         } else
1106                 pos_adj = 0;
1107         for (i = 0; i < periods; i++) {
1108                 if (i == periods - 1 && pos_adj)
1109                         ofs = setup_bdle(substream, azx_dev, &bdl, ofs,
1110                                          period_bytes - pos_adj, 0);
1111                 else
1112                         ofs = setup_bdle(substream, azx_dev, &bdl, ofs,
1113                                          period_bytes, 1);
1114                 if (ofs < 0)
1115                         goto error;
1116         }
1117         return 0;
1118
1119  error:
1120         snd_printk(KERN_ERR "Too many BDL entries: buffer=%d, period=%d\n",
1121                    azx_dev->bufsize, period_bytes);
1122         /* reset */
1123         azx_sd_writel(azx_dev, SD_BDLPL, 0);
1124         azx_sd_writel(azx_dev, SD_BDLPU, 0);
1125         return -EINVAL;
1126 }
1127
1128 /*
1129  * set up the SD for streaming
1130  */
1131 static int azx_setup_controller(struct azx *chip, struct azx_dev *azx_dev)
1132 {
1133         unsigned char val;
1134         int timeout;
1135
1136         /* make sure the run bit is zero for SD */
1137         azx_sd_writeb(azx_dev, SD_CTL, azx_sd_readb(azx_dev, SD_CTL) &
1138                       ~SD_CTL_DMA_START);
1139         /* reset stream */
1140         azx_sd_writeb(azx_dev, SD_CTL, azx_sd_readb(azx_dev, SD_CTL) |
1141                       SD_CTL_STREAM_RESET);
1142         udelay(3);
1143         timeout = 300;
1144         while (!((val = azx_sd_readb(azx_dev, SD_CTL)) & SD_CTL_STREAM_RESET) &&
1145                --timeout)
1146                 ;
1147         val &= ~SD_CTL_STREAM_RESET;
1148         azx_sd_writeb(azx_dev, SD_CTL, val);
1149         udelay(3);
1150
1151         timeout = 300;
1152         /* waiting for hardware to report that the stream is out of reset */
1153         while (((val = azx_sd_readb(azx_dev, SD_CTL)) & SD_CTL_STREAM_RESET) &&
1154                --timeout)
1155                 ;
1156
1157         /* program the stream_tag */
1158         azx_sd_writel(azx_dev, SD_CTL,
1159                       (azx_sd_readl(azx_dev, SD_CTL) & ~SD_CTL_STREAM_TAG_MASK)|
1160                       (azx_dev->stream_tag << SD_CTL_STREAM_TAG_SHIFT));
1161
1162         /* program the length of samples in cyclic buffer */
1163         azx_sd_writel(azx_dev, SD_CBL, azx_dev->bufsize);
1164
1165         /* program the stream format */
1166         /* this value needs to be the same as the one programmed */
1167         azx_sd_writew(azx_dev, SD_FORMAT, azx_dev->format_val);
1168
1169         /* program the stream LVI (last valid index) of the BDL */
1170         azx_sd_writew(azx_dev, SD_LVI, azx_dev->frags - 1);
1171
1172         /* program the BDL address */
1173         /* lower BDL address */
1174         azx_sd_writel(azx_dev, SD_BDLPL, (u32)azx_dev->bdl.addr);
1175         /* upper BDL address */
1176         azx_sd_writel(azx_dev, SD_BDLPU, upper_32_bits(azx_dev->bdl.addr));
1177
1178         /* enable the position buffer */
1179         if (chip->position_fix == POS_FIX_POSBUF ||
1180             chip->position_fix == POS_FIX_AUTO ||
1181             chip->via_dmapos_patch) {
1182                 if (!(azx_readl(chip, DPLBASE) & ICH6_DPLBASE_ENABLE))
1183                         azx_writel(chip, DPLBASE,
1184                                 (u32)chip->posbuf.addr | ICH6_DPLBASE_ENABLE);
1185         }
1186
1187         /* set the interrupt enable bits in the descriptor control register */
1188         azx_sd_writel(azx_dev, SD_CTL,
1189                       azx_sd_readl(azx_dev, SD_CTL) | SD_INT_MASK);
1190
1191         return 0;
1192 }
1193
1194 /*
1195  * Probe the given codec address
1196  */
1197 static int probe_codec(struct azx *chip, int addr)
1198 {
1199         unsigned int cmd = (addr << 28) | (AC_NODE_ROOT << 20) |
1200                 (AC_VERB_PARAMETERS << 8) | AC_PAR_VENDOR_ID;
1201         unsigned int res;
1202
1203         chip->probing = 1;
1204         azx_send_cmd(chip->bus, cmd);
1205         res = azx_get_response(chip->bus);
1206         chip->probing = 0;
1207         if (res == -1)
1208                 return -EIO;
1209         snd_printdd("hda_intel: codec #%d probed OK\n", addr);
1210         return 0;
1211 }
1212
1213 static int azx_attach_pcm_stream(struct hda_bus *bus, struct hda_codec *codec,
1214                                  struct hda_pcm *cpcm);
1215 static void azx_stop_chip(struct azx *chip);
1216
1217 /*
1218  * Codec initialization
1219  */
1220
1221 /* number of codec slots for each chipset: 0 = default slots (i.e. 4) */
1222 static unsigned int azx_max_codecs[AZX_NUM_DRIVERS] __devinitdata = {
1223         [AZX_DRIVER_TERA] = 1,
1224 };
1225
1226 static int __devinit azx_codec_create(struct azx *chip, const char *model,
1227                                       unsigned int codec_probe_mask)
1228 {
1229         struct hda_bus_template bus_temp;
1230         int c, codecs, err;
1231         int max_slots;
1232
1233         memset(&bus_temp, 0, sizeof(bus_temp));
1234         bus_temp.private_data = chip;
1235         bus_temp.modelname = model;
1236         bus_temp.pci = chip->pci;
1237         bus_temp.ops.command = azx_send_cmd;
1238         bus_temp.ops.get_response = azx_get_response;
1239         bus_temp.ops.attach_pcm = azx_attach_pcm_stream;
1240 #ifdef CONFIG_SND_HDA_POWER_SAVE
1241         bus_temp.power_save = &power_save;
1242         bus_temp.ops.pm_notify = azx_power_notify;
1243 #endif
1244
1245         err = snd_hda_bus_new(chip->card, &bus_temp, &chip->bus);
1246         if (err < 0)
1247                 return err;
1248
1249         if (chip->driver_type == AZX_DRIVER_NVIDIA)
1250                 chip->bus->needs_damn_long_delay = 1;
1251
1252         codecs = 0;
1253         max_slots = azx_max_codecs[chip->driver_type];
1254         if (!max_slots)
1255                 max_slots = AZX_MAX_CODECS;
1256
1257         /* First try to probe all given codec slots */
1258         for (c = 0; c < max_slots; c++) {
1259                 if ((chip->codec_mask & (1 << c)) & codec_probe_mask) {
1260                         if (probe_codec(chip, c) < 0) {
1261                                 /* Some BIOSen give you wrong codec addresses
1262                                  * that don't exist
1263                                  */
1264                                 snd_printk(KERN_WARNING
1265                                            "hda_intel: Codec #%d probe error; "
1266                                            "disabling it...\n", c);
1267                                 chip->codec_mask &= ~(1 << c);
1268                                 /* More badly, accessing to a non-existing
1269                                  * codec often screws up the controller chip,
1270                                  * and distrubs the further communications.
1271                                  * Thus if an error occurs during probing,
1272                                  * better to reset the controller chip to
1273                                  * get back to the sanity state.
1274                                  */
1275                                 azx_stop_chip(chip);
1276                                 azx_init_chip(chip);
1277                         }
1278                 }
1279         }
1280
1281         /* Then create codec instances */
1282         for (c = 0; c < max_slots; c++) {
1283                 if ((chip->codec_mask & (1 << c)) & codec_probe_mask) {
1284                         struct hda_codec *codec;
1285                         err = snd_hda_codec_new(chip->bus, c, &codec);
1286                         if (err < 0)
1287                                 continue;
1288                         codecs++;
1289                 }
1290         }
1291         if (!codecs) {
1292                 snd_printk(KERN_ERR SFX "no codecs initialized\n");
1293                 return -ENXIO;
1294         }
1295
1296         return 0;
1297 }
1298
1299
1300 /*
1301  * PCM support
1302  */
1303
1304 /* assign a stream for the PCM */
1305 static inline struct azx_dev *azx_assign_device(struct azx *chip, int stream)
1306 {
1307         int dev, i, nums;
1308         if (stream == SNDRV_PCM_STREAM_PLAYBACK) {
1309                 dev = chip->playback_index_offset;
1310                 nums = chip->playback_streams;
1311         } else {
1312                 dev = chip->capture_index_offset;
1313                 nums = chip->capture_streams;
1314         }
1315         for (i = 0; i < nums; i++, dev++)
1316                 if (!chip->azx_dev[dev].opened) {
1317                         chip->azx_dev[dev].opened = 1;
1318                         return &chip->azx_dev[dev];
1319                 }
1320         return NULL;
1321 }
1322
1323 /* release the assigned stream */
1324 static inline void azx_release_device(struct azx_dev *azx_dev)
1325 {
1326         azx_dev->opened = 0;
1327 }
1328
1329 static struct snd_pcm_hardware azx_pcm_hw = {
1330         .info =                 (SNDRV_PCM_INFO_MMAP |
1331                                  SNDRV_PCM_INFO_INTERLEAVED |
1332                                  SNDRV_PCM_INFO_BLOCK_TRANSFER |
1333                                  SNDRV_PCM_INFO_MMAP_VALID |
1334                                  /* No full-resume yet implemented */
1335                                  /* SNDRV_PCM_INFO_RESUME |*/
1336                                  SNDRV_PCM_INFO_PAUSE |
1337                                  SNDRV_PCM_INFO_SYNC_START),
1338         .formats =              SNDRV_PCM_FMTBIT_S16_LE,
1339         .rates =                SNDRV_PCM_RATE_48000,
1340         .rate_min =             48000,
1341         .rate_max =             48000,
1342         .channels_min =         2,
1343         .channels_max =         2,
1344         .buffer_bytes_max =     AZX_MAX_BUF_SIZE,
1345         .period_bytes_min =     128,
1346         .period_bytes_max =     AZX_MAX_BUF_SIZE / 2,
1347         .periods_min =          2,
1348         .periods_max =          AZX_MAX_FRAG,
1349         .fifo_size =            0,
1350 };
1351
1352 struct azx_pcm {
1353         struct azx *chip;
1354         struct hda_codec *codec;
1355         struct hda_pcm_stream *hinfo[2];
1356 };
1357
1358 static int azx_pcm_open(struct snd_pcm_substream *substream)
1359 {
1360         struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1361         struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream];
1362         struct azx *chip = apcm->chip;
1363         struct azx_dev *azx_dev;
1364         struct snd_pcm_runtime *runtime = substream->runtime;
1365         unsigned long flags;
1366         int err;
1367
1368         mutex_lock(&chip->open_mutex);
1369         azx_dev = azx_assign_device(chip, substream->stream);
1370         if (azx_dev == NULL) {
1371                 mutex_unlock(&chip->open_mutex);
1372                 return -EBUSY;
1373         }
1374         runtime->hw = azx_pcm_hw;
1375         runtime->hw.channels_min = hinfo->channels_min;
1376         runtime->hw.channels_max = hinfo->channels_max;
1377         runtime->hw.formats = hinfo->formats;
1378         runtime->hw.rates = hinfo->rates;
1379         snd_pcm_limit_hw_rates(runtime);
1380         snd_pcm_hw_constraint_integer(runtime, SNDRV_PCM_HW_PARAM_PERIODS);
1381         snd_pcm_hw_constraint_step(runtime, 0, SNDRV_PCM_HW_PARAM_BUFFER_BYTES,
1382                                    128);
1383         snd_pcm_hw_constraint_step(runtime, 0, SNDRV_PCM_HW_PARAM_PERIOD_BYTES,
1384                                    128);
1385         snd_hda_power_up(apcm->codec);
1386         err = hinfo->ops.open(hinfo, apcm->codec, substream);
1387         if (err < 0) {
1388                 azx_release_device(azx_dev);
1389                 snd_hda_power_down(apcm->codec);
1390                 mutex_unlock(&chip->open_mutex);
1391                 return err;
1392         }
1393         spin_lock_irqsave(&chip->reg_lock, flags);
1394         azx_dev->substream = substream;
1395         azx_dev->running = 0;
1396         spin_unlock_irqrestore(&chip->reg_lock, flags);
1397
1398         runtime->private_data = azx_dev;
1399         snd_pcm_set_sync(substream);
1400         mutex_unlock(&chip->open_mutex);
1401         return 0;
1402 }
1403
1404 static int azx_pcm_close(struct snd_pcm_substream *substream)
1405 {
1406         struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1407         struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream];
1408         struct azx *chip = apcm->chip;
1409         struct azx_dev *azx_dev = get_azx_dev(substream);
1410         unsigned long flags;
1411
1412         mutex_lock(&chip->open_mutex);
1413         spin_lock_irqsave(&chip->reg_lock, flags);
1414         azx_dev->substream = NULL;
1415         azx_dev->running = 0;
1416         spin_unlock_irqrestore(&chip->reg_lock, flags);
1417         azx_release_device(azx_dev);
1418         hinfo->ops.close(hinfo, apcm->codec, substream);
1419         snd_hda_power_down(apcm->codec);
1420         mutex_unlock(&chip->open_mutex);
1421         return 0;
1422 }
1423
1424 static int azx_pcm_hw_params(struct snd_pcm_substream *substream,
1425                              struct snd_pcm_hw_params *hw_params)
1426 {
1427         return snd_pcm_lib_malloc_pages(substream,
1428                                         params_buffer_bytes(hw_params));
1429 }
1430
1431 static int azx_pcm_hw_free(struct snd_pcm_substream *substream)
1432 {
1433         struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1434         struct azx_dev *azx_dev = get_azx_dev(substream);
1435         struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream];
1436
1437         /* reset BDL address */
1438         azx_sd_writel(azx_dev, SD_BDLPL, 0);
1439         azx_sd_writel(azx_dev, SD_BDLPU, 0);
1440         azx_sd_writel(azx_dev, SD_CTL, 0);
1441
1442         hinfo->ops.cleanup(hinfo, apcm->codec, substream);
1443
1444         return snd_pcm_lib_free_pages(substream);
1445 }
1446
1447 static int azx_pcm_prepare(struct snd_pcm_substream *substream)
1448 {
1449         struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1450         struct azx *chip = apcm->chip;
1451         struct azx_dev *azx_dev = get_azx_dev(substream);
1452         struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream];
1453         struct snd_pcm_runtime *runtime = substream->runtime;
1454
1455         azx_dev->bufsize = snd_pcm_lib_buffer_bytes(substream);
1456         azx_dev->format_val = snd_hda_calc_stream_format(runtime->rate,
1457                                                          runtime->channels,
1458                                                          runtime->format,
1459                                                          hinfo->maxbps);
1460         if (!azx_dev->format_val) {
1461                 snd_printk(KERN_ERR SFX
1462                            "invalid format_val, rate=%d, ch=%d, format=%d\n",
1463                            runtime->rate, runtime->channels, runtime->format);
1464                 return -EINVAL;
1465         }
1466
1467         snd_printdd("azx_pcm_prepare: bufsize=0x%x, format=0x%x\n",
1468                     azx_dev->bufsize, azx_dev->format_val);
1469         if (azx_setup_periods(chip, substream, azx_dev) < 0)
1470                 return -EINVAL;
1471         azx_setup_controller(chip, azx_dev);
1472         if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
1473                 azx_dev->fifo_size = azx_sd_readw(azx_dev, SD_FIFOSIZE) + 1;
1474         else
1475                 azx_dev->fifo_size = 0;
1476
1477         return hinfo->ops.prepare(hinfo, apcm->codec, azx_dev->stream_tag,
1478                                   azx_dev->format_val, substream);
1479 }
1480
1481 static int azx_pcm_trigger(struct snd_pcm_substream *substream, int cmd)
1482 {
1483         struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1484         struct azx *chip = apcm->chip;
1485         struct azx_dev *azx_dev;
1486         struct snd_pcm_substream *s;
1487         int start, nsync = 0, sbits = 0;
1488         int nwait, timeout;
1489
1490         switch (cmd) {
1491         case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
1492         case SNDRV_PCM_TRIGGER_RESUME:
1493         case SNDRV_PCM_TRIGGER_START:
1494                 start = 1;
1495                 break;
1496         case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
1497         case SNDRV_PCM_TRIGGER_SUSPEND:
1498         case SNDRV_PCM_TRIGGER_STOP:
1499                 start = 0;
1500                 break;
1501         default:
1502                 return -EINVAL;
1503         }
1504
1505         snd_pcm_group_for_each_entry(s, substream) {
1506                 if (s->pcm->card != substream->pcm->card)
1507                         continue;
1508                 azx_dev = get_azx_dev(s);
1509                 sbits |= 1 << azx_dev->index;
1510                 nsync++;
1511                 snd_pcm_trigger_done(s, substream);
1512         }
1513
1514         spin_lock(&chip->reg_lock);
1515         if (nsync > 1) {
1516                 /* first, set SYNC bits of corresponding streams */
1517                 azx_writel(chip, SYNC, azx_readl(chip, SYNC) | sbits);
1518         }
1519         snd_pcm_group_for_each_entry(s, substream) {
1520                 if (s->pcm->card != substream->pcm->card)
1521                         continue;
1522                 azx_dev = get_azx_dev(s);
1523                 if (start)
1524                         azx_stream_start(chip, azx_dev);
1525                 else
1526                         azx_stream_stop(chip, azx_dev);
1527                 azx_dev->running = start;
1528         }
1529         spin_unlock(&chip->reg_lock);
1530         if (start) {
1531                 if (nsync == 1)
1532                         return 0;
1533                 /* wait until all FIFOs get ready */
1534                 for (timeout = 5000; timeout; timeout--) {
1535                         nwait = 0;
1536                         snd_pcm_group_for_each_entry(s, substream) {
1537                                 if (s->pcm->card != substream->pcm->card)
1538                                         continue;
1539                                 azx_dev = get_azx_dev(s);
1540                                 if (!(azx_sd_readb(azx_dev, SD_STS) &
1541                                       SD_STS_FIFO_READY))
1542                                         nwait++;
1543                         }
1544                         if (!nwait)
1545                                 break;
1546                         cpu_relax();
1547                 }
1548         } else {
1549                 /* wait until all RUN bits are cleared */
1550                 for (timeout = 5000; timeout; timeout--) {
1551                         nwait = 0;
1552                         snd_pcm_group_for_each_entry(s, substream) {
1553                                 if (s->pcm->card != substream->pcm->card)
1554                                         continue;
1555                                 azx_dev = get_azx_dev(s);
1556                                 if (azx_sd_readb(azx_dev, SD_CTL) &
1557                                     SD_CTL_DMA_START)
1558                                         nwait++;
1559                         }
1560                         if (!nwait)
1561                                 break;
1562                         cpu_relax();
1563                 }
1564         }
1565         if (nsync > 1) {
1566                 spin_lock(&chip->reg_lock);
1567                 /* reset SYNC bits */
1568                 azx_writel(chip, SYNC, azx_readl(chip, SYNC) & ~sbits);
1569                 spin_unlock(&chip->reg_lock);
1570         }
1571         return 0;
1572 }
1573
1574 /* get the current DMA position with correction on VIA chips */
1575 static unsigned int azx_via_get_position(struct azx *chip,
1576                                          struct azx_dev *azx_dev)
1577 {
1578         unsigned int link_pos, mini_pos, bound_pos;
1579         unsigned int mod_link_pos, mod_dma_pos, mod_mini_pos;
1580         unsigned int fifo_size;
1581
1582         link_pos = azx_sd_readl(azx_dev, SD_LPIB);
1583         if (azx_dev->index >= 4) {
1584                 /* Playback, no problem using link position */
1585                 return link_pos;
1586         }
1587
1588         /* Capture */
1589         /* For new chipset,
1590          * use mod to get the DMA position just like old chipset
1591          */
1592         mod_dma_pos = le32_to_cpu(*azx_dev->posbuf);
1593         mod_dma_pos %= azx_dev->period_bytes;
1594
1595         /* azx_dev->fifo_size can't get FIFO size of in stream.
1596          * Get from base address + offset.
1597          */
1598         fifo_size = readw(chip->remap_addr + VIA_IN_STREAM0_FIFO_SIZE_OFFSET);
1599
1600         if (azx_dev->insufficient) {
1601                 /* Link position never gather than FIFO size */
1602                 if (link_pos <= fifo_size)
1603                         return 0;
1604
1605                 azx_dev->insufficient = 0;
1606         }
1607
1608         if (link_pos <= fifo_size)
1609                 mini_pos = azx_dev->bufsize + link_pos - fifo_size;
1610         else
1611                 mini_pos = link_pos - fifo_size;
1612
1613         /* Find nearest previous boudary */
1614         mod_mini_pos = mini_pos % azx_dev->period_bytes;
1615         mod_link_pos = link_pos % azx_dev->period_bytes;
1616         if (mod_link_pos >= fifo_size)
1617                 bound_pos = link_pos - mod_link_pos;
1618         else if (mod_dma_pos >= mod_mini_pos)
1619                 bound_pos = mini_pos - mod_mini_pos;
1620         else {
1621                 bound_pos = mini_pos - mod_mini_pos + azx_dev->period_bytes;
1622                 if (bound_pos >= azx_dev->bufsize)
1623                         bound_pos = 0;
1624         }
1625
1626         /* Calculate real DMA position we want */
1627         return bound_pos + mod_dma_pos;
1628 }
1629
1630 static unsigned int azx_get_position(struct azx *chip,
1631                                      struct azx_dev *azx_dev)
1632 {
1633         unsigned int pos;
1634
1635         if (chip->via_dmapos_patch)
1636                 pos = azx_via_get_position(chip, azx_dev);
1637         else if (chip->position_fix == POS_FIX_POSBUF ||
1638                  chip->position_fix == POS_FIX_AUTO) {
1639                 /* use the position buffer */
1640                 pos = le32_to_cpu(*azx_dev->posbuf);
1641         } else {
1642                 /* read LPIB */
1643                 pos = azx_sd_readl(azx_dev, SD_LPIB);
1644         }
1645         if (pos >= azx_dev->bufsize)
1646                 pos = 0;
1647         return pos;
1648 }
1649
1650 static snd_pcm_uframes_t azx_pcm_pointer(struct snd_pcm_substream *substream)
1651 {
1652         struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1653         struct azx *chip = apcm->chip;
1654         struct azx_dev *azx_dev = get_azx_dev(substream);
1655         return bytes_to_frames(substream->runtime,
1656                                azx_get_position(chip, azx_dev));
1657 }
1658
1659 /*
1660  * Check whether the current DMA position is acceptable for updating
1661  * periods.  Returns non-zero if it's OK.
1662  *
1663  * Many HD-audio controllers appear pretty inaccurate about
1664  * the update-IRQ timing.  The IRQ is issued before actually the
1665  * data is processed.  So, we need to process it afterwords in a
1666  * workqueue.
1667  */
1668 static int azx_position_ok(struct azx *chip, struct azx_dev *azx_dev)
1669 {
1670         unsigned int pos;
1671
1672         pos = azx_get_position(chip, azx_dev);
1673         if (chip->position_fix == POS_FIX_AUTO) {
1674                 if (!pos) {
1675                         printk(KERN_WARNING
1676                                "hda-intel: Invalid position buffer, "
1677                                "using LPIB read method instead.\n");
1678                         chip->position_fix = POS_FIX_LPIB;
1679                         pos = azx_get_position(chip, azx_dev);
1680                 } else
1681                         chip->position_fix = POS_FIX_POSBUF;
1682         }
1683
1684         if (!bdl_pos_adj[chip->dev_index])
1685                 return 1; /* no delayed ack */
1686         if (pos % azx_dev->period_bytes > azx_dev->period_bytes / 2)
1687                 return 0; /* NG - it's below the period boundary */
1688         return 1; /* OK, it's fine */
1689 }
1690
1691 /*
1692  * The work for pending PCM period updates.
1693  */
1694 static void azx_irq_pending_work(struct work_struct *work)
1695 {
1696         struct azx *chip = container_of(work, struct azx, irq_pending_work);
1697         int i, pending;
1698
1699         if (!chip->irq_pending_warned) {
1700                 printk(KERN_WARNING
1701                        "hda-intel: IRQ timing workaround is activated "
1702                        "for card #%d. Suggest a bigger bdl_pos_adj.\n",
1703                        chip->card->number);
1704                 chip->irq_pending_warned = 1;
1705         }
1706
1707         for (;;) {
1708                 pending = 0;
1709                 spin_lock_irq(&chip->reg_lock);
1710                 for (i = 0; i < chip->num_streams; i++) {
1711                         struct azx_dev *azx_dev = &chip->azx_dev[i];
1712                         if (!azx_dev->irq_pending ||
1713                             !azx_dev->substream ||
1714                             !azx_dev->running)
1715                                 continue;
1716                         if (azx_position_ok(chip, azx_dev)) {
1717                                 azx_dev->irq_pending = 0;
1718                                 spin_unlock(&chip->reg_lock);
1719                                 snd_pcm_period_elapsed(azx_dev->substream);
1720                                 spin_lock(&chip->reg_lock);
1721                         } else
1722                                 pending++;
1723                 }
1724                 spin_unlock_irq(&chip->reg_lock);
1725                 if (!pending)
1726                         return;
1727                 cond_resched();
1728         }
1729 }
1730
1731 /* clear irq_pending flags and assure no on-going workq */
1732 static void azx_clear_irq_pending(struct azx *chip)
1733 {
1734         int i;
1735
1736         spin_lock_irq(&chip->reg_lock);
1737         for (i = 0; i < chip->num_streams; i++)
1738                 chip->azx_dev[i].irq_pending = 0;
1739         spin_unlock_irq(&chip->reg_lock);
1740         flush_scheduled_work();
1741 }
1742
1743 static struct snd_pcm_ops azx_pcm_ops = {
1744         .open = azx_pcm_open,
1745         .close = azx_pcm_close,
1746         .ioctl = snd_pcm_lib_ioctl,
1747         .hw_params = azx_pcm_hw_params,
1748         .hw_free = azx_pcm_hw_free,
1749         .prepare = azx_pcm_prepare,
1750         .trigger = azx_pcm_trigger,
1751         .pointer = azx_pcm_pointer,
1752         .page = snd_pcm_sgbuf_ops_page,
1753 };
1754
1755 static void azx_pcm_free(struct snd_pcm *pcm)
1756 {
1757         struct azx_pcm *apcm = pcm->private_data;
1758         if (apcm) {
1759                 apcm->chip->pcm[pcm->device] = NULL;
1760                 kfree(apcm);
1761         }
1762 }
1763
1764 static int
1765 azx_attach_pcm_stream(struct hda_bus *bus, struct hda_codec *codec,
1766                       struct hda_pcm *cpcm)
1767 {
1768         struct azx *chip = bus->private_data;
1769         struct snd_pcm *pcm;
1770         struct azx_pcm *apcm;
1771         int pcm_dev = cpcm->device;
1772         int s, err;
1773
1774         if (pcm_dev >= AZX_MAX_PCMS) {
1775                 snd_printk(KERN_ERR SFX "Invalid PCM device number %d\n",
1776                            pcm_dev);
1777                 return -EINVAL;
1778         }
1779         if (chip->pcm[pcm_dev]) {
1780                 snd_printk(KERN_ERR SFX "PCM %d already exists\n", pcm_dev);
1781                 return -EBUSY;
1782         }
1783         err = snd_pcm_new(chip->card, cpcm->name, pcm_dev,
1784                           cpcm->stream[SNDRV_PCM_STREAM_PLAYBACK].substreams,
1785                           cpcm->stream[SNDRV_PCM_STREAM_CAPTURE].substreams,
1786                           &pcm);
1787         if (err < 0)
1788                 return err;
1789         strcpy(pcm->name, cpcm->name);
1790         apcm = kzalloc(sizeof(*apcm), GFP_KERNEL);
1791         if (apcm == NULL)
1792                 return -ENOMEM;
1793         apcm->chip = chip;
1794         apcm->codec = codec;
1795         pcm->private_data = apcm;
1796         pcm->private_free = azx_pcm_free;
1797         if (cpcm->pcm_type == HDA_PCM_TYPE_MODEM)
1798                 pcm->dev_class = SNDRV_PCM_CLASS_MODEM;
1799         chip->pcm[pcm_dev] = pcm;
1800         cpcm->pcm = pcm;
1801         for (s = 0; s < 2; s++) {
1802                 apcm->hinfo[s] = &cpcm->stream[s];
1803                 if (cpcm->stream[s].substreams)
1804                         snd_pcm_set_ops(pcm, s, &azx_pcm_ops);
1805         }
1806         /* buffer pre-allocation */
1807         snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV_SG,
1808                                               snd_dma_pci_data(chip->pci),
1809                                               1024 * 64, 32 * 1024 * 1024);
1810         return 0;
1811 }
1812
1813 /*
1814  * mixer creation - all stuff is implemented in hda module
1815  */
1816 static int __devinit azx_mixer_create(struct azx *chip)
1817 {
1818         return snd_hda_build_controls(chip->bus);
1819 }
1820
1821
1822 /*
1823  * initialize SD streams
1824  */
1825 static int __devinit azx_init_stream(struct azx *chip)
1826 {
1827         int i;
1828
1829         /* initialize each stream (aka device)
1830          * assign the starting bdl address to each stream (device)
1831          * and initialize
1832          */
1833         for (i = 0; i < chip->num_streams; i++) {
1834                 struct azx_dev *azx_dev = &chip->azx_dev[i];
1835                 azx_dev->posbuf = (u32 __iomem *)(chip->posbuf.area + i * 8);
1836                 /* offset: SDI0=0x80, SDI1=0xa0, ... SDO3=0x160 */
1837                 azx_dev->sd_addr = chip->remap_addr + (0x20 * i + 0x80);
1838                 /* int mask: SDI0=0x01, SDI1=0x02, ... SDO3=0x80 */
1839                 azx_dev->sd_int_sta_mask = 1 << i;
1840                 /* stream tag: must be non-zero and unique */
1841                 azx_dev->index = i;
1842                 azx_dev->stream_tag = i + 1;
1843         }
1844
1845         return 0;
1846 }
1847
1848 static int azx_acquire_irq(struct azx *chip, int do_disconnect)
1849 {
1850         if (request_irq(chip->pci->irq, azx_interrupt,
1851                         chip->msi ? 0 : IRQF_SHARED,
1852                         "HDA Intel", chip)) {
1853                 printk(KERN_ERR "hda-intel: unable to grab IRQ %d, "
1854                        "disabling device\n", chip->pci->irq);
1855                 if (do_disconnect)
1856                         snd_card_disconnect(chip->card);
1857                 return -1;
1858         }
1859         chip->irq = chip->pci->irq;
1860         pci_intx(chip->pci, !chip->msi);
1861         return 0;
1862 }
1863
1864
1865 static void azx_stop_chip(struct azx *chip)
1866 {
1867         if (!chip->initialized)
1868                 return;
1869
1870         /* disable interrupts */
1871         azx_int_disable(chip);
1872         azx_int_clear(chip);
1873
1874         /* disable CORB/RIRB */
1875         azx_free_cmd_io(chip);
1876
1877         /* disable position buffer */
1878         azx_writel(chip, DPLBASE, 0);
1879         azx_writel(chip, DPUBASE, 0);
1880
1881         chip->initialized = 0;
1882 }
1883
1884 #ifdef CONFIG_SND_HDA_POWER_SAVE
1885 /* power-up/down the controller */
1886 static void azx_power_notify(struct hda_bus *bus)
1887 {
1888         struct azx *chip = bus->private_data;
1889         struct hda_codec *c;
1890         int power_on = 0;
1891
1892         list_for_each_entry(c, &bus->codec_list, list) {
1893                 if (c->power_on) {
1894                         power_on = 1;
1895                         break;
1896                 }
1897         }
1898         if (power_on)
1899                 azx_init_chip(chip);
1900         else if (chip->running && power_save_controller)
1901                 azx_stop_chip(chip);
1902 }
1903 #endif /* CONFIG_SND_HDA_POWER_SAVE */
1904
1905 #ifdef CONFIG_PM
1906 /*
1907  * power management
1908  */
1909
1910 static int snd_hda_codecs_inuse(struct hda_bus *bus)
1911 {
1912         struct hda_codec *codec;
1913
1914         list_for_each_entry(codec, &bus->codec_list, list) {
1915                 if (snd_hda_codec_needs_resume(codec))
1916                         return 1;
1917         }
1918         return 0;
1919 }
1920
1921 static int azx_suspend(struct pci_dev *pci, pm_message_t state)
1922 {
1923         struct snd_card *card = pci_get_drvdata(pci);
1924         struct azx *chip = card->private_data;
1925         int i;
1926
1927         snd_power_change_state(card, SNDRV_CTL_POWER_D3hot);
1928         azx_clear_irq_pending(chip);
1929         for (i = 0; i < AZX_MAX_PCMS; i++)
1930                 snd_pcm_suspend_all(chip->pcm[i]);
1931         if (chip->initialized)
1932                 snd_hda_suspend(chip->bus, state);
1933         azx_stop_chip(chip);
1934         if (chip->irq >= 0) {
1935                 free_irq(chip->irq, chip);
1936                 chip->irq = -1;
1937         }
1938         if (chip->msi)
1939                 pci_disable_msi(chip->pci);
1940         pci_disable_device(pci);
1941         pci_save_state(pci);
1942         pci_set_power_state(pci, pci_choose_state(pci, state));
1943         return 0;
1944 }
1945
1946 static int azx_resume(struct pci_dev *pci)
1947 {
1948         struct snd_card *card = pci_get_drvdata(pci);
1949         struct azx *chip = card->private_data;
1950
1951         pci_set_power_state(pci, PCI_D0);
1952         pci_restore_state(pci);
1953         if (pci_enable_device(pci) < 0) {
1954                 printk(KERN_ERR "hda-intel: pci_enable_device failed, "
1955                        "disabling device\n");
1956                 snd_card_disconnect(card);
1957                 return -EIO;
1958         }
1959         pci_set_master(pci);
1960         if (chip->msi)
1961                 if (pci_enable_msi(pci) < 0)
1962                         chip->msi = 0;
1963         if (azx_acquire_irq(chip, 1) < 0)
1964                 return -EIO;
1965         azx_init_pci(chip);
1966
1967         if (snd_hda_codecs_inuse(chip->bus))
1968                 azx_init_chip(chip);
1969
1970         snd_hda_resume(chip->bus);
1971         snd_power_change_state(card, SNDRV_CTL_POWER_D0);
1972         return 0;
1973 }
1974 #endif /* CONFIG_PM */
1975
1976
1977 /*
1978  * reboot notifier for hang-up problem at power-down
1979  */
1980 static int azx_halt(struct notifier_block *nb, unsigned long event, void *buf)
1981 {
1982         struct azx *chip = container_of(nb, struct azx, reboot_notifier);
1983         azx_stop_chip(chip);
1984         return NOTIFY_OK;
1985 }
1986
1987 static void azx_notifier_register(struct azx *chip)
1988 {
1989         chip->reboot_notifier.notifier_call = azx_halt;
1990         register_reboot_notifier(&chip->reboot_notifier);
1991 }
1992
1993 static void azx_notifier_unregister(struct azx *chip)
1994 {
1995         if (chip->reboot_notifier.notifier_call)
1996                 unregister_reboot_notifier(&chip->reboot_notifier);
1997 }
1998
1999 /*
2000  * destructor
2001  */
2002 static int azx_free(struct azx *chip)
2003 {
2004         int i;
2005
2006         azx_notifier_unregister(chip);
2007
2008         if (chip->initialized) {
2009                 azx_clear_irq_pending(chip);
2010                 for (i = 0; i < chip->num_streams; i++)
2011                         azx_stream_stop(chip, &chip->azx_dev[i]);
2012                 azx_stop_chip(chip);
2013         }
2014
2015         if (chip->irq >= 0)
2016                 free_irq(chip->irq, (void*)chip);
2017         if (chip->msi)
2018                 pci_disable_msi(chip->pci);
2019         if (chip->remap_addr)
2020                 iounmap(chip->remap_addr);
2021
2022         if (chip->azx_dev) {
2023                 for (i = 0; i < chip->num_streams; i++)
2024                         if (chip->azx_dev[i].bdl.area)
2025                                 snd_dma_free_pages(&chip->azx_dev[i].bdl);
2026         }
2027         if (chip->rb.area)
2028                 snd_dma_free_pages(&chip->rb);
2029         if (chip->posbuf.area)
2030                 snd_dma_free_pages(&chip->posbuf);
2031         pci_release_regions(chip->pci);
2032         pci_disable_device(chip->pci);
2033         kfree(chip->azx_dev);
2034         kfree(chip);
2035
2036         return 0;
2037 }
2038
2039 static int azx_dev_free(struct snd_device *device)
2040 {
2041         return azx_free(device->device_data);
2042 }
2043
2044 /*
2045  * white/black-listing for position_fix
2046  */
2047 static struct snd_pci_quirk position_fix_list[] __devinitdata = {
2048         SND_PCI_QUIRK(0x1028, 0x01cc, "Dell D820", POS_FIX_LPIB),
2049         SND_PCI_QUIRK(0x1028, 0x01de, "Dell Precision 390", POS_FIX_LPIB),
2050         SND_PCI_QUIRK(0x1043, 0x813d, "ASUS P5AD2", POS_FIX_LPIB),
2051         {}
2052 };
2053
2054 static int __devinit check_position_fix(struct azx *chip, int fix)
2055 {
2056         const struct snd_pci_quirk *q;
2057
2058         /* Check VIA HD Audio Controller exist */
2059         if (chip->pci->vendor == PCI_VENDOR_ID_VIA &&
2060             chip->pci->device == VIA_HDAC_DEVICE_ID) {
2061                 chip->via_dmapos_patch = 1;
2062                 /* Use link position directly, avoid any transfer problem. */
2063                 return POS_FIX_LPIB;
2064         }
2065         chip->via_dmapos_patch = 0;
2066
2067         if (fix == POS_FIX_AUTO) {
2068                 q = snd_pci_quirk_lookup(chip->pci, position_fix_list);
2069                 if (q) {
2070                         printk(KERN_INFO
2071                                     "hda_intel: position_fix set to %d "
2072                                     "for device %04x:%04x\n",
2073                                     q->value, q->subvendor, q->subdevice);
2074                         return q->value;
2075                 }
2076         }
2077         return fix;
2078 }
2079
2080 /*
2081  * black-lists for probe_mask
2082  */
2083 static struct snd_pci_quirk probe_mask_list[] __devinitdata = {
2084         /* Thinkpad often breaks the controller communication when accessing
2085          * to the non-working (or non-existing) modem codec slot.
2086          */
2087         SND_PCI_QUIRK(0x1014, 0x05b7, "Thinkpad Z60", 0x01),
2088         SND_PCI_QUIRK(0x17aa, 0x2010, "Thinkpad X/T/R60", 0x01),
2089         SND_PCI_QUIRK(0x17aa, 0x20ac, "Thinkpad X/T/R61", 0x01),
2090         /* broken BIOS */
2091         SND_PCI_QUIRK(0x1028, 0x20ac, "Dell Studio Desktop", 0x01),
2092         /* including bogus ALC268 in slot#2 that conflicts with ALC888 */
2093         SND_PCI_QUIRK(0x17c0, 0x4085, "Medion MD96630", 0x01),
2094         {}
2095 };
2096
2097 static void __devinit check_probe_mask(struct azx *chip, int dev)
2098 {
2099         const struct snd_pci_quirk *q;
2100
2101         if (probe_mask[dev] == -1) {
2102                 q = snd_pci_quirk_lookup(chip->pci, probe_mask_list);
2103                 if (q) {
2104                         printk(KERN_INFO
2105                                "hda_intel: probe_mask set to 0x%x "
2106                                "for device %04x:%04x\n",
2107                                q->value, q->subvendor, q->subdevice);
2108                         probe_mask[dev] = q->value;
2109                 }
2110         }
2111 }
2112
2113
2114 /*
2115  * constructor
2116  */
2117 static int __devinit azx_create(struct snd_card *card, struct pci_dev *pci,
2118                                 int dev, int driver_type,
2119                                 struct azx **rchip)
2120 {
2121         struct azx *chip;
2122         int i, err;
2123         unsigned short gcap;
2124         static struct snd_device_ops ops = {
2125                 .dev_free = azx_dev_free,
2126         };
2127
2128         *rchip = NULL;
2129
2130         err = pci_enable_device(pci);
2131         if (err < 0)
2132                 return err;
2133
2134         chip = kzalloc(sizeof(*chip), GFP_KERNEL);
2135         if (!chip) {
2136                 snd_printk(KERN_ERR SFX "cannot allocate chip\n");
2137                 pci_disable_device(pci);
2138                 return -ENOMEM;
2139         }
2140
2141         spin_lock_init(&chip->reg_lock);
2142         mutex_init(&chip->open_mutex);
2143         chip->card = card;
2144         chip->pci = pci;
2145         chip->irq = -1;
2146         chip->driver_type = driver_type;
2147         chip->msi = enable_msi;
2148         chip->dev_index = dev;
2149         INIT_WORK(&chip->irq_pending_work, azx_irq_pending_work);
2150
2151         chip->position_fix = check_position_fix(chip, position_fix[dev]);
2152         check_probe_mask(chip, dev);
2153
2154         chip->single_cmd = single_cmd;
2155
2156         if (bdl_pos_adj[dev] < 0) {
2157                 switch (chip->driver_type) {
2158                 case AZX_DRIVER_ICH:
2159                         bdl_pos_adj[dev] = 1;
2160                         break;
2161                 default:
2162                         bdl_pos_adj[dev] = 32;
2163                         break;
2164                 }
2165         }
2166
2167 #if BITS_PER_LONG != 64
2168         /* Fix up base address on ULI M5461 */
2169         if (chip->driver_type == AZX_DRIVER_ULI) {
2170                 u16 tmp3;
2171                 pci_read_config_word(pci, 0x40, &tmp3);
2172                 pci_write_config_word(pci, 0x40, tmp3 | 0x10);
2173                 pci_write_config_dword(pci, PCI_BASE_ADDRESS_1, 0);
2174         }
2175 #endif
2176
2177         err = pci_request_regions(pci, "ICH HD audio");
2178         if (err < 0) {
2179                 kfree(chip);
2180                 pci_disable_device(pci);
2181                 return err;
2182         }
2183
2184         chip->addr = pci_resource_start(pci, 0);
2185         chip->remap_addr = pci_ioremap_bar(pci, 0);
2186         if (chip->remap_addr == NULL) {
2187                 snd_printk(KERN_ERR SFX "ioremap error\n");
2188                 err = -ENXIO;
2189                 goto errout;
2190         }
2191
2192         if (chip->msi)
2193                 if (pci_enable_msi(pci) < 0)
2194                         chip->msi = 0;
2195
2196         if (azx_acquire_irq(chip, 0) < 0) {
2197                 err = -EBUSY;
2198                 goto errout;
2199         }
2200
2201         pci_set_master(pci);
2202         synchronize_irq(chip->irq);
2203
2204         gcap = azx_readw(chip, GCAP);
2205         snd_printdd("chipset global capabilities = 0x%x\n", gcap);
2206
2207         /* allow 64bit DMA address if supported by H/W */
2208         if ((gcap & 0x01) && !pci_set_dma_mask(pci, DMA_64BIT_MASK))
2209                 pci_set_consistent_dma_mask(pci, DMA_64BIT_MASK);
2210
2211         /* read number of streams from GCAP register instead of using
2212          * hardcoded value
2213          */
2214         chip->capture_streams = (gcap >> 8) & 0x0f;
2215         chip->playback_streams = (gcap >> 12) & 0x0f;
2216         if (!chip->playback_streams && !chip->capture_streams) {
2217                 /* gcap didn't give any info, switching to old method */
2218
2219                 switch (chip->driver_type) {
2220                 case AZX_DRIVER_ULI:
2221                         chip->playback_streams = ULI_NUM_PLAYBACK;
2222                         chip->capture_streams = ULI_NUM_CAPTURE;
2223                         break;
2224                 case AZX_DRIVER_ATIHDMI:
2225                         chip->playback_streams = ATIHDMI_NUM_PLAYBACK;
2226                         chip->capture_streams = ATIHDMI_NUM_CAPTURE;
2227                         break;
2228                 case AZX_DRIVER_GENERIC:
2229                 default:
2230                         chip->playback_streams = ICH6_NUM_PLAYBACK;
2231                         chip->capture_streams = ICH6_NUM_CAPTURE;
2232                         break;
2233                 }
2234         }
2235         chip->capture_index_offset = 0;
2236         chip->playback_index_offset = chip->capture_streams;
2237         chip->num_streams = chip->playback_streams + chip->capture_streams;
2238         chip->azx_dev = kcalloc(chip->num_streams, sizeof(*chip->azx_dev),
2239                                 GFP_KERNEL);
2240         if (!chip->azx_dev) {
2241                 snd_printk(KERN_ERR "cannot malloc azx_dev\n");
2242                 goto errout;
2243         }
2244
2245         for (i = 0; i < chip->num_streams; i++) {
2246                 /* allocate memory for the BDL for each stream */
2247                 err = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV,
2248                                           snd_dma_pci_data(chip->pci),
2249                                           BDL_SIZE, &chip->azx_dev[i].bdl);
2250                 if (err < 0) {
2251                         snd_printk(KERN_ERR SFX "cannot allocate BDL\n");
2252                         goto errout;
2253                 }
2254         }
2255         /* allocate memory for the position buffer */
2256         err = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV,
2257                                   snd_dma_pci_data(chip->pci),
2258                                   chip->num_streams * 8, &chip->posbuf);
2259         if (err < 0) {
2260                 snd_printk(KERN_ERR SFX "cannot allocate posbuf\n");
2261                 goto errout;
2262         }
2263         /* allocate CORB/RIRB */
2264         if (!chip->single_cmd) {
2265                 err = azx_alloc_cmd_io(chip);
2266                 if (err < 0)
2267                         goto errout;
2268         }
2269
2270         /* initialize streams */
2271         azx_init_stream(chip);
2272
2273         /* initialize chip */
2274         azx_init_pci(chip);
2275         azx_init_chip(chip);
2276
2277         /* codec detection */
2278         if (!chip->codec_mask) {
2279                 snd_printk(KERN_ERR SFX "no codecs found!\n");
2280                 err = -ENODEV;
2281                 goto errout;
2282         }
2283
2284         err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, chip, &ops);
2285         if (err <0) {
2286                 snd_printk(KERN_ERR SFX "Error creating device [card]!\n");
2287                 goto errout;
2288         }
2289
2290         strcpy(card->driver, "HDA-Intel");
2291         strcpy(card->shortname, driver_short_names[chip->driver_type]);
2292         sprintf(card->longname, "%s at 0x%lx irq %i",
2293                 card->shortname, chip->addr, chip->irq);
2294
2295         *rchip = chip;
2296         return 0;
2297
2298  errout:
2299         azx_free(chip);
2300         return err;
2301 }
2302
2303 static void power_down_all_codecs(struct azx *chip)
2304 {
2305 #ifdef CONFIG_SND_HDA_POWER_SAVE
2306         /* The codecs were powered up in snd_hda_codec_new().
2307          * Now all initialization done, so turn them down if possible
2308          */
2309         struct hda_codec *codec;
2310         list_for_each_entry(codec, &chip->bus->codec_list, list) {
2311                 snd_hda_power_down(codec);
2312         }
2313 #endif
2314 }
2315
2316 static int __devinit azx_probe(struct pci_dev *pci,
2317                                const struct pci_device_id *pci_id)
2318 {
2319         static int dev;
2320         struct snd_card *card;
2321         struct azx *chip;
2322         int err;
2323
2324         if (dev >= SNDRV_CARDS)
2325                 return -ENODEV;
2326         if (!enable[dev]) {
2327                 dev++;
2328                 return -ENOENT;
2329         }
2330
2331         card = snd_card_new(index[dev], id[dev], THIS_MODULE, 0);
2332         if (!card) {
2333                 snd_printk(KERN_ERR SFX "Error creating card!\n");
2334                 return -ENOMEM;
2335         }
2336
2337         err = azx_create(card, pci, dev, pci_id->driver_data, &chip);
2338         if (err < 0)
2339                 goto out_free;
2340         card->private_data = chip;
2341
2342         /* create codec instances */
2343         err = azx_codec_create(chip, model[dev], probe_mask[dev]);
2344         if (err < 0)
2345                 goto out_free;
2346
2347         /* create PCM streams */
2348         err = snd_hda_build_pcms(chip->bus);
2349         if (err < 0)
2350                 goto out_free;
2351
2352         /* create mixer controls */
2353         err = azx_mixer_create(chip);
2354         if (err < 0)
2355                 goto out_free;
2356
2357         snd_card_set_dev(card, &pci->dev);
2358
2359         err = snd_card_register(card);
2360         if (err < 0)
2361                 goto out_free;
2362
2363         pci_set_drvdata(pci, card);
2364         chip->running = 1;
2365         power_down_all_codecs(chip);
2366         azx_notifier_register(chip);
2367
2368         dev++;
2369         return err;
2370 out_free:
2371         snd_card_free(card);
2372         return err;
2373 }
2374
2375 static void __devexit azx_remove(struct pci_dev *pci)
2376 {
2377         snd_card_free(pci_get_drvdata(pci));
2378         pci_set_drvdata(pci, NULL);
2379 }
2380
2381 /* PCI IDs */
2382 static struct pci_device_id azx_ids[] = {
2383         /* ICH 6..10 */
2384         { PCI_DEVICE(0x8086, 0x2668), .driver_data = AZX_DRIVER_ICH },
2385         { PCI_DEVICE(0x8086, 0x27d8), .driver_data = AZX_DRIVER_ICH },
2386         { PCI_DEVICE(0x8086, 0x269a), .driver_data = AZX_DRIVER_ICH },
2387         { PCI_DEVICE(0x8086, 0x284b), .driver_data = AZX_DRIVER_ICH },
2388         { PCI_DEVICE(0x8086, 0x2911), .driver_data = AZX_DRIVER_ICH },
2389         { PCI_DEVICE(0x8086, 0x293e), .driver_data = AZX_DRIVER_ICH },
2390         { PCI_DEVICE(0x8086, 0x293f), .driver_data = AZX_DRIVER_ICH },
2391         { PCI_DEVICE(0x8086, 0x3a3e), .driver_data = AZX_DRIVER_ICH },
2392         { PCI_DEVICE(0x8086, 0x3a6e), .driver_data = AZX_DRIVER_ICH },
2393         /* PCH */
2394         { PCI_DEVICE(0x8086, 0x3b56), .driver_data = AZX_DRIVER_ICH },
2395         /* SCH */
2396         { PCI_DEVICE(0x8086, 0x811b), .driver_data = AZX_DRIVER_SCH },
2397         /* ATI SB 450/600 */
2398         { PCI_DEVICE(0x1002, 0x437b), .driver_data = AZX_DRIVER_ATI },
2399         { PCI_DEVICE(0x1002, 0x4383), .driver_data = AZX_DRIVER_ATI },
2400         /* ATI HDMI */
2401         { PCI_DEVICE(0x1002, 0x793b), .driver_data = AZX_DRIVER_ATIHDMI },
2402         { PCI_DEVICE(0x1002, 0x7919), .driver_data = AZX_DRIVER_ATIHDMI },
2403         { PCI_DEVICE(0x1002, 0x960f), .driver_data = AZX_DRIVER_ATIHDMI },
2404         { PCI_DEVICE(0x1002, 0x970f), .driver_data = AZX_DRIVER_ATIHDMI },
2405         { PCI_DEVICE(0x1002, 0xaa00), .driver_data = AZX_DRIVER_ATIHDMI },
2406         { PCI_DEVICE(0x1002, 0xaa08), .driver_data = AZX_DRIVER_ATIHDMI },
2407         { PCI_DEVICE(0x1002, 0xaa10), .driver_data = AZX_DRIVER_ATIHDMI },
2408         { PCI_DEVICE(0x1002, 0xaa18), .driver_data = AZX_DRIVER_ATIHDMI },
2409         { PCI_DEVICE(0x1002, 0xaa20), .driver_data = AZX_DRIVER_ATIHDMI },
2410         { PCI_DEVICE(0x1002, 0xaa28), .driver_data = AZX_DRIVER_ATIHDMI },
2411         { PCI_DEVICE(0x1002, 0xaa30), .driver_data = AZX_DRIVER_ATIHDMI },
2412         { PCI_DEVICE(0x1002, 0xaa38), .driver_data = AZX_DRIVER_ATIHDMI },
2413         { PCI_DEVICE(0x1002, 0xaa40), .driver_data = AZX_DRIVER_ATIHDMI },
2414         { PCI_DEVICE(0x1002, 0xaa48), .driver_data = AZX_DRIVER_ATIHDMI },
2415         /* VIA VT8251/VT8237A */
2416         { PCI_DEVICE(0x1106, 0x3288), .driver_data = AZX_DRIVER_VIA },
2417         /* SIS966 */
2418         { PCI_DEVICE(0x1039, 0x7502), .driver_data = AZX_DRIVER_SIS },
2419         /* ULI M5461 */
2420         { PCI_DEVICE(0x10b9, 0x5461), .driver_data = AZX_DRIVER_ULI },
2421         /* NVIDIA MCP */
2422         { PCI_DEVICE(0x10de, 0x026c), .driver_data = AZX_DRIVER_NVIDIA },
2423         { PCI_DEVICE(0x10de, 0x0371), .driver_data = AZX_DRIVER_NVIDIA },
2424         { PCI_DEVICE(0x10de, 0x03e4), .driver_data = AZX_DRIVER_NVIDIA },
2425         { PCI_DEVICE(0x10de, 0x03f0), .driver_data = AZX_DRIVER_NVIDIA },
2426         { PCI_DEVICE(0x10de, 0x044a), .driver_data = AZX_DRIVER_NVIDIA },
2427         { PCI_DEVICE(0x10de, 0x044b), .driver_data = AZX_DRIVER_NVIDIA },
2428         { PCI_DEVICE(0x10de, 0x055c), .driver_data = AZX_DRIVER_NVIDIA },
2429         { PCI_DEVICE(0x10de, 0x055d), .driver_data = AZX_DRIVER_NVIDIA },
2430         { PCI_DEVICE(0x10de, 0x0774), .driver_data = AZX_DRIVER_NVIDIA },
2431         { PCI_DEVICE(0x10de, 0x0775), .driver_data = AZX_DRIVER_NVIDIA },
2432         { PCI_DEVICE(0x10de, 0x0776), .driver_data = AZX_DRIVER_NVIDIA },
2433         { PCI_DEVICE(0x10de, 0x0777), .driver_data = AZX_DRIVER_NVIDIA },
2434         { PCI_DEVICE(0x10de, 0x07fc), .driver_data = AZX_DRIVER_NVIDIA },
2435         { PCI_DEVICE(0x10de, 0x07fd), .driver_data = AZX_DRIVER_NVIDIA },
2436         { PCI_DEVICE(0x10de, 0x0ac0), .driver_data = AZX_DRIVER_NVIDIA },
2437         { PCI_DEVICE(0x10de, 0x0ac1), .driver_data = AZX_DRIVER_NVIDIA },
2438         { PCI_DEVICE(0x10de, 0x0ac2), .driver_data = AZX_DRIVER_NVIDIA },
2439         { PCI_DEVICE(0x10de, 0x0ac3), .driver_data = AZX_DRIVER_NVIDIA },
2440         { PCI_DEVICE(0x10de, 0x0bd4), .driver_data = AZX_DRIVER_NVIDIA },
2441         { PCI_DEVICE(0x10de, 0x0bd5), .driver_data = AZX_DRIVER_NVIDIA },
2442         { PCI_DEVICE(0x10de, 0x0bd6), .driver_data = AZX_DRIVER_NVIDIA },
2443         { PCI_DEVICE(0x10de, 0x0bd7), .driver_data = AZX_DRIVER_NVIDIA },
2444         /* Teradici */
2445         { PCI_DEVICE(0x6549, 0x1200), .driver_data = AZX_DRIVER_TERA },
2446         /* AMD Generic, PCI class code and Vendor ID for HD Audio */
2447         { PCI_DEVICE(PCI_VENDOR_ID_ATI, PCI_ANY_ID),
2448           .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
2449           .class_mask = 0xffffff,
2450           .driver_data = AZX_DRIVER_GENERIC },
2451         { 0, }
2452 };
2453 MODULE_DEVICE_TABLE(pci, azx_ids);
2454
2455 /* pci_driver definition */
2456 static struct pci_driver driver = {
2457         .name = "HDA Intel",
2458         .id_table = azx_ids,
2459         .probe = azx_probe,
2460         .remove = __devexit_p(azx_remove),
2461 #ifdef CONFIG_PM
2462         .suspend = azx_suspend,
2463         .resume = azx_resume,
2464 #endif
2465 };
2466
2467 static int __init alsa_card_azx_init(void)
2468 {
2469         return pci_register_driver(&driver);
2470 }
2471
2472 static void __exit alsa_card_azx_exit(void)
2473 {
2474         pci_unregister_driver(&driver);
2475 }
2476
2477 module_init(alsa_card_azx_init)
2478 module_exit(alsa_card_azx_exit)