[ALSA] ens1370 - Fix resume
[linux-2.6.git] / sound / pci / ens1370.c
1 /*
2  *  Driver for Ensoniq ES1370/ES1371 AudioPCI soundcard
3  *  Copyright (c) by Jaroslav Kysela <perex@suse.cz>,
4  *                   Thomas Sailer <sailer@ife.ee.ethz.ch>
5  *
6  *   This program is free software; you can redistribute it and/or modify
7  *   it under the terms of the GNU General Public License as published by
8  *   the Free Software Foundation; either version 2 of the License, or
9  *   (at your option) any later version.
10  *
11  *   This program is distributed in the hope that it will be useful,
12  *   but WITHOUT ANY WARRANTY; without even the implied warranty of
13  *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
14  *   GNU General Public License for more details.
15  *
16  *   You should have received a copy of the GNU General Public License
17  *   along with this program; if not, write to the Free Software
18  *   Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307 USA
19  *
20  */
21
22 /* Power-Management-Code ( CONFIG_PM )
23  * for ens1371 only ( FIXME )
24  * derived from cs4281.c, atiixp.c and via82xx.c
25  * using http://www.alsa-project.org/~iwai/writing-an-alsa-driver/c1540.htm
26  * by Kurt J. Bosch
27  */
28
29 #include <sound/driver.h>
30 #include <asm/io.h>
31 #include <linux/delay.h>
32 #include <linux/interrupt.h>
33 #include <linux/init.h>
34 #include <linux/pci.h>
35 #include <linux/slab.h>
36 #include <linux/gameport.h>
37 #include <linux/moduleparam.h>
38 #include <sound/core.h>
39 #include <sound/control.h>
40 #include <sound/pcm.h>
41 #include <sound/rawmidi.h>
42 #ifdef CHIP1371
43 #include <sound/ac97_codec.h>
44 #else
45 #include <sound/ak4531_codec.h>
46 #endif
47 #include <sound/initval.h>
48 #include <sound/asoundef.h>
49
50 #ifndef CHIP1371
51 #undef CHIP1370
52 #define CHIP1370
53 #endif
54
55 #ifdef CHIP1370
56 #define DRIVER_NAME "ENS1370"
57 #else
58 #define DRIVER_NAME "ENS1371"
59 #endif
60
61
62 MODULE_AUTHOR("Jaroslav Kysela <perex@suse.cz>, Thomas Sailer <sailer@ife.ee.ethz.ch>");
63 MODULE_LICENSE("GPL");
64 #ifdef CHIP1370
65 MODULE_DESCRIPTION("Ensoniq AudioPCI ES1370");
66 MODULE_SUPPORTED_DEVICE("{{Ensoniq,AudioPCI-97 ES1370},"
67                 "{Creative Labs,SB PCI64/128 (ES1370)}}");
68 #endif
69 #ifdef CHIP1371
70 MODULE_DESCRIPTION("Ensoniq/Creative AudioPCI ES1371+");
71 MODULE_SUPPORTED_DEVICE("{{Ensoniq,AudioPCI ES1371/73},"
72                 "{Ensoniq,AudioPCI ES1373},"
73                 "{Creative Labs,Ectiva EV1938},"
74                 "{Creative Labs,SB PCI64/128 (ES1371/73)},"
75                 "{Creative Labs,Vibra PCI128},"
76                 "{Ectiva,EV1938}}");
77 #endif
78
79 #if defined(CONFIG_GAMEPORT) || (defined(MODULE) && defined(CONFIG_GAMEPORT_MODULE))
80 #define SUPPORT_JOYSTICK
81 #endif
82
83 static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX;      /* Index 0-MAX */
84 static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR;       /* ID for this card */
85 static int enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP;      /* Enable switches */
86 #ifdef SUPPORT_JOYSTICK
87 #ifdef CHIP1371
88 static int joystick_port[SNDRV_CARDS];
89 #else
90 static int joystick[SNDRV_CARDS];
91 #endif
92 #endif
93 #ifdef CHIP1371
94 static int spdif[SNDRV_CARDS];
95 static int lineio[SNDRV_CARDS];
96 #endif
97
98 module_param_array(index, int, NULL, 0444);
99 MODULE_PARM_DESC(index, "Index value for Ensoniq AudioPCI soundcard.");
100 module_param_array(id, charp, NULL, 0444);
101 MODULE_PARM_DESC(id, "ID string for Ensoniq AudioPCI soundcard.");
102 module_param_array(enable, bool, NULL, 0444);
103 MODULE_PARM_DESC(enable, "Enable Ensoniq AudioPCI soundcard.");
104 #ifdef SUPPORT_JOYSTICK
105 #ifdef CHIP1371
106 module_param_array(joystick_port, int, NULL, 0444);
107 MODULE_PARM_DESC(joystick_port, "Joystick port address.");
108 #else
109 module_param_array(joystick, bool, NULL, 0444);
110 MODULE_PARM_DESC(joystick, "Enable joystick.");
111 #endif
112 #endif /* SUPPORT_JOYSTICK */
113 #ifdef CHIP1371
114 module_param_array(spdif, int, NULL, 0444);
115 MODULE_PARM_DESC(spdif, "S/PDIF output (-1 = none, 0 = auto, 1 = force).");
116 module_param_array(lineio, int, NULL, 0444);
117 MODULE_PARM_DESC(lineio, "Line In to Rear Out (0 = auto, 1 = force).");
118 #endif
119
120 /* ES1371 chip ID */
121 /* This is a little confusing because all ES1371 compatible chips have the
122    same DEVICE_ID, the only thing differentiating them is the REV_ID field.
123    This is only significant if you want to enable features on the later parts.
124    Yes, I know it's stupid and why didn't we use the sub IDs?
125 */
126 #define ES1371REV_ES1373_A  0x04
127 #define ES1371REV_ES1373_B  0x06
128 #define ES1371REV_CT5880_A  0x07
129 #define CT5880REV_CT5880_C  0x02
130 #define CT5880REV_CT5880_D  0x03        /* ??? -jk */
131 #define CT5880REV_CT5880_E  0x04        /* mw */
132 #define ES1371REV_ES1371_B  0x09
133 #define EV1938REV_EV1938_A  0x00
134 #define ES1371REV_ES1373_8  0x08
135
136 /*
137  * Direct registers
138  */
139
140 #define ES_REG(ensoniq, x) ((ensoniq)->port + ES_REG_##x)
141
142 #define ES_REG_CONTROL  0x00    /* R/W: Interrupt/Chip select control register */
143 #define   ES_1370_ADC_STOP      (1<<31)         /* disable capture buffer transfers */
144 #define   ES_1370_XCTL1         (1<<30)         /* general purpose output bit */
145 #define   ES_1373_BYPASS_P1     (1<<31)         /* bypass SRC for PB1 */
146 #define   ES_1373_BYPASS_P2     (1<<30)         /* bypass SRC for PB2 */
147 #define   ES_1373_BYPASS_R      (1<<29)         /* bypass SRC for REC */
148 #define   ES_1373_TEST_BIT      (1<<28)         /* should be set to 0 for normal operation */
149 #define   ES_1373_RECEN_B       (1<<27)         /* mix record with playback for I2S/SPDIF out */
150 #define   ES_1373_SPDIF_THRU    (1<<26)         /* 0 = SPDIF thru mode, 1 = SPDIF == dig out */
151 #define   ES_1371_JOY_ASEL(o)   (((o)&0x03)<<24)/* joystick port mapping */
152 #define   ES_1371_JOY_ASELM     (0x03<<24)      /* mask for above */
153 #define   ES_1371_JOY_ASELI(i)  (((i)>>24)&0x03)
154 #define   ES_1371_GPIO_IN(i)    (((i)>>20)&0x0f)/* GPIO in [3:0] pins - R/O */
155 #define   ES_1370_PCLKDIVO(o)   (((o)&0x1fff)<<16)/* clock divide ratio for DAC2 */
156 #define   ES_1370_PCLKDIVM      ((0x1fff)<<16)  /* mask for above */
157 #define   ES_1370_PCLKDIVI(i)   (((i)>>16)&0x1fff)/* clock divide ratio for DAC2 */
158 #define   ES_1371_GPIO_OUT(o)   (((o)&0x0f)<<16)/* GPIO out [3:0] pins - W/R */
159 #define   ES_1371_GPIO_OUTM     (0x0f<<16)      /* mask for above */
160 #define   ES_MSFMTSEL           (1<<15)         /* MPEG serial data format; 0 = SONY, 1 = I2S */
161 #define   ES_1370_M_SBB         (1<<14)         /* clock source for DAC - 0 = clock generator; 1 = MPEG clocks */
162 #define   ES_1371_SYNC_RES      (1<<14)         /* Warm AC97 reset */
163 #define   ES_1370_WTSRSEL(o)    (((o)&0x03)<<12)/* fixed frequency clock for DAC1 */
164 #define   ES_1370_WTSRSELM      (0x03<<12)      /* mask for above */
165 #define   ES_1371_ADC_STOP      (1<<13)         /* disable CCB transfer capture information */
166 #define   ES_1371_PWR_INTRM     (1<<12)         /* power level change interrupts enable */
167 #define   ES_1370_DAC_SYNC      (1<<11)         /* DAC's are synchronous */
168 #define   ES_1371_M_CB          (1<<11)         /* capture clock source; 0 = AC'97 ADC; 1 = I2S */
169 #define   ES_CCB_INTRM          (1<<10)         /* CCB voice interrupts enable */
170 #define   ES_1370_M_CB          (1<<9)          /* capture clock source; 0 = ADC; 1 = MPEG */
171 #define   ES_1370_XCTL0         (1<<8)          /* generap purpose output bit */
172 #define   ES_1371_PDLEV(o)      (((o)&0x03)<<8) /* current power down level */
173 #define   ES_1371_PDLEVM        (0x03<<8)       /* mask for above */
174 #define   ES_BREQ               (1<<7)          /* memory bus request enable */
175 #define   ES_DAC1_EN            (1<<6)          /* DAC1 playback channel enable */
176 #define   ES_DAC2_EN            (1<<5)          /* DAC2 playback channel enable */
177 #define   ES_ADC_EN             (1<<4)          /* ADC capture channel enable */
178 #define   ES_UART_EN            (1<<3)          /* UART enable */
179 #define   ES_JYSTK_EN           (1<<2)          /* Joystick module enable */
180 #define   ES_1370_CDC_EN        (1<<1)          /* Codec interface enable */
181 #define   ES_1371_XTALCKDIS     (1<<1)          /* Xtal clock disable */
182 #define   ES_1370_SERR_DISABLE  (1<<0)          /* PCI serr signal disable */
183 #define   ES_1371_PCICLKDIS     (1<<0)          /* PCI clock disable */
184 #define ES_REG_STATUS   0x04    /* R/O: Interrupt/Chip select status register */
185 #define   ES_INTR               (1<<31)         /* Interrupt is pending */
186 #define   ES_1371_ST_AC97_RST   (1<<29)         /* CT5880 AC'97 Reset bit */
187 #define   ES_1373_REAR_BIT27    (1<<27)         /* rear bits: 000 - front, 010 - mirror, 101 - separate */
188 #define   ES_1373_REAR_BIT26    (1<<26)
189 #define   ES_1373_REAR_BIT24    (1<<24)
190 #define   ES_1373_GPIO_INT_EN(o)(((o)&0x0f)<<20)/* GPIO [3:0] pins - interrupt enable */
191 #define   ES_1373_SPDIF_EN      (1<<18)         /* SPDIF enable */
192 #define   ES_1373_SPDIF_TEST    (1<<17)         /* SPDIF test */
193 #define   ES_1371_TEST          (1<<16)         /* test ASIC */
194 #define   ES_1373_GPIO_INT(i)   (((i)&0x0f)>>12)/* GPIO [3:0] pins - interrupt pending */
195 #define   ES_1370_CSTAT         (1<<10)         /* CODEC is busy or register write in progress */
196 #define   ES_1370_CBUSY         (1<<9)          /* CODEC is busy */
197 #define   ES_1370_CWRIP         (1<<8)          /* CODEC register write in progress */
198 #define   ES_1371_SYNC_ERR      (1<<8)          /* CODEC synchronization error occurred */
199 #define   ES_1371_VC(i)         (((i)>>6)&0x03) /* voice code from CCB module */
200 #define   ES_1370_VC(i)         (((i)>>5)&0x03) /* voice code from CCB module */
201 #define   ES_1371_MPWR          (1<<5)          /* power level interrupt pending */
202 #define   ES_MCCB               (1<<4)          /* CCB interrupt pending */
203 #define   ES_UART               (1<<3)          /* UART interrupt pending */
204 #define   ES_DAC1               (1<<2)          /* DAC1 channel interrupt pending */
205 #define   ES_DAC2               (1<<1)          /* DAC2 channel interrupt pending */
206 #define   ES_ADC                (1<<0)          /* ADC channel interrupt pending */
207 #define ES_REG_UART_DATA 0x08   /* R/W: UART data register */
208 #define ES_REG_UART_STATUS 0x09 /* R/O: UART status register */
209 #define   ES_RXINT              (1<<7)          /* RX interrupt occurred */
210 #define   ES_TXINT              (1<<2)          /* TX interrupt occurred */
211 #define   ES_TXRDY              (1<<1)          /* transmitter ready */
212 #define   ES_RXRDY              (1<<0)          /* receiver ready */
213 #define ES_REG_UART_CONTROL 0x09        /* W/O: UART control register */
214 #define   ES_RXINTEN            (1<<7)          /* RX interrupt enable */
215 #define   ES_TXINTENO(o)        (((o)&0x03)<<5) /* TX interrupt enable */
216 #define   ES_TXINTENM           (0x03<<5)       /* mask for above */
217 #define   ES_TXINTENI(i)        (((i)>>5)&0x03)
218 #define   ES_CNTRL(o)           (((o)&0x03)<<0) /* control */
219 #define   ES_CNTRLM             (0x03<<0)       /* mask for above */
220 #define ES_REG_UART_RES 0x0a    /* R/W: UART reserver register */
221 #define   ES_TEST_MODE          (1<<0)          /* test mode enabled */
222 #define ES_REG_MEM_PAGE 0x0c    /* R/W: Memory page register */
223 #define   ES_MEM_PAGEO(o)       (((o)&0x0f)<<0) /* memory page select - out */
224 #define   ES_MEM_PAGEM          (0x0f<<0)       /* mask for above */
225 #define   ES_MEM_PAGEI(i)       (((i)>>0)&0x0f) /* memory page select - in */
226 #define ES_REG_1370_CODEC 0x10  /* W/O: Codec write register address */
227 #define   ES_1370_CODEC_WRITE(a,d) ((((a)&0xff)<<8)|(((d)&0xff)<<0))
228 #define ES_REG_1371_CODEC 0x14  /* W/R: Codec Read/Write register address */
229 #define   ES_1371_CODEC_RDY        (1<<31)      /* codec ready */
230 #define   ES_1371_CODEC_WIP        (1<<30)      /* codec register access in progress */
231 #define   ES_1371_CODEC_PIRD       (1<<23)      /* codec read/write select register */
232 #define   ES_1371_CODEC_WRITE(a,d) ((((a)&0x7f)<<16)|(((d)&0xffff)<<0))
233 #define   ES_1371_CODEC_READS(a)   ((((a)&0x7f)<<16)|ES_1371_CODEC_PIRD)
234 #define   ES_1371_CODEC_READ(i)    (((i)>>0)&0xffff)
235
236 #define ES_REG_1371_SMPRATE 0x10        /* W/R: Codec rate converter interface register */
237 #define   ES_1371_SRC_RAM_ADDRO(o) (((o)&0x7f)<<25)/* address of the sample rate converter */
238 #define   ES_1371_SRC_RAM_ADDRM    (0x7f<<25)   /* mask for above */
239 #define   ES_1371_SRC_RAM_ADDRI(i) (((i)>>25)&0x7f)/* address of the sample rate converter */
240 #define   ES_1371_SRC_RAM_WE       (1<<24)      /* R/W: read/write control for sample rate converter */
241 #define   ES_1371_SRC_RAM_BUSY     (1<<23)      /* R/O: sample rate memory is busy */
242 #define   ES_1371_SRC_DISABLE      (1<<22)      /* sample rate converter disable */
243 #define   ES_1371_DIS_P1           (1<<21)      /* playback channel 1 accumulator update disable */
244 #define   ES_1371_DIS_P2           (1<<20)      /* playback channel 1 accumulator update disable */
245 #define   ES_1371_DIS_R1           (1<<19)      /* capture channel accumulator update disable */
246 #define   ES_1371_SRC_RAM_DATAO(o) (((o)&0xffff)<<0)/* current value of the sample rate converter */
247 #define   ES_1371_SRC_RAM_DATAM    (0xffff<<0)  /* mask for above */
248 #define   ES_1371_SRC_RAM_DATAI(i) (((i)>>0)&0xffff)/* current value of the sample rate converter */
249
250 #define ES_REG_1371_LEGACY 0x18 /* W/R: Legacy control/status register */
251 #define   ES_1371_JFAST         (1<<31)         /* fast joystick timing */
252 #define   ES_1371_HIB           (1<<30)         /* host interrupt blocking enable */
253 #define   ES_1371_VSB           (1<<29)         /* SB; 0 = addr 0x220xH, 1 = 0x22FxH */
254 #define   ES_1371_VMPUO(o)      (((o)&0x03)<<27)/* base register address; 0 = 0x320xH; 1 = 0x330xH; 2 = 0x340xH; 3 = 0x350xH */
255 #define   ES_1371_VMPUM         (0x03<<27)      /* mask for above */
256 #define   ES_1371_VMPUI(i)      (((i)>>27)&0x03)/* base register address */
257 #define   ES_1371_VCDCO(o)      (((o)&0x03)<<25)/* CODEC; 0 = 0x530xH; 1 = undefined; 2 = 0xe80xH; 3 = 0xF40xH */
258 #define   ES_1371_VCDCM         (0x03<<25)      /* mask for above */
259 #define   ES_1371_VCDCI(i)      (((i)>>25)&0x03)/* CODEC address */
260 #define   ES_1371_FIRQ          (1<<24)         /* force an interrupt */
261 #define   ES_1371_SDMACAP       (1<<23)         /* enable event capture for slave DMA controller */
262 #define   ES_1371_SPICAP        (1<<22)         /* enable event capture for slave IRQ controller */
263 #define   ES_1371_MDMACAP       (1<<21)         /* enable event capture for master DMA controller */
264 #define   ES_1371_MPICAP        (1<<20)         /* enable event capture for master IRQ controller */
265 #define   ES_1371_ADCAP         (1<<19)         /* enable event capture for ADLIB register; 0x388xH */
266 #define   ES_1371_SVCAP         (1<<18)         /* enable event capture for SB registers */
267 #define   ES_1371_CDCCAP        (1<<17)         /* enable event capture for CODEC registers */
268 #define   ES_1371_BACAP         (1<<16)         /* enable event capture for SoundScape base address */
269 #define   ES_1371_EXI(i)        (((i)>>8)&0x07) /* event number */
270 #define   ES_1371_AI(i)         (((i)>>3)&0x1f) /* event significant I/O address */
271 #define   ES_1371_WR            (1<<2)  /* event capture; 0 = read; 1 = write */
272 #define   ES_1371_LEGINT        (1<<0)  /* interrupt for legacy events; 0 = interrupt did occur */
273
274 #define ES_REG_CHANNEL_STATUS 0x1c /* R/W: first 32-bits from S/PDIF channel status block, es1373 */
275
276 #define ES_REG_SERIAL   0x20    /* R/W: Serial interface control register */
277 #define   ES_1371_DAC_TEST      (1<<22)         /* DAC test mode enable */
278 #define   ES_P2_END_INCO(o)     (((o)&0x07)<<19)/* binary offset value to increment / loop end */
279 #define   ES_P2_END_INCM        (0x07<<19)      /* mask for above */
280 #define   ES_P2_END_INCI(i)     (((i)>>16)&0x07)/* binary offset value to increment / loop end */
281 #define   ES_P2_ST_INCO(o)      (((o)&0x07)<<16)/* binary offset value to increment / start */
282 #define   ES_P2_ST_INCM         (0x07<<16)      /* mask for above */
283 #define   ES_P2_ST_INCI(i)      (((i)<<16)&0x07)/* binary offset value to increment / start */
284 #define   ES_R1_LOOP_SEL        (1<<15)         /* ADC; 0 - loop mode; 1 = stop mode */
285 #define   ES_P2_LOOP_SEL        (1<<14)         /* DAC2; 0 - loop mode; 1 = stop mode */
286 #define   ES_P1_LOOP_SEL        (1<<13)         /* DAC1; 0 - loop mode; 1 = stop mode */
287 #define   ES_P2_PAUSE           (1<<12)         /* DAC2; 0 - play mode; 1 = pause mode */
288 #define   ES_P1_PAUSE           (1<<11)         /* DAC1; 0 - play mode; 1 = pause mode */
289 #define   ES_R1_INT_EN          (1<<10)         /* ADC interrupt enable */
290 #define   ES_P2_INT_EN          (1<<9)          /* DAC2 interrupt enable */
291 #define   ES_P1_INT_EN          (1<<8)          /* DAC1 interrupt enable */
292 #define   ES_P1_SCT_RLD         (1<<7)          /* force sample counter reload for DAC1 */
293 #define   ES_P2_DAC_SEN         (1<<6)          /* when stop mode: 0 - DAC2 play back zeros; 1 = DAC2 play back last sample */
294 #define   ES_R1_MODEO(o)        (((o)&0x03)<<4) /* ADC mode; 0 = 8-bit mono; 1 = 8-bit stereo; 2 = 16-bit mono; 3 = 16-bit stereo */
295 #define   ES_R1_MODEM           (0x03<<4)       /* mask for above */
296 #define   ES_R1_MODEI(i)        (((i)>>4)&0x03)
297 #define   ES_P2_MODEO(o)        (((o)&0x03)<<2) /* DAC2 mode; -- '' -- */
298 #define   ES_P2_MODEM           (0x03<<2)       /* mask for above */
299 #define   ES_P2_MODEI(i)        (((i)>>2)&0x03)
300 #define   ES_P1_MODEO(o)        (((o)&0x03)<<0) /* DAC1 mode; -- '' -- */
301 #define   ES_P1_MODEM           (0x03<<0)       /* mask for above */
302 #define   ES_P1_MODEI(i)        (((i)>>0)&0x03)
303
304 #define ES_REG_DAC1_COUNT 0x24  /* R/W: DAC1 sample count register */
305 #define ES_REG_DAC2_COUNT 0x28  /* R/W: DAC2 sample count register */
306 #define ES_REG_ADC_COUNT  0x2c  /* R/W: ADC sample count register */
307 #define   ES_REG_CURR_COUNT(i)  (((i)>>16)&0xffff)
308 #define   ES_REG_COUNTO(o)      (((o)&0xffff)<<0)
309 #define   ES_REG_COUNTM         (0xffff<<0)
310 #define   ES_REG_COUNTI(i)      (((i)>>0)&0xffff)
311
312 #define ES_REG_DAC1_FRAME 0x30  /* R/W: PAGE 0x0c; DAC1 frame address */
313 #define ES_REG_DAC1_SIZE  0x34  /* R/W: PAGE 0x0c; DAC1 frame size */
314 #define ES_REG_DAC2_FRAME 0x38  /* R/W: PAGE 0x0c; DAC2 frame address */
315 #define ES_REG_DAC2_SIZE  0x3c  /* R/W: PAGE 0x0c; DAC2 frame size */
316 #define ES_REG_ADC_FRAME  0x30  /* R/W: PAGE 0x0d; ADC frame address */
317 #define ES_REG_ADC_SIZE   0x34  /* R/W: PAGE 0x0d; ADC frame size */
318 #define   ES_REG_FCURR_COUNTO(o) (((o)&0xffff)<<16)
319 #define   ES_REG_FCURR_COUNTM    (0xffff<<16)
320 #define   ES_REG_FCURR_COUNTI(i) (((i)>>14)&0x3fffc)
321 #define   ES_REG_FSIZEO(o)       (((o)&0xffff)<<0)
322 #define   ES_REG_FSIZEM          (0xffff<<0)
323 #define   ES_REG_FSIZEI(i)       (((i)>>0)&0xffff)
324 #define ES_REG_PHANTOM_FRAME 0x38 /* R/W: PAGE 0x0d: phantom frame address */
325 #define ES_REG_PHANTOM_COUNT 0x3c /* R/W: PAGE 0x0d: phantom frame count */
326
327 #define ES_REG_UART_FIFO  0x30  /* R/W: PAGE 0x0e; UART FIFO register */
328 #define   ES_REG_UF_VALID        (1<<8)
329 #define   ES_REG_UF_BYTEO(o)     (((o)&0xff)<<0)
330 #define   ES_REG_UF_BYTEM        (0xff<<0)
331 #define   ES_REG_UF_BYTEI(i)     (((i)>>0)&0xff)
332
333
334 /*
335  *  Pages
336  */
337
338 #define ES_PAGE_DAC     0x0c
339 #define ES_PAGE_ADC     0x0d
340 #define ES_PAGE_UART    0x0e
341 #define ES_PAGE_UART1   0x0f
342
343 /*
344  *  Sample rate converter addresses
345  */
346
347 #define ES_SMPREG_DAC1          0x70
348 #define ES_SMPREG_DAC2          0x74
349 #define ES_SMPREG_ADC           0x78
350 #define ES_SMPREG_VOL_ADC       0x6c
351 #define ES_SMPREG_VOL_DAC1      0x7c
352 #define ES_SMPREG_VOL_DAC2      0x7e
353 #define ES_SMPREG_TRUNC_N       0x00
354 #define ES_SMPREG_INT_REGS      0x01
355 #define ES_SMPREG_ACCUM_FRAC    0x02
356 #define ES_SMPREG_VFREQ_FRAC    0x03
357
358 /*
359  *  Some contants
360  */
361
362 #define ES_1370_SRCLOCK    1411200
363 #define ES_1370_SRTODIV(x) (ES_1370_SRCLOCK/(x)-2)
364
365 /*
366  *  Open modes
367  */
368
369 #define ES_MODE_PLAY1   0x0001
370 #define ES_MODE_PLAY2   0x0002
371 #define ES_MODE_CAPTURE 0x0004
372
373 #define ES_MODE_OUTPUT  0x0001  /* for MIDI */
374 #define ES_MODE_INPUT   0x0002  /* for MIDI */
375
376 /*
377
378  */
379
380 struct ensoniq {
381         spinlock_t reg_lock;
382         struct semaphore src_mutex;
383
384         int irq;
385
386         unsigned long playback1size;
387         unsigned long playback2size;
388         unsigned long capture3size;
389
390         unsigned long port;
391         unsigned int mode;
392         unsigned int uartm;     /* UART mode */
393
394         unsigned int ctrl;      /* control register */
395         unsigned int sctrl;     /* serial control register */
396         unsigned int cssr;      /* control status register */
397         unsigned int uartc;     /* uart control register */
398         unsigned int rev;       /* chip revision */
399
400         union {
401 #ifdef CHIP1371
402                 struct {
403                         struct snd_ac97 *ac97;
404                 } es1371;
405 #else
406                 struct {
407                         int pclkdiv_lock;
408                         struct snd_ak4531 *ak4531;
409                 } es1370;
410 #endif
411         } u;
412
413         struct pci_dev *pci;
414         unsigned short subsystem_vendor_id;
415         unsigned short subsystem_device_id;
416         struct snd_card *card;
417         struct snd_pcm *pcm1;   /* DAC1/ADC PCM */
418         struct snd_pcm *pcm2;   /* DAC2 PCM */
419         struct snd_pcm_substream *playback1_substream;
420         struct snd_pcm_substream *playback2_substream;
421         struct snd_pcm_substream *capture_substream;
422         unsigned int p1_dma_size;
423         unsigned int p2_dma_size;
424         unsigned int c_dma_size;
425         unsigned int p1_period_size;
426         unsigned int p2_period_size;
427         unsigned int c_period_size;
428         struct snd_rawmidi *rmidi;
429         struct snd_rawmidi_substream *midi_input;
430         struct snd_rawmidi_substream *midi_output;
431
432         unsigned int spdif;
433         unsigned int spdif_default;
434         unsigned int spdif_stream;
435
436 #ifdef CHIP1370
437         struct snd_dma_buffer dma_bug;
438 #endif
439
440 #ifdef SUPPORT_JOYSTICK
441         struct gameport *gameport;
442 #endif
443 };
444
445 static irqreturn_t snd_audiopci_interrupt(int irq, void *dev_id, struct pt_regs *regs);
446
447 static struct pci_device_id snd_audiopci_ids[] = {
448 #ifdef CHIP1370
449         { 0x1274, 0x5000, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0, },   /* ES1370 */
450 #endif
451 #ifdef CHIP1371
452         { 0x1274, 0x1371, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0, },   /* ES1371 */
453         { 0x1274, 0x5880, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0, },   /* ES1373 - CT5880 */
454         { 0x1102, 0x8938, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0, },   /* Ectiva EV1938 */
455 #endif
456         { 0, }
457 };
458
459 MODULE_DEVICE_TABLE(pci, snd_audiopci_ids);
460
461 /*
462  *  constants
463  */
464
465 #define POLL_COUNT      0xa000
466
467 #ifdef CHIP1370
468 static unsigned int snd_es1370_fixed_rates[] =
469         {5512, 11025, 22050, 44100};
470 static struct snd_pcm_hw_constraint_list snd_es1370_hw_constraints_rates = {
471         .count = 4, 
472         .list = snd_es1370_fixed_rates,
473         .mask = 0,
474 };
475 static struct snd_ratnum es1370_clock = {
476         .num = ES_1370_SRCLOCK,
477         .den_min = 29, 
478         .den_max = 353,
479         .den_step = 1,
480 };
481 static struct snd_pcm_hw_constraint_ratnums snd_es1370_hw_constraints_clock = {
482         .nrats = 1,
483         .rats = &es1370_clock,
484 };
485 #else
486 static struct snd_ratden es1371_dac_clock = {
487         .num_min = 3000 * (1 << 15),
488         .num_max = 48000 * (1 << 15),
489         .num_step = 3000,
490         .den = 1 << 15,
491 };
492 static struct snd_pcm_hw_constraint_ratdens snd_es1371_hw_constraints_dac_clock = {
493         .nrats = 1,
494         .rats = &es1371_dac_clock,
495 };
496 static struct snd_ratnum es1371_adc_clock = {
497         .num = 48000 << 15,
498         .den_min = 32768, 
499         .den_max = 393216,
500         .den_step = 1,
501 };
502 static struct snd_pcm_hw_constraint_ratnums snd_es1371_hw_constraints_adc_clock = {
503         .nrats = 1,
504         .rats = &es1371_adc_clock,
505 };
506 #endif
507 static const unsigned int snd_ensoniq_sample_shift[] =
508         {0, 1, 1, 2};
509
510 /*
511  *  common I/O routines
512  */
513
514 #ifdef CHIP1371
515
516 static unsigned int snd_es1371_wait_src_ready(struct ensoniq * ensoniq)
517 {
518         unsigned int t, r = 0;
519
520         for (t = 0; t < POLL_COUNT; t++) {
521                 r = inl(ES_REG(ensoniq, 1371_SMPRATE));
522                 if ((r & ES_1371_SRC_RAM_BUSY) == 0)
523                         return r;
524                 cond_resched();
525         }
526         snd_printk(KERN_ERR "wait source ready timeout 0x%lx [0x%x]\n",
527                    ES_REG(ensoniq, 1371_SMPRATE), r);
528         return 0;
529 }
530
531 static unsigned int snd_es1371_src_read(struct ensoniq * ensoniq, unsigned short reg)
532 {
533         unsigned int temp, i, orig, r;
534
535         /* wait for ready */
536         temp = orig = snd_es1371_wait_src_ready(ensoniq);
537
538         /* expose the SRC state bits */
539         r = temp & (ES_1371_SRC_DISABLE | ES_1371_DIS_P1 |
540                     ES_1371_DIS_P2 | ES_1371_DIS_R1);
541         r |= ES_1371_SRC_RAM_ADDRO(reg) | 0x10000;
542         outl(r, ES_REG(ensoniq, 1371_SMPRATE));
543
544         /* now, wait for busy and the correct time to read */
545         temp = snd_es1371_wait_src_ready(ensoniq);
546         
547         if ((temp & 0x00870000) != 0x00010000) {
548                 /* wait for the right state */
549                 for (i = 0; i < POLL_COUNT; i++) {
550                         temp = inl(ES_REG(ensoniq, 1371_SMPRATE));
551                         if ((temp & 0x00870000) == 0x00010000)
552                                 break;
553                 }
554         }
555
556         /* hide the state bits */       
557         r = orig & (ES_1371_SRC_DISABLE | ES_1371_DIS_P1 |
558                    ES_1371_DIS_P2 | ES_1371_DIS_R1);
559         r |= ES_1371_SRC_RAM_ADDRO(reg);
560         outl(r, ES_REG(ensoniq, 1371_SMPRATE));
561         
562         return temp;
563 }
564
565 static void snd_es1371_src_write(struct ensoniq * ensoniq,
566                                  unsigned short reg, unsigned short data)
567 {
568         unsigned int r;
569
570         r = snd_es1371_wait_src_ready(ensoniq) &
571             (ES_1371_SRC_DISABLE | ES_1371_DIS_P1 |
572              ES_1371_DIS_P2 | ES_1371_DIS_R1);
573         r |= ES_1371_SRC_RAM_ADDRO(reg) | ES_1371_SRC_RAM_DATAO(data);
574         outl(r | ES_1371_SRC_RAM_WE, ES_REG(ensoniq, 1371_SMPRATE));
575 }
576
577 #endif /* CHIP1371 */
578
579 #ifdef CHIP1370
580
581 static void snd_es1370_codec_write(struct snd_ak4531 *ak4531,
582                                    unsigned short reg, unsigned short val)
583 {
584         struct ensoniq *ensoniq = ak4531->private_data;
585         unsigned long end_time = jiffies + HZ / 10;
586
587 #if 0
588         printk("CODEC WRITE: reg = 0x%x, val = 0x%x (0x%x), creg = 0x%x\n",
589                reg, val, ES_1370_CODEC_WRITE(reg, val), ES_REG(ensoniq, 1370_CODEC));
590 #endif
591         do {
592                 if (!(inl(ES_REG(ensoniq, STATUS)) & ES_1370_CSTAT)) {
593                         outw(ES_1370_CODEC_WRITE(reg, val), ES_REG(ensoniq, 1370_CODEC));
594                         return;
595                 }
596                 schedule_timeout_uninterruptible(1);
597         } while (time_after(end_time, jiffies));
598         snd_printk(KERN_ERR "codec write timeout, status = 0x%x\n",
599                    inl(ES_REG(ensoniq, STATUS)));
600 }
601
602 #endif /* CHIP1370 */
603
604 #ifdef CHIP1371
605
606 static void snd_es1371_codec_write(struct snd_ac97 *ac97,
607                                    unsigned short reg, unsigned short val)
608 {
609         struct ensoniq *ensoniq = ac97->private_data;
610         unsigned int t, x;
611
612         down(&ensoniq->src_mutex);
613         for (t = 0; t < POLL_COUNT; t++) {
614                 if (!(inl(ES_REG(ensoniq, 1371_CODEC)) & ES_1371_CODEC_WIP)) {
615                         /* save the current state for latter */
616                         x = snd_es1371_wait_src_ready(ensoniq);
617                         outl((x & (ES_1371_SRC_DISABLE | ES_1371_DIS_P1 |
618                                    ES_1371_DIS_P2 | ES_1371_DIS_R1)) | 0x00010000,
619                              ES_REG(ensoniq, 1371_SMPRATE));
620                         /* wait for not busy (state 0) first to avoid
621                            transition states */
622                         for (t = 0; t < POLL_COUNT; t++) {
623                                 if ((inl(ES_REG(ensoniq, 1371_SMPRATE)) & 0x00870000) ==
624                                     0x00000000)
625                                         break;
626                         }
627                         /* wait for a SAFE time to write addr/data and then do it, dammit */
628                         for (t = 0; t < POLL_COUNT; t++) {
629                                 if ((inl(ES_REG(ensoniq, 1371_SMPRATE)) & 0x00870000) ==
630                                     0x00010000)
631                                         break;
632                         }
633                         outl(ES_1371_CODEC_WRITE(reg, val), ES_REG(ensoniq, 1371_CODEC));
634                         /* restore SRC reg */
635                         snd_es1371_wait_src_ready(ensoniq);
636                         outl(x, ES_REG(ensoniq, 1371_SMPRATE));
637                         up(&ensoniq->src_mutex);
638                         return;
639                 }
640         }
641         up(&ensoniq->src_mutex);
642         snd_printk(KERN_ERR "codec write timeout at 0x%lx [0x%x]\n",
643                    ES_REG(ensoniq, 1371_CODEC), inl(ES_REG(ensoniq, 1371_CODEC)));
644 }
645
646 static unsigned short snd_es1371_codec_read(struct snd_ac97 *ac97,
647                                             unsigned short reg)
648 {
649         struct ensoniq *ensoniq = ac97->private_data;
650         unsigned int t, x, fail = 0;
651
652       __again:
653         down(&ensoniq->src_mutex);
654         for (t = 0; t < POLL_COUNT; t++) {
655                 if (!(inl(ES_REG(ensoniq, 1371_CODEC)) & ES_1371_CODEC_WIP)) {
656                         /* save the current state for latter */
657                         x = snd_es1371_wait_src_ready(ensoniq);
658                         outl((x & (ES_1371_SRC_DISABLE | ES_1371_DIS_P1 |
659                                    ES_1371_DIS_P2 | ES_1371_DIS_R1)) | 0x00010000,
660                              ES_REG(ensoniq, 1371_SMPRATE));
661                         /* wait for not busy (state 0) first to avoid
662                            transition states */
663                         for (t = 0; t < POLL_COUNT; t++) {
664                                 if ((inl(ES_REG(ensoniq, 1371_SMPRATE)) & 0x00870000) ==
665                                     0x00000000)
666                                         break;
667                         }
668                         /* wait for a SAFE time to write addr/data and then do it, dammit */
669                         for (t = 0; t < POLL_COUNT; t++) {
670                                 if ((inl(ES_REG(ensoniq, 1371_SMPRATE)) & 0x00870000) ==
671                                     0x00010000)
672                                         break;
673                         }
674                         outl(ES_1371_CODEC_READS(reg), ES_REG(ensoniq, 1371_CODEC));
675                         /* restore SRC reg */
676                         snd_es1371_wait_src_ready(ensoniq);
677                         outl(x, ES_REG(ensoniq, 1371_SMPRATE));
678                         /* wait for WIP again */
679                         for (t = 0; t < POLL_COUNT; t++) {
680                                 if (!(inl(ES_REG(ensoniq, 1371_CODEC)) & ES_1371_CODEC_WIP))
681                                         break;          
682                         }
683                         /* now wait for the stinkin' data (RDY) */
684                         for (t = 0; t < POLL_COUNT; t++) {
685                                 if ((x = inl(ES_REG(ensoniq, 1371_CODEC))) & ES_1371_CODEC_RDY) {
686                                         up(&ensoniq->src_mutex);
687                                         return ES_1371_CODEC_READ(x);
688                                 }
689                         }
690                         up(&ensoniq->src_mutex);
691                         if (++fail > 10) {
692                                 snd_printk(KERN_ERR "codec read timeout (final) "
693                                            "at 0x%lx, reg = 0x%x [0x%x]\n",
694                                            ES_REG(ensoniq, 1371_CODEC), reg,
695                                            inl(ES_REG(ensoniq, 1371_CODEC)));
696                                 return 0;
697                         }
698                         goto __again;
699                 }
700         }
701         up(&ensoniq->src_mutex);
702         snd_printk(KERN_ERR "es1371: codec read timeout at 0x%lx [0x%x]\n",
703                    ES_REG(ensoniq, 1371_CODEC), inl(ES_REG(ensoniq, 1371_CODEC)));
704         return 0;
705 }
706
707 static void snd_es1371_codec_wait(struct snd_ac97 *ac97)
708 {
709         msleep(750);
710         snd_es1371_codec_read(ac97, AC97_RESET);
711         snd_es1371_codec_read(ac97, AC97_VENDOR_ID1);
712         snd_es1371_codec_read(ac97, AC97_VENDOR_ID2);
713         msleep(50);
714 }
715
716 static void snd_es1371_adc_rate(struct ensoniq * ensoniq, unsigned int rate)
717 {
718         unsigned int n, truncm, freq, result;
719
720         down(&ensoniq->src_mutex);
721         n = rate / 3000;
722         if ((1 << n) & ((1 << 15) | (1 << 13) | (1 << 11) | (1 << 9)))
723                 n--;
724         truncm = (21 * n - 1) | 1;
725         freq = ((48000UL << 15) / rate) * n;
726         result = (48000UL << 15) / (freq / n);
727         if (rate >= 24000) {
728                 if (truncm > 239)
729                         truncm = 239;
730                 snd_es1371_src_write(ensoniq, ES_SMPREG_ADC + ES_SMPREG_TRUNC_N,
731                                 (((239 - truncm) >> 1) << 9) | (n << 4));
732         } else {
733                 if (truncm > 119)
734                         truncm = 119;
735                 snd_es1371_src_write(ensoniq, ES_SMPREG_ADC + ES_SMPREG_TRUNC_N,
736                                 0x8000 | (((119 - truncm) >> 1) << 9) | (n << 4));
737         }
738         snd_es1371_src_write(ensoniq, ES_SMPREG_ADC + ES_SMPREG_INT_REGS,
739                              (snd_es1371_src_read(ensoniq, ES_SMPREG_ADC +
740                                                   ES_SMPREG_INT_REGS) & 0x00ff) |
741                              ((freq >> 5) & 0xfc00));
742         snd_es1371_src_write(ensoniq, ES_SMPREG_ADC + ES_SMPREG_VFREQ_FRAC, freq & 0x7fff);
743         snd_es1371_src_write(ensoniq, ES_SMPREG_VOL_ADC, n << 8);
744         snd_es1371_src_write(ensoniq, ES_SMPREG_VOL_ADC + 1, n << 8);
745         up(&ensoniq->src_mutex);
746 }
747
748 static void snd_es1371_dac1_rate(struct ensoniq * ensoniq, unsigned int rate)
749 {
750         unsigned int freq, r;
751
752         down(&ensoniq->src_mutex);
753         freq = ((rate << 15) + 1500) / 3000;
754         r = (snd_es1371_wait_src_ready(ensoniq) & (ES_1371_SRC_DISABLE |
755                                                    ES_1371_DIS_P2 | ES_1371_DIS_R1)) |
756                 ES_1371_DIS_P1;
757         outl(r, ES_REG(ensoniq, 1371_SMPRATE));
758         snd_es1371_src_write(ensoniq, ES_SMPREG_DAC1 + ES_SMPREG_INT_REGS,
759                              (snd_es1371_src_read(ensoniq, ES_SMPREG_DAC1 +
760                                                   ES_SMPREG_INT_REGS) & 0x00ff) |
761                              ((freq >> 5) & 0xfc00));
762         snd_es1371_src_write(ensoniq, ES_SMPREG_DAC1 + ES_SMPREG_VFREQ_FRAC, freq & 0x7fff);
763         r = (snd_es1371_wait_src_ready(ensoniq) & (ES_1371_SRC_DISABLE |
764                                                    ES_1371_DIS_P2 | ES_1371_DIS_R1));
765         outl(r, ES_REG(ensoniq, 1371_SMPRATE));
766         up(&ensoniq->src_mutex);
767 }
768
769 static void snd_es1371_dac2_rate(struct ensoniq * ensoniq, unsigned int rate)
770 {
771         unsigned int freq, r;
772
773         down(&ensoniq->src_mutex);
774         freq = ((rate << 15) + 1500) / 3000;
775         r = (snd_es1371_wait_src_ready(ensoniq) & (ES_1371_SRC_DISABLE |
776                                                    ES_1371_DIS_P1 | ES_1371_DIS_R1)) |
777                 ES_1371_DIS_P2;
778         outl(r, ES_REG(ensoniq, 1371_SMPRATE));
779         snd_es1371_src_write(ensoniq, ES_SMPREG_DAC2 + ES_SMPREG_INT_REGS,
780                              (snd_es1371_src_read(ensoniq, ES_SMPREG_DAC2 +
781                                                   ES_SMPREG_INT_REGS) & 0x00ff) |
782                              ((freq >> 5) & 0xfc00));
783         snd_es1371_src_write(ensoniq, ES_SMPREG_DAC2 + ES_SMPREG_VFREQ_FRAC,
784                              freq & 0x7fff);
785         r = (snd_es1371_wait_src_ready(ensoniq) & (ES_1371_SRC_DISABLE |
786                                                    ES_1371_DIS_P1 | ES_1371_DIS_R1));
787         outl(r, ES_REG(ensoniq, 1371_SMPRATE));
788         up(&ensoniq->src_mutex);
789 }
790
791 #endif /* CHIP1371 */
792
793 static int snd_ensoniq_trigger(struct snd_pcm_substream *substream, int cmd)
794 {
795         struct ensoniq *ensoniq = snd_pcm_substream_chip(substream);
796         switch (cmd) {
797         case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
798         case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
799         {
800                 unsigned int what = 0;
801                 struct list_head *pos;
802                 struct snd_pcm_substream *s;
803                 snd_pcm_group_for_each(pos, substream) {
804                         s = snd_pcm_group_substream_entry(pos);
805                         if (s == ensoniq->playback1_substream) {
806                                 what |= ES_P1_PAUSE;
807                                 snd_pcm_trigger_done(s, substream);
808                         } else if (s == ensoniq->playback2_substream) {
809                                 what |= ES_P2_PAUSE;
810                                 snd_pcm_trigger_done(s, substream);
811                         } else if (s == ensoniq->capture_substream)
812                                 return -EINVAL;
813                 }
814                 spin_lock(&ensoniq->reg_lock);
815                 if (cmd == SNDRV_PCM_TRIGGER_PAUSE_PUSH)
816                         ensoniq->sctrl |= what;
817                 else
818                         ensoniq->sctrl &= ~what;
819                 outl(ensoniq->sctrl, ES_REG(ensoniq, SERIAL));
820                 spin_unlock(&ensoniq->reg_lock);
821                 break;
822         }
823         case SNDRV_PCM_TRIGGER_START:
824         case SNDRV_PCM_TRIGGER_STOP:
825         {
826                 unsigned int what = 0;
827                 struct list_head *pos;
828                 struct snd_pcm_substream *s;
829                 snd_pcm_group_for_each(pos, substream) {
830                         s = snd_pcm_group_substream_entry(pos);
831                         if (s == ensoniq->playback1_substream) {
832                                 what |= ES_DAC1_EN;
833                                 snd_pcm_trigger_done(s, substream);
834                         } else if (s == ensoniq->playback2_substream) {
835                                 what |= ES_DAC2_EN;
836                                 snd_pcm_trigger_done(s, substream);
837                         } else if (s == ensoniq->capture_substream) {
838                                 what |= ES_ADC_EN;
839                                 snd_pcm_trigger_done(s, substream);
840                         }
841                 }
842                 spin_lock(&ensoniq->reg_lock);
843                 if (cmd == SNDRV_PCM_TRIGGER_START)
844                         ensoniq->ctrl |= what;
845                 else
846                         ensoniq->ctrl &= ~what;
847                 outl(ensoniq->ctrl, ES_REG(ensoniq, CONTROL));
848                 spin_unlock(&ensoniq->reg_lock);
849                 break;
850         }
851         default:
852                 return -EINVAL;
853         }
854         return 0;
855 }
856
857 /*
858  *  PCM part
859  */
860
861 static int snd_ensoniq_hw_params(struct snd_pcm_substream *substream,
862                                  struct snd_pcm_hw_params *hw_params)
863 {
864         return snd_pcm_lib_malloc_pages(substream, params_buffer_bytes(hw_params));
865 }
866
867 static int snd_ensoniq_hw_free(struct snd_pcm_substream *substream)
868 {
869         return snd_pcm_lib_free_pages(substream);
870 }
871
872 static int snd_ensoniq_playback1_prepare(struct snd_pcm_substream *substream)
873 {
874         struct ensoniq *ensoniq = snd_pcm_substream_chip(substream);
875         struct snd_pcm_runtime *runtime = substream->runtime;
876         unsigned int mode = 0;
877
878         ensoniq->p1_dma_size = snd_pcm_lib_buffer_bytes(substream);
879         ensoniq->p1_period_size = snd_pcm_lib_period_bytes(substream);
880         if (snd_pcm_format_width(runtime->format) == 16)
881                 mode |= 0x02;
882         if (runtime->channels > 1)
883                 mode |= 0x01;
884         spin_lock_irq(&ensoniq->reg_lock);
885         ensoniq->ctrl &= ~ES_DAC1_EN;
886 #ifdef CHIP1371
887         /* 48k doesn't need SRC (it breaks AC3-passthru) */
888         if (runtime->rate == 48000)
889                 ensoniq->ctrl |= ES_1373_BYPASS_P1;
890         else
891                 ensoniq->ctrl &= ~ES_1373_BYPASS_P1;
892 #endif
893         outl(ensoniq->ctrl, ES_REG(ensoniq, CONTROL));
894         outl(ES_MEM_PAGEO(ES_PAGE_DAC), ES_REG(ensoniq, MEM_PAGE));
895         outl(runtime->dma_addr, ES_REG(ensoniq, DAC1_FRAME));
896         outl((ensoniq->p1_dma_size >> 2) - 1, ES_REG(ensoniq, DAC1_SIZE));
897         ensoniq->sctrl &= ~(ES_P1_LOOP_SEL | ES_P1_PAUSE | ES_P1_SCT_RLD | ES_P1_MODEM);
898         ensoniq->sctrl |= ES_P1_INT_EN | ES_P1_MODEO(mode);
899         outl(ensoniq->sctrl, ES_REG(ensoniq, SERIAL));
900         outl((ensoniq->p1_period_size >> snd_ensoniq_sample_shift[mode]) - 1,
901              ES_REG(ensoniq, DAC1_COUNT));
902 #ifdef CHIP1370
903         ensoniq->ctrl &= ~ES_1370_WTSRSELM;
904         switch (runtime->rate) {
905         case 5512: ensoniq->ctrl |= ES_1370_WTSRSEL(0); break;
906         case 11025: ensoniq->ctrl |= ES_1370_WTSRSEL(1); break;
907         case 22050: ensoniq->ctrl |= ES_1370_WTSRSEL(2); break;
908         case 44100: ensoniq->ctrl |= ES_1370_WTSRSEL(3); break;
909         default: snd_BUG();
910         }
911 #endif
912         outl(ensoniq->ctrl, ES_REG(ensoniq, CONTROL));
913         spin_unlock_irq(&ensoniq->reg_lock);
914 #ifndef CHIP1370
915         snd_es1371_dac1_rate(ensoniq, runtime->rate);
916 #endif
917         return 0;
918 }
919
920 static int snd_ensoniq_playback2_prepare(struct snd_pcm_substream *substream)
921 {
922         struct ensoniq *ensoniq = snd_pcm_substream_chip(substream);
923         struct snd_pcm_runtime *runtime = substream->runtime;
924         unsigned int mode = 0;
925
926         ensoniq->p2_dma_size = snd_pcm_lib_buffer_bytes(substream);
927         ensoniq->p2_period_size = snd_pcm_lib_period_bytes(substream);
928         if (snd_pcm_format_width(runtime->format) == 16)
929                 mode |= 0x02;
930         if (runtime->channels > 1)
931                 mode |= 0x01;
932         spin_lock_irq(&ensoniq->reg_lock);
933         ensoniq->ctrl &= ~ES_DAC2_EN;
934         outl(ensoniq->ctrl, ES_REG(ensoniq, CONTROL));
935         outl(ES_MEM_PAGEO(ES_PAGE_DAC), ES_REG(ensoniq, MEM_PAGE));
936         outl(runtime->dma_addr, ES_REG(ensoniq, DAC2_FRAME));
937         outl((ensoniq->p2_dma_size >> 2) - 1, ES_REG(ensoniq, DAC2_SIZE));
938         ensoniq->sctrl &= ~(ES_P2_LOOP_SEL | ES_P2_PAUSE | ES_P2_DAC_SEN |
939                             ES_P2_END_INCM | ES_P2_ST_INCM | ES_P2_MODEM);
940         ensoniq->sctrl |= ES_P2_INT_EN | ES_P2_MODEO(mode) |
941                           ES_P2_END_INCO(mode & 2 ? 2 : 1) | ES_P2_ST_INCO(0);
942         outl(ensoniq->sctrl, ES_REG(ensoniq, SERIAL));
943         outl((ensoniq->p2_period_size >> snd_ensoniq_sample_shift[mode]) - 1,
944              ES_REG(ensoniq, DAC2_COUNT));
945 #ifdef CHIP1370
946         if (!(ensoniq->u.es1370.pclkdiv_lock & ES_MODE_CAPTURE)) {
947                 ensoniq->ctrl &= ~ES_1370_PCLKDIVM;
948                 ensoniq->ctrl |= ES_1370_PCLKDIVO(ES_1370_SRTODIV(runtime->rate));
949                 ensoniq->u.es1370.pclkdiv_lock |= ES_MODE_PLAY2;
950         }
951 #endif
952         outl(ensoniq->ctrl, ES_REG(ensoniq, CONTROL));
953         spin_unlock_irq(&ensoniq->reg_lock);
954 #ifndef CHIP1370
955         snd_es1371_dac2_rate(ensoniq, runtime->rate);
956 #endif
957         return 0;
958 }
959
960 static int snd_ensoniq_capture_prepare(struct snd_pcm_substream *substream)
961 {
962         struct ensoniq *ensoniq = snd_pcm_substream_chip(substream);
963         struct snd_pcm_runtime *runtime = substream->runtime;
964         unsigned int mode = 0;
965
966         ensoniq->c_dma_size = snd_pcm_lib_buffer_bytes(substream);
967         ensoniq->c_period_size = snd_pcm_lib_period_bytes(substream);
968         if (snd_pcm_format_width(runtime->format) == 16)
969                 mode |= 0x02;
970         if (runtime->channels > 1)
971                 mode |= 0x01;
972         spin_lock_irq(&ensoniq->reg_lock);
973         ensoniq->ctrl &= ~ES_ADC_EN;
974         outl(ensoniq->ctrl, ES_REG(ensoniq, CONTROL));
975         outl(ES_MEM_PAGEO(ES_PAGE_ADC), ES_REG(ensoniq, MEM_PAGE));
976         outl(runtime->dma_addr, ES_REG(ensoniq, ADC_FRAME));
977         outl((ensoniq->c_dma_size >> 2) - 1, ES_REG(ensoniq, ADC_SIZE));
978         ensoniq->sctrl &= ~(ES_R1_LOOP_SEL | ES_R1_MODEM);
979         ensoniq->sctrl |= ES_R1_INT_EN | ES_R1_MODEO(mode);
980         outl(ensoniq->sctrl, ES_REG(ensoniq, SERIAL));
981         outl((ensoniq->c_period_size >> snd_ensoniq_sample_shift[mode]) - 1,
982              ES_REG(ensoniq, ADC_COUNT));
983 #ifdef CHIP1370
984         if (!(ensoniq->u.es1370.pclkdiv_lock & ES_MODE_PLAY2)) {
985                 ensoniq->ctrl &= ~ES_1370_PCLKDIVM;
986                 ensoniq->ctrl |= ES_1370_PCLKDIVO(ES_1370_SRTODIV(runtime->rate));
987                 ensoniq->u.es1370.pclkdiv_lock |= ES_MODE_CAPTURE;
988         }
989 #endif
990         outl(ensoniq->ctrl, ES_REG(ensoniq, CONTROL));
991         spin_unlock_irq(&ensoniq->reg_lock);
992 #ifndef CHIP1370
993         snd_es1371_adc_rate(ensoniq, runtime->rate);
994 #endif
995         return 0;
996 }
997
998 static snd_pcm_uframes_t snd_ensoniq_playback1_pointer(struct snd_pcm_substream *substream)
999 {
1000         struct ensoniq *ensoniq = snd_pcm_substream_chip(substream);
1001         size_t ptr;
1002
1003         spin_lock(&ensoniq->reg_lock);
1004         if (inl(ES_REG(ensoniq, CONTROL)) & ES_DAC1_EN) {
1005                 outl(ES_MEM_PAGEO(ES_PAGE_DAC), ES_REG(ensoniq, MEM_PAGE));
1006                 ptr = ES_REG_FCURR_COUNTI(inl(ES_REG(ensoniq, DAC1_SIZE)));
1007                 ptr = bytes_to_frames(substream->runtime, ptr);
1008         } else {
1009                 ptr = 0;
1010         }
1011         spin_unlock(&ensoniq->reg_lock);
1012         return ptr;
1013 }
1014
1015 static snd_pcm_uframes_t snd_ensoniq_playback2_pointer(struct snd_pcm_substream *substream)
1016 {
1017         struct ensoniq *ensoniq = snd_pcm_substream_chip(substream);
1018         size_t ptr;
1019
1020         spin_lock(&ensoniq->reg_lock);
1021         if (inl(ES_REG(ensoniq, CONTROL)) & ES_DAC2_EN) {
1022                 outl(ES_MEM_PAGEO(ES_PAGE_DAC), ES_REG(ensoniq, MEM_PAGE));
1023                 ptr = ES_REG_FCURR_COUNTI(inl(ES_REG(ensoniq, DAC2_SIZE)));
1024                 ptr = bytes_to_frames(substream->runtime, ptr);
1025         } else {
1026                 ptr = 0;
1027         }
1028         spin_unlock(&ensoniq->reg_lock);
1029         return ptr;
1030 }
1031
1032 static snd_pcm_uframes_t snd_ensoniq_capture_pointer(struct snd_pcm_substream *substream)
1033 {
1034         struct ensoniq *ensoniq = snd_pcm_substream_chip(substream);
1035         size_t ptr;
1036
1037         spin_lock(&ensoniq->reg_lock);
1038         if (inl(ES_REG(ensoniq, CONTROL)) & ES_ADC_EN) {
1039                 outl(ES_MEM_PAGEO(ES_PAGE_ADC), ES_REG(ensoniq, MEM_PAGE));
1040                 ptr = ES_REG_FCURR_COUNTI(inl(ES_REG(ensoniq, ADC_SIZE)));
1041                 ptr = bytes_to_frames(substream->runtime, ptr);
1042         } else {
1043                 ptr = 0;
1044         }
1045         spin_unlock(&ensoniq->reg_lock);
1046         return ptr;
1047 }
1048
1049 static struct snd_pcm_hardware snd_ensoniq_playback1 =
1050 {
1051         .info =                 (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED |
1052                                  SNDRV_PCM_INFO_BLOCK_TRANSFER |
1053                                  SNDRV_PCM_INFO_MMAP_VALID |
1054                                  SNDRV_PCM_INFO_PAUSE | SNDRV_PCM_INFO_SYNC_START),
1055         .formats =              SNDRV_PCM_FMTBIT_U8 | SNDRV_PCM_FMTBIT_S16_LE,
1056         .rates =
1057 #ifndef CHIP1370
1058                                 SNDRV_PCM_RATE_CONTINUOUS | SNDRV_PCM_RATE_8000_48000,
1059 #else
1060                                 (SNDRV_PCM_RATE_KNOT |  /* 5512Hz rate */
1061                                  SNDRV_PCM_RATE_11025 | SNDRV_PCM_RATE_22050 | 
1062                                  SNDRV_PCM_RATE_44100),
1063 #endif
1064         .rate_min =             4000,
1065         .rate_max =             48000,
1066         .channels_min =         1,
1067         .channels_max =         2,
1068         .buffer_bytes_max =     (128*1024),
1069         .period_bytes_min =     64,
1070         .period_bytes_max =     (128*1024),
1071         .periods_min =          1,
1072         .periods_max =          1024,
1073         .fifo_size =            0,
1074 };
1075
1076 static struct snd_pcm_hardware snd_ensoniq_playback2 =
1077 {
1078         .info =                 (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED |
1079                                  SNDRV_PCM_INFO_BLOCK_TRANSFER |
1080                                  SNDRV_PCM_INFO_MMAP_VALID | SNDRV_PCM_INFO_PAUSE | 
1081                                  SNDRV_PCM_INFO_SYNC_START),
1082         .formats =              SNDRV_PCM_FMTBIT_U8 | SNDRV_PCM_FMTBIT_S16_LE,
1083         .rates =                SNDRV_PCM_RATE_CONTINUOUS | SNDRV_PCM_RATE_8000_48000,
1084         .rate_min =             4000,
1085         .rate_max =             48000,
1086         .channels_min =         1,
1087         .channels_max =         2,
1088         .buffer_bytes_max =     (128*1024),
1089         .period_bytes_min =     64,
1090         .period_bytes_max =     (128*1024),
1091         .periods_min =          1,
1092         .periods_max =          1024,
1093         .fifo_size =            0,
1094 };
1095
1096 static struct snd_pcm_hardware snd_ensoniq_capture =
1097 {
1098         .info =                 (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED |
1099                                  SNDRV_PCM_INFO_BLOCK_TRANSFER |
1100                                  SNDRV_PCM_INFO_MMAP_VALID | SNDRV_PCM_INFO_SYNC_START),
1101         .formats =              SNDRV_PCM_FMTBIT_U8 | SNDRV_PCM_FMTBIT_S16_LE,
1102         .rates =                SNDRV_PCM_RATE_CONTINUOUS | SNDRV_PCM_RATE_8000_48000,
1103         .rate_min =             4000,
1104         .rate_max =             48000,
1105         .channels_min =         1,
1106         .channels_max =         2,
1107         .buffer_bytes_max =     (128*1024),
1108         .period_bytes_min =     64,
1109         .period_bytes_max =     (128*1024),
1110         .periods_min =          1,
1111         .periods_max =          1024,
1112         .fifo_size =            0,
1113 };
1114
1115 static int snd_ensoniq_playback1_open(struct snd_pcm_substream *substream)
1116 {
1117         struct ensoniq *ensoniq = snd_pcm_substream_chip(substream);
1118         struct snd_pcm_runtime *runtime = substream->runtime;
1119
1120         ensoniq->mode |= ES_MODE_PLAY1;
1121         ensoniq->playback1_substream = substream;
1122         runtime->hw = snd_ensoniq_playback1;
1123         snd_pcm_set_sync(substream);
1124         spin_lock_irq(&ensoniq->reg_lock);
1125         if (ensoniq->spdif && ensoniq->playback2_substream == NULL)
1126                 ensoniq->spdif_stream = ensoniq->spdif_default;
1127         spin_unlock_irq(&ensoniq->reg_lock);
1128 #ifdef CHIP1370
1129         snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_RATE,
1130                                    &snd_es1370_hw_constraints_rates);
1131 #else
1132         snd_pcm_hw_constraint_ratdens(runtime, 0, SNDRV_PCM_HW_PARAM_RATE,
1133                                       &snd_es1371_hw_constraints_dac_clock);
1134 #endif
1135         return 0;
1136 }
1137
1138 static int snd_ensoniq_playback2_open(struct snd_pcm_substream *substream)
1139 {
1140         struct ensoniq *ensoniq = snd_pcm_substream_chip(substream);
1141         struct snd_pcm_runtime *runtime = substream->runtime;
1142
1143         ensoniq->mode |= ES_MODE_PLAY2;
1144         ensoniq->playback2_substream = substream;
1145         runtime->hw = snd_ensoniq_playback2;
1146         snd_pcm_set_sync(substream);
1147         spin_lock_irq(&ensoniq->reg_lock);
1148         if (ensoniq->spdif && ensoniq->playback1_substream == NULL)
1149                 ensoniq->spdif_stream = ensoniq->spdif_default;
1150         spin_unlock_irq(&ensoniq->reg_lock);
1151 #ifdef CHIP1370
1152         snd_pcm_hw_constraint_ratnums(runtime, 0, SNDRV_PCM_HW_PARAM_RATE,
1153                                       &snd_es1370_hw_constraints_clock);
1154 #else
1155         snd_pcm_hw_constraint_ratdens(runtime, 0, SNDRV_PCM_HW_PARAM_RATE,
1156                                       &snd_es1371_hw_constraints_dac_clock);
1157 #endif
1158         return 0;
1159 }
1160
1161 static int snd_ensoniq_capture_open(struct snd_pcm_substream *substream)
1162 {
1163         struct ensoniq *ensoniq = snd_pcm_substream_chip(substream);
1164         struct snd_pcm_runtime *runtime = substream->runtime;
1165
1166         ensoniq->mode |= ES_MODE_CAPTURE;
1167         ensoniq->capture_substream = substream;
1168         runtime->hw = snd_ensoniq_capture;
1169         snd_pcm_set_sync(substream);
1170 #ifdef CHIP1370
1171         snd_pcm_hw_constraint_ratnums(runtime, 0, SNDRV_PCM_HW_PARAM_RATE,
1172                                       &snd_es1370_hw_constraints_clock);
1173 #else
1174         snd_pcm_hw_constraint_ratnums(runtime, 0, SNDRV_PCM_HW_PARAM_RATE,
1175                                       &snd_es1371_hw_constraints_adc_clock);
1176 #endif
1177         return 0;
1178 }
1179
1180 static int snd_ensoniq_playback1_close(struct snd_pcm_substream *substream)
1181 {
1182         struct ensoniq *ensoniq = snd_pcm_substream_chip(substream);
1183
1184         ensoniq->playback1_substream = NULL;
1185         ensoniq->mode &= ~ES_MODE_PLAY1;
1186         return 0;
1187 }
1188
1189 static int snd_ensoniq_playback2_close(struct snd_pcm_substream *substream)
1190 {
1191         struct ensoniq *ensoniq = snd_pcm_substream_chip(substream);
1192
1193         ensoniq->playback2_substream = NULL;
1194         spin_lock_irq(&ensoniq->reg_lock);
1195 #ifdef CHIP1370
1196         ensoniq->u.es1370.pclkdiv_lock &= ~ES_MODE_PLAY2;
1197 #endif
1198         ensoniq->mode &= ~ES_MODE_PLAY2;
1199         spin_unlock_irq(&ensoniq->reg_lock);
1200         return 0;
1201 }
1202
1203 static int snd_ensoniq_capture_close(struct snd_pcm_substream *substream)
1204 {
1205         struct ensoniq *ensoniq = snd_pcm_substream_chip(substream);
1206
1207         ensoniq->capture_substream = NULL;
1208         spin_lock_irq(&ensoniq->reg_lock);
1209 #ifdef CHIP1370
1210         ensoniq->u.es1370.pclkdiv_lock &= ~ES_MODE_CAPTURE;
1211 #endif
1212         ensoniq->mode &= ~ES_MODE_CAPTURE;
1213         spin_unlock_irq(&ensoniq->reg_lock);
1214         return 0;
1215 }
1216
1217 static struct snd_pcm_ops snd_ensoniq_playback1_ops = {
1218         .open =         snd_ensoniq_playback1_open,
1219         .close =        snd_ensoniq_playback1_close,
1220         .ioctl =        snd_pcm_lib_ioctl,
1221         .hw_params =    snd_ensoniq_hw_params,
1222         .hw_free =      snd_ensoniq_hw_free,
1223         .prepare =      snd_ensoniq_playback1_prepare,
1224         .trigger =      snd_ensoniq_trigger,
1225         .pointer =      snd_ensoniq_playback1_pointer,
1226 };
1227
1228 static struct snd_pcm_ops snd_ensoniq_playback2_ops = {
1229         .open =         snd_ensoniq_playback2_open,
1230         .close =        snd_ensoniq_playback2_close,
1231         .ioctl =        snd_pcm_lib_ioctl,
1232         .hw_params =    snd_ensoniq_hw_params,
1233         .hw_free =      snd_ensoniq_hw_free,
1234         .prepare =      snd_ensoniq_playback2_prepare,
1235         .trigger =      snd_ensoniq_trigger,
1236         .pointer =      snd_ensoniq_playback2_pointer,
1237 };
1238
1239 static struct snd_pcm_ops snd_ensoniq_capture_ops = {
1240         .open =         snd_ensoniq_capture_open,
1241         .close =        snd_ensoniq_capture_close,
1242         .ioctl =        snd_pcm_lib_ioctl,
1243         .hw_params =    snd_ensoniq_hw_params,
1244         .hw_free =      snd_ensoniq_hw_free,
1245         .prepare =      snd_ensoniq_capture_prepare,
1246         .trigger =      snd_ensoniq_trigger,
1247         .pointer =      snd_ensoniq_capture_pointer,
1248 };
1249
1250 static int __devinit snd_ensoniq_pcm(struct ensoniq * ensoniq, int device,
1251                                      struct snd_pcm ** rpcm)
1252 {
1253         struct snd_pcm *pcm;
1254         int err;
1255
1256         if (rpcm)
1257                 *rpcm = NULL;
1258 #ifdef CHIP1370
1259         err = snd_pcm_new(ensoniq->card, "ES1370/1", device, 1, 1, &pcm);
1260 #else
1261         err = snd_pcm_new(ensoniq->card, "ES1371/1", device, 1, 1, &pcm);
1262 #endif
1263         if (err < 0)
1264                 return err;
1265
1266 #ifdef CHIP1370
1267         snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_ensoniq_playback2_ops);
1268 #else
1269         snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_ensoniq_playback1_ops);
1270 #endif
1271         snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, &snd_ensoniq_capture_ops);
1272
1273         pcm->private_data = ensoniq;
1274         pcm->info_flags = 0;
1275 #ifdef CHIP1370
1276         strcpy(pcm->name, "ES1370 DAC2/ADC");
1277 #else
1278         strcpy(pcm->name, "ES1371 DAC2/ADC");
1279 #endif
1280         ensoniq->pcm1 = pcm;
1281
1282         snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV,
1283                                               snd_dma_pci_data(ensoniq->pci), 64*1024, 128*1024);
1284
1285         if (rpcm)
1286                 *rpcm = pcm;
1287         return 0;
1288 }
1289
1290 static int __devinit snd_ensoniq_pcm2(struct ensoniq * ensoniq, int device,
1291                                       struct snd_pcm ** rpcm)
1292 {
1293         struct snd_pcm *pcm;
1294         int err;
1295
1296         if (rpcm)
1297                 *rpcm = NULL;
1298 #ifdef CHIP1370
1299         err = snd_pcm_new(ensoniq->card, "ES1370/2", device, 1, 0, &pcm);
1300 #else
1301         err = snd_pcm_new(ensoniq->card, "ES1371/2", device, 1, 0, &pcm);
1302 #endif
1303         if (err < 0)
1304                 return err;
1305
1306 #ifdef CHIP1370
1307         snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_ensoniq_playback1_ops);
1308 #else
1309         snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_ensoniq_playback2_ops);
1310 #endif
1311         pcm->private_data = ensoniq;
1312         pcm->info_flags = 0;
1313 #ifdef CHIP1370
1314         strcpy(pcm->name, "ES1370 DAC1");
1315 #else
1316         strcpy(pcm->name, "ES1371 DAC1");
1317 #endif
1318         ensoniq->pcm2 = pcm;
1319
1320         snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV,
1321                                               snd_dma_pci_data(ensoniq->pci), 64*1024, 128*1024);
1322
1323         if (rpcm)
1324                 *rpcm = pcm;
1325         return 0;
1326 }
1327
1328 /*
1329  *  Mixer section
1330  */
1331
1332 /*
1333  * ENS1371 mixer (including SPDIF interface)
1334  */
1335 #ifdef CHIP1371
1336 static int snd_ens1373_spdif_info(struct snd_kcontrol *kcontrol,
1337                                   struct snd_ctl_elem_info *uinfo)
1338 {
1339         uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958;
1340         uinfo->count = 1;
1341         return 0;
1342 }
1343
1344 static int snd_ens1373_spdif_default_get(struct snd_kcontrol *kcontrol,
1345                                          struct snd_ctl_elem_value *ucontrol)
1346 {
1347         struct ensoniq *ensoniq = snd_kcontrol_chip(kcontrol);
1348         spin_lock_irq(&ensoniq->reg_lock);
1349         ucontrol->value.iec958.status[0] = (ensoniq->spdif_default >> 0) & 0xff;
1350         ucontrol->value.iec958.status[1] = (ensoniq->spdif_default >> 8) & 0xff;
1351         ucontrol->value.iec958.status[2] = (ensoniq->spdif_default >> 16) & 0xff;
1352         ucontrol->value.iec958.status[3] = (ensoniq->spdif_default >> 24) & 0xff;
1353         spin_unlock_irq(&ensoniq->reg_lock);
1354         return 0;
1355 }
1356
1357 static int snd_ens1373_spdif_default_put(struct snd_kcontrol *kcontrol,
1358                                          struct snd_ctl_elem_value *ucontrol)
1359 {
1360         struct ensoniq *ensoniq = snd_kcontrol_chip(kcontrol);
1361         unsigned int val;
1362         int change;
1363
1364         val = ((u32)ucontrol->value.iec958.status[0] << 0) |
1365               ((u32)ucontrol->value.iec958.status[1] << 8) |
1366               ((u32)ucontrol->value.iec958.status[2] << 16) |
1367               ((u32)ucontrol->value.iec958.status[3] << 24);
1368         spin_lock_irq(&ensoniq->reg_lock);
1369         change = ensoniq->spdif_default != val;
1370         ensoniq->spdif_default = val;
1371         if (change && ensoniq->playback1_substream == NULL &&
1372             ensoniq->playback2_substream == NULL)
1373                 outl(val, ES_REG(ensoniq, CHANNEL_STATUS));
1374         spin_unlock_irq(&ensoniq->reg_lock);
1375         return change;
1376 }
1377
1378 static int snd_ens1373_spdif_mask_get(struct snd_kcontrol *kcontrol,
1379                                       struct snd_ctl_elem_value *ucontrol)
1380 {
1381         ucontrol->value.iec958.status[0] = 0xff;
1382         ucontrol->value.iec958.status[1] = 0xff;
1383         ucontrol->value.iec958.status[2] = 0xff;
1384         ucontrol->value.iec958.status[3] = 0xff;
1385         return 0;
1386 }
1387
1388 static int snd_ens1373_spdif_stream_get(struct snd_kcontrol *kcontrol,
1389                                         struct snd_ctl_elem_value *ucontrol)
1390 {
1391         struct ensoniq *ensoniq = snd_kcontrol_chip(kcontrol);
1392         spin_lock_irq(&ensoniq->reg_lock);
1393         ucontrol->value.iec958.status[0] = (ensoniq->spdif_stream >> 0) & 0xff;
1394         ucontrol->value.iec958.status[1] = (ensoniq->spdif_stream >> 8) & 0xff;
1395         ucontrol->value.iec958.status[2] = (ensoniq->spdif_stream >> 16) & 0xff;
1396         ucontrol->value.iec958.status[3] = (ensoniq->spdif_stream >> 24) & 0xff;
1397         spin_unlock_irq(&ensoniq->reg_lock);
1398         return 0;
1399 }
1400
1401 static int snd_ens1373_spdif_stream_put(struct snd_kcontrol *kcontrol,
1402                                         struct snd_ctl_elem_value *ucontrol)
1403 {
1404         struct ensoniq *ensoniq = snd_kcontrol_chip(kcontrol);
1405         unsigned int val;
1406         int change;
1407
1408         val = ((u32)ucontrol->value.iec958.status[0] << 0) |
1409               ((u32)ucontrol->value.iec958.status[1] << 8) |
1410               ((u32)ucontrol->value.iec958.status[2] << 16) |
1411               ((u32)ucontrol->value.iec958.status[3] << 24);
1412         spin_lock_irq(&ensoniq->reg_lock);
1413         change = ensoniq->spdif_stream != val;
1414         ensoniq->spdif_stream = val;
1415         if (change && (ensoniq->playback1_substream != NULL ||
1416                        ensoniq->playback2_substream != NULL))
1417                 outl(val, ES_REG(ensoniq, CHANNEL_STATUS));
1418         spin_unlock_irq(&ensoniq->reg_lock);
1419         return change;
1420 }
1421
1422 #define ES1371_SPDIF(xname) \
1423 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, .info = snd_es1371_spdif_info, \
1424   .get = snd_es1371_spdif_get, .put = snd_es1371_spdif_put }
1425
1426 static int snd_es1371_spdif_info(struct snd_kcontrol *kcontrol,
1427                                  struct snd_ctl_elem_info *uinfo)
1428 {
1429         uinfo->type = SNDRV_CTL_ELEM_TYPE_BOOLEAN;
1430         uinfo->count = 1;
1431         uinfo->value.integer.min = 0;
1432         uinfo->value.integer.max = 1;
1433         return 0;
1434 }
1435
1436 static int snd_es1371_spdif_get(struct snd_kcontrol *kcontrol,
1437                                 struct snd_ctl_elem_value *ucontrol)
1438 {
1439         struct ensoniq *ensoniq = snd_kcontrol_chip(kcontrol);
1440         
1441         spin_lock_irq(&ensoniq->reg_lock);
1442         ucontrol->value.integer.value[0] = ensoniq->ctrl & ES_1373_SPDIF_THRU ? 1 : 0;
1443         spin_unlock_irq(&ensoniq->reg_lock);
1444         return 0;
1445 }
1446
1447 static int snd_es1371_spdif_put(struct snd_kcontrol *kcontrol,
1448                                 struct snd_ctl_elem_value *ucontrol)
1449 {
1450         struct ensoniq *ensoniq = snd_kcontrol_chip(kcontrol);
1451         unsigned int nval1, nval2;
1452         int change;
1453         
1454         nval1 = ucontrol->value.integer.value[0] ? ES_1373_SPDIF_THRU : 0;
1455         nval2 = ucontrol->value.integer.value[0] ? ES_1373_SPDIF_EN : 0;
1456         spin_lock_irq(&ensoniq->reg_lock);
1457         change = (ensoniq->ctrl & ES_1373_SPDIF_THRU) != nval1;
1458         ensoniq->ctrl &= ~ES_1373_SPDIF_THRU;
1459         ensoniq->ctrl |= nval1;
1460         ensoniq->cssr &= ~ES_1373_SPDIF_EN;
1461         ensoniq->cssr |= nval2;
1462         outl(ensoniq->ctrl, ES_REG(ensoniq, CONTROL));
1463         outl(ensoniq->cssr, ES_REG(ensoniq, STATUS));
1464         spin_unlock_irq(&ensoniq->reg_lock);
1465         return change;
1466 }
1467
1468
1469 /* spdif controls */
1470 static struct snd_kcontrol_new snd_es1371_mixer_spdif[] __devinitdata = {
1471         ES1371_SPDIF(SNDRV_CTL_NAME_IEC958("",PLAYBACK,SWITCH)),
1472         {
1473                 .iface =        SNDRV_CTL_ELEM_IFACE_PCM,
1474                 .name =         SNDRV_CTL_NAME_IEC958("",PLAYBACK,DEFAULT),
1475                 .info =         snd_ens1373_spdif_info,
1476                 .get =          snd_ens1373_spdif_default_get,
1477                 .put =          snd_ens1373_spdif_default_put,
1478         },
1479         {
1480                 .access =       SNDRV_CTL_ELEM_ACCESS_READ,
1481                 .iface =        SNDRV_CTL_ELEM_IFACE_PCM,
1482                 .name =         SNDRV_CTL_NAME_IEC958("",PLAYBACK,MASK),
1483                 .info =         snd_ens1373_spdif_info,
1484                 .get =          snd_ens1373_spdif_mask_get
1485         },
1486         {
1487                 .iface =        SNDRV_CTL_ELEM_IFACE_PCM,
1488                 .name =         SNDRV_CTL_NAME_IEC958("",PLAYBACK,PCM_STREAM),
1489                 .info =         snd_ens1373_spdif_info,
1490                 .get =          snd_ens1373_spdif_stream_get,
1491                 .put =          snd_ens1373_spdif_stream_put
1492         },
1493 };
1494
1495
1496 static int snd_es1373_rear_info(struct snd_kcontrol *kcontrol,
1497                                 struct snd_ctl_elem_info *uinfo)
1498 {
1499         uinfo->type = SNDRV_CTL_ELEM_TYPE_BOOLEAN;
1500         uinfo->count = 1;
1501         uinfo->value.integer.min = 0;
1502         uinfo->value.integer.max = 1;
1503         return 0;
1504 }
1505
1506 static int snd_es1373_rear_get(struct snd_kcontrol *kcontrol,
1507                                struct snd_ctl_elem_value *ucontrol)
1508 {
1509         struct ensoniq *ensoniq = snd_kcontrol_chip(kcontrol);
1510         int val = 0;
1511         
1512         spin_lock_irq(&ensoniq->reg_lock);
1513         if ((ensoniq->cssr & (ES_1373_REAR_BIT27|ES_1373_REAR_BIT26|
1514                               ES_1373_REAR_BIT24)) == ES_1373_REAR_BIT26)
1515                 val = 1;
1516         ucontrol->value.integer.value[0] = val;
1517         spin_unlock_irq(&ensoniq->reg_lock);
1518         return 0;
1519 }
1520
1521 static int snd_es1373_rear_put(struct snd_kcontrol *kcontrol,
1522                                struct snd_ctl_elem_value *ucontrol)
1523 {
1524         struct ensoniq *ensoniq = snd_kcontrol_chip(kcontrol);
1525         unsigned int nval1;
1526         int change;
1527         
1528         nval1 = ucontrol->value.integer.value[0] ?
1529                 ES_1373_REAR_BIT26 : (ES_1373_REAR_BIT27|ES_1373_REAR_BIT24);
1530         spin_lock_irq(&ensoniq->reg_lock);
1531         change = (ensoniq->cssr & (ES_1373_REAR_BIT27|
1532                                    ES_1373_REAR_BIT26|ES_1373_REAR_BIT24)) != nval1;
1533         ensoniq->cssr &= ~(ES_1373_REAR_BIT27|ES_1373_REAR_BIT26|ES_1373_REAR_BIT24);
1534         ensoniq->cssr |= nval1;
1535         outl(ensoniq->cssr, ES_REG(ensoniq, STATUS));
1536         spin_unlock_irq(&ensoniq->reg_lock);
1537         return change;
1538 }
1539
1540 static struct snd_kcontrol_new snd_ens1373_rear __devinitdata =
1541 {
1542         .iface =        SNDRV_CTL_ELEM_IFACE_MIXER,
1543         .name =         "AC97 2ch->4ch Copy Switch",
1544         .info =         snd_es1373_rear_info,
1545         .get =          snd_es1373_rear_get,
1546         .put =          snd_es1373_rear_put,
1547 };
1548
1549 static int snd_es1373_line_info(struct snd_kcontrol *kcontrol,
1550                                 struct snd_ctl_elem_info *uinfo)
1551 {
1552         uinfo->type = SNDRV_CTL_ELEM_TYPE_BOOLEAN;
1553         uinfo->count = 1;
1554         uinfo->value.integer.min = 0;
1555         uinfo->value.integer.max = 1;
1556         return 0;
1557 }
1558
1559 static int snd_es1373_line_get(struct snd_kcontrol *kcontrol,
1560                                struct snd_ctl_elem_value *ucontrol)
1561 {
1562         struct ensoniq *ensoniq = snd_kcontrol_chip(kcontrol);
1563         int val = 0;
1564         
1565         spin_lock_irq(&ensoniq->reg_lock);
1566         if ((ensoniq->ctrl & ES_1371_GPIO_OUTM) >= 4)
1567                 val = 1;
1568         ucontrol->value.integer.value[0] = val;
1569         spin_unlock_irq(&ensoniq->reg_lock);
1570         return 0;
1571 }
1572
1573 static int snd_es1373_line_put(struct snd_kcontrol *kcontrol,
1574                                struct snd_ctl_elem_value *ucontrol)
1575 {
1576         struct ensoniq *ensoniq = snd_kcontrol_chip(kcontrol);
1577         int changed;
1578         unsigned int ctrl;
1579         
1580         spin_lock_irq(&ensoniq->reg_lock);
1581         ctrl = ensoniq->ctrl;
1582         if (ucontrol->value.integer.value[0])
1583                 ensoniq->ctrl |= ES_1371_GPIO_OUT(4);   /* switch line-in -> rear out */
1584         else
1585                 ensoniq->ctrl &= ~ES_1371_GPIO_OUT(4);
1586         changed = (ctrl != ensoniq->ctrl);
1587         if (changed)
1588                 outl(ensoniq->ctrl, ES_REG(ensoniq, CONTROL));
1589         spin_unlock_irq(&ensoniq->reg_lock);
1590         return changed;
1591 }
1592
1593 static struct snd_kcontrol_new snd_ens1373_line __devinitdata =
1594 {
1595         .iface =        SNDRV_CTL_ELEM_IFACE_MIXER,
1596         .name =         "Line In->Rear Out Switch",
1597         .info =         snd_es1373_line_info,
1598         .get =          snd_es1373_line_get,
1599         .put =          snd_es1373_line_put,
1600 };
1601
1602 static void snd_ensoniq_mixer_free_ac97(struct snd_ac97 *ac97)
1603 {
1604         struct ensoniq *ensoniq = ac97->private_data;
1605         ensoniq->u.es1371.ac97 = NULL;
1606 }
1607
1608 static struct {
1609         unsigned short vid;             /* vendor ID */
1610         unsigned short did;             /* device ID */
1611         unsigned char rev;              /* revision */
1612 } es1371_spdif_present[] __devinitdata = {
1613         { .vid = PCI_VENDOR_ID_ENSONIQ, .did = PCI_DEVICE_ID_ENSONIQ_CT5880, .rev = CT5880REV_CT5880_C },
1614         { .vid = PCI_VENDOR_ID_ENSONIQ, .did = PCI_DEVICE_ID_ENSONIQ_CT5880, .rev = CT5880REV_CT5880_D },
1615         { .vid = PCI_VENDOR_ID_ENSONIQ, .did = PCI_DEVICE_ID_ENSONIQ_CT5880, .rev = CT5880REV_CT5880_E },
1616         { .vid = PCI_VENDOR_ID_ENSONIQ, .did = PCI_DEVICE_ID_ENSONIQ_ES1371, .rev = ES1371REV_CT5880_A },
1617         { .vid = PCI_VENDOR_ID_ENSONIQ, .did = PCI_DEVICE_ID_ENSONIQ_ES1371, .rev = ES1371REV_ES1373_8 },
1618         { .vid = PCI_ANY_ID, .did = PCI_ANY_ID }
1619 };
1620
1621 static int snd_ensoniq_1371_mixer(struct ensoniq * ensoniq, int has_spdif, int has_line)
1622 {
1623         struct snd_card *card = ensoniq->card;
1624         struct snd_ac97_bus *pbus;
1625         struct snd_ac97_template ac97;
1626         int err, idx;
1627         static struct snd_ac97_bus_ops ops = {
1628                 .write = snd_es1371_codec_write,
1629                 .read = snd_es1371_codec_read,
1630                 .wait = snd_es1371_codec_wait,
1631         };
1632
1633         if ((err = snd_ac97_bus(card, 0, &ops, NULL, &pbus)) < 0)
1634                 return err;
1635
1636         memset(&ac97, 0, sizeof(ac97));
1637         ac97.private_data = ensoniq;
1638         ac97.private_free = snd_ensoniq_mixer_free_ac97;
1639         ac97.scaps = AC97_SCAP_AUDIO;
1640         if ((err = snd_ac97_mixer(pbus, &ac97, &ensoniq->u.es1371.ac97)) < 0)
1641                 return err;
1642         for (idx = 0; es1371_spdif_present[idx].vid != (unsigned short)PCI_ANY_ID; idx++)
1643                 if ((ensoniq->pci->vendor == es1371_spdif_present[idx].vid &&
1644                      ensoniq->pci->device == es1371_spdif_present[idx].did &&
1645                      ensoniq->rev == es1371_spdif_present[idx].rev) || has_spdif > 0) {
1646                         struct snd_kcontrol *kctl;
1647                         int i, index = 0; 
1648
1649                         if (has_spdif < 0)
1650                                 break;
1651
1652                         ensoniq->spdif_default = ensoniq->spdif_stream =
1653                                 SNDRV_PCM_DEFAULT_CON_SPDIF;
1654                         outl(ensoniq->spdif_default, ES_REG(ensoniq, CHANNEL_STATUS));
1655
1656                         if (ensoniq->u.es1371.ac97->ext_id & AC97_EI_SPDIF)
1657                                 index++;
1658
1659                         for (i = 0; i < (int)ARRAY_SIZE(snd_es1371_mixer_spdif); i++) {
1660                                 kctl = snd_ctl_new1(&snd_es1371_mixer_spdif[i], ensoniq);
1661                                 if (! kctl)
1662                                         return -ENOMEM;
1663                                 kctl->id.index = index;
1664                                 if ((err = snd_ctl_add(card, kctl)) < 0)
1665                                         return err;
1666                         }
1667                         break;
1668                 }
1669         if (ensoniq->u.es1371.ac97->ext_id & AC97_EI_SDAC) {
1670                 /* mirror rear to front speakers */
1671                 ensoniq->cssr &= ~(ES_1373_REAR_BIT27|ES_1373_REAR_BIT24);
1672                 ensoniq->cssr |= ES_1373_REAR_BIT26;
1673                 err = snd_ctl_add(card, snd_ctl_new1(&snd_ens1373_rear, ensoniq));
1674                 if (err < 0)
1675                         return err;
1676         }
1677         if (((ensoniq->subsystem_vendor_id == 0x1274) &&
1678             (ensoniq->subsystem_device_id == 0x2000)) || /* GA-7DXR */
1679             ((ensoniq->subsystem_vendor_id == 0x1458) &&
1680             (ensoniq->subsystem_device_id == 0xa000)) || /* GA-8IEXP */
1681             has_line > 0) {
1682                  err = snd_ctl_add(card, snd_ctl_new1(&snd_ens1373_line, ensoniq));
1683                  if (err < 0)
1684                          return err;
1685         }
1686
1687         return 0;
1688 }
1689
1690 #endif /* CHIP1371 */
1691
1692 /* generic control callbacks for ens1370 */
1693 #ifdef CHIP1370
1694 #define ENSONIQ_CONTROL(xname, mask) \
1695 { .iface = SNDRV_CTL_ELEM_IFACE_CARD, .name = xname, .info = snd_ensoniq_control_info, \
1696   .get = snd_ensoniq_control_get, .put = snd_ensoniq_control_put, \
1697   .private_value = mask }
1698
1699 static int snd_ensoniq_control_info(struct snd_kcontrol *kcontrol,
1700                                     struct snd_ctl_elem_info *uinfo)
1701 {
1702         uinfo->type = SNDRV_CTL_ELEM_TYPE_BOOLEAN;
1703         uinfo->count = 1;
1704         uinfo->value.integer.min = 0;
1705         uinfo->value.integer.max = 1;
1706         return 0;
1707 }
1708
1709 static int snd_ensoniq_control_get(struct snd_kcontrol *kcontrol,
1710                                    struct snd_ctl_elem_value *ucontrol)
1711 {
1712         struct ensoniq *ensoniq = snd_kcontrol_chip(kcontrol);
1713         int mask = kcontrol->private_value;
1714         
1715         spin_lock_irq(&ensoniq->reg_lock);
1716         ucontrol->value.integer.value[0] = ensoniq->ctrl & mask ? 1 : 0;
1717         spin_unlock_irq(&ensoniq->reg_lock);
1718         return 0;
1719 }
1720
1721 static int snd_ensoniq_control_put(struct snd_kcontrol *kcontrol,
1722                                    struct snd_ctl_elem_value *ucontrol)
1723 {
1724         struct ensoniq *ensoniq = snd_kcontrol_chip(kcontrol);
1725         int mask = kcontrol->private_value;
1726         unsigned int nval;
1727         int change;
1728         
1729         nval = ucontrol->value.integer.value[0] ? mask : 0;
1730         spin_lock_irq(&ensoniq->reg_lock);
1731         change = (ensoniq->ctrl & mask) != nval;
1732         ensoniq->ctrl &= ~mask;
1733         ensoniq->ctrl |= nval;
1734         outl(ensoniq->ctrl, ES_REG(ensoniq, CONTROL));
1735         spin_unlock_irq(&ensoniq->reg_lock);
1736         return change;
1737 }
1738
1739 /*
1740  * ENS1370 mixer
1741  */
1742
1743 static struct snd_kcontrol_new snd_es1370_controls[2] __devinitdata = {
1744 ENSONIQ_CONTROL("PCM 0 Output also on Line-In Jack", ES_1370_XCTL0),
1745 ENSONIQ_CONTROL("Mic +5V bias", ES_1370_XCTL1)
1746 };
1747
1748 #define ES1370_CONTROLS ARRAY_SIZE(snd_es1370_controls)
1749
1750 static void snd_ensoniq_mixer_free_ak4531(struct snd_ak4531 *ak4531)
1751 {
1752         struct ensoniq *ensoniq = ak4531->private_data;
1753         ensoniq->u.es1370.ak4531 = NULL;
1754 }
1755
1756 static int __devinit snd_ensoniq_1370_mixer(struct ensoniq * ensoniq)
1757 {
1758         struct snd_card *card = ensoniq->card;
1759         struct snd_ak4531 ak4531;
1760         unsigned int idx;
1761         int err;
1762
1763         /* try reset AK4531 */
1764         outw(ES_1370_CODEC_WRITE(AK4531_RESET, 0x02), ES_REG(ensoniq, 1370_CODEC));
1765         inw(ES_REG(ensoniq, 1370_CODEC));
1766         udelay(100);
1767         outw(ES_1370_CODEC_WRITE(AK4531_RESET, 0x03), ES_REG(ensoniq, 1370_CODEC));
1768         inw(ES_REG(ensoniq, 1370_CODEC));
1769         udelay(100);
1770
1771         memset(&ak4531, 0, sizeof(ak4531));
1772         ak4531.write = snd_es1370_codec_write;
1773         ak4531.private_data = ensoniq;
1774         ak4531.private_free = snd_ensoniq_mixer_free_ak4531;
1775         if ((err = snd_ak4531_mixer(card, &ak4531, &ensoniq->u.es1370.ak4531)) < 0)
1776                 return err;
1777         for (idx = 0; idx < ES1370_CONTROLS; idx++) {
1778                 err = snd_ctl_add(card, snd_ctl_new1(&snd_es1370_controls[idx], ensoniq));
1779                 if (err < 0)
1780                         return err;
1781         }
1782         return 0;
1783 }
1784
1785 #endif /* CHIP1370 */
1786
1787 #ifdef SUPPORT_JOYSTICK
1788
1789 #ifdef CHIP1371
1790 static int __devinit snd_ensoniq_get_joystick_port(int dev)
1791 {
1792         switch (joystick_port[dev]) {
1793         case 0: /* disabled */
1794         case 1: /* auto-detect */
1795         case 0x200:
1796         case 0x208:
1797         case 0x210:
1798         case 0x218:
1799                 return joystick_port[dev];
1800
1801         default:
1802                 printk(KERN_ERR "ens1371: invalid joystick port %#x", joystick_port[dev]);
1803                 return 0;
1804         }
1805 }
1806 #else
1807 static inline int snd_ensoniq_get_joystick_port(int dev)
1808 {
1809         return joystick[dev] ? 0x200 : 0;
1810 }
1811 #endif
1812
1813 static int __devinit snd_ensoniq_create_gameport(struct ensoniq *ensoniq, int dev)
1814 {
1815         struct gameport *gp;
1816         int io_port;
1817
1818         io_port = snd_ensoniq_get_joystick_port(dev);
1819
1820         switch (io_port) {
1821         case 0:
1822                 return -ENOSYS;
1823
1824         case 1: /* auto_detect */
1825                 for (io_port = 0x200; io_port <= 0x218; io_port += 8)
1826                         if (request_region(io_port, 8, "ens137x: gameport"))
1827                                 break;
1828                 if (io_port > 0x218) {
1829                         printk(KERN_WARNING "ens137x: no gameport ports available\n");
1830                         return -EBUSY;
1831                 }
1832                 break;
1833
1834         default:
1835                 if (!request_region(io_port, 8, "ens137x: gameport")) {
1836                         printk(KERN_WARNING "ens137x: gameport io port 0x%#x in use\n",
1837                                io_port);
1838                         return -EBUSY;
1839                 }
1840                 break;
1841         }
1842
1843         ensoniq->gameport = gp = gameport_allocate_port();
1844         if (!gp) {
1845                 printk(KERN_ERR "ens137x: cannot allocate memory for gameport\n");
1846                 release_region(io_port, 8);
1847                 return -ENOMEM;
1848         }
1849
1850         gameport_set_name(gp, "ES137x");
1851         gameport_set_phys(gp, "pci%s/gameport0", pci_name(ensoniq->pci));
1852         gameport_set_dev_parent(gp, &ensoniq->pci->dev);
1853         gp->io = io_port;
1854
1855         ensoniq->ctrl |= ES_JYSTK_EN;
1856 #ifdef CHIP1371
1857         ensoniq->ctrl &= ~ES_1371_JOY_ASELM;
1858         ensoniq->ctrl |= ES_1371_JOY_ASEL((io_port - 0x200) / 8);
1859 #endif
1860         outl(ensoniq->ctrl, ES_REG(ensoniq, CONTROL));
1861
1862         gameport_register_port(ensoniq->gameport);
1863
1864         return 0;
1865 }
1866
1867 static void snd_ensoniq_free_gameport(struct ensoniq *ensoniq)
1868 {
1869         if (ensoniq->gameport) {
1870                 int port = ensoniq->gameport->io;
1871
1872                 gameport_unregister_port(ensoniq->gameport);
1873                 ensoniq->gameport = NULL;
1874                 ensoniq->ctrl &= ~ES_JYSTK_EN;
1875                 outl(ensoniq->ctrl, ES_REG(ensoniq, CONTROL));
1876                 release_region(port, 8);
1877         }
1878 }
1879 #else
1880 static inline int snd_ensoniq_create_gameport(struct ensoniq *ensoniq, long port) { return -ENOSYS; }
1881 static inline void snd_ensoniq_free_gameport(struct ensoniq *ensoniq) { }
1882 #endif /* SUPPORT_JOYSTICK */
1883
1884 /*
1885
1886  */
1887
1888 static void snd_ensoniq_proc_read(struct snd_info_entry *entry, 
1889                                   struct snd_info_buffer *buffer)
1890 {
1891         struct ensoniq *ensoniq = entry->private_data;
1892
1893 #ifdef CHIP1370
1894         snd_iprintf(buffer, "Ensoniq AudioPCI ES1370\n\n");
1895 #else
1896         snd_iprintf(buffer, "Ensoniq AudioPCI ES1371\n\n");
1897 #endif
1898         snd_iprintf(buffer, "Joystick enable  : %s\n",
1899                     ensoniq->ctrl & ES_JYSTK_EN ? "on" : "off");
1900 #ifdef CHIP1370
1901         snd_iprintf(buffer, "MIC +5V bias     : %s\n",
1902                     ensoniq->ctrl & ES_1370_XCTL1 ? "on" : "off");
1903         snd_iprintf(buffer, "Line In to AOUT  : %s\n",
1904                     ensoniq->ctrl & ES_1370_XCTL0 ? "on" : "off");
1905 #else
1906         snd_iprintf(buffer, "Joystick port    : 0x%x\n",
1907                     (ES_1371_JOY_ASELI(ensoniq->ctrl) * 8) + 0x200);
1908 #endif
1909 }
1910
1911 static void __devinit snd_ensoniq_proc_init(struct ensoniq * ensoniq)
1912 {
1913         struct snd_info_entry *entry;
1914
1915         if (! snd_card_proc_new(ensoniq->card, "audiopci", &entry))
1916                 snd_info_set_text_ops(entry, ensoniq, 1024, snd_ensoniq_proc_read);
1917 }
1918
1919 /*
1920
1921  */
1922
1923 static int snd_ensoniq_free(struct ensoniq *ensoniq)
1924 {
1925         snd_ensoniq_free_gameport(ensoniq);
1926         if (ensoniq->irq < 0)
1927                 goto __hw_end;
1928 #ifdef CHIP1370
1929         outl(ES_1370_SERR_DISABLE, ES_REG(ensoniq, CONTROL));   /* switch everything off */
1930         outl(0, ES_REG(ensoniq, SERIAL));       /* clear serial interface */
1931 #else
1932         outl(0, ES_REG(ensoniq, CONTROL));      /* switch everything off */
1933         outl(0, ES_REG(ensoniq, SERIAL));       /* clear serial interface */
1934 #endif
1935         synchronize_irq(ensoniq->irq);
1936         pci_set_power_state(ensoniq->pci, 3);
1937       __hw_end:
1938 #ifdef CHIP1370
1939         if (ensoniq->dma_bug.area)
1940                 snd_dma_free_pages(&ensoniq->dma_bug);
1941 #endif
1942         if (ensoniq->irq >= 0)
1943                 free_irq(ensoniq->irq, ensoniq);
1944         pci_release_regions(ensoniq->pci);
1945         pci_disable_device(ensoniq->pci);
1946         kfree(ensoniq);
1947         return 0;
1948 }
1949
1950 static int snd_ensoniq_dev_free(struct snd_device *device)
1951 {
1952         struct ensoniq *ensoniq = device->device_data;
1953         return snd_ensoniq_free(ensoniq);
1954 }
1955
1956 #ifdef CHIP1371
1957 static struct {
1958         unsigned short svid;            /* subsystem vendor ID */
1959         unsigned short sdid;            /* subsystem device ID */
1960 } es1371_amplifier_hack[] = {
1961         { .svid = 0x107b, .sdid = 0x2150 },     /* Gateway Solo 2150 */
1962         { .svid = 0x13bd, .sdid = 0x100c },     /* EV1938 on Mebius PC-MJ100V */
1963         { .svid = 0x1102, .sdid = 0x5938 },     /* Targa Xtender300 */
1964         { .svid = 0x1102, .sdid = 0x8938 },     /* IPC Topnote G notebook */
1965         { .svid = PCI_ANY_ID, .sdid = PCI_ANY_ID }
1966 };
1967 static struct {
1968         unsigned short vid;             /* vendor ID */
1969         unsigned short did;             /* device ID */
1970         unsigned char rev;              /* revision */
1971 } es1371_ac97_reset_hack[] = {
1972         { .vid = PCI_VENDOR_ID_ENSONIQ, .did = PCI_DEVICE_ID_ENSONIQ_CT5880, .rev = CT5880REV_CT5880_C },
1973         { .vid = PCI_VENDOR_ID_ENSONIQ, .did = PCI_DEVICE_ID_ENSONIQ_CT5880, .rev = CT5880REV_CT5880_D },
1974         { .vid = PCI_VENDOR_ID_ENSONIQ, .did = PCI_DEVICE_ID_ENSONIQ_CT5880, .rev = CT5880REV_CT5880_E },
1975         { .vid = PCI_VENDOR_ID_ENSONIQ, .did = PCI_DEVICE_ID_ENSONIQ_ES1371, .rev = ES1371REV_CT5880_A },
1976         { .vid = PCI_VENDOR_ID_ENSONIQ, .did = PCI_DEVICE_ID_ENSONIQ_ES1371, .rev = ES1371REV_ES1373_8 },
1977         { .vid = PCI_ANY_ID, .did = PCI_ANY_ID }
1978 };
1979 #endif
1980
1981 static void snd_ensoniq_chip_init(struct ensoniq *ensoniq)
1982 {
1983 #ifdef CHIP1371
1984         int idx;
1985         struct pci_dev *pci = ensoniq->pci;
1986 #endif
1987         /* this code was part of snd_ensoniq_create before intruduction
1988           * of suspend/resume
1989           */
1990 #ifdef CHIP1370
1991         outl(ensoniq->ctrl, ES_REG(ensoniq, CONTROL));
1992         outl(ensoniq->sctrl, ES_REG(ensoniq, SERIAL));
1993         outl(ES_MEM_PAGEO(ES_PAGE_ADC), ES_REG(ensoniq, MEM_PAGE));
1994         outl(ensoniq->dma_bug.addr, ES_REG(ensoniq, PHANTOM_FRAME));
1995         outl(0, ES_REG(ensoniq, PHANTOM_COUNT));
1996 #else
1997         outl(ensoniq->ctrl, ES_REG(ensoniq, CONTROL));
1998         outl(ensoniq->sctrl, ES_REG(ensoniq, SERIAL));
1999         outl(0, ES_REG(ensoniq, 1371_LEGACY));
2000         for (idx = 0; es1371_ac97_reset_hack[idx].vid != (unsigned short)PCI_ANY_ID; idx++)
2001                 if (pci->vendor == es1371_ac97_reset_hack[idx].vid &&
2002                     pci->device == es1371_ac97_reset_hack[idx].did &&
2003                     ensoniq->rev == es1371_ac97_reset_hack[idx].rev) {
2004                         outl(ensoniq->cssr, ES_REG(ensoniq, STATUS));
2005                         /* need to delay around 20ms(bleech) to give
2006                         some CODECs enough time to wakeup */
2007                         msleep(20);
2008                         break;
2009                 }
2010         /* AC'97 warm reset to start the bitclk */
2011         outl(ensoniq->ctrl | ES_1371_SYNC_RES, ES_REG(ensoniq, CONTROL));
2012         inl(ES_REG(ensoniq, CONTROL));
2013         udelay(20);
2014         outl(ensoniq->ctrl, ES_REG(ensoniq, CONTROL));
2015         /* Init the sample rate converter */
2016         snd_es1371_wait_src_ready(ensoniq);     
2017         outl(ES_1371_SRC_DISABLE, ES_REG(ensoniq, 1371_SMPRATE));
2018         for (idx = 0; idx < 0x80; idx++)
2019                 snd_es1371_src_write(ensoniq, idx, 0);
2020         snd_es1371_src_write(ensoniq, ES_SMPREG_DAC1 + ES_SMPREG_TRUNC_N, 16 << 4);
2021         snd_es1371_src_write(ensoniq, ES_SMPREG_DAC1 + ES_SMPREG_INT_REGS, 16 << 10);
2022         snd_es1371_src_write(ensoniq, ES_SMPREG_DAC2 + ES_SMPREG_TRUNC_N, 16 << 4);
2023         snd_es1371_src_write(ensoniq, ES_SMPREG_DAC2 + ES_SMPREG_INT_REGS, 16 << 10);
2024         snd_es1371_src_write(ensoniq, ES_SMPREG_VOL_ADC, 1 << 12);
2025         snd_es1371_src_write(ensoniq, ES_SMPREG_VOL_ADC + 1, 1 << 12);
2026         snd_es1371_src_write(ensoniq, ES_SMPREG_VOL_DAC1, 1 << 12);
2027         snd_es1371_src_write(ensoniq, ES_SMPREG_VOL_DAC1 + 1, 1 << 12);
2028         snd_es1371_src_write(ensoniq, ES_SMPREG_VOL_DAC2, 1 << 12);
2029         snd_es1371_src_write(ensoniq, ES_SMPREG_VOL_DAC2 + 1, 1 << 12);
2030         snd_es1371_adc_rate(ensoniq, 22050);
2031         snd_es1371_dac1_rate(ensoniq, 22050);
2032         snd_es1371_dac2_rate(ensoniq, 22050);
2033         /* WARNING:
2034          * enabling the sample rate converter without properly programming
2035          * its parameters causes the chip to lock up (the SRC busy bit will
2036          * be stuck high, and I've found no way to rectify this other than
2037          * power cycle) - Thomas Sailer
2038          */
2039         snd_es1371_wait_src_ready(ensoniq);
2040         outl(0, ES_REG(ensoniq, 1371_SMPRATE));
2041         /* try reset codec directly */
2042         outl(ES_1371_CODEC_WRITE(0, 0), ES_REG(ensoniq, 1371_CODEC));
2043 #endif
2044         outb(ensoniq->uartc = 0x00, ES_REG(ensoniq, UART_CONTROL));
2045         outb(0x00, ES_REG(ensoniq, UART_RES));
2046         outl(ensoniq->cssr, ES_REG(ensoniq, STATUS));
2047         synchronize_irq(ensoniq->irq);
2048 }
2049
2050 #ifdef CONFIG_PM
2051 static int snd_ensoniq_suspend(struct pci_dev *pci, pm_message_t state)
2052 {
2053         struct snd_card *card = pci_get_drvdata(pci);
2054         struct ensoniq *ensoniq = card->private_data;
2055         
2056         snd_power_change_state(card, SNDRV_CTL_POWER_D3hot);
2057
2058         snd_pcm_suspend_all(ensoniq->pcm1);
2059         snd_pcm_suspend_all(ensoniq->pcm2);
2060         
2061 #ifdef CHIP1371 
2062         snd_ac97_suspend(ensoniq->u.es1371.ac97);
2063 #else
2064         /* try to reset AK4531 */
2065         outw(ES_1370_CODEC_WRITE(AK4531_RESET, 0x02), ES_REG(ensoniq, 1370_CODEC));
2066         inw(ES_REG(ensoniq, 1370_CODEC));
2067         udelay(100);
2068         outw(ES_1370_CODEC_WRITE(AK4531_RESET, 0x03), ES_REG(ensoniq, 1370_CODEC));
2069         inw(ES_REG(ensoniq, 1370_CODEC));
2070         udelay(100);
2071         snd_ak4531_suspend(ensoniq->u.es1370.ak4531);
2072 #endif  
2073         pci_set_power_state(pci, PCI_D3hot);
2074         pci_disable_device(pci);
2075         pci_save_state(pci);
2076         return 0;
2077 }
2078
2079 static int snd_ensoniq_resume(struct pci_dev *pci)
2080 {
2081         struct snd_card *card = pci_get_drvdata(pci);
2082         struct ensoniq *ensoniq = card->private_data;
2083
2084         pci_restore_state(pci);
2085         pci_enable_device(pci);
2086         pci_set_power_state(pci, PCI_D0);
2087         pci_set_master(pci);
2088
2089         snd_ensoniq_chip_init(ensoniq);
2090
2091 #ifdef CHIP1371 
2092         snd_ac97_resume(ensoniq->u.es1371.ac97);
2093 #else
2094         snd_ak4531_resume(ensoniq->u.es1370.ak4531);
2095 #endif  
2096         snd_power_change_state(card, SNDRV_CTL_POWER_D0);
2097         return 0;
2098 }
2099 #endif /* CONFIG_PM */
2100
2101
2102 static int __devinit snd_ensoniq_create(struct snd_card *card,
2103                                      struct pci_dev *pci,
2104                                      struct ensoniq ** rensoniq)
2105 {
2106         struct ensoniq *ensoniq;
2107         unsigned short cmdw;
2108         unsigned char cmdb;
2109 #ifdef CHIP1371
2110         int idx;
2111 #endif
2112         int err;
2113         static struct snd_device_ops ops = {
2114                 .dev_free =     snd_ensoniq_dev_free,
2115         };
2116
2117         *rensoniq = NULL;
2118         if ((err = pci_enable_device(pci)) < 0)
2119                 return err;
2120         ensoniq = kzalloc(sizeof(*ensoniq), GFP_KERNEL);
2121         if (ensoniq == NULL) {
2122                 pci_disable_device(pci);
2123                 return -ENOMEM;
2124         }
2125         spin_lock_init(&ensoniq->reg_lock);
2126         init_MUTEX(&ensoniq->src_mutex);
2127         ensoniq->card = card;
2128         ensoniq->pci = pci;
2129         ensoniq->irq = -1;
2130         if ((err = pci_request_regions(pci, "Ensoniq AudioPCI")) < 0) {
2131                 kfree(ensoniq);
2132                 pci_disable_device(pci);
2133                 return err;
2134         }
2135         ensoniq->port = pci_resource_start(pci, 0);
2136         if (request_irq(pci->irq, snd_audiopci_interrupt, SA_INTERRUPT|SA_SHIRQ,
2137                         "Ensoniq AudioPCI", ensoniq)) {
2138                 snd_printk(KERN_ERR "unable to grab IRQ %d\n", pci->irq);
2139                 snd_ensoniq_free(ensoniq);
2140                 return -EBUSY;
2141         }
2142         ensoniq->irq = pci->irq;
2143 #ifdef CHIP1370
2144         if (snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV, snd_dma_pci_data(pci),
2145                                 16, &ensoniq->dma_bug) < 0) {
2146                 snd_printk(KERN_ERR "unable to allocate space for phantom area - dma_bug\n");
2147                 snd_ensoniq_free(ensoniq);
2148                 return -EBUSY;
2149         }
2150 #endif
2151         pci_set_master(pci);
2152         pci_read_config_byte(pci, PCI_REVISION_ID, &cmdb);
2153         ensoniq->rev = cmdb;
2154         pci_read_config_word(pci, PCI_SUBSYSTEM_VENDOR_ID, &cmdw);
2155         ensoniq->subsystem_vendor_id = cmdw;
2156         pci_read_config_word(pci, PCI_SUBSYSTEM_ID, &cmdw);
2157         ensoniq->subsystem_device_id = cmdw;
2158 #ifdef CHIP1370
2159 #if 0
2160         ensoniq->ctrl = ES_1370_CDC_EN | ES_1370_SERR_DISABLE |
2161                 ES_1370_PCLKDIVO(ES_1370_SRTODIV(8000));
2162 #else   /* get microphone working */
2163         ensoniq->ctrl = ES_1370_CDC_EN | ES_1370_PCLKDIVO(ES_1370_SRTODIV(8000));
2164 #endif
2165         ensoniq->sctrl = 0;
2166 #else
2167         ensoniq->ctrl = 0;
2168         ensoniq->sctrl = 0;
2169         ensoniq->cssr = 0;
2170         for (idx = 0; es1371_amplifier_hack[idx].svid != (unsigned short)PCI_ANY_ID; idx++)
2171                 if (ensoniq->subsystem_vendor_id == es1371_amplifier_hack[idx].svid &&
2172                     ensoniq->subsystem_device_id == es1371_amplifier_hack[idx].sdid) {
2173                         ensoniq->ctrl |= ES_1371_GPIO_OUT(1);   /* turn amplifier on */
2174                         break;
2175                 }
2176         for (idx = 0; es1371_ac97_reset_hack[idx].vid != (unsigned short)PCI_ANY_ID; idx++)
2177                 if (pci->vendor == es1371_ac97_reset_hack[idx].vid &&
2178                     pci->device == es1371_ac97_reset_hack[idx].did &&
2179                     ensoniq->rev == es1371_ac97_reset_hack[idx].rev) {
2180                         ensoniq->cssr |= ES_1371_ST_AC97_RST;
2181                         break;
2182                 }
2183 #endif
2184
2185         snd_ensoniq_chip_init(ensoniq);
2186
2187         if ((err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, ensoniq, &ops)) < 0) {
2188                 snd_ensoniq_free(ensoniq);
2189                 return err;
2190         }
2191
2192         snd_ensoniq_proc_init(ensoniq);
2193
2194         snd_card_set_dev(card, &pci->dev);
2195
2196         *rensoniq = ensoniq;
2197         return 0;
2198 }
2199
2200 /*
2201  *  MIDI section
2202  */
2203
2204 static void snd_ensoniq_midi_interrupt(struct ensoniq * ensoniq)
2205 {
2206         struct snd_rawmidi *rmidi = ensoniq->rmidi;
2207         unsigned char status, mask, byte;
2208
2209         if (rmidi == NULL)
2210                 return;
2211         /* do Rx at first */
2212         spin_lock(&ensoniq->reg_lock);
2213         mask = ensoniq->uartm & ES_MODE_INPUT ? ES_RXRDY : 0;
2214         while (mask) {
2215                 status = inb(ES_REG(ensoniq, UART_STATUS));
2216                 if ((status & mask) == 0)
2217                         break;
2218                 byte = inb(ES_REG(ensoniq, UART_DATA));
2219                 snd_rawmidi_receive(ensoniq->midi_input, &byte, 1);
2220         }
2221         spin_unlock(&ensoniq->reg_lock);
2222
2223         /* do Tx at second */
2224         spin_lock(&ensoniq->reg_lock);
2225         mask = ensoniq->uartm & ES_MODE_OUTPUT ? ES_TXRDY : 0;
2226         while (mask) {
2227                 status = inb(ES_REG(ensoniq, UART_STATUS));
2228                 if ((status & mask) == 0)
2229                         break;
2230                 if (snd_rawmidi_transmit(ensoniq->midi_output, &byte, 1) != 1) {
2231                         ensoniq->uartc &= ~ES_TXINTENM;
2232                         outb(ensoniq->uartc, ES_REG(ensoniq, UART_CONTROL));
2233                         mask &= ~ES_TXRDY;
2234                 } else {
2235                         outb(byte, ES_REG(ensoniq, UART_DATA));
2236                 }
2237         }
2238         spin_unlock(&ensoniq->reg_lock);
2239 }
2240
2241 static int snd_ensoniq_midi_input_open(struct snd_rawmidi_substream *substream)
2242 {
2243         struct ensoniq *ensoniq = substream->rmidi->private_data;
2244
2245         spin_lock_irq(&ensoniq->reg_lock);
2246         ensoniq->uartm |= ES_MODE_INPUT;
2247         ensoniq->midi_input = substream;
2248         if (!(ensoniq->uartm & ES_MODE_OUTPUT)) {
2249                 outb(ES_CNTRL(3), ES_REG(ensoniq, UART_CONTROL));
2250                 outb(ensoniq->uartc = 0, ES_REG(ensoniq, UART_CONTROL));
2251                 outl(ensoniq->ctrl |= ES_UART_EN, ES_REG(ensoniq, CONTROL));
2252         }
2253         spin_unlock_irq(&ensoniq->reg_lock);
2254         return 0;
2255 }
2256
2257 static int snd_ensoniq_midi_input_close(struct snd_rawmidi_substream *substream)
2258 {
2259         struct ensoniq *ensoniq = substream->rmidi->private_data;
2260
2261         spin_lock_irq(&ensoniq->reg_lock);
2262         if (!(ensoniq->uartm & ES_MODE_OUTPUT)) {
2263                 outb(ensoniq->uartc = 0, ES_REG(ensoniq, UART_CONTROL));
2264                 outl(ensoniq->ctrl &= ~ES_UART_EN, ES_REG(ensoniq, CONTROL));
2265         } else {
2266                 outb(ensoniq->uartc &= ~ES_RXINTEN, ES_REG(ensoniq, UART_CONTROL));
2267         }
2268         ensoniq->midi_input = NULL;
2269         ensoniq->uartm &= ~ES_MODE_INPUT;
2270         spin_unlock_irq(&ensoniq->reg_lock);
2271         return 0;
2272 }
2273
2274 static int snd_ensoniq_midi_output_open(struct snd_rawmidi_substream *substream)
2275 {
2276         struct ensoniq *ensoniq = substream->rmidi->private_data;
2277
2278         spin_lock_irq(&ensoniq->reg_lock);
2279         ensoniq->uartm |= ES_MODE_OUTPUT;
2280         ensoniq->midi_output = substream;
2281         if (!(ensoniq->uartm & ES_MODE_INPUT)) {
2282                 outb(ES_CNTRL(3), ES_REG(ensoniq, UART_CONTROL));
2283                 outb(ensoniq->uartc = 0, ES_REG(ensoniq, UART_CONTROL));
2284                 outl(ensoniq->ctrl |= ES_UART_EN, ES_REG(ensoniq, CONTROL));
2285         }
2286         spin_unlock_irq(&ensoniq->reg_lock);
2287         return 0;
2288 }
2289
2290 static int snd_ensoniq_midi_output_close(struct snd_rawmidi_substream *substream)
2291 {
2292         struct ensoniq *ensoniq = substream->rmidi->private_data;
2293
2294         spin_lock_irq(&ensoniq->reg_lock);
2295         if (!(ensoniq->uartm & ES_MODE_INPUT)) {
2296                 outb(ensoniq->uartc = 0, ES_REG(ensoniq, UART_CONTROL));
2297                 outl(ensoniq->ctrl &= ~ES_UART_EN, ES_REG(ensoniq, CONTROL));
2298         } else {
2299                 outb(ensoniq->uartc &= ~ES_TXINTENM, ES_REG(ensoniq, UART_CONTROL));
2300         }
2301         ensoniq->midi_output = NULL;
2302         ensoniq->uartm &= ~ES_MODE_OUTPUT;
2303         spin_unlock_irq(&ensoniq->reg_lock);
2304         return 0;
2305 }
2306
2307 static void snd_ensoniq_midi_input_trigger(struct snd_rawmidi_substream *substream, int up)
2308 {
2309         unsigned long flags;
2310         struct ensoniq *ensoniq = substream->rmidi->private_data;
2311         int idx;
2312
2313         spin_lock_irqsave(&ensoniq->reg_lock, flags);
2314         if (up) {
2315                 if ((ensoniq->uartc & ES_RXINTEN) == 0) {
2316                         /* empty input FIFO */
2317                         for (idx = 0; idx < 32; idx++)
2318                                 inb(ES_REG(ensoniq, UART_DATA));
2319                         ensoniq->uartc |= ES_RXINTEN;
2320                         outb(ensoniq->uartc, ES_REG(ensoniq, UART_CONTROL));
2321                 }
2322         } else {
2323                 if (ensoniq->uartc & ES_RXINTEN) {
2324                         ensoniq->uartc &= ~ES_RXINTEN;
2325                         outb(ensoniq->uartc, ES_REG(ensoniq, UART_CONTROL));
2326                 }
2327         }
2328         spin_unlock_irqrestore(&ensoniq->reg_lock, flags);
2329 }
2330
2331 static void snd_ensoniq_midi_output_trigger(struct snd_rawmidi_substream *substream, int up)
2332 {
2333         unsigned long flags;
2334         struct ensoniq *ensoniq = substream->rmidi->private_data;
2335         unsigned char byte;
2336
2337         spin_lock_irqsave(&ensoniq->reg_lock, flags);
2338         if (up) {
2339                 if (ES_TXINTENI(ensoniq->uartc) == 0) {
2340                         ensoniq->uartc |= ES_TXINTENO(1);
2341                         /* fill UART FIFO buffer at first, and turn Tx interrupts only if necessary */
2342                         while (ES_TXINTENI(ensoniq->uartc) == 1 &&
2343                                (inb(ES_REG(ensoniq, UART_STATUS)) & ES_TXRDY)) {
2344                                 if (snd_rawmidi_transmit(substream, &byte, 1) != 1) {
2345                                         ensoniq->uartc &= ~ES_TXINTENM;
2346                                 } else {
2347                                         outb(byte, ES_REG(ensoniq, UART_DATA));
2348                                 }
2349                         }
2350                         outb(ensoniq->uartc, ES_REG(ensoniq, UART_CONTROL));
2351                 }
2352         } else {
2353                 if (ES_TXINTENI(ensoniq->uartc) == 1) {
2354                         ensoniq->uartc &= ~ES_TXINTENM;
2355                         outb(ensoniq->uartc, ES_REG(ensoniq, UART_CONTROL));
2356                 }
2357         }
2358         spin_unlock_irqrestore(&ensoniq->reg_lock, flags);
2359 }
2360
2361 static struct snd_rawmidi_ops snd_ensoniq_midi_output =
2362 {
2363         .open =         snd_ensoniq_midi_output_open,
2364         .close =        snd_ensoniq_midi_output_close,
2365         .trigger =      snd_ensoniq_midi_output_trigger,
2366 };
2367
2368 static struct snd_rawmidi_ops snd_ensoniq_midi_input =
2369 {
2370         .open =         snd_ensoniq_midi_input_open,
2371         .close =        snd_ensoniq_midi_input_close,
2372         .trigger =      snd_ensoniq_midi_input_trigger,
2373 };
2374
2375 static int __devinit snd_ensoniq_midi(struct ensoniq * ensoniq, int device,
2376                                       struct snd_rawmidi **rrawmidi)
2377 {
2378         struct snd_rawmidi *rmidi;
2379         int err;
2380
2381         if (rrawmidi)
2382                 *rrawmidi = NULL;
2383         if ((err = snd_rawmidi_new(ensoniq->card, "ES1370/1", device, 1, 1, &rmidi)) < 0)
2384                 return err;
2385 #ifdef CHIP1370
2386         strcpy(rmidi->name, "ES1370");
2387 #else
2388         strcpy(rmidi->name, "ES1371");
2389 #endif
2390         snd_rawmidi_set_ops(rmidi, SNDRV_RAWMIDI_STREAM_OUTPUT, &snd_ensoniq_midi_output);
2391         snd_rawmidi_set_ops(rmidi, SNDRV_RAWMIDI_STREAM_INPUT, &snd_ensoniq_midi_input);
2392         rmidi->info_flags |= SNDRV_RAWMIDI_INFO_OUTPUT | SNDRV_RAWMIDI_INFO_INPUT |
2393                 SNDRV_RAWMIDI_INFO_DUPLEX;
2394         rmidi->private_data = ensoniq;
2395         ensoniq->rmidi = rmidi;
2396         if (rrawmidi)
2397                 *rrawmidi = rmidi;
2398         return 0;
2399 }
2400
2401 /*
2402  *  Interrupt handler
2403  */
2404
2405 static irqreturn_t snd_audiopci_interrupt(int irq, void *dev_id, struct pt_regs *regs)
2406 {
2407         struct ensoniq *ensoniq = dev_id;
2408         unsigned int status, sctrl;
2409
2410         if (ensoniq == NULL)
2411                 return IRQ_NONE;
2412
2413         status = inl(ES_REG(ensoniq, STATUS));
2414         if (!(status & ES_INTR))
2415                 return IRQ_NONE;
2416
2417         spin_lock(&ensoniq->reg_lock);
2418         sctrl = ensoniq->sctrl;
2419         if (status & ES_DAC1)
2420                 sctrl &= ~ES_P1_INT_EN;
2421         if (status & ES_DAC2)
2422                 sctrl &= ~ES_P2_INT_EN;
2423         if (status & ES_ADC)
2424                 sctrl &= ~ES_R1_INT_EN;
2425         outl(sctrl, ES_REG(ensoniq, SERIAL));
2426         outl(ensoniq->sctrl, ES_REG(ensoniq, SERIAL));
2427         spin_unlock(&ensoniq->reg_lock);
2428
2429         if (status & ES_UART)
2430                 snd_ensoniq_midi_interrupt(ensoniq);
2431         if ((status & ES_DAC2) && ensoniq->playback2_substream)
2432                 snd_pcm_period_elapsed(ensoniq->playback2_substream);
2433         if ((status & ES_ADC) && ensoniq->capture_substream)
2434                 snd_pcm_period_elapsed(ensoniq->capture_substream);
2435         if ((status & ES_DAC1) && ensoniq->playback1_substream)
2436                 snd_pcm_period_elapsed(ensoniq->playback1_substream);
2437         return IRQ_HANDLED;
2438 }
2439
2440 static int __devinit snd_audiopci_probe(struct pci_dev *pci,
2441                                         const struct pci_device_id *pci_id)
2442 {
2443         static int dev;
2444         struct snd_card *card;
2445         struct ensoniq *ensoniq;
2446         int err, pcm_devs[2];
2447
2448         if (dev >= SNDRV_CARDS)
2449                 return -ENODEV;
2450         if (!enable[dev]) {
2451                 dev++;
2452                 return -ENOENT;
2453         }
2454
2455         card = snd_card_new(index[dev], id[dev], THIS_MODULE, 0);
2456         if (card == NULL)
2457                 return -ENOMEM;
2458
2459         if ((err = snd_ensoniq_create(card, pci, &ensoniq)) < 0) {
2460                 snd_card_free(card);
2461                 return err;
2462         }
2463         card->private_data = ensoniq;
2464
2465         pcm_devs[0] = 0; pcm_devs[1] = 1;
2466 #ifdef CHIP1370
2467         if ((err = snd_ensoniq_1370_mixer(ensoniq)) < 0) {
2468                 snd_card_free(card);
2469                 return err;
2470         }
2471 #endif
2472 #ifdef CHIP1371
2473         if ((err = snd_ensoniq_1371_mixer(ensoniq, spdif[dev], lineio[dev])) < 0) {
2474                 snd_card_free(card);
2475                 return err;
2476         }
2477 #endif
2478         if ((err = snd_ensoniq_pcm(ensoniq, 0, NULL)) < 0) {
2479                 snd_card_free(card);
2480                 return err;
2481         }
2482         if ((err = snd_ensoniq_pcm2(ensoniq, 1, NULL)) < 0) {
2483                 snd_card_free(card);
2484                 return err;
2485         }
2486         if ((err = snd_ensoniq_midi(ensoniq, 0, NULL)) < 0) {
2487                 snd_card_free(card);
2488                 return err;
2489         }
2490
2491         snd_ensoniq_create_gameport(ensoniq, dev);
2492
2493         strcpy(card->driver, DRIVER_NAME);
2494
2495         strcpy(card->shortname, "Ensoniq AudioPCI");
2496         sprintf(card->longname, "%s %s at 0x%lx, irq %i",
2497                 card->shortname,
2498                 card->driver,
2499                 ensoniq->port,
2500                 ensoniq->irq);
2501
2502         if ((err = snd_card_register(card)) < 0) {
2503                 snd_card_free(card);
2504                 return err;
2505         }
2506
2507         pci_set_drvdata(pci, card);
2508         dev++;
2509         return 0;
2510 }
2511
2512 static void __devexit snd_audiopci_remove(struct pci_dev *pci)
2513 {
2514         snd_card_free(pci_get_drvdata(pci));
2515         pci_set_drvdata(pci, NULL);
2516 }
2517
2518 static struct pci_driver driver = {
2519         .name = DRIVER_NAME,
2520         .id_table = snd_audiopci_ids,
2521         .probe = snd_audiopci_probe,
2522         .remove = __devexit_p(snd_audiopci_remove),
2523 #ifdef CONFIG_PM
2524         .suspend = snd_ensoniq_suspend,
2525         .resume = snd_ensoniq_resume,
2526 #endif
2527 };
2528         
2529 static int __init alsa_card_ens137x_init(void)
2530 {
2531         return pci_register_driver(&driver);
2532 }
2533
2534 static void __exit alsa_card_ens137x_exit(void)
2535 {
2536         pci_unregister_driver(&driver);
2537 }
2538
2539 module_init(alsa_card_ens137x_init)
2540 module_exit(alsa_card_ens137x_exit)