ALSA: ctxfi - Add prefix to debug prints
[linux-2.6.git] / sound / pci / ctxfi / cthw20k2.c
1 /**
2  * Copyright (C) 2008, Creative Technology Ltd. All Rights Reserved.
3  *
4  * This source file is released under GPL v2 license (no other versions).
5  * See the COPYING file included in the main directory of this source
6  * distribution for the license terms and conditions.
7  *
8  * @File        cthw20k2.c
9  *
10  * @Brief
11  * This file contains the implementation of hardware access methord for 20k2.
12  *
13  * @Author      Liu Chun
14  * @Date        May 14 2008
15  *
16  */
17
18 #include "cthw20k2.h"
19 #include "ct20k2reg.h"
20 #include <linux/types.h>
21 #include <linux/slab.h>
22 #include <linux/pci.h>
23 #include <linux/io.h>
24 #include <linux/string.h>
25 #include <linux/kernel.h>
26 #include <linux/interrupt.h>
27 #include <linux/delay.h>
28
29 #define CT_XFI_DMA_MASK         DMA_BIT_MASK(32) /* 32 bits */
30
31 static u32 hw_read_20kx(struct hw *hw, u32 reg);
32 static void hw_write_20kx(struct hw *hw, u32 reg, u32 data);
33
34 /*
35  * Type definition block.
36  * The layout of control structures can be directly applied on 20k2 chip.
37  */
38
39 /*
40  * SRC control block definitions.
41  */
42
43 /* SRC resource control block */
44 #define SRCCTL_STATE    0x00000007
45 #define SRCCTL_BM       0x00000008
46 #define SRCCTL_RSR      0x00000030
47 #define SRCCTL_SF       0x000001C0
48 #define SRCCTL_WR       0x00000200
49 #define SRCCTL_PM       0x00000400
50 #define SRCCTL_ROM      0x00001800
51 #define SRCCTL_VO       0x00002000
52 #define SRCCTL_ST       0x00004000
53 #define SRCCTL_IE       0x00008000
54 #define SRCCTL_ILSZ     0x000F0000
55 #define SRCCTL_BP       0x00100000
56
57 #define SRCCCR_CISZ     0x000007FF
58 #define SRCCCR_CWA      0x001FF800
59 #define SRCCCR_D        0x00200000
60 #define SRCCCR_RS       0x01C00000
61 #define SRCCCR_NAL      0x3E000000
62 #define SRCCCR_RA       0xC0000000
63
64 #define SRCCA_CA        0x0FFFFFFF
65 #define SRCCA_RS        0xE0000000
66
67 #define SRCSA_SA        0x0FFFFFFF
68
69 #define SRCLA_LA        0x0FFFFFFF
70
71 /* Mixer Parameter Ring ram Low and Hight register.
72  * Fixed-point value in 8.24 format for parameter channel */
73 #define MPRLH_PITCH     0xFFFFFFFF
74
75 /* SRC resource register dirty flags */
76 union src_dirty {
77         struct {
78                 u16 ctl:1;
79                 u16 ccr:1;
80                 u16 sa:1;
81                 u16 la:1;
82                 u16 ca:1;
83                 u16 mpr:1;
84                 u16 czbfs:1;    /* Clear Z-Buffers */
85                 u16 rsv:9;
86         } bf;
87         u16 data;
88 };
89
90 struct src_rsc_ctrl_blk {
91         unsigned int    ctl;
92         unsigned int    ccr;
93         unsigned int    ca;
94         unsigned int    sa;
95         unsigned int    la;
96         unsigned int    mpr;
97         union src_dirty dirty;
98 };
99
100 /* SRC manager control block */
101 union src_mgr_dirty {
102         struct {
103                 u16 enb0:1;
104                 u16 enb1:1;
105                 u16 enb2:1;
106                 u16 enb3:1;
107                 u16 enb4:1;
108                 u16 enb5:1;
109                 u16 enb6:1;
110                 u16 enb7:1;
111                 u16 enbsa:1;
112                 u16 rsv:7;
113         } bf;
114         u16 data;
115 };
116
117 struct src_mgr_ctrl_blk {
118         unsigned int            enbsa;
119         unsigned int            enb[8];
120         union src_mgr_dirty     dirty;
121 };
122
123 /* SRCIMP manager control block */
124 #define SRCAIM_ARC      0x00000FFF
125 #define SRCAIM_NXT      0x00FF0000
126 #define SRCAIM_SRC      0xFF000000
127
128 struct srcimap {
129         unsigned int srcaim;
130         unsigned int idx;
131 };
132
133 /* SRCIMP manager register dirty flags */
134 union srcimp_mgr_dirty {
135         struct {
136                 u16 srcimap:1;
137                 u16 rsv:15;
138         } bf;
139         u16 data;
140 };
141
142 struct srcimp_mgr_ctrl_blk {
143         struct srcimap          srcimap;
144         union srcimp_mgr_dirty  dirty;
145 };
146
147 /*
148  * Function implementation block.
149  */
150
151 static int src_get_rsc_ctrl_blk(void **rblk)
152 {
153         struct src_rsc_ctrl_blk *blk;
154
155         *rblk = NULL;
156         blk = kzalloc(sizeof(*blk), GFP_KERNEL);
157         if (NULL == blk)
158                 return -ENOMEM;
159
160         *rblk = blk;
161
162         return 0;
163 }
164
165 static int src_put_rsc_ctrl_blk(void *blk)
166 {
167         kfree((struct src_rsc_ctrl_blk *)blk);
168
169         return 0;
170 }
171
172 static int src_set_state(void *blk, unsigned int state)
173 {
174         struct src_rsc_ctrl_blk *ctl = blk;
175
176         set_field(&ctl->ctl, SRCCTL_STATE, state);
177         ctl->dirty.bf.ctl = 1;
178         return 0;
179 }
180
181 static int src_set_bm(void *blk, unsigned int bm)
182 {
183         struct src_rsc_ctrl_blk *ctl = blk;
184
185         set_field(&ctl->ctl, SRCCTL_BM, bm);
186         ctl->dirty.bf.ctl = 1;
187         return 0;
188 }
189
190 static int src_set_rsr(void *blk, unsigned int rsr)
191 {
192         struct src_rsc_ctrl_blk *ctl = blk;
193
194         set_field(&ctl->ctl, SRCCTL_RSR, rsr);
195         ctl->dirty.bf.ctl = 1;
196         return 0;
197 }
198
199 static int src_set_sf(void *blk, unsigned int sf)
200 {
201         struct src_rsc_ctrl_blk *ctl = blk;
202
203         set_field(&ctl->ctl, SRCCTL_SF, sf);
204         ctl->dirty.bf.ctl = 1;
205         return 0;
206 }
207
208 static int src_set_wr(void *blk, unsigned int wr)
209 {
210         struct src_rsc_ctrl_blk *ctl = blk;
211
212         set_field(&ctl->ctl, SRCCTL_WR, wr);
213         ctl->dirty.bf.ctl = 1;
214         return 0;
215 }
216
217 static int src_set_pm(void *blk, unsigned int pm)
218 {
219         struct src_rsc_ctrl_blk *ctl = blk;
220
221         set_field(&ctl->ctl, SRCCTL_PM, pm);
222         ctl->dirty.bf.ctl = 1;
223         return 0;
224 }
225
226 static int src_set_rom(void *blk, unsigned int rom)
227 {
228         struct src_rsc_ctrl_blk *ctl = blk;
229
230         set_field(&ctl->ctl, SRCCTL_ROM, rom);
231         ctl->dirty.bf.ctl = 1;
232         return 0;
233 }
234
235 static int src_set_vo(void *blk, unsigned int vo)
236 {
237         struct src_rsc_ctrl_blk *ctl = blk;
238
239         set_field(&ctl->ctl, SRCCTL_VO, vo);
240         ctl->dirty.bf.ctl = 1;
241         return 0;
242 }
243
244 static int src_set_st(void *blk, unsigned int st)
245 {
246         struct src_rsc_ctrl_blk *ctl = blk;
247
248         set_field(&ctl->ctl, SRCCTL_ST, st);
249         ctl->dirty.bf.ctl = 1;
250         return 0;
251 }
252
253 static int src_set_ie(void *blk, unsigned int ie)
254 {
255         struct src_rsc_ctrl_blk *ctl = blk;
256
257         set_field(&ctl->ctl, SRCCTL_IE, ie);
258         ctl->dirty.bf.ctl = 1;
259         return 0;
260 }
261
262 static int src_set_ilsz(void *blk, unsigned int ilsz)
263 {
264         struct src_rsc_ctrl_blk *ctl = blk;
265
266         set_field(&ctl->ctl, SRCCTL_ILSZ, ilsz);
267         ctl->dirty.bf.ctl = 1;
268         return 0;
269 }
270
271 static int src_set_bp(void *blk, unsigned int bp)
272 {
273         struct src_rsc_ctrl_blk *ctl = blk;
274
275         set_field(&ctl->ctl, SRCCTL_BP, bp);
276         ctl->dirty.bf.ctl = 1;
277         return 0;
278 }
279
280 static int src_set_cisz(void *blk, unsigned int cisz)
281 {
282         struct src_rsc_ctrl_blk *ctl = blk;
283
284         set_field(&ctl->ccr, SRCCCR_CISZ, cisz);
285         ctl->dirty.bf.ccr = 1;
286         return 0;
287 }
288
289 static int src_set_ca(void *blk, unsigned int ca)
290 {
291         struct src_rsc_ctrl_blk *ctl = blk;
292
293         set_field(&ctl->ca, SRCCA_CA, ca);
294         ctl->dirty.bf.ca = 1;
295         return 0;
296 }
297
298 static int src_set_sa(void *blk, unsigned int sa)
299 {
300         struct src_rsc_ctrl_blk *ctl = blk;
301
302         set_field(&ctl->sa, SRCSA_SA, sa);
303         ctl->dirty.bf.sa = 1;
304         return 0;
305 }
306
307 static int src_set_la(void *blk, unsigned int la)
308 {
309         struct src_rsc_ctrl_blk *ctl = blk;
310
311         set_field(&ctl->la, SRCLA_LA, la);
312         ctl->dirty.bf.la = 1;
313         return 0;
314 }
315
316 static int src_set_pitch(void *blk, unsigned int pitch)
317 {
318         struct src_rsc_ctrl_blk *ctl = blk;
319
320         set_field(&ctl->mpr, MPRLH_PITCH, pitch);
321         ctl->dirty.bf.mpr = 1;
322         return 0;
323 }
324
325 static int src_set_clear_zbufs(void *blk, unsigned int clear)
326 {
327         ((struct src_rsc_ctrl_blk *)blk)->dirty.bf.czbfs = (clear ? 1 : 0);
328         return 0;
329 }
330
331 static int src_set_dirty(void *blk, unsigned int flags)
332 {
333         ((struct src_rsc_ctrl_blk *)blk)->dirty.data = (flags & 0xffff);
334         return 0;
335 }
336
337 static int src_set_dirty_all(void *blk)
338 {
339         ((struct src_rsc_ctrl_blk *)blk)->dirty.data = ~(0x0);
340         return 0;
341 }
342
343 #define AR_SLOT_SIZE            4096
344 #define AR_SLOT_BLOCK_SIZE      16
345 #define AR_PTS_PITCH            6
346 #define AR_PARAM_SRC_OFFSET     0x60
347
348 static unsigned int src_param_pitch_mixer(unsigned int src_idx)
349 {
350         return ((src_idx << 4) + AR_PTS_PITCH + AR_SLOT_SIZE
351                         - AR_PARAM_SRC_OFFSET) % AR_SLOT_SIZE;
352
353 }
354
355 static int src_commit_write(struct hw *hw, unsigned int idx, void *blk)
356 {
357         struct src_rsc_ctrl_blk *ctl = blk;
358         int i = 0;
359
360         if (ctl->dirty.bf.czbfs) {
361                 /* Clear Z-Buffer registers */
362                 for (i = 0; i < 8; i++)
363                         hw_write_20kx(hw, SRC_UPZ+idx*0x100+i*0x4, 0);
364
365                 for (i = 0; i < 4; i++)
366                         hw_write_20kx(hw, SRC_DN0Z+idx*0x100+i*0x4, 0);
367
368                 for (i = 0; i < 8; i++)
369                         hw_write_20kx(hw, SRC_DN1Z+idx*0x100+i*0x4, 0);
370
371                 ctl->dirty.bf.czbfs = 0;
372         }
373         if (ctl->dirty.bf.mpr) {
374                 /* Take the parameter mixer resource in the same group as that
375                  * the idx src is in for simplicity. Unlike src, all conjugate
376                  * parameter mixer resources must be programmed for
377                  * corresponding conjugate src resources. */
378                 unsigned int pm_idx = src_param_pitch_mixer(idx);
379                 hw_write_20kx(hw, MIXER_PRING_LO_HI+4*pm_idx, ctl->mpr);
380                 hw_write_20kx(hw, MIXER_PMOPLO+8*pm_idx, 0x3);
381                 hw_write_20kx(hw, MIXER_PMOPHI+8*pm_idx, 0x0);
382                 ctl->dirty.bf.mpr = 0;
383         }
384         if (ctl->dirty.bf.sa) {
385                 hw_write_20kx(hw, SRC_SA+idx*0x100, ctl->sa);
386                 ctl->dirty.bf.sa = 0;
387         }
388         if (ctl->dirty.bf.la) {
389                 hw_write_20kx(hw, SRC_LA+idx*0x100, ctl->la);
390                 ctl->dirty.bf.la = 0;
391         }
392         if (ctl->dirty.bf.ca) {
393                 hw_write_20kx(hw, SRC_CA+idx*0x100, ctl->ca);
394                 ctl->dirty.bf.ca = 0;
395         }
396
397         /* Write srccf register */
398         hw_write_20kx(hw, SRC_CF+idx*0x100, 0x0);
399
400         if (ctl->dirty.bf.ccr) {
401                 hw_write_20kx(hw, SRC_CCR+idx*0x100, ctl->ccr);
402                 ctl->dirty.bf.ccr = 0;
403         }
404         if (ctl->dirty.bf.ctl) {
405                 hw_write_20kx(hw, SRC_CTL+idx*0x100, ctl->ctl);
406                 ctl->dirty.bf.ctl = 0;
407         }
408
409         return 0;
410 }
411
412 static int src_get_ca(struct hw *hw, unsigned int idx, void *blk)
413 {
414         struct src_rsc_ctrl_blk *ctl = blk;
415
416         ctl->ca = hw_read_20kx(hw, SRC_CA+idx*0x100);
417         ctl->dirty.bf.ca = 0;
418
419         return get_field(ctl->ca, SRCCA_CA);
420 }
421
422 static unsigned int src_get_dirty(void *blk)
423 {
424         return ((struct src_rsc_ctrl_blk *)blk)->dirty.data;
425 }
426
427 static unsigned int src_dirty_conj_mask(void)
428 {
429         return 0x20;
430 }
431
432 static int src_mgr_enbs_src(void *blk, unsigned int idx)
433 {
434         ((struct src_mgr_ctrl_blk *)blk)->enbsa |= (0x1 << ((idx%128)/4));
435         ((struct src_mgr_ctrl_blk *)blk)->dirty.bf.enbsa = 1;
436         ((struct src_mgr_ctrl_blk *)blk)->enb[idx/32] |= (0x1 << (idx%32));
437         return 0;
438 }
439
440 static int src_mgr_enb_src(void *blk, unsigned int idx)
441 {
442         ((struct src_mgr_ctrl_blk *)blk)->enb[idx/32] |= (0x1 << (idx%32));
443         ((struct src_mgr_ctrl_blk *)blk)->dirty.data |= (0x1 << (idx/32));
444         return 0;
445 }
446
447 static int src_mgr_dsb_src(void *blk, unsigned int idx)
448 {
449         ((struct src_mgr_ctrl_blk *)blk)->enb[idx/32] &= ~(0x1 << (idx%32));
450         ((struct src_mgr_ctrl_blk *)blk)->dirty.data |= (0x1 << (idx/32));
451         return 0;
452 }
453
454 static int src_mgr_commit_write(struct hw *hw, void *blk)
455 {
456         struct src_mgr_ctrl_blk *ctl = blk;
457         int i = 0;
458         unsigned int ret = 0;
459
460         if (ctl->dirty.bf.enbsa) {
461                 do {
462                         ret = hw_read_20kx(hw, SRC_ENBSTAT);
463                 } while (ret & 0x1);
464                 hw_write_20kx(hw, SRC_ENBSA, ctl->enbsa);
465                 ctl->dirty.bf.enbsa = 0;
466         }
467         for (i = 0; i < 8; i++) {
468                 if ((ctl->dirty.data & (0x1 << i))) {
469                         hw_write_20kx(hw, SRC_ENB+(i*0x100), ctl->enb[i]);
470                         ctl->dirty.data &= ~(0x1 << i);
471                 }
472         }
473
474         return 0;
475 }
476
477 static int src_mgr_get_ctrl_blk(void **rblk)
478 {
479         struct src_mgr_ctrl_blk *blk;
480
481         *rblk = NULL;
482         blk = kzalloc(sizeof(*blk), GFP_KERNEL);
483         if (NULL == blk)
484                 return -ENOMEM;
485
486         *rblk = blk;
487
488         return 0;
489 }
490
491 static int src_mgr_put_ctrl_blk(void *blk)
492 {
493         kfree((struct src_mgr_ctrl_blk *)blk);
494
495         return 0;
496 }
497
498 static int srcimp_mgr_get_ctrl_blk(void **rblk)
499 {
500         struct srcimp_mgr_ctrl_blk *blk;
501
502         *rblk = NULL;
503         blk = kzalloc(sizeof(*blk), GFP_KERNEL);
504         if (NULL == blk)
505                 return -ENOMEM;
506
507         *rblk = blk;
508
509         return 0;
510 }
511
512 static int srcimp_mgr_put_ctrl_blk(void *blk)
513 {
514         kfree((struct srcimp_mgr_ctrl_blk *)blk);
515
516         return 0;
517 }
518
519 static int srcimp_mgr_set_imaparc(void *blk, unsigned int slot)
520 {
521         struct srcimp_mgr_ctrl_blk *ctl = blk;
522
523         set_field(&ctl->srcimap.srcaim, SRCAIM_ARC, slot);
524         ctl->dirty.bf.srcimap = 1;
525         return 0;
526 }
527
528 static int srcimp_mgr_set_imapuser(void *blk, unsigned int user)
529 {
530         struct srcimp_mgr_ctrl_blk *ctl = blk;
531
532         set_field(&ctl->srcimap.srcaim, SRCAIM_SRC, user);
533         ctl->dirty.bf.srcimap = 1;
534         return 0;
535 }
536
537 static int srcimp_mgr_set_imapnxt(void *blk, unsigned int next)
538 {
539         struct srcimp_mgr_ctrl_blk *ctl = blk;
540
541         set_field(&ctl->srcimap.srcaim, SRCAIM_NXT, next);
542         ctl->dirty.bf.srcimap = 1;
543         return 0;
544 }
545
546 static int srcimp_mgr_set_imapaddr(void *blk, unsigned int addr)
547 {
548         ((struct srcimp_mgr_ctrl_blk *)blk)->srcimap.idx = addr;
549         ((struct srcimp_mgr_ctrl_blk *)blk)->dirty.bf.srcimap = 1;
550         return 0;
551 }
552
553 static int srcimp_mgr_commit_write(struct hw *hw, void *blk)
554 {
555         struct srcimp_mgr_ctrl_blk *ctl = blk;
556
557         if (ctl->dirty.bf.srcimap) {
558                 hw_write_20kx(hw, SRC_IMAP+ctl->srcimap.idx*0x100,
559                                                 ctl->srcimap.srcaim);
560                 ctl->dirty.bf.srcimap = 0;
561         }
562
563         return 0;
564 }
565
566 /*
567  * AMIXER control block definitions.
568  */
569
570 #define AMOPLO_M        0x00000003
571 #define AMOPLO_IV       0x00000004
572 #define AMOPLO_X        0x0003FFF0
573 #define AMOPLO_Y        0xFFFC0000
574
575 #define AMOPHI_SADR     0x000000FF
576 #define AMOPHI_SE       0x80000000
577
578 /* AMIXER resource register dirty flags */
579 union amixer_dirty {
580         struct {
581                 u16 amoplo:1;
582                 u16 amophi:1;
583                 u16 rsv:14;
584         } bf;
585         u16 data;
586 };
587
588 /* AMIXER resource control block */
589 struct amixer_rsc_ctrl_blk {
590         unsigned int            amoplo;
591         unsigned int            amophi;
592         union amixer_dirty      dirty;
593 };
594
595 static int amixer_set_mode(void *blk, unsigned int mode)
596 {
597         struct amixer_rsc_ctrl_blk *ctl = blk;
598
599         set_field(&ctl->amoplo, AMOPLO_M, mode);
600         ctl->dirty.bf.amoplo = 1;
601         return 0;
602 }
603
604 static int amixer_set_iv(void *blk, unsigned int iv)
605 {
606         struct amixer_rsc_ctrl_blk *ctl = blk;
607
608         set_field(&ctl->amoplo, AMOPLO_IV, iv);
609         ctl->dirty.bf.amoplo = 1;
610         return 0;
611 }
612
613 static int amixer_set_x(void *blk, unsigned int x)
614 {
615         struct amixer_rsc_ctrl_blk *ctl = blk;
616
617         set_field(&ctl->amoplo, AMOPLO_X, x);
618         ctl->dirty.bf.amoplo = 1;
619         return 0;
620 }
621
622 static int amixer_set_y(void *blk, unsigned int y)
623 {
624         struct amixer_rsc_ctrl_blk *ctl = blk;
625
626         set_field(&ctl->amoplo, AMOPLO_Y, y);
627         ctl->dirty.bf.amoplo = 1;
628         return 0;
629 }
630
631 static int amixer_set_sadr(void *blk, unsigned int sadr)
632 {
633         struct amixer_rsc_ctrl_blk *ctl = blk;
634
635         set_field(&ctl->amophi, AMOPHI_SADR, sadr);
636         ctl->dirty.bf.amophi = 1;
637         return 0;
638 }
639
640 static int amixer_set_se(void *blk, unsigned int se)
641 {
642         struct amixer_rsc_ctrl_blk *ctl = blk;
643
644         set_field(&ctl->amophi, AMOPHI_SE, se);
645         ctl->dirty.bf.amophi = 1;
646         return 0;
647 }
648
649 static int amixer_set_dirty(void *blk, unsigned int flags)
650 {
651         ((struct amixer_rsc_ctrl_blk *)blk)->dirty.data = (flags & 0xffff);
652         return 0;
653 }
654
655 static int amixer_set_dirty_all(void *blk)
656 {
657         ((struct amixer_rsc_ctrl_blk *)blk)->dirty.data = ~(0x0);
658         return 0;
659 }
660
661 static int amixer_commit_write(struct hw *hw, unsigned int idx, void *blk)
662 {
663         struct amixer_rsc_ctrl_blk *ctl = blk;
664
665         if (ctl->dirty.bf.amoplo || ctl->dirty.bf.amophi) {
666                 hw_write_20kx(hw, MIXER_AMOPLO+idx*8, ctl->amoplo);
667                 ctl->dirty.bf.amoplo = 0;
668                 hw_write_20kx(hw, MIXER_AMOPHI+idx*8, ctl->amophi);
669                 ctl->dirty.bf.amophi = 0;
670         }
671
672         return 0;
673 }
674
675 static int amixer_get_y(void *blk)
676 {
677         struct amixer_rsc_ctrl_blk *ctl = blk;
678
679         return get_field(ctl->amoplo, AMOPLO_Y);
680 }
681
682 static unsigned int amixer_get_dirty(void *blk)
683 {
684         return ((struct amixer_rsc_ctrl_blk *)blk)->dirty.data;
685 }
686
687 static int amixer_rsc_get_ctrl_blk(void **rblk)
688 {
689         struct amixer_rsc_ctrl_blk *blk;
690
691         *rblk = NULL;
692         blk = kzalloc(sizeof(*blk), GFP_KERNEL);
693         if (NULL == blk)
694                 return -ENOMEM;
695
696         *rblk = blk;
697
698         return 0;
699 }
700
701 static int amixer_rsc_put_ctrl_blk(void *blk)
702 {
703         kfree((struct amixer_rsc_ctrl_blk *)blk);
704
705         return 0;
706 }
707
708 static int amixer_mgr_get_ctrl_blk(void **rblk)
709 {
710         *rblk = NULL;
711
712         return 0;
713 }
714
715 static int amixer_mgr_put_ctrl_blk(void *blk)
716 {
717         return 0;
718 }
719
720 /*
721  * DAIO control block definitions.
722  */
723
724 /* Receiver Sample Rate Tracker Control register */
725 #define SRTCTL_SRCO     0x000000FF
726 #define SRTCTL_SRCM     0x0000FF00
727 #define SRTCTL_RSR      0x00030000
728 #define SRTCTL_DRAT     0x00300000
729 #define SRTCTL_EC       0x01000000
730 #define SRTCTL_ET       0x10000000
731
732 /* DAIO Receiver register dirty flags */
733 union dai_dirty {
734         struct {
735                 u16 srt:1;
736                 u16 rsv:15;
737         } bf;
738         u16 data;
739 };
740
741 /* DAIO Receiver control block */
742 struct dai_ctrl_blk {
743         unsigned int    srt;
744         union dai_dirty dirty;
745 };
746
747 /* Audio Input Mapper RAM */
748 #define AIM_ARC         0x00000FFF
749 #define AIM_NXT         0x007F0000
750
751 struct daoimap {
752         unsigned int aim;
753         unsigned int idx;
754 };
755
756 /* Audio Transmitter Control and Status register */
757 #define ATXCTL_EN       0x00000001
758 #define ATXCTL_MODE     0x00000010
759 #define ATXCTL_CD       0x00000020
760 #define ATXCTL_RAW      0x00000100
761 #define ATXCTL_MT       0x00000200
762 #define ATXCTL_NUC      0x00003000
763 #define ATXCTL_BEN      0x00010000
764 #define ATXCTL_BMUX     0x00700000
765 #define ATXCTL_B24      0x01000000
766 #define ATXCTL_CPF      0x02000000
767 #define ATXCTL_RIV      0x10000000
768 #define ATXCTL_LIV      0x20000000
769 #define ATXCTL_RSAT     0x40000000
770 #define ATXCTL_LSAT     0x80000000
771
772 /* XDIF Transmitter register dirty flags */
773 union dao_dirty {
774         struct {
775                 u16 atxcsl:1;
776                 u16 rsv:15;
777         } bf;
778         u16 data;
779 };
780
781 /* XDIF Transmitter control block */
782 struct dao_ctrl_blk {
783         /* XDIF Transmitter Channel Status Low Register */
784         unsigned int    atxcsl;
785         union dao_dirty dirty;
786 };
787
788 /* Audio Receiver Control register */
789 #define ARXCTL_EN       0x00000001
790
791 /* DAIO manager register dirty flags */
792 union daio_mgr_dirty {
793         struct {
794                 u32 atxctl:8;
795                 u32 arxctl:8;
796                 u32 daoimap:1;
797                 u32 rsv:15;
798         } bf;
799         u32 data;
800 };
801
802 /* DAIO manager control block */
803 struct daio_mgr_ctrl_blk {
804         struct daoimap          daoimap;
805         unsigned int            txctl[8];
806         unsigned int            rxctl[8];
807         union daio_mgr_dirty    dirty;
808 };
809
810 static int dai_srt_set_srco(void *blk, unsigned int src)
811 {
812         struct dai_ctrl_blk *ctl = blk;
813
814         set_field(&ctl->srt, SRTCTL_SRCO, src);
815         ctl->dirty.bf.srt = 1;
816         return 0;
817 }
818
819 static int dai_srt_set_srcm(void *blk, unsigned int src)
820 {
821         struct dai_ctrl_blk *ctl = blk;
822
823         set_field(&ctl->srt, SRTCTL_SRCM, src);
824         ctl->dirty.bf.srt = 1;
825         return 0;
826 }
827
828 static int dai_srt_set_rsr(void *blk, unsigned int rsr)
829 {
830         struct dai_ctrl_blk *ctl = blk;
831
832         set_field(&ctl->srt, SRTCTL_RSR, rsr);
833         ctl->dirty.bf.srt = 1;
834         return 0;
835 }
836
837 static int dai_srt_set_drat(void *blk, unsigned int drat)
838 {
839         struct dai_ctrl_blk *ctl = blk;
840
841         set_field(&ctl->srt, SRTCTL_DRAT, drat);
842         ctl->dirty.bf.srt = 1;
843         return 0;
844 }
845
846 static int dai_srt_set_ec(void *blk, unsigned int ec)
847 {
848         struct dai_ctrl_blk *ctl = blk;
849
850         set_field(&ctl->srt, SRTCTL_EC, ec ? 1 : 0);
851         ctl->dirty.bf.srt = 1;
852         return 0;
853 }
854
855 static int dai_srt_set_et(void *blk, unsigned int et)
856 {
857         struct dai_ctrl_blk *ctl = blk;
858
859         set_field(&ctl->srt, SRTCTL_ET, et ? 1 : 0);
860         ctl->dirty.bf.srt = 1;
861         return 0;
862 }
863
864 static int dai_commit_write(struct hw *hw, unsigned int idx, void *blk)
865 {
866         struct dai_ctrl_blk *ctl = blk;
867
868         if (ctl->dirty.bf.srt) {
869                 hw_write_20kx(hw, AUDIO_IO_RX_SRT_CTL+0x40*idx, ctl->srt);
870                 ctl->dirty.bf.srt = 0;
871         }
872
873         return 0;
874 }
875
876 static int dai_get_ctrl_blk(void **rblk)
877 {
878         struct dai_ctrl_blk *blk;
879
880         *rblk = NULL;
881         blk = kzalloc(sizeof(*blk), GFP_KERNEL);
882         if (NULL == blk)
883                 return -ENOMEM;
884
885         *rblk = blk;
886
887         return 0;
888 }
889
890 static int dai_put_ctrl_blk(void *blk)
891 {
892         kfree((struct dai_ctrl_blk *)blk);
893
894         return 0;
895 }
896
897 static int dao_set_spos(void *blk, unsigned int spos)
898 {
899         ((struct dao_ctrl_blk *)blk)->atxcsl = spos;
900         ((struct dao_ctrl_blk *)blk)->dirty.bf.atxcsl = 1;
901         return 0;
902 }
903
904 static int dao_commit_write(struct hw *hw, unsigned int idx, void *blk)
905 {
906         struct dao_ctrl_blk *ctl = blk;
907
908         if (ctl->dirty.bf.atxcsl) {
909                 if (idx < 4) {
910                         /* S/PDIF SPOSx */
911                         hw_write_20kx(hw, AUDIO_IO_TX_CSTAT_L+0x40*idx,
912                                                         ctl->atxcsl);
913                 }
914                 ctl->dirty.bf.atxcsl = 0;
915         }
916
917         return 0;
918 }
919
920 static int dao_get_spos(void *blk, unsigned int *spos)
921 {
922         *spos = ((struct dao_ctrl_blk *)blk)->atxcsl;
923         return 0;
924 }
925
926 static int dao_get_ctrl_blk(void **rblk)
927 {
928         struct dao_ctrl_blk *blk;
929
930         *rblk = NULL;
931         blk = kzalloc(sizeof(*blk), GFP_KERNEL);
932         if (NULL == blk)
933                 return -ENOMEM;
934
935         *rblk = blk;
936
937         return 0;
938 }
939
940 static int dao_put_ctrl_blk(void *blk)
941 {
942         kfree((struct dao_ctrl_blk *)blk);
943
944         return 0;
945 }
946
947 static int daio_mgr_enb_dai(void *blk, unsigned int idx)
948 {
949         struct daio_mgr_ctrl_blk *ctl = blk;
950
951         set_field(&ctl->rxctl[idx], ARXCTL_EN, 1);
952         ctl->dirty.bf.arxctl |= (0x1 << idx);
953         return 0;
954 }
955
956 static int daio_mgr_dsb_dai(void *blk, unsigned int idx)
957 {
958         struct daio_mgr_ctrl_blk *ctl = blk;
959
960         set_field(&ctl->rxctl[idx], ARXCTL_EN, 0);
961
962         ctl->dirty.bf.arxctl |= (0x1 << idx);
963         return 0;
964 }
965
966 static int daio_mgr_enb_dao(void *blk, unsigned int idx)
967 {
968         struct daio_mgr_ctrl_blk *ctl = blk;
969
970         set_field(&ctl->txctl[idx], ATXCTL_EN, 1);
971         ctl->dirty.bf.atxctl |= (0x1 << idx);
972         return 0;
973 }
974
975 static int daio_mgr_dsb_dao(void *blk, unsigned int idx)
976 {
977         struct daio_mgr_ctrl_blk *ctl = blk;
978
979         set_field(&ctl->txctl[idx], ATXCTL_EN, 0);
980         ctl->dirty.bf.atxctl |= (0x1 << idx);
981         return 0;
982 }
983
984 static int daio_mgr_dao_init(void *blk, unsigned int idx, unsigned int conf)
985 {
986         struct daio_mgr_ctrl_blk *ctl = blk;
987
988         if (idx < 4) {
989                 /* S/PDIF output */
990                 switch ((conf & 0x7)) {
991                 case 1:
992                         set_field(&ctl->txctl[idx], ATXCTL_NUC, 0);
993                         break;
994                 case 2:
995                         set_field(&ctl->txctl[idx], ATXCTL_NUC, 1);
996                         break;
997                 case 4:
998                         set_field(&ctl->txctl[idx], ATXCTL_NUC, 2);
999                         break;
1000                 case 8:
1001                         set_field(&ctl->txctl[idx], ATXCTL_NUC, 3);
1002                         break;
1003                 default:
1004                         break;
1005                 }
1006                 /* CDIF */
1007                 set_field(&ctl->txctl[idx], ATXCTL_CD, (!(conf & 0x7)));
1008                 /* Non-audio */
1009                 set_field(&ctl->txctl[idx], ATXCTL_LIV, (conf >> 4) & 0x1);
1010                 /* Non-audio */
1011                 set_field(&ctl->txctl[idx], ATXCTL_RIV, (conf >> 4) & 0x1);
1012                 set_field(&ctl->txctl[idx], ATXCTL_RAW,
1013                           ((conf >> 3) & 0x1) ? 0 : 0);
1014                 ctl->dirty.bf.atxctl |= (0x1 << idx);
1015         } else {
1016                 /* I2S output */
1017                 /*idx %= 4; */
1018         }
1019         return 0;
1020 }
1021
1022 static int daio_mgr_set_imaparc(void *blk, unsigned int slot)
1023 {
1024         struct daio_mgr_ctrl_blk *ctl = blk;
1025
1026         set_field(&ctl->daoimap.aim, AIM_ARC, slot);
1027         ctl->dirty.bf.daoimap = 1;
1028         return 0;
1029 }
1030
1031 static int daio_mgr_set_imapnxt(void *blk, unsigned int next)
1032 {
1033         struct daio_mgr_ctrl_blk *ctl = blk;
1034
1035         set_field(&ctl->daoimap.aim, AIM_NXT, next);
1036         ctl->dirty.bf.daoimap = 1;
1037         return 0;
1038 }
1039
1040 static int daio_mgr_set_imapaddr(void *blk, unsigned int addr)
1041 {
1042         ((struct daio_mgr_ctrl_blk *)blk)->daoimap.idx = addr;
1043         ((struct daio_mgr_ctrl_blk *)blk)->dirty.bf.daoimap = 1;
1044         return 0;
1045 }
1046
1047 static int daio_mgr_commit_write(struct hw *hw, void *blk)
1048 {
1049         struct daio_mgr_ctrl_blk *ctl = blk;
1050         unsigned int data = 0;
1051         int i = 0;
1052
1053         for (i = 0; i < 8; i++) {
1054                 if ((ctl->dirty.bf.atxctl & (0x1 << i))) {
1055                         data = ctl->txctl[i];
1056                         hw_write_20kx(hw, (AUDIO_IO_TX_CTL+(0x40*i)), data);
1057                         ctl->dirty.bf.atxctl &= ~(0x1 << i);
1058                         mdelay(1);
1059                 }
1060                 if ((ctl->dirty.bf.arxctl & (0x1 << i))) {
1061                         data = ctl->rxctl[i];
1062                         hw_write_20kx(hw, (AUDIO_IO_RX_CTL+(0x40*i)), data);
1063                         ctl->dirty.bf.arxctl &= ~(0x1 << i);
1064                         mdelay(1);
1065                 }
1066         }
1067         if (ctl->dirty.bf.daoimap) {
1068                 hw_write_20kx(hw, AUDIO_IO_AIM+ctl->daoimap.idx*4,
1069                                                 ctl->daoimap.aim);
1070                 ctl->dirty.bf.daoimap = 0;
1071         }
1072
1073         return 0;
1074 }
1075
1076 static int daio_mgr_get_ctrl_blk(struct hw *hw, void **rblk)
1077 {
1078         struct daio_mgr_ctrl_blk *blk;
1079         int i = 0;
1080
1081         *rblk = NULL;
1082         blk = kzalloc(sizeof(*blk), GFP_KERNEL);
1083         if (NULL == blk)
1084                 return -ENOMEM;
1085
1086         for (i = 0; i < 8; i++) {
1087                 blk->txctl[i] = hw_read_20kx(hw, AUDIO_IO_TX_CTL+(0x40*i));
1088                 blk->rxctl[i] = hw_read_20kx(hw, AUDIO_IO_RX_CTL+(0x40*i));
1089         }
1090
1091         *rblk = blk;
1092
1093         return 0;
1094 }
1095
1096 static int daio_mgr_put_ctrl_blk(void *blk)
1097 {
1098         kfree((struct daio_mgr_ctrl_blk *)blk);
1099
1100         return 0;
1101 }
1102
1103 /* Card hardware initialization block */
1104 struct dac_conf {
1105         unsigned int msr; /* master sample rate in rsrs */
1106 };
1107
1108 struct adc_conf {
1109         unsigned int msr;       /* master sample rate in rsrs */
1110         unsigned char input;    /* the input source of ADC */
1111         unsigned char mic20db;  /* boost mic by 20db if input is microphone */
1112 };
1113
1114 struct daio_conf {
1115         unsigned int msr; /* master sample rate in rsrs */
1116 };
1117
1118 struct trn_conf {
1119         unsigned long vm_pgt_phys;
1120 };
1121
1122 static int hw_daio_init(struct hw *hw, const struct daio_conf *info)
1123 {
1124         u32 dwData = 0;
1125         int i;
1126
1127         /* Program I2S with proper sample rate and enable the correct I2S
1128          * channel. ED(0/8/16/24): Enable all I2S/I2X master clock output */
1129         if (1 == info->msr) {
1130                 hw_write_20kx(hw, AUDIO_IO_MCLK, 0x01010101);
1131                 hw_write_20kx(hw, AUDIO_IO_TX_BLRCLK, 0x01010101);
1132                 hw_write_20kx(hw, AUDIO_IO_RX_BLRCLK, 0);
1133         } else if (2 == info->msr) {
1134                 hw_write_20kx(hw, AUDIO_IO_MCLK, 0x11111111);
1135                 /* Specify all playing 96khz
1136                  * EA [0]       - Enabled
1137                  * RTA [4:5]    - 96kHz
1138                  * EB [8]       - Enabled
1139                  * RTB [12:13]  - 96kHz
1140                  * EC [16]      - Enabled
1141                  * RTC [20:21]  - 96kHz
1142                  * ED [24]      - Enabled
1143                  * RTD [28:29]  - 96kHz */
1144                 hw_write_20kx(hw, AUDIO_IO_TX_BLRCLK, 0x11111111);
1145                 hw_write_20kx(hw, AUDIO_IO_RX_BLRCLK, 0);
1146         } else {
1147                 printk(KERN_ALERT "ctxfi: ERROR!!! Invalid sampling rate!!!\n");
1148                 return -EINVAL;
1149         }
1150
1151         for (i = 0; i < 8; i++) {
1152                 if (i <= 3) {
1153                         /* 1st 3 channels are SPDIFs (SB0960) */
1154                         if (i == 3)
1155                                 dwData = 0x1001001;
1156                         else
1157                                 dwData = 0x1000001;
1158
1159                         hw_write_20kx(hw, (AUDIO_IO_TX_CTL+(0x40*i)), dwData);
1160                         hw_write_20kx(hw, (AUDIO_IO_RX_CTL+(0x40*i)), dwData);
1161
1162                         /* Initialize the SPDIF Out Channel status registers.
1163                          * The value specified here is based on the typical
1164                          * values provided in the specification, namely: Clock
1165                          * Accuracy of 1000ppm, Sample Rate of 48KHz,
1166                          * unspecified source number, Generation status = 1,
1167                          * Category code = 0x12 (Digital Signal Mixer),
1168                          * Mode = 0, Emph = 0, Copy Permitted, AN = 0
1169                          * (indicating that we're transmitting digital audio,
1170                          * and the Professional Use bit is 0. */
1171
1172                         hw_write_20kx(hw, AUDIO_IO_TX_CSTAT_L+(0x40*i),
1173                                         0x02109204); /* Default to 48kHz */
1174
1175                         hw_write_20kx(hw, AUDIO_IO_TX_CSTAT_H+(0x40*i), 0x0B);
1176                 } else {
1177                         /* Next 5 channels are I2S (SB0960) */
1178                         dwData = 0x11;
1179                         hw_write_20kx(hw, AUDIO_IO_RX_CTL+(0x40*i), dwData);
1180                         if (2 == info->msr) {
1181                                 /* Four channels per sample period */
1182                                 dwData |= 0x1000;
1183                         }
1184                         hw_write_20kx(hw, AUDIO_IO_TX_CTL+(0x40*i), dwData);
1185                 }
1186         }
1187
1188         return 0;
1189 }
1190
1191 /* TRANSPORT operations */
1192 static int hw_trn_init(struct hw *hw, const struct trn_conf *info)
1193 {
1194         u32 vmctl = 0, data = 0;
1195         unsigned long ptp_phys_low = 0, ptp_phys_high = 0;
1196         int i = 0;
1197
1198         /* Set up device page table */
1199         if ((~0UL) == info->vm_pgt_phys) {
1200                 printk(KERN_ALERT "ctxfi: "
1201                        "Wrong device page table page address!!!\n");
1202                 return -1;
1203         }
1204
1205         vmctl = 0x80000C0F;  /* 32-bit, 4k-size page */
1206 #if BITS_PER_LONG == 64
1207         ptp_phys_low = info->vm_pgt_phys & ((1UL<<32)-1);
1208         ptp_phys_high = (info->vm_pgt_phys>>32) & ((1UL<<32)-1);
1209         vmctl |= (3<<8);
1210 #elif BITS_PER_LONG == 32
1211         ptp_phys_low = info->vm_pgt_phys & (~0UL);
1212         ptp_phys_high = 0;
1213 #else
1214 #       error "Unknown BITS_PER_LONG!"
1215 #endif
1216 #if PAGE_SIZE == 8192
1217 #       error "Don't support 8k-page!"
1218 #endif
1219         /* Write page table physical address to all PTPAL registers */
1220         for (i = 0; i < 64; i++) {
1221                 hw_write_20kx(hw, VMEM_PTPAL+(16*i), ptp_phys_low);
1222                 hw_write_20kx(hw, VMEM_PTPAH+(16*i), ptp_phys_high);
1223         }
1224         /* Enable virtual memory transfer */
1225         hw_write_20kx(hw, VMEM_CTL, vmctl);
1226         /* Enable transport bus master and queueing of request */
1227         hw_write_20kx(hw, TRANSPORT_CTL, 0x03);
1228         hw_write_20kx(hw, TRANSPORT_INT, 0x200c01);
1229         /* Enable transport ring */
1230         data = hw_read_20kx(hw, TRANSPORT_ENB);
1231         hw_write_20kx(hw, TRANSPORT_ENB, (data | 0x03));
1232
1233         return 0;
1234 }
1235
1236 /* Card initialization */
1237 #define GCTL_AIE        0x00000001
1238 #define GCTL_UAA        0x00000002
1239 #define GCTL_DPC        0x00000004
1240 #define GCTL_DBP        0x00000008
1241 #define GCTL_ABP        0x00000010
1242 #define GCTL_TBP        0x00000020
1243 #define GCTL_SBP        0x00000040
1244 #define GCTL_FBP        0x00000080
1245 #define GCTL_ME         0x00000100
1246 #define GCTL_AID        0x00001000
1247
1248 #define PLLCTL_SRC      0x00000007
1249 #define PLLCTL_SPE      0x00000008
1250 #define PLLCTL_RD       0x000000F0
1251 #define PLLCTL_FD       0x0001FF00
1252 #define PLLCTL_OD       0x00060000
1253 #define PLLCTL_B        0x00080000
1254 #define PLLCTL_AS       0x00100000
1255 #define PLLCTL_LF       0x03E00000
1256 #define PLLCTL_SPS      0x1C000000
1257 #define PLLCTL_AD       0x60000000
1258
1259 #define PLLSTAT_CCS     0x00000007
1260 #define PLLSTAT_SPL     0x00000008
1261 #define PLLSTAT_CRD     0x000000F0
1262 #define PLLSTAT_CFD     0x0001FF00
1263 #define PLLSTAT_SL      0x00020000
1264 #define PLLSTAT_FAS     0x00040000
1265 #define PLLSTAT_B       0x00080000
1266 #define PLLSTAT_PD      0x00100000
1267 #define PLLSTAT_OCA     0x00200000
1268 #define PLLSTAT_NCA     0x00400000
1269
1270 static int hw_pll_init(struct hw *hw, unsigned int rsr)
1271 {
1272         unsigned int pllenb;
1273         unsigned int pllctl;
1274         unsigned int pllstat;
1275         int i;
1276
1277         pllenb = 0xB;
1278         hw_write_20kx(hw, PLL_ENB, pllenb);
1279         pllctl = 0x20D00000;
1280         set_field(&pllctl, PLLCTL_FD, 16 - 4);
1281         hw_write_20kx(hw, PLL_CTL, pllctl);
1282         mdelay(40);
1283         pllctl = hw_read_20kx(hw, PLL_CTL);
1284         set_field(&pllctl, PLLCTL_B, 0);
1285         if (48000 == rsr) {
1286                 set_field(&pllctl, PLLCTL_FD, 16 - 2);
1287                 set_field(&pllctl, PLLCTL_RD, 1 - 1);
1288         } else { /* 44100 */
1289                 set_field(&pllctl, PLLCTL_FD, 147 - 2);
1290                 set_field(&pllctl, PLLCTL_RD, 10 - 1);
1291         }
1292         hw_write_20kx(hw, PLL_CTL, pllctl);
1293         mdelay(40);
1294         for (i = 0; i < 1000; i++) {
1295                 pllstat = hw_read_20kx(hw, PLL_STAT);
1296                 if (get_field(pllstat, PLLSTAT_PD))
1297                         continue;
1298
1299                 if (get_field(pllstat, PLLSTAT_B) !=
1300                                         get_field(pllctl, PLLCTL_B))
1301                         continue;
1302
1303                 if (get_field(pllstat, PLLSTAT_CCS) !=
1304                                         get_field(pllctl, PLLCTL_SRC))
1305                         continue;
1306
1307                 if (get_field(pllstat, PLLSTAT_CRD) !=
1308                                         get_field(pllctl, PLLCTL_RD))
1309                         continue;
1310
1311                 if (get_field(pllstat, PLLSTAT_CFD) !=
1312                                         get_field(pllctl, PLLCTL_FD))
1313                         continue;
1314
1315                 break;
1316         }
1317         if (i >= 1000) {
1318                 printk(KERN_ALERT "ctxfi: PLL initialization failed!!!\n");
1319                 return -EBUSY;
1320         }
1321
1322         return 0;
1323 }
1324
1325 static int hw_auto_init(struct hw *hw)
1326 {
1327         unsigned int gctl;
1328         int i;
1329
1330         gctl = hw_read_20kx(hw, GLOBAL_CNTL_GCTL);
1331         set_field(&gctl, GCTL_AIE, 0);
1332         hw_write_20kx(hw, GLOBAL_CNTL_GCTL, gctl);
1333         set_field(&gctl, GCTL_AIE, 1);
1334         hw_write_20kx(hw, GLOBAL_CNTL_GCTL, gctl);
1335         mdelay(10);
1336         for (i = 0; i < 400000; i++) {
1337                 gctl = hw_read_20kx(hw, GLOBAL_CNTL_GCTL);
1338                 if (get_field(gctl, GCTL_AID))
1339                         break;
1340         }
1341         if (!get_field(gctl, GCTL_AID)) {
1342                 printk(KERN_ALERT "ctxfi: Card Auto-init failed!!!\n");
1343                 return -EBUSY;
1344         }
1345
1346         return 0;
1347 }
1348
1349 /* DAC operations */
1350
1351 #define CS4382_MC1              0x1
1352 #define CS4382_MC2              0x2
1353 #define CS4382_MC3              0x3
1354 #define CS4382_FC               0x4
1355 #define CS4382_IC               0x5
1356 #define CS4382_XC1              0x6
1357 #define CS4382_VCA1             0x7
1358 #define CS4382_VCB1             0x8
1359 #define CS4382_XC2              0x9
1360 #define CS4382_VCA2             0xA
1361 #define CS4382_VCB2             0xB
1362 #define CS4382_XC3              0xC
1363 #define CS4382_VCA3             0xD
1364 #define CS4382_VCB3             0xE
1365 #define CS4382_XC4              0xF
1366 #define CS4382_VCA4             0x10
1367 #define CS4382_VCB4             0x11
1368 #define CS4382_CREV             0x12
1369
1370 /* I2C status */
1371 #define STATE_LOCKED            0x00
1372 #define STATE_UNLOCKED          0xAA
1373 #define DATA_READY              0x800000    /* Used with I2C_IF_STATUS */
1374 #define DATA_ABORT              0x10000     /* Used with I2C_IF_STATUS */
1375
1376 #define I2C_STATUS_DCM  0x00000001
1377 #define I2C_STATUS_BC   0x00000006
1378 #define I2C_STATUS_APD  0x00000008
1379 #define I2C_STATUS_AB   0x00010000
1380 #define I2C_STATUS_DR   0x00800000
1381
1382 #define I2C_ADDRESS_PTAD        0x0000FFFF
1383 #define I2C_ADDRESS_SLAD        0x007F0000
1384
1385 struct REGS_CS4382 {
1386         u32 dwModeControl_1;
1387         u32 dwModeControl_2;
1388         u32 dwModeControl_3;
1389
1390         u32 dwFilterControl;
1391         u32 dwInvertControl;
1392
1393         u32 dwMixControl_P1;
1394         u32 dwVolControl_A1;
1395         u32 dwVolControl_B1;
1396
1397         u32 dwMixControl_P2;
1398         u32 dwVolControl_A2;
1399         u32 dwVolControl_B2;
1400
1401         u32 dwMixControl_P3;
1402         u32 dwVolControl_A3;
1403         u32 dwVolControl_B3;
1404
1405         u32 dwMixControl_P4;
1406         u32 dwVolControl_A4;
1407         u32 dwVolControl_B4;
1408 };
1409
1410 static u8 m_bAddressSize, m_bDataSize, m_bDeviceID;
1411
1412 static int I2CUnlockFullAccess(struct hw *hw)
1413 {
1414         u8 UnlockKeySequence_FLASH_FULLACCESS_MODE[2] =  {0xB3, 0xD4};
1415
1416         /* Send keys for forced BIOS mode */
1417         hw_write_20kx(hw, I2C_IF_WLOCK,
1418                         UnlockKeySequence_FLASH_FULLACCESS_MODE[0]);
1419         hw_write_20kx(hw, I2C_IF_WLOCK,
1420                         UnlockKeySequence_FLASH_FULLACCESS_MODE[1]);
1421         /* Check whether the chip is unlocked */
1422         if (hw_read_20kx(hw, I2C_IF_WLOCK) == STATE_UNLOCKED)
1423                 return 0;
1424
1425         return -1;
1426 }
1427
1428 static int I2CLockChip(struct hw *hw)
1429 {
1430         /* Write twice */
1431         hw_write_20kx(hw, I2C_IF_WLOCK, STATE_LOCKED);
1432         hw_write_20kx(hw, I2C_IF_WLOCK, STATE_LOCKED);
1433         if (hw_read_20kx(hw, I2C_IF_WLOCK) == STATE_LOCKED)
1434                 return 0;
1435
1436         return -1;
1437 }
1438
1439 static int I2CInit(struct hw *hw, u8 bDeviceID, u8 bAddressSize, u8 bDataSize)
1440 {
1441         int err = 0;
1442         unsigned int RegI2CStatus;
1443         unsigned int RegI2CAddress;
1444
1445         err = I2CUnlockFullAccess(hw);
1446         if (err < 0)
1447                 return err;
1448
1449         m_bAddressSize = bAddressSize;
1450         m_bDataSize = bDataSize;
1451         m_bDeviceID = bDeviceID;
1452
1453         RegI2CAddress = 0;
1454         set_field(&RegI2CAddress, I2C_ADDRESS_SLAD, bDeviceID);
1455
1456         hw_write_20kx(hw, I2C_IF_ADDRESS, RegI2CAddress);
1457
1458         RegI2CStatus = hw_read_20kx(hw, I2C_IF_STATUS);
1459
1460         set_field(&RegI2CStatus, I2C_STATUS_DCM, 1); /* Direct control mode */
1461
1462         hw_write_20kx(hw, I2C_IF_STATUS, RegI2CStatus);
1463
1464         return 0;
1465 }
1466
1467 static int I2CUninit(struct hw *hw)
1468 {
1469         unsigned int RegI2CStatus;
1470         unsigned int RegI2CAddress;
1471
1472         RegI2CAddress = 0;
1473         set_field(&RegI2CAddress, I2C_ADDRESS_SLAD, 0x57); /* I2C id */
1474
1475         hw_write_20kx(hw, I2C_IF_ADDRESS, RegI2CAddress);
1476
1477         RegI2CStatus = hw_read_20kx(hw, I2C_IF_STATUS);
1478
1479         set_field(&RegI2CStatus, I2C_STATUS_DCM, 0); /* I2C mode */
1480
1481         hw_write_20kx(hw, I2C_IF_STATUS, RegI2CStatus);
1482
1483         return I2CLockChip(hw);
1484 }
1485
1486 static int I2CWaitDataReady(struct hw *hw)
1487 {
1488         int i = 0x400000;
1489         unsigned int ret = 0;
1490
1491         do {
1492                 ret = hw_read_20kx(hw, I2C_IF_STATUS);
1493         } while ((!(ret & DATA_READY)) && --i);
1494
1495         return i;
1496 }
1497
1498 static int I2CRead(struct hw *hw, u16 wAddress, u32 *pdwData)
1499 {
1500         unsigned int RegI2CStatus;
1501
1502         RegI2CStatus = hw_read_20kx(hw, I2C_IF_STATUS);
1503         set_field(&RegI2CStatus, I2C_STATUS_BC,
1504                         (4 == m_bAddressSize) ? 0 : m_bAddressSize);
1505         hw_write_20kx(hw, I2C_IF_STATUS, RegI2CStatus);
1506         if (!I2CWaitDataReady(hw))
1507                 return -1;
1508
1509         hw_write_20kx(hw, I2C_IF_WDATA, (u32)wAddress);
1510         if (!I2CWaitDataReady(hw))
1511                 return -1;
1512
1513         /* Force a read operation */
1514         hw_write_20kx(hw, I2C_IF_RDATA, 0);
1515         if (!I2CWaitDataReady(hw))
1516                 return -1;
1517
1518         *pdwData = hw_read_20kx(hw, I2C_IF_RDATA);
1519
1520         return 0;
1521 }
1522
1523 static int I2CWrite(struct hw *hw, u16 wAddress, u32 dwData)
1524 {
1525         unsigned int dwI2CData = (dwData << (m_bAddressSize * 8)) | wAddress;
1526         unsigned int RegI2CStatus;
1527
1528         RegI2CStatus = hw_read_20kx(hw, I2C_IF_STATUS);
1529
1530         set_field(&RegI2CStatus, I2C_STATUS_BC,
1531                   (4 == (m_bAddressSize + m_bDataSize)) ?
1532                   0 : (m_bAddressSize + m_bDataSize));
1533
1534         hw_write_20kx(hw, I2C_IF_STATUS, RegI2CStatus);
1535         I2CWaitDataReady(hw);
1536         /* Dummy write to trigger the write oprtation */
1537         hw_write_20kx(hw, I2C_IF_WDATA, 0);
1538         I2CWaitDataReady(hw);
1539
1540         /* This is the real data */
1541         hw_write_20kx(hw, I2C_IF_WDATA, dwI2CData);
1542         I2CWaitDataReady(hw);
1543
1544         return 0;
1545 }
1546
1547 static int hw_dac_init(struct hw *hw, const struct dac_conf *info)
1548 {
1549         int err = 0;
1550         u32 dwData = 0;
1551         int i = 0;
1552         struct REGS_CS4382 cs4382_Read = {0};
1553         struct REGS_CS4382 cs4382_Def = {
1554                                    0x00000001,  /* Mode Control 1 */
1555                                    0x00000000,  /* Mode Control 2 */
1556                                    0x00000084,  /* Mode Control 3 */
1557                                    0x00000000,  /* Filter Control */
1558                                    0x00000000,  /* Invert Control */
1559                                    0x00000024,  /* Mixing Control Pair 1 */
1560                                    0x00000000,  /* Vol Control A1 */
1561                                    0x00000000,  /* Vol Control B1 */
1562                                    0x00000024,  /* Mixing Control Pair 2 */
1563                                    0x00000000,  /* Vol Control A2 */
1564                                    0x00000000,  /* Vol Control B2 */
1565                                    0x00000024,  /* Mixing Control Pair 3 */
1566                                    0x00000000,  /* Vol Control A3 */
1567                                    0x00000000,  /* Vol Control B3 */
1568                                    0x00000024,  /* Mixing Control Pair 4 */
1569                                    0x00000000,  /* Vol Control A4 */
1570                                    0x00000000   /* Vol Control B4 */
1571                                  };
1572
1573         /* Set DAC reset bit as output */
1574         dwData = hw_read_20kx(hw, GPIO_CTRL);
1575         dwData |= 0x02;
1576         hw_write_20kx(hw, GPIO_CTRL, dwData);
1577
1578         err = I2CInit(hw, 0x18, 1, 1);
1579         if (err < 0)
1580                 goto End;
1581
1582         for (i = 0; i < 2; i++) {
1583                 /* Reset DAC twice just in-case the chip
1584                  * didn't initialized properly */
1585                 dwData = hw_read_20kx(hw, GPIO_DATA);
1586                 /* GPIO data bit 1 */
1587                 dwData &= 0xFFFFFFFD;
1588                 hw_write_20kx(hw, GPIO_DATA, dwData);
1589                 mdelay(10);
1590                 dwData |= 0x2;
1591                 hw_write_20kx(hw, GPIO_DATA, dwData);
1592                 mdelay(50);
1593
1594                 /* Reset the 2nd time */
1595                 dwData &= 0xFFFFFFFD;
1596                 hw_write_20kx(hw, GPIO_DATA, dwData);
1597                 mdelay(10);
1598                 dwData |= 0x2;
1599                 hw_write_20kx(hw, GPIO_DATA, dwData);
1600                 mdelay(50);
1601
1602                 if (I2CRead(hw, CS4382_MC1,  &cs4382_Read.dwModeControl_1))
1603                         continue;
1604
1605                 if (I2CRead(hw, CS4382_MC2,  &cs4382_Read.dwModeControl_2))
1606                         continue;
1607
1608                 if (I2CRead(hw, CS4382_MC3,  &cs4382_Read.dwModeControl_3))
1609                         continue;
1610
1611                 if (I2CRead(hw, CS4382_FC,   &cs4382_Read.dwFilterControl))
1612                         continue;
1613
1614                 if (I2CRead(hw, CS4382_IC,   &cs4382_Read.dwInvertControl))
1615                         continue;
1616
1617                 if (I2CRead(hw, CS4382_XC1,  &cs4382_Read.dwMixControl_P1))
1618                         continue;
1619
1620                 if (I2CRead(hw, CS4382_VCA1, &cs4382_Read.dwVolControl_A1))
1621                         continue;
1622
1623                 if (I2CRead(hw, CS4382_VCB1, &cs4382_Read.dwVolControl_B1))
1624                         continue;
1625
1626                 if (I2CRead(hw, CS4382_XC2,  &cs4382_Read.dwMixControl_P2))
1627                         continue;
1628
1629                 if (I2CRead(hw, CS4382_VCA2, &cs4382_Read.dwVolControl_A2))
1630                         continue;
1631
1632                 if (I2CRead(hw, CS4382_VCB2, &cs4382_Read.dwVolControl_B2))
1633                         continue;
1634
1635                 if (I2CRead(hw, CS4382_XC3,  &cs4382_Read.dwMixControl_P3))
1636                         continue;
1637
1638                 if (I2CRead(hw, CS4382_VCA3, &cs4382_Read.dwVolControl_A3))
1639                         continue;
1640
1641                 if (I2CRead(hw, CS4382_VCB3, &cs4382_Read.dwVolControl_B3))
1642                         continue;
1643
1644                 if (I2CRead(hw, CS4382_XC4,  &cs4382_Read.dwMixControl_P4))
1645                         continue;
1646
1647                 if (I2CRead(hw, CS4382_VCA4, &cs4382_Read.dwVolControl_A4))
1648                         continue;
1649
1650                 if (I2CRead(hw, CS4382_VCB4, &cs4382_Read.dwVolControl_B4))
1651                         continue;
1652
1653                 if (memcmp(&cs4382_Read, &cs4382_Def,
1654                                                 sizeof(struct REGS_CS4382)))
1655                         continue;
1656                 else
1657                         break;
1658         }
1659
1660         if (i >= 2)
1661                 goto End;
1662
1663         /* Note: Every I2C write must have some delay.
1664          * This is not a requirement but the delay works here... */
1665         I2CWrite(hw, CS4382_MC1, 0x80);
1666         I2CWrite(hw, CS4382_MC2, 0x10);
1667         if (1 == info->msr) {
1668                 I2CWrite(hw, CS4382_XC1, 0x24);
1669                 I2CWrite(hw, CS4382_XC2, 0x24);
1670                 I2CWrite(hw, CS4382_XC3, 0x24);
1671                 I2CWrite(hw, CS4382_XC4, 0x24);
1672         } else if (2 == info->msr) {
1673                 I2CWrite(hw, CS4382_XC1, 0x25);
1674                 I2CWrite(hw, CS4382_XC2, 0x25);
1675                 I2CWrite(hw, CS4382_XC3, 0x25);
1676                 I2CWrite(hw, CS4382_XC4, 0x25);
1677         } else {
1678                 I2CWrite(hw, CS4382_XC1, 0x26);
1679                 I2CWrite(hw, CS4382_XC2, 0x26);
1680                 I2CWrite(hw, CS4382_XC3, 0x26);
1681                 I2CWrite(hw, CS4382_XC4, 0x26);
1682         }
1683
1684         return 0;
1685 End:
1686
1687         I2CUninit(hw);
1688         return -1;
1689 }
1690
1691 /* ADC operations */
1692 #define MAKE_WM8775_ADDR(addr, data)    (u32)(((addr<<1)&0xFE)|((data>>8)&0x1))
1693 #define MAKE_WM8775_DATA(data)  (u32)(data&0xFF)
1694
1695 #define WM8775_IC       0x0B
1696 #define WM8775_MMC      0x0C
1697 #define WM8775_AADCL    0x0E
1698 #define WM8775_AADCR    0x0F
1699 #define WM8775_ADCMC    0x15
1700 #define WM8775_RESET    0x17
1701
1702 static int hw_is_adc_input_selected(struct hw *hw, enum ADCSRC type)
1703 {
1704         u32 data = 0;
1705
1706         data = hw_read_20kx(hw, GPIO_DATA);
1707         switch (type) {
1708         case ADC_MICIN:
1709                 data = (data & (0x1 << 14)) ? 1 : 0;
1710                 break;
1711         case ADC_LINEIN:
1712                 data = (data & (0x1 << 14)) ? 0 : 1;
1713                 break;
1714         default:
1715                 data = 0;
1716         }
1717         return data;
1718 }
1719
1720 static int hw_adc_input_select(struct hw *hw, enum ADCSRC type)
1721 {
1722         u32 data = 0;
1723
1724         data = hw_read_20kx(hw, GPIO_DATA);
1725         switch (type) {
1726         case ADC_MICIN:
1727                 data |= (0x1 << 14);
1728                 hw_write_20kx(hw, GPIO_DATA, data);
1729                 I2CWrite(hw, MAKE_WM8775_ADDR(WM8775_ADCMC, 0x101),
1730                                 MAKE_WM8775_DATA(0x101)); /* Mic-in */
1731                 I2CWrite(hw, MAKE_WM8775_ADDR(WM8775_AADCL, 0xE7),
1732                                 MAKE_WM8775_DATA(0xE7)); /* +12dB boost */
1733                 I2CWrite(hw, MAKE_WM8775_ADDR(WM8775_AADCR, 0xE7),
1734                                 MAKE_WM8775_DATA(0xE7)); /* +12dB boost */
1735                 break;
1736         case ADC_LINEIN:
1737                 data &= ~(0x1 << 14);
1738                 hw_write_20kx(hw, GPIO_DATA, data);
1739                 I2CWrite(hw, MAKE_WM8775_ADDR(WM8775_ADCMC, 0x102),
1740                                 MAKE_WM8775_DATA(0x102)); /* Line-in */
1741                 I2CWrite(hw, MAKE_WM8775_ADDR(WM8775_AADCL, 0xCF),
1742                                 MAKE_WM8775_DATA(0xCF)); /* No boost */
1743                 I2CWrite(hw, MAKE_WM8775_ADDR(WM8775_AADCR, 0xCF),
1744                                 MAKE_WM8775_DATA(0xCF)); /* No boost */
1745                 break;
1746         default:
1747                 break;
1748         }
1749
1750         return 0;
1751 }
1752
1753 static int hw_adc_init(struct hw *hw, const struct adc_conf *info)
1754 {
1755         int err = 0;
1756         u32 dwMux = 2, dwData = 0, dwCtl = 0;
1757
1758         /*  Set ADC reset bit as output */
1759         dwData = hw_read_20kx(hw, GPIO_CTRL);
1760         dwData |= (0x1 << 15);
1761         hw_write_20kx(hw, GPIO_CTRL, dwData);
1762
1763         /* Initialize I2C */
1764         err = I2CInit(hw, 0x1A, 1, 1);
1765         if (err < 0) {
1766                 printk(KERN_ALERT "ctxfi: Failure to acquire I2C!!!\n");
1767                 goto error;
1768         }
1769
1770         /* Make ADC in normal operation */
1771         dwData = hw_read_20kx(hw, GPIO_DATA);
1772         dwData &= ~(0x1 << 15);
1773         mdelay(10);
1774         dwData |= (0x1 << 15);
1775         hw_write_20kx(hw, GPIO_DATA, dwData);
1776         mdelay(50);
1777
1778         /* Set the master mode (256fs) */
1779         if (1 == info->msr) {
1780                 I2CWrite(hw, MAKE_WM8775_ADDR(WM8775_MMC, 0x02),
1781                                                 MAKE_WM8775_DATA(0x02));
1782         } else if (2 == info->msr) {
1783                 I2CWrite(hw, MAKE_WM8775_ADDR(WM8775_MMC, 0x0A),
1784                                                 MAKE_WM8775_DATA(0x0A));
1785         } else {
1786                 printk(KERN_ALERT "ctxfi: Invalid master sampling "
1787                                   "rate (msr %d)!!!\n", info->msr);
1788                 err = -EINVAL;
1789                 goto error;
1790         }
1791
1792         /* Configure GPIO bit 14 change to line-in/mic-in */
1793         dwCtl = hw_read_20kx(hw, GPIO_CTRL);
1794         dwCtl |= 0x1<<14;
1795         hw_write_20kx(hw, GPIO_CTRL, dwCtl);
1796
1797         /* Check using Mic-in or Line-in */
1798         dwData = hw_read_20kx(hw, GPIO_DATA);
1799
1800         if (dwMux == 1) {
1801                 /* Configures GPIO data to select Mic-in */
1802                 dwData |= 0x1<<14;
1803                 hw_write_20kx(hw, GPIO_DATA, dwData);
1804
1805                 I2CWrite(hw, MAKE_WM8775_ADDR(WM8775_ADCMC, 0x101),
1806                                 MAKE_WM8775_DATA(0x101)); /* Mic-in */
1807                 I2CWrite(hw, MAKE_WM8775_ADDR(WM8775_AADCL, 0xE7),
1808                                 MAKE_WM8775_DATA(0xE7)); /* +12dB boost */
1809                 I2CWrite(hw, MAKE_WM8775_ADDR(WM8775_AADCR, 0xE7),
1810                                 MAKE_WM8775_DATA(0xE7)); /* +12dB boost */
1811         } else if (dwMux == 2) {
1812                 /* Configures GPIO data to select Line-in */
1813                 dwData &= ~(0x1<<14);
1814                 hw_write_20kx(hw, GPIO_DATA, dwData);
1815
1816                 /* Setup ADC */
1817                 I2CWrite(hw, MAKE_WM8775_ADDR(WM8775_ADCMC, 0x102),
1818                                 MAKE_WM8775_DATA(0x102)); /* Line-in */
1819                 I2CWrite(hw, MAKE_WM8775_ADDR(WM8775_AADCL, 0xCF),
1820                                 MAKE_WM8775_DATA(0xCF)); /* No boost */
1821                 I2CWrite(hw, MAKE_WM8775_ADDR(WM8775_AADCR, 0xCF),
1822                                 MAKE_WM8775_DATA(0xCF)); /* No boost */
1823         } else {
1824                 printk(KERN_ALERT "ctxfi: ERROR!!! Invalid input mux!!!\n");
1825                 err = -EINVAL;
1826                 goto error;
1827         }
1828
1829         return 0;
1830
1831 error:
1832         I2CUninit(hw);
1833         return err;
1834 }
1835
1836 static int hw_have_digit_io_switch(struct hw *hw)
1837 {
1838         return 0;
1839 }
1840
1841 static int hw_card_start(struct hw *hw)
1842 {
1843         int err = 0;
1844         struct pci_dev *pci = hw->pci;
1845         unsigned int gctl;
1846         unsigned int dma_mask = 0;
1847
1848         err = pci_enable_device(pci);
1849         if (err < 0)
1850                 return err;
1851
1852         /* Set DMA transfer mask */
1853         dma_mask = CT_XFI_DMA_MASK;
1854         if (pci_set_dma_mask(pci, dma_mask) < 0 ||
1855             pci_set_consistent_dma_mask(pci, dma_mask) < 0) {
1856                 printk(KERN_ERR "ctxfi: architecture does not support PCI "
1857                 "busmaster DMA with mask 0x%x\n", dma_mask);
1858                 err = -ENXIO;
1859                 goto error1;
1860         }
1861
1862         err = pci_request_regions(pci, "XFi");
1863         if (err < 0)
1864                 goto error1;
1865
1866         hw->io_base = pci_resource_start(hw->pci, 2);
1867         hw->mem_base = (unsigned long)ioremap(hw->io_base,
1868                                         pci_resource_len(hw->pci, 2));
1869         if (NULL == (void *)hw->mem_base) {
1870                 err = -ENOENT;
1871                 goto error2;
1872         }
1873
1874         /* Switch to 20k2 mode from UAA mode. */
1875         gctl = hw_read_20kx(hw, GLOBAL_CNTL_GCTL);
1876         set_field(&gctl, GCTL_UAA, 0);
1877         hw_write_20kx(hw, GLOBAL_CNTL_GCTL, gctl);
1878
1879         /*if ((err = request_irq(pci->irq, ct_atc_interrupt, IRQF_SHARED,
1880                                 atc->chip_details->nm_card, hw))) {
1881                 goto error3;
1882         }
1883         hw->irq = pci->irq;
1884         */
1885
1886         pci_set_master(pci);
1887
1888         return 0;
1889
1890 /*error3:
1891         iounmap((void *)hw->mem_base);
1892         hw->mem_base = (unsigned long)NULL;*/
1893 error2:
1894         pci_release_regions(pci);
1895         hw->io_base = 0;
1896 error1:
1897         pci_disable_device(pci);
1898         return err;
1899 }
1900
1901 static int hw_card_stop(struct hw *hw)
1902 {
1903         /* TODO: Disable interrupt and so on... */
1904         return 0;
1905 }
1906
1907 static int hw_card_shutdown(struct hw *hw)
1908 {
1909         if (hw->irq >= 0)
1910                 free_irq(hw->irq, hw);
1911
1912         hw->irq = -1;
1913
1914         if (NULL != ((void *)hw->mem_base))
1915                 iounmap((void *)hw->mem_base);
1916
1917         hw->mem_base = (unsigned long)NULL;
1918
1919         if (hw->io_base)
1920                 pci_release_regions(hw->pci);
1921
1922         hw->io_base = 0;
1923
1924         pci_disable_device(hw->pci);
1925
1926         return 0;
1927 }
1928
1929 static int hw_card_init(struct hw *hw, struct card_conf *info)
1930 {
1931         int err;
1932         unsigned int gctl;
1933         u32 data = 0;
1934         struct dac_conf dac_info = {0};
1935         struct adc_conf adc_info = {0};
1936         struct daio_conf daio_info = {0};
1937         struct trn_conf trn_info = {0};
1938
1939         /* Get PCI io port/memory base address and
1940          * do 20kx core switch if needed. */
1941         if (!hw->io_base) {
1942                 err = hw_card_start(hw);
1943                 if (err)
1944                         return err;
1945         }
1946
1947         /* PLL init */
1948         err = hw_pll_init(hw, info->rsr);
1949         if (err < 0)
1950                 return err;
1951
1952         /* kick off auto-init */
1953         err = hw_auto_init(hw);
1954         if (err < 0)
1955                 return err;
1956
1957         gctl = hw_read_20kx(hw, GLOBAL_CNTL_GCTL);
1958         set_field(&gctl, GCTL_DBP, 1);
1959         set_field(&gctl, GCTL_TBP, 1);
1960         set_field(&gctl, GCTL_FBP, 1);
1961         set_field(&gctl, GCTL_DPC, 0);
1962         hw_write_20kx(hw, GLOBAL_CNTL_GCTL, gctl);
1963
1964         /* Reset all global pending interrupts */
1965         hw_write_20kx(hw, INTERRUPT_GIE, 0);
1966         /* Reset all SRC pending interrupts */
1967         hw_write_20kx(hw, SRC_IP, 0);
1968
1969         /* TODO: detect the card ID and configure GPIO accordingly. */
1970         /* Configures GPIO (0xD802 0x98028) */
1971         /*hw_write_20kx(hw, GPIO_CTRL, 0x7F07);*/
1972         /* Configures GPIO (SB0880) */
1973         /*hw_write_20kx(hw, GPIO_CTRL, 0xFF07);*/
1974         hw_write_20kx(hw, GPIO_CTRL, 0xD802);
1975
1976         /* Enable audio ring */
1977         hw_write_20kx(hw, MIXER_AR_ENABLE, 0x01);
1978
1979         trn_info.vm_pgt_phys = info->vm_pgt_phys;
1980         err = hw_trn_init(hw, &trn_info);
1981         if (err < 0)
1982                 return err;
1983
1984         daio_info.msr = info->msr;
1985         err = hw_daio_init(hw, &daio_info);
1986         if (err < 0)
1987                 return err;
1988
1989         dac_info.msr = info->msr;
1990         err = hw_dac_init(hw, &dac_info);
1991         if (err < 0)
1992                 return err;
1993
1994         adc_info.msr = info->msr;
1995         adc_info.input = ADC_LINEIN;
1996         adc_info.mic20db = 0;
1997         err = hw_adc_init(hw, &adc_info);
1998         if (err < 0)
1999                 return err;
2000
2001         data = hw_read_20kx(hw, SRC_MCTL);
2002         data |= 0x1; /* Enables input from the audio ring */
2003         hw_write_20kx(hw, SRC_MCTL, data);
2004
2005         return 0;
2006 }
2007
2008 static u32 hw_read_20kx(struct hw *hw, u32 reg)
2009 {
2010         return readl((void *)(hw->mem_base + reg));
2011 }
2012
2013 static void hw_write_20kx(struct hw *hw, u32 reg, u32 data)
2014 {
2015         writel(data, (void *)(hw->mem_base + reg));
2016 }
2017
2018 int create_20k2_hw_obj(struct hw **rhw)
2019 {
2020         struct hw *hw;
2021
2022         *rhw = NULL;
2023         hw = kzalloc(sizeof(*hw), GFP_KERNEL);
2024         if (NULL == hw)
2025                 return -ENOMEM;
2026
2027         hw->io_base = 0;
2028         hw->mem_base = (unsigned long)NULL;
2029         hw->irq = -1;
2030
2031         hw->card_init = hw_card_init;
2032         hw->card_stop = hw_card_stop;
2033         hw->pll_init = hw_pll_init;
2034         hw->is_adc_source_selected = hw_is_adc_input_selected;
2035         hw->select_adc_source = hw_adc_input_select;
2036         hw->have_digit_io_switch = hw_have_digit_io_switch;
2037
2038         hw->src_rsc_get_ctrl_blk = src_get_rsc_ctrl_blk;
2039         hw->src_rsc_put_ctrl_blk = src_put_rsc_ctrl_blk;
2040         hw->src_mgr_get_ctrl_blk = src_mgr_get_ctrl_blk;
2041         hw->src_mgr_put_ctrl_blk = src_mgr_put_ctrl_blk;
2042         hw->src_set_state = src_set_state;
2043         hw->src_set_bm = src_set_bm;
2044         hw->src_set_rsr = src_set_rsr;
2045         hw->src_set_sf = src_set_sf;
2046         hw->src_set_wr = src_set_wr;
2047         hw->src_set_pm = src_set_pm;
2048         hw->src_set_rom = src_set_rom;
2049         hw->src_set_vo = src_set_vo;
2050         hw->src_set_st = src_set_st;
2051         hw->src_set_ie = src_set_ie;
2052         hw->src_set_ilsz = src_set_ilsz;
2053         hw->src_set_bp = src_set_bp;
2054         hw->src_set_cisz = src_set_cisz;
2055         hw->src_set_ca = src_set_ca;
2056         hw->src_set_sa = src_set_sa;
2057         hw->src_set_la = src_set_la;
2058         hw->src_set_pitch = src_set_pitch;
2059         hw->src_set_dirty = src_set_dirty;
2060         hw->src_set_clear_zbufs = src_set_clear_zbufs;
2061         hw->src_set_dirty_all = src_set_dirty_all;
2062         hw->src_commit_write = src_commit_write;
2063         hw->src_get_ca = src_get_ca;
2064         hw->src_get_dirty = src_get_dirty;
2065         hw->src_dirty_conj_mask = src_dirty_conj_mask;
2066         hw->src_mgr_enbs_src = src_mgr_enbs_src;
2067         hw->src_mgr_enb_src = src_mgr_enb_src;
2068         hw->src_mgr_dsb_src = src_mgr_dsb_src;
2069         hw->src_mgr_commit_write = src_mgr_commit_write;
2070
2071         hw->srcimp_mgr_get_ctrl_blk = srcimp_mgr_get_ctrl_blk;
2072         hw->srcimp_mgr_put_ctrl_blk = srcimp_mgr_put_ctrl_blk;
2073         hw->srcimp_mgr_set_imaparc = srcimp_mgr_set_imaparc;
2074         hw->srcimp_mgr_set_imapuser = srcimp_mgr_set_imapuser;
2075         hw->srcimp_mgr_set_imapnxt = srcimp_mgr_set_imapnxt;
2076         hw->srcimp_mgr_set_imapaddr = srcimp_mgr_set_imapaddr;
2077         hw->srcimp_mgr_commit_write = srcimp_mgr_commit_write;
2078
2079         hw->amixer_rsc_get_ctrl_blk = amixer_rsc_get_ctrl_blk;
2080         hw->amixer_rsc_put_ctrl_blk = amixer_rsc_put_ctrl_blk;
2081         hw->amixer_mgr_get_ctrl_blk = amixer_mgr_get_ctrl_blk;
2082         hw->amixer_mgr_put_ctrl_blk = amixer_mgr_put_ctrl_blk;
2083         hw->amixer_set_mode = amixer_set_mode;
2084         hw->amixer_set_iv = amixer_set_iv;
2085         hw->amixer_set_x = amixer_set_x;
2086         hw->amixer_set_y = amixer_set_y;
2087         hw->amixer_set_sadr = amixer_set_sadr;
2088         hw->amixer_set_se = amixer_set_se;
2089         hw->amixer_set_dirty = amixer_set_dirty;
2090         hw->amixer_set_dirty_all = amixer_set_dirty_all;
2091         hw->amixer_commit_write = amixer_commit_write;
2092         hw->amixer_get_y = amixer_get_y;
2093         hw->amixer_get_dirty = amixer_get_dirty;
2094
2095         hw->dai_get_ctrl_blk = dai_get_ctrl_blk;
2096         hw->dai_put_ctrl_blk = dai_put_ctrl_blk;
2097         hw->dai_srt_set_srco = dai_srt_set_srco;
2098         hw->dai_srt_set_srcm = dai_srt_set_srcm;
2099         hw->dai_srt_set_rsr = dai_srt_set_rsr;
2100         hw->dai_srt_set_drat = dai_srt_set_drat;
2101         hw->dai_srt_set_ec = dai_srt_set_ec;
2102         hw->dai_srt_set_et = dai_srt_set_et;
2103         hw->dai_commit_write = dai_commit_write;
2104
2105         hw->dao_get_ctrl_blk = dao_get_ctrl_blk;
2106         hw->dao_put_ctrl_blk = dao_put_ctrl_blk;
2107         hw->dao_set_spos = dao_set_spos;
2108         hw->dao_commit_write = dao_commit_write;
2109         hw->dao_get_spos = dao_get_spos;
2110
2111         hw->daio_mgr_get_ctrl_blk = daio_mgr_get_ctrl_blk;
2112         hw->daio_mgr_put_ctrl_blk = daio_mgr_put_ctrl_blk;
2113         hw->daio_mgr_enb_dai = daio_mgr_enb_dai;
2114         hw->daio_mgr_dsb_dai = daio_mgr_dsb_dai;
2115         hw->daio_mgr_enb_dao = daio_mgr_enb_dao;
2116         hw->daio_mgr_dsb_dao = daio_mgr_dsb_dao;
2117         hw->daio_mgr_dao_init = daio_mgr_dao_init;
2118         hw->daio_mgr_set_imaparc = daio_mgr_set_imaparc;
2119         hw->daio_mgr_set_imapnxt = daio_mgr_set_imapnxt;
2120         hw->daio_mgr_set_imapaddr = daio_mgr_set_imapaddr;
2121         hw->daio_mgr_commit_write = daio_mgr_commit_write;
2122
2123         *rhw = hw;
2124
2125         return 0;
2126 }
2127
2128 int destroy_20k2_hw_obj(struct hw *hw)
2129 {
2130         if (hw->io_base)
2131                 hw_card_shutdown(hw);
2132
2133         kfree(hw);
2134         return 0;
2135 }