ALSA: SB X-Fi driver merge
[linux-2.6.git] / sound / pci / ctxfi / cthw20k2.c
1 /**
2  * Copyright (C) 2008, Creative Technology Ltd. All Rights Reserved.
3  *
4  * This source file is released under GPL v2 license (no other versions).
5  * See the COPYING file included in the main directory of this source
6  * distribution for the license terms and conditions.
7  *
8  * @File        cthw20k2.c
9  *
10  * @Brief
11  * This file contains the implementation of hardware access methord for 20k2.
12  *
13  * @Author      Liu Chun
14  * @Date        May 14 2008
15  *
16  */
17
18 #include "cthw20k2.h"
19 #include "ct20k2reg.h"
20 #include <linux/types.h>
21 #include <linux/slab.h>
22 #include <linux/pci.h>
23 #include <linux/io.h>
24 #include <linux/string.h>
25 #include <linux/kernel.h>
26 #include <linux/interrupt.h>
27
28 #define CT_XFI_DMA_MASK         DMA_BIT_MASK(32) /* 32 bits */
29
30 static u32 hw_read_20kx(struct hw *hw, u32 reg);
31 static void hw_write_20kx(struct hw *hw, u32 reg, u32 data);
32
33 /*
34  * Type definition block.
35  * The layout of control structures can be directly applied on 20k2 chip.
36  */
37
38 /*
39  * SRC control block definitions.
40  */
41
42 /* SRC resource control block */
43 #define SRCCTL_STATE    0x00000007
44 #define SRCCTL_BM       0x00000008
45 #define SRCCTL_RSR      0x00000030
46 #define SRCCTL_SF       0x000001C0
47 #define SRCCTL_WR       0x00000200
48 #define SRCCTL_PM       0x00000400
49 #define SRCCTL_ROM      0x00001800
50 #define SRCCTL_VO       0x00002000
51 #define SRCCTL_ST       0x00004000
52 #define SRCCTL_IE       0x00008000
53 #define SRCCTL_ILSZ     0x000F0000
54 #define SRCCTL_BP       0x00100000
55
56 #define SRCCCR_CISZ     0x000007FF
57 #define SRCCCR_CWA      0x001FF800
58 #define SRCCCR_D        0x00200000
59 #define SRCCCR_RS       0x01C00000
60 #define SRCCCR_NAL      0x3E000000
61 #define SRCCCR_RA       0xC0000000
62
63 #define SRCCA_CA        0x0FFFFFFF
64 #define SRCCA_RS        0xE0000000
65
66 #define SRCSA_SA        0x0FFFFFFF
67
68 #define SRCLA_LA        0x0FFFFFFF
69
70 /* Mixer Parameter Ring ram Low and Hight register.
71  * Fixed-point value in 8.24 format for parameter channel */
72 #define MPRLH_PITCH     0xFFFFFFFF
73
74 /* SRC resource register dirty flags */
75 union src_dirty {
76         struct {
77                 u16 ctl:1;
78                 u16 ccr:1;
79                 u16 sa:1;
80                 u16 la:1;
81                 u16 ca:1;
82                 u16 mpr:1;
83                 u16 czbfs:1;    /* Clear Z-Buffers */
84                 u16 rsv:9;
85         } bf;
86         u16 data;
87 };
88
89 struct src_rsc_ctrl_blk {
90         unsigned int    ctl;
91         unsigned int    ccr;
92         unsigned int    ca;
93         unsigned int    sa;
94         unsigned int    la;
95         unsigned int    mpr;
96         union src_dirty dirty;
97 };
98
99 /* SRC manager control block */
100 union src_mgr_dirty {
101         struct {
102                 u16 enb0:1;
103                 u16 enb1:1;
104                 u16 enb2:1;
105                 u16 enb3:1;
106                 u16 enb4:1;
107                 u16 enb5:1;
108                 u16 enb6:1;
109                 u16 enb7:1;
110                 u16 enbsa:1;
111                 u16 rsv:7;
112         } bf;
113         u16 data;
114 };
115
116 struct src_mgr_ctrl_blk {
117         unsigned int            enbsa;
118         unsigned int            enb[8];
119         union src_mgr_dirty     dirty;
120 };
121
122 /* SRCIMP manager control block */
123 #define SRCAIM_ARC      0x00000FFF
124 #define SRCAIM_NXT      0x00FF0000
125 #define SRCAIM_SRC      0xFF000000
126
127 struct srcimap {
128         unsigned int srcaim;
129         unsigned int idx;
130 };
131
132 /* SRCIMP manager register dirty flags */
133 union srcimp_mgr_dirty {
134         struct {
135                 u16 srcimap:1;
136                 u16 rsv:15;
137         } bf;
138         u16 data;
139 };
140
141 struct srcimp_mgr_ctrl_blk {
142         struct srcimap          srcimap;
143         union srcimp_mgr_dirty  dirty;
144 };
145
146 /*
147  * Function implementation block.
148  */
149
150 static int src_get_rsc_ctrl_blk(void **rblk)
151 {
152         struct src_rsc_ctrl_blk *blk;
153
154         *rblk = NULL;
155         blk = kzalloc(sizeof(*blk), GFP_KERNEL);
156         if (NULL == blk)
157                 return -ENOMEM;
158
159         *rblk = blk;
160
161         return 0;
162 }
163
164 static int src_put_rsc_ctrl_blk(void *blk)
165 {
166         kfree((struct src_rsc_ctrl_blk *)blk);
167
168         return 0;
169 }
170
171 static int src_set_state(void *blk, unsigned int state)
172 {
173         struct src_rsc_ctrl_blk *ctl = blk;
174
175         set_field(&ctl->ctl, SRCCTL_STATE, state);
176         ctl->dirty.bf.ctl = 1;
177         return 0;
178 }
179
180 static int src_set_bm(void *blk, unsigned int bm)
181 {
182         struct src_rsc_ctrl_blk *ctl = blk;
183
184         set_field(&ctl->ctl, SRCCTL_BM, bm);
185         ctl->dirty.bf.ctl = 1;
186         return 0;
187 }
188
189 static int src_set_rsr(void *blk, unsigned int rsr)
190 {
191         struct src_rsc_ctrl_blk *ctl = blk;
192
193         set_field(&ctl->ctl, SRCCTL_RSR, rsr);
194         ctl->dirty.bf.ctl = 1;
195         return 0;
196 }
197
198 static int src_set_sf(void *blk, unsigned int sf)
199 {
200         struct src_rsc_ctrl_blk *ctl = blk;
201
202         set_field(&ctl->ctl, SRCCTL_SF, sf);
203         ctl->dirty.bf.ctl = 1;
204         return 0;
205 }
206
207 static int src_set_wr(void *blk, unsigned int wr)
208 {
209         struct src_rsc_ctrl_blk *ctl = blk;
210
211         set_field(&ctl->ctl, SRCCTL_WR, wr);
212         ctl->dirty.bf.ctl = 1;
213         return 0;
214 }
215
216 static int src_set_pm(void *blk, unsigned int pm)
217 {
218         struct src_rsc_ctrl_blk *ctl = blk;
219
220         set_field(&ctl->ctl, SRCCTL_PM, pm);
221         ctl->dirty.bf.ctl = 1;
222         return 0;
223 }
224
225 static int src_set_rom(void *blk, unsigned int rom)
226 {
227         struct src_rsc_ctrl_blk *ctl = blk;
228
229         set_field(&ctl->ctl, SRCCTL_ROM, rom);
230         ctl->dirty.bf.ctl = 1;
231         return 0;
232 }
233
234 static int src_set_vo(void *blk, unsigned int vo)
235 {
236         struct src_rsc_ctrl_blk *ctl = blk;
237
238         set_field(&ctl->ctl, SRCCTL_VO, vo);
239         ctl->dirty.bf.ctl = 1;
240         return 0;
241 }
242
243 static int src_set_st(void *blk, unsigned int st)
244 {
245         struct src_rsc_ctrl_blk *ctl = blk;
246
247         set_field(&ctl->ctl, SRCCTL_ST, st);
248         ctl->dirty.bf.ctl = 1;
249         return 0;
250 }
251
252 static int src_set_ie(void *blk, unsigned int ie)
253 {
254         struct src_rsc_ctrl_blk *ctl = blk;
255
256         set_field(&ctl->ctl, SRCCTL_IE, ie);
257         ctl->dirty.bf.ctl = 1;
258         return 0;
259 }
260
261 static int src_set_ilsz(void *blk, unsigned int ilsz)
262 {
263         struct src_rsc_ctrl_blk *ctl = blk;
264
265         set_field(&ctl->ctl, SRCCTL_ILSZ, ilsz);
266         ctl->dirty.bf.ctl = 1;
267         return 0;
268 }
269
270 static int src_set_bp(void *blk, unsigned int bp)
271 {
272         struct src_rsc_ctrl_blk *ctl = blk;
273
274         set_field(&ctl->ctl, SRCCTL_BP, bp);
275         ctl->dirty.bf.ctl = 1;
276         return 0;
277 }
278
279 static int src_set_cisz(void *blk, unsigned int cisz)
280 {
281         struct src_rsc_ctrl_blk *ctl = blk;
282
283         set_field(&ctl->ccr, SRCCCR_CISZ, cisz);
284         ctl->dirty.bf.ccr = 1;
285         return 0;
286 }
287
288 static int src_set_ca(void *blk, unsigned int ca)
289 {
290         struct src_rsc_ctrl_blk *ctl = blk;
291
292         set_field(&ctl->ca, SRCCA_CA, ca);
293         ctl->dirty.bf.ca = 1;
294         return 0;
295 }
296
297 static int src_set_sa(void *blk, unsigned int sa)
298 {
299         struct src_rsc_ctrl_blk *ctl = blk;
300
301         set_field(&ctl->sa, SRCSA_SA, sa);
302         ctl->dirty.bf.sa = 1;
303         return 0;
304 }
305
306 static int src_set_la(void *blk, unsigned int la)
307 {
308         struct src_rsc_ctrl_blk *ctl = blk;
309
310         set_field(&ctl->la, SRCLA_LA, la);
311         ctl->dirty.bf.la = 1;
312         return 0;
313 }
314
315 static int src_set_pitch(void *blk, unsigned int pitch)
316 {
317         struct src_rsc_ctrl_blk *ctl = blk;
318
319         set_field(&ctl->mpr, MPRLH_PITCH, pitch);
320         ctl->dirty.bf.mpr = 1;
321         return 0;
322 }
323
324 static int src_set_clear_zbufs(void *blk, unsigned int clear)
325 {
326         ((struct src_rsc_ctrl_blk *)blk)->dirty.bf.czbfs = (clear ? 1 : 0);
327         return 0;
328 }
329
330 static int src_set_dirty(void *blk, unsigned int flags)
331 {
332         ((struct src_rsc_ctrl_blk *)blk)->dirty.data = (flags & 0xffff);
333         return 0;
334 }
335
336 static int src_set_dirty_all(void *blk)
337 {
338         ((struct src_rsc_ctrl_blk *)blk)->dirty.data = ~(0x0);
339         return 0;
340 }
341
342 #define AR_SLOT_SIZE            4096
343 #define AR_SLOT_BLOCK_SIZE      16
344 #define AR_PTS_PITCH            6
345 #define AR_PARAM_SRC_OFFSET     0x60
346
347 static unsigned int src_param_pitch_mixer(unsigned int src_idx)
348 {
349         return ((src_idx << 4) + AR_PTS_PITCH + AR_SLOT_SIZE
350                         - AR_PARAM_SRC_OFFSET) % AR_SLOT_SIZE;
351
352 }
353
354 static int src_commit_write(struct hw *hw, unsigned int idx, void *blk)
355 {
356         struct src_rsc_ctrl_blk *ctl = blk;
357         int i = 0;
358
359         if (ctl->dirty.bf.czbfs) {
360                 /* Clear Z-Buffer registers */
361                 for (i = 0; i < 8; i++)
362                         hw_write_20kx(hw, SRC_UPZ+idx*0x100+i*0x4, 0);
363
364                 for (i = 0; i < 4; i++)
365                         hw_write_20kx(hw, SRC_DN0Z+idx*0x100+i*0x4, 0);
366
367                 for (i = 0; i < 8; i++)
368                         hw_write_20kx(hw, SRC_DN1Z+idx*0x100+i*0x4, 0);
369
370                 ctl->dirty.bf.czbfs = 0;
371         }
372         if (ctl->dirty.bf.mpr) {
373                 /* Take the parameter mixer resource in the same group as that
374                  * the idx src is in for simplicity. Unlike src, all conjugate
375                  * parameter mixer resources must be programmed for
376                  * corresponding conjugate src resources. */
377                 unsigned int pm_idx = src_param_pitch_mixer(idx);
378                 hw_write_20kx(hw, MIXER_PRING_LO_HI+4*pm_idx, ctl->mpr);
379                 hw_write_20kx(hw, MIXER_PMOPLO+8*pm_idx, 0x3);
380                 hw_write_20kx(hw, MIXER_PMOPHI+8*pm_idx, 0x0);
381                 ctl->dirty.bf.mpr = 0;
382         }
383         if (ctl->dirty.bf.sa) {
384                 hw_write_20kx(hw, SRC_SA+idx*0x100, ctl->sa);
385                 ctl->dirty.bf.sa = 0;
386         }
387         if (ctl->dirty.bf.la) {
388                 hw_write_20kx(hw, SRC_LA+idx*0x100, ctl->la);
389                 ctl->dirty.bf.la = 0;
390         }
391         if (ctl->dirty.bf.ca) {
392                 hw_write_20kx(hw, SRC_CA+idx*0x100, ctl->ca);
393                 ctl->dirty.bf.ca = 0;
394         }
395
396         /* Write srccf register */
397         hw_write_20kx(hw, SRC_CF+idx*0x100, 0x0);
398
399         if (ctl->dirty.bf.ccr) {
400                 hw_write_20kx(hw, SRC_CCR+idx*0x100, ctl->ccr);
401                 ctl->dirty.bf.ccr = 0;
402         }
403         if (ctl->dirty.bf.ctl) {
404                 hw_write_20kx(hw, SRC_CTL+idx*0x100, ctl->ctl);
405                 ctl->dirty.bf.ctl = 0;
406         }
407
408         return 0;
409 }
410
411 static int src_get_ca(struct hw *hw, unsigned int idx, void *blk)
412 {
413         struct src_rsc_ctrl_blk *ctl = blk;
414
415         ctl->ca = hw_read_20kx(hw, SRC_CA+idx*0x100);
416         ctl->dirty.bf.ca = 0;
417
418         return get_field(ctl->ca, SRCCA_CA);
419 }
420
421 static unsigned int src_get_dirty(void *blk)
422 {
423         return ((struct src_rsc_ctrl_blk *)blk)->dirty.data;
424 }
425
426 static unsigned int src_dirty_conj_mask(void)
427 {
428         return 0x20;
429 }
430
431 static int src_mgr_enbs_src(void *blk, unsigned int idx)
432 {
433         ((struct src_mgr_ctrl_blk *)blk)->enbsa |= (0x1 << ((idx%128)/4));
434         ((struct src_mgr_ctrl_blk *)blk)->dirty.bf.enbsa = 1;
435         ((struct src_mgr_ctrl_blk *)blk)->enb[idx/32] |= (0x1 << (idx%32));
436         return 0;
437 }
438
439 static int src_mgr_enb_src(void *blk, unsigned int idx)
440 {
441         ((struct src_mgr_ctrl_blk *)blk)->enb[idx/32] |= (0x1 << (idx%32));
442         ((struct src_mgr_ctrl_blk *)blk)->dirty.data |= (0x1 << (idx/32));
443         return 0;
444 }
445
446 static int src_mgr_dsb_src(void *blk, unsigned int idx)
447 {
448         ((struct src_mgr_ctrl_blk *)blk)->enb[idx/32] &= ~(0x1 << (idx%32));
449         ((struct src_mgr_ctrl_blk *)blk)->dirty.data |= (0x1 << (idx/32));
450         return 0;
451 }
452
453 static int src_mgr_commit_write(struct hw *hw, void *blk)
454 {
455         struct src_mgr_ctrl_blk *ctl = blk;
456         int i = 0;
457         unsigned int ret = 0;
458
459         if (ctl->dirty.bf.enbsa) {
460                 do {
461                         ret = hw_read_20kx(hw, SRC_ENBSTAT);
462                 } while (ret & 0x1);
463                 hw_write_20kx(hw, SRC_ENBSA, ctl->enbsa);
464                 ctl->dirty.bf.enbsa = 0;
465         }
466         for (i = 0; i < 8; i++) {
467                 if ((ctl->dirty.data & (0x1 << i))) {
468                         hw_write_20kx(hw, SRC_ENB+(i*0x100), ctl->enb[i]);
469                         ctl->dirty.data &= ~(0x1 << i);
470                 }
471         }
472
473         return 0;
474 }
475
476 static int src_mgr_get_ctrl_blk(void **rblk)
477 {
478         struct src_mgr_ctrl_blk *blk;
479
480         *rblk = NULL;
481         blk = kzalloc(sizeof(*blk), GFP_KERNEL);
482         if (NULL == blk)
483                 return -ENOMEM;
484
485         *rblk = blk;
486
487         return 0;
488 }
489
490 static int src_mgr_put_ctrl_blk(void *blk)
491 {
492         kfree((struct src_mgr_ctrl_blk *)blk);
493
494         return 0;
495 }
496
497 static int srcimp_mgr_get_ctrl_blk(void **rblk)
498 {
499         struct srcimp_mgr_ctrl_blk *blk;
500
501         *rblk = NULL;
502         blk = kzalloc(sizeof(*blk), GFP_KERNEL);
503         if (NULL == blk)
504                 return -ENOMEM;
505
506         *rblk = blk;
507
508         return 0;
509 }
510
511 static int srcimp_mgr_put_ctrl_blk(void *blk)
512 {
513         kfree((struct srcimp_mgr_ctrl_blk *)blk);
514
515         return 0;
516 }
517
518 static int srcimp_mgr_set_imaparc(void *blk, unsigned int slot)
519 {
520         struct srcimp_mgr_ctrl_blk *ctl = blk;
521
522         set_field(&ctl->srcimap.srcaim, SRCAIM_ARC, slot);
523         ctl->dirty.bf.srcimap = 1;
524         return 0;
525 }
526
527 static int srcimp_mgr_set_imapuser(void *blk, unsigned int user)
528 {
529         struct srcimp_mgr_ctrl_blk *ctl = blk;
530
531         set_field(&ctl->srcimap.srcaim, SRCAIM_SRC, user);
532         ctl->dirty.bf.srcimap = 1;
533         return 0;
534 }
535
536 static int srcimp_mgr_set_imapnxt(void *blk, unsigned int next)
537 {
538         struct srcimp_mgr_ctrl_blk *ctl = blk;
539
540         set_field(&ctl->srcimap.srcaim, SRCAIM_NXT, next);
541         ctl->dirty.bf.srcimap = 1;
542         return 0;
543 }
544
545 static int srcimp_mgr_set_imapaddr(void *blk, unsigned int addr)
546 {
547         ((struct srcimp_mgr_ctrl_blk *)blk)->srcimap.idx = addr;
548         ((struct srcimp_mgr_ctrl_blk *)blk)->dirty.bf.srcimap = 1;
549         return 0;
550 }
551
552 static int srcimp_mgr_commit_write(struct hw *hw, void *blk)
553 {
554         struct srcimp_mgr_ctrl_blk *ctl = blk;
555
556         if (ctl->dirty.bf.srcimap) {
557                 hw_write_20kx(hw, SRC_IMAP+ctl->srcimap.idx*0x100,
558                                                 ctl->srcimap.srcaim);
559                 ctl->dirty.bf.srcimap = 0;
560         }
561
562         return 0;
563 }
564
565 /*
566  * AMIXER control block definitions.
567  */
568
569 #define AMOPLO_M        0x00000003
570 #define AMOPLO_IV       0x00000004
571 #define AMOPLO_X        0x0003FFF0
572 #define AMOPLO_Y        0xFFFC0000
573
574 #define AMOPHI_SADR     0x000000FF
575 #define AMOPHI_SE       0x80000000
576
577 /* AMIXER resource register dirty flags */
578 union amixer_dirty {
579         struct {
580                 u16 amoplo:1;
581                 u16 amophi:1;
582                 u16 rsv:14;
583         } bf;
584         u16 data;
585 };
586
587 /* AMIXER resource control block */
588 struct amixer_rsc_ctrl_blk {
589         unsigned int            amoplo;
590         unsigned int            amophi;
591         union amixer_dirty      dirty;
592 };
593
594 static int amixer_set_mode(void *blk, unsigned int mode)
595 {
596         struct amixer_rsc_ctrl_blk *ctl = blk;
597
598         set_field(&ctl->amoplo, AMOPLO_M, mode);
599         ctl->dirty.bf.amoplo = 1;
600         return 0;
601 }
602
603 static int amixer_set_iv(void *blk, unsigned int iv)
604 {
605         struct amixer_rsc_ctrl_blk *ctl = blk;
606
607         set_field(&ctl->amoplo, AMOPLO_IV, iv);
608         ctl->dirty.bf.amoplo = 1;
609         return 0;
610 }
611
612 static int amixer_set_x(void *blk, unsigned int x)
613 {
614         struct amixer_rsc_ctrl_blk *ctl = blk;
615
616         set_field(&ctl->amoplo, AMOPLO_X, x);
617         ctl->dirty.bf.amoplo = 1;
618         return 0;
619 }
620
621 static int amixer_set_y(void *blk, unsigned int y)
622 {
623         struct amixer_rsc_ctrl_blk *ctl = blk;
624
625         set_field(&ctl->amoplo, AMOPLO_Y, y);
626         ctl->dirty.bf.amoplo = 1;
627         return 0;
628 }
629
630 static int amixer_set_sadr(void *blk, unsigned int sadr)
631 {
632         struct amixer_rsc_ctrl_blk *ctl = blk;
633
634         set_field(&ctl->amophi, AMOPHI_SADR, sadr);
635         ctl->dirty.bf.amophi = 1;
636         return 0;
637 }
638
639 static int amixer_set_se(void *blk, unsigned int se)
640 {
641         struct amixer_rsc_ctrl_blk *ctl = blk;
642
643         set_field(&ctl->amophi, AMOPHI_SE, se);
644         ctl->dirty.bf.amophi = 1;
645         return 0;
646 }
647
648 static int amixer_set_dirty(void *blk, unsigned int flags)
649 {
650         ((struct amixer_rsc_ctrl_blk *)blk)->dirty.data = (flags & 0xffff);
651         return 0;
652 }
653
654 static int amixer_set_dirty_all(void *blk)
655 {
656         ((struct amixer_rsc_ctrl_blk *)blk)->dirty.data = ~(0x0);
657         return 0;
658 }
659
660 static int amixer_commit_write(struct hw *hw, unsigned int idx, void *blk)
661 {
662         struct amixer_rsc_ctrl_blk *ctl = blk;
663
664         if (ctl->dirty.bf.amoplo || ctl->dirty.bf.amophi) {
665                 hw_write_20kx(hw, MIXER_AMOPLO+idx*8, ctl->amoplo);
666                 ctl->dirty.bf.amoplo = 0;
667                 hw_write_20kx(hw, MIXER_AMOPHI+idx*8, ctl->amophi);
668                 ctl->dirty.bf.amophi = 0;
669         }
670
671         return 0;
672 }
673
674 static int amixer_get_y(void *blk)
675 {
676         struct amixer_rsc_ctrl_blk *ctl = blk;
677
678         return get_field(ctl->amoplo, AMOPLO_Y);
679 }
680
681 static unsigned int amixer_get_dirty(void *blk)
682 {
683         return ((struct amixer_rsc_ctrl_blk *)blk)->dirty.data;
684 }
685
686 static int amixer_rsc_get_ctrl_blk(void **rblk)
687 {
688         struct amixer_rsc_ctrl_blk *blk;
689
690         *rblk = NULL;
691         blk = kzalloc(sizeof(*blk), GFP_KERNEL);
692         if (NULL == blk)
693                 return -ENOMEM;
694
695         *rblk = blk;
696
697         return 0;
698 }
699
700 static int amixer_rsc_put_ctrl_blk(void *blk)
701 {
702         kfree((struct amixer_rsc_ctrl_blk *)blk);
703
704         return 0;
705 }
706
707 static int amixer_mgr_get_ctrl_blk(void **rblk)
708 {
709         *rblk = NULL;
710
711         return 0;
712 }
713
714 static int amixer_mgr_put_ctrl_blk(void *blk)
715 {
716         return 0;
717 }
718
719 /*
720  * DAIO control block definitions.
721  */
722
723 /* Receiver Sample Rate Tracker Control register */
724 #define SRTCTL_SRCO     0x000000FF
725 #define SRTCTL_SRCM     0x0000FF00
726 #define SRTCTL_RSR      0x00030000
727 #define SRTCTL_DRAT     0x00300000
728 #define SRTCTL_EC       0x01000000
729 #define SRTCTL_ET       0x10000000
730
731 /* DAIO Receiver register dirty flags */
732 union dai_dirty {
733         struct {
734                 u16 srt:1;
735                 u16 rsv:15;
736         } bf;
737         u16 data;
738 };
739
740 /* DAIO Receiver control block */
741 struct dai_ctrl_blk {
742         unsigned int    srt;
743         union dai_dirty dirty;
744 };
745
746 /* Audio Input Mapper RAM */
747 #define AIM_ARC         0x00000FFF
748 #define AIM_NXT         0x007F0000
749
750 struct daoimap {
751         unsigned int aim;
752         unsigned int idx;
753 };
754
755 /* Audio Transmitter Control and Status register */
756 #define ATXCTL_EN       0x00000001
757 #define ATXCTL_MODE     0x00000010
758 #define ATXCTL_CD       0x00000020
759 #define ATXCTL_RAW      0x00000100
760 #define ATXCTL_MT       0x00000200
761 #define ATXCTL_NUC      0x00003000
762 #define ATXCTL_BEN      0x00010000
763 #define ATXCTL_BMUX     0x00700000
764 #define ATXCTL_B24      0x01000000
765 #define ATXCTL_CPF      0x02000000
766 #define ATXCTL_RIV      0x10000000
767 #define ATXCTL_LIV      0x20000000
768 #define ATXCTL_RSAT     0x40000000
769 #define ATXCTL_LSAT     0x80000000
770
771 /* XDIF Transmitter register dirty flags */
772 union dao_dirty {
773         struct {
774                 u16 atxcsl:1;
775                 u16 rsv:15;
776         } bf;
777         u16 data;
778 };
779
780 /* XDIF Transmitter control block */
781 struct dao_ctrl_blk {
782         /* XDIF Transmitter Channel Status Low Register */
783         unsigned int    atxcsl;
784         union dao_dirty dirty;
785 };
786
787 /* Audio Receiver Control register */
788 #define ARXCTL_EN       0x00000001
789
790 /* DAIO manager register dirty flags */
791 union daio_mgr_dirty {
792         struct {
793                 u32 atxctl:8;
794                 u32 arxctl:8;
795                 u32 daoimap:1;
796                 u32 rsv:15;
797         } bf;
798         u32 data;
799 };
800
801 /* DAIO manager control block */
802 struct daio_mgr_ctrl_blk {
803         struct daoimap          daoimap;
804         unsigned int            txctl[8];
805         unsigned int            rxctl[8];
806         union daio_mgr_dirty    dirty;
807 };
808
809 static int dai_srt_set_srco(void *blk, unsigned int src)
810 {
811         struct dai_ctrl_blk *ctl = blk;
812
813         set_field(&ctl->srt, SRTCTL_SRCO, src);
814         ctl->dirty.bf.srt = 1;
815         return 0;
816 }
817
818 static int dai_srt_set_srcm(void *blk, unsigned int src)
819 {
820         struct dai_ctrl_blk *ctl = blk;
821
822         set_field(&ctl->srt, SRTCTL_SRCM, src);
823         ctl->dirty.bf.srt = 1;
824         return 0;
825 }
826
827 static int dai_srt_set_rsr(void *blk, unsigned int rsr)
828 {
829         struct dai_ctrl_blk *ctl = blk;
830
831         set_field(&ctl->srt, SRTCTL_RSR, rsr);
832         ctl->dirty.bf.srt = 1;
833         return 0;
834 }
835
836 static int dai_srt_set_drat(void *blk, unsigned int drat)
837 {
838         struct dai_ctrl_blk *ctl = blk;
839
840         set_field(&ctl->srt, SRTCTL_DRAT, drat);
841         ctl->dirty.bf.srt = 1;
842         return 0;
843 }
844
845 static int dai_srt_set_ec(void *blk, unsigned int ec)
846 {
847         struct dai_ctrl_blk *ctl = blk;
848
849         set_field(&ctl->srt, SRTCTL_EC, ec ? 1 : 0);
850         ctl->dirty.bf.srt = 1;
851         return 0;
852 }
853
854 static int dai_srt_set_et(void *blk, unsigned int et)
855 {
856         struct dai_ctrl_blk *ctl = blk;
857
858         set_field(&ctl->srt, SRTCTL_ET, et ? 1 : 0);
859         ctl->dirty.bf.srt = 1;
860         return 0;
861 }
862
863 static int dai_commit_write(struct hw *hw, unsigned int idx, void *blk)
864 {
865         struct dai_ctrl_blk *ctl = blk;
866
867         if (ctl->dirty.bf.srt) {
868                 hw_write_20kx(hw, AUDIO_IO_RX_SRT_CTL+0x40*idx, ctl->srt);
869                 ctl->dirty.bf.srt = 0;
870         }
871
872         return 0;
873 }
874
875 static int dai_get_ctrl_blk(void **rblk)
876 {
877         struct dai_ctrl_blk *blk;
878
879         *rblk = NULL;
880         blk = kzalloc(sizeof(*blk), GFP_KERNEL);
881         if (NULL == blk)
882                 return -ENOMEM;
883
884         *rblk = blk;
885
886         return 0;
887 }
888
889 static int dai_put_ctrl_blk(void *blk)
890 {
891         kfree((struct dai_ctrl_blk *)blk);
892
893         return 0;
894 }
895
896 static int dao_set_spos(void *blk, unsigned int spos)
897 {
898         ((struct dao_ctrl_blk *)blk)->atxcsl = spos;
899         ((struct dao_ctrl_blk *)blk)->dirty.bf.atxcsl = 1;
900         return 0;
901 }
902
903 static int dao_commit_write(struct hw *hw, unsigned int idx, void *blk)
904 {
905         struct dao_ctrl_blk *ctl = blk;
906
907         if (ctl->dirty.bf.atxcsl) {
908                 if (idx < 4) {
909                         /* S/PDIF SPOSx */
910                         hw_write_20kx(hw, AUDIO_IO_TX_CSTAT_L+0x40*idx,
911                                                         ctl->atxcsl);
912                 }
913                 ctl->dirty.bf.atxcsl = 0;
914         }
915
916         return 0;
917 }
918
919 static int dao_get_spos(void *blk, unsigned int *spos)
920 {
921         *spos = ((struct dao_ctrl_blk *)blk)->atxcsl;
922         return 0;
923 }
924
925 static int dao_get_ctrl_blk(void **rblk)
926 {
927         struct dao_ctrl_blk *blk;
928
929         *rblk = NULL;
930         blk = kzalloc(sizeof(*blk), GFP_KERNEL);
931         if (NULL == blk)
932                 return -ENOMEM;
933
934         *rblk = blk;
935
936         return 0;
937 }
938
939 static int dao_put_ctrl_blk(void *blk)
940 {
941         kfree((struct dao_ctrl_blk *)blk);
942
943         return 0;
944 }
945
946 static int daio_mgr_enb_dai(void *blk, unsigned int idx)
947 {
948         struct daio_mgr_ctrl_blk *ctl = blk;
949
950         set_field(&ctl->rxctl[idx], ARXCTL_EN, 1);
951         ctl->dirty.bf.arxctl |= (0x1 << idx);
952         return 0;
953 }
954
955 static int daio_mgr_dsb_dai(void *blk, unsigned int idx)
956 {
957         struct daio_mgr_ctrl_blk *ctl = blk;
958
959         set_field(&ctl->rxctl[idx], ARXCTL_EN, 0);
960
961         ctl->dirty.bf.arxctl |= (0x1 << idx);
962         return 0;
963 }
964
965 static int daio_mgr_enb_dao(void *blk, unsigned int idx)
966 {
967         struct daio_mgr_ctrl_blk *ctl = blk;
968
969         set_field(&ctl->txctl[idx], ATXCTL_EN, 1);
970         ctl->dirty.bf.atxctl |= (0x1 << idx);
971         return 0;
972 }
973
974 static int daio_mgr_dsb_dao(void *blk, unsigned int idx)
975 {
976         struct daio_mgr_ctrl_blk *ctl = blk;
977
978         set_field(&ctl->txctl[idx], ATXCTL_EN, 0);
979         ctl->dirty.bf.atxctl |= (0x1 << idx);
980         return 0;
981 }
982
983 static int daio_mgr_dao_init(void *blk, unsigned int idx, unsigned int conf)
984 {
985         struct daio_mgr_ctrl_blk *ctl = blk;
986
987         if (idx < 4) {
988                 /* S/PDIF output */
989                 switch ((conf & 0x7)) {
990                 case 1:
991                         set_field(&ctl->txctl[idx], ATXCTL_NUC, 0);
992                         break;
993                 case 2:
994                         set_field(&ctl->txctl[idx], ATXCTL_NUC, 1);
995                         break;
996                 case 4:
997                         set_field(&ctl->txctl[idx], ATXCTL_NUC, 2);
998                         break;
999                 case 8:
1000                         set_field(&ctl->txctl[idx], ATXCTL_NUC, 3);
1001                         break;
1002                 default:
1003                         break;
1004                 }
1005                 /* CDIF */
1006                 set_field(&ctl->txctl[idx], ATXCTL_CD, (!(conf & 0x7)));
1007                 /* Non-audio */
1008                 set_field(&ctl->txctl[idx], ATXCTL_LIV, (conf >> 4) & 0x1);
1009                 /* Non-audio */
1010                 set_field(&ctl->txctl[idx], ATXCTL_RIV, (conf >> 4) & 0x1);
1011                 set_field(&ctl->txctl[idx], ATXCTL_RAW,
1012                           ((conf >> 3) & 0x1) ? 0 : 0);
1013                 ctl->dirty.bf.atxctl |= (0x1 << idx);
1014         } else {
1015                 /* I2S output */
1016                 /*idx %= 4; */
1017         }
1018         return 0;
1019 }
1020
1021 static int daio_mgr_set_imaparc(void *blk, unsigned int slot)
1022 {
1023         struct daio_mgr_ctrl_blk *ctl = blk;
1024
1025         set_field(&ctl->daoimap.aim, AIM_ARC, slot);
1026         ctl->dirty.bf.daoimap = 1;
1027         return 0;
1028 }
1029
1030 static int daio_mgr_set_imapnxt(void *blk, unsigned int next)
1031 {
1032         struct daio_mgr_ctrl_blk *ctl = blk;
1033
1034         set_field(&ctl->daoimap.aim, AIM_NXT, next);
1035         ctl->dirty.bf.daoimap = 1;
1036         return 0;
1037 }
1038
1039 static int daio_mgr_set_imapaddr(void *blk, unsigned int addr)
1040 {
1041         ((struct daio_mgr_ctrl_blk *)blk)->daoimap.idx = addr;
1042         ((struct daio_mgr_ctrl_blk *)blk)->dirty.bf.daoimap = 1;
1043         return 0;
1044 }
1045
1046 static int daio_mgr_commit_write(struct hw *hw, void *blk)
1047 {
1048         struct daio_mgr_ctrl_blk *ctl = blk;
1049         unsigned int data = 0;
1050         int i = 0;
1051
1052         for (i = 0; i < 8; i++) {
1053                 if ((ctl->dirty.bf.atxctl & (0x1 << i))) {
1054                         data = ctl->txctl[i];
1055                         hw_write_20kx(hw, (AUDIO_IO_TX_CTL+(0x40*i)), data);
1056                         ctl->dirty.bf.atxctl &= ~(0x1 << i);
1057                         mdelay(1);
1058                 }
1059                 if ((ctl->dirty.bf.arxctl & (0x1 << i))) {
1060                         data = ctl->rxctl[i];
1061                         hw_write_20kx(hw, (AUDIO_IO_RX_CTL+(0x40*i)), data);
1062                         ctl->dirty.bf.arxctl &= ~(0x1 << i);
1063                         mdelay(1);
1064                 }
1065         }
1066         if (ctl->dirty.bf.daoimap) {
1067                 hw_write_20kx(hw, AUDIO_IO_AIM+ctl->daoimap.idx*4,
1068                                                 ctl->daoimap.aim);
1069                 ctl->dirty.bf.daoimap = 0;
1070         }
1071
1072         return 0;
1073 }
1074
1075 static int daio_mgr_get_ctrl_blk(struct hw *hw, void **rblk)
1076 {
1077         struct daio_mgr_ctrl_blk *blk;
1078         int i = 0;
1079
1080         *rblk = NULL;
1081         blk = kzalloc(sizeof(*blk), GFP_KERNEL);
1082         if (NULL == blk)
1083                 return -ENOMEM;
1084
1085         for (i = 0; i < 8; i++) {
1086                 blk->txctl[i] = hw_read_20kx(hw, AUDIO_IO_TX_CTL+(0x40*i));
1087                 blk->rxctl[i] = hw_read_20kx(hw, AUDIO_IO_RX_CTL+(0x40*i));
1088         }
1089
1090         *rblk = blk;
1091
1092         return 0;
1093 }
1094
1095 static int daio_mgr_put_ctrl_blk(void *blk)
1096 {
1097         kfree((struct daio_mgr_ctrl_blk *)blk);
1098
1099         return 0;
1100 }
1101
1102 /* Card hardware initialization block */
1103 struct dac_conf {
1104         unsigned int msr; /* master sample rate in rsrs */
1105 };
1106
1107 struct adc_conf {
1108         unsigned int msr;       /* master sample rate in rsrs */
1109         unsigned char input;    /* the input source of ADC */
1110         unsigned char mic20db;  /* boost mic by 20db if input is microphone */
1111 };
1112
1113 struct daio_conf {
1114         unsigned int msr; /* master sample rate in rsrs */
1115 };
1116
1117 struct trn_conf {
1118         unsigned long vm_pgt_phys;
1119 };
1120
1121 static int hw_daio_init(struct hw *hw, const struct daio_conf *info)
1122 {
1123         u32 dwData = 0;
1124         int i;
1125
1126         /* Program I2S with proper sample rate and enable the correct I2S
1127          * channel. ED(0/8/16/24): Enable all I2S/I2X master clock output */
1128         if (1 == info->msr) {
1129                 hw_write_20kx(hw, AUDIO_IO_MCLK, 0x01010101);
1130                 hw_write_20kx(hw, AUDIO_IO_TX_BLRCLK, 0x01010101);
1131                 hw_write_20kx(hw, AUDIO_IO_RX_BLRCLK, 0);
1132         } else if (2 == info->msr) {
1133                 hw_write_20kx(hw, AUDIO_IO_MCLK, 0x11111111);
1134                 /* Specify all playing 96khz
1135                  * EA [0]       - Enabled
1136                  * RTA [4:5]    - 96kHz
1137                  * EB [8]       - Enabled
1138                  * RTB [12:13]  - 96kHz
1139                  * EC [16]      - Enabled
1140                  * RTC [20:21]  - 96kHz
1141                  * ED [24]      - Enabled
1142                  * RTD [28:29]  - 96kHz */
1143                 hw_write_20kx(hw, AUDIO_IO_TX_BLRCLK, 0x11111111);
1144                 hw_write_20kx(hw, AUDIO_IO_RX_BLRCLK, 0);
1145         } else {
1146                 printk(KERN_ALERT "ERROR!!! Invalid sampling rate!!!\n");
1147                 return -EINVAL;
1148         }
1149
1150         for (i = 0; i < 8; i++) {
1151                 if (i <= 3) {
1152                         /* 1st 3 channels are SPDIFs (SB0960) */
1153                         if (i == 3)
1154                                 dwData = 0x1001001;
1155                         else
1156                                 dwData = 0x1000001;
1157
1158                         hw_write_20kx(hw, (AUDIO_IO_TX_CTL+(0x40*i)), dwData);
1159                         hw_write_20kx(hw, (AUDIO_IO_RX_CTL+(0x40*i)), dwData);
1160
1161                         /* Initialize the SPDIF Out Channel status registers.
1162                          * The value specified here is based on the typical
1163                          * values provided in the specification, namely: Clock
1164                          * Accuracy of 1000ppm, Sample Rate of 48KHz,
1165                          * unspecified source number, Generation status = 1,
1166                          * Category code = 0x12 (Digital Signal Mixer),
1167                          * Mode = 0, Emph = 0, Copy Permitted, AN = 0
1168                          * (indicating that we're transmitting digital audio,
1169                          * and the Professional Use bit is 0. */
1170
1171                         hw_write_20kx(hw, AUDIO_IO_TX_CSTAT_L+(0x40*i),
1172                                         0x02109204); /* Default to 48kHz */
1173
1174                         hw_write_20kx(hw, AUDIO_IO_TX_CSTAT_H+(0x40*i), 0x0B);
1175                 } else {
1176                         /* Next 5 channels are I2S (SB0960) */
1177                         dwData = 0x11;
1178                         hw_write_20kx(hw, AUDIO_IO_RX_CTL+(0x40*i), dwData);
1179                         if (2 == info->msr) {
1180                                 /* Four channels per sample period */
1181                                 dwData |= 0x1000;
1182                         }
1183                         hw_write_20kx(hw, AUDIO_IO_TX_CTL+(0x40*i), dwData);
1184                 }
1185         }
1186
1187         return 0;
1188 }
1189
1190 /* TRANSPORT operations */
1191 static int hw_trn_init(struct hw *hw, const struct trn_conf *info)
1192 {
1193         u32 vmctl = 0, data = 0;
1194         unsigned long ptp_phys_low = 0, ptp_phys_high = 0;
1195         int i = 0;
1196
1197         /* Set up device page table */
1198         if ((~0UL) == info->vm_pgt_phys) {
1199                 printk(KERN_ALERT "Wrong device page table page address!!!\n");
1200                 return -1;
1201         }
1202
1203         vmctl = 0x80000C0F;  /* 32-bit, 4k-size page */
1204 #if BITS_PER_LONG == 64
1205         ptp_phys_low = info->vm_pgt_phys & ((1UL<<32)-1);
1206         ptp_phys_high = (info->vm_pgt_phys>>32) & ((1UL<<32)-1);
1207         vmctl |= (3<<8);
1208 #elif BITS_PER_LONG == 32
1209         ptp_phys_low = info->vm_pgt_phys & (~0UL);
1210         ptp_phys_high = 0;
1211 #else
1212 #       error "Unknown BITS_PER_LONG!"
1213 #endif
1214 #if PAGE_SIZE == 8192
1215 #       error "Don't support 8k-page!"
1216 #endif
1217         /* Write page table physical address to all PTPAL registers */
1218         for (i = 0; i < 64; i++) {
1219                 hw_write_20kx(hw, VMEM_PTPAL+(16*i), ptp_phys_low);
1220                 hw_write_20kx(hw, VMEM_PTPAH+(16*i), ptp_phys_high);
1221         }
1222         /* Enable virtual memory transfer */
1223         hw_write_20kx(hw, VMEM_CTL, vmctl);
1224         /* Enable transport bus master and queueing of request */
1225         hw_write_20kx(hw, TRANSPORT_CTL, 0x03);
1226         hw_write_20kx(hw, TRANSPORT_INT, 0x200c01);
1227         /* Enable transport ring */
1228         data = hw_read_20kx(hw, TRANSPORT_ENB);
1229         hw_write_20kx(hw, TRANSPORT_ENB, (data | 0x03));
1230
1231         return 0;
1232 }
1233
1234 /* Card initialization */
1235 #define GCTL_AIE        0x00000001
1236 #define GCTL_UAA        0x00000002
1237 #define GCTL_DPC        0x00000004
1238 #define GCTL_DBP        0x00000008
1239 #define GCTL_ABP        0x00000010
1240 #define GCTL_TBP        0x00000020
1241 #define GCTL_SBP        0x00000040
1242 #define GCTL_FBP        0x00000080
1243 #define GCTL_ME         0x00000100
1244 #define GCTL_AID        0x00001000
1245
1246 #define PLLCTL_SRC      0x00000007
1247 #define PLLCTL_SPE      0x00000008
1248 #define PLLCTL_RD       0x000000F0
1249 #define PLLCTL_FD       0x0001FF00
1250 #define PLLCTL_OD       0x00060000
1251 #define PLLCTL_B        0x00080000
1252 #define PLLCTL_AS       0x00100000
1253 #define PLLCTL_LF       0x03E00000
1254 #define PLLCTL_SPS      0x1C000000
1255 #define PLLCTL_AD       0x60000000
1256
1257 #define PLLSTAT_CCS     0x00000007
1258 #define PLLSTAT_SPL     0x00000008
1259 #define PLLSTAT_CRD     0x000000F0
1260 #define PLLSTAT_CFD     0x0001FF00
1261 #define PLLSTAT_SL      0x00020000
1262 #define PLLSTAT_FAS     0x00040000
1263 #define PLLSTAT_B       0x00080000
1264 #define PLLSTAT_PD      0x00100000
1265 #define PLLSTAT_OCA     0x00200000
1266 #define PLLSTAT_NCA     0x00400000
1267
1268 static int hw_pll_init(struct hw *hw, unsigned int rsr)
1269 {
1270         unsigned int pllenb;
1271         unsigned int pllctl;
1272         unsigned int pllstat;
1273         int i;
1274
1275         pllenb = 0xB;
1276         hw_write_20kx(hw, PLL_ENB, pllenb);
1277         pllctl = 0x20D00000;
1278         set_field(&pllctl, PLLCTL_FD, 16 - 4);
1279         hw_write_20kx(hw, PLL_CTL, pllctl);
1280         mdelay(40);
1281         pllctl = hw_read_20kx(hw, PLL_CTL);
1282         set_field(&pllctl, PLLCTL_B, 0);
1283         if (48000 == rsr) {
1284                 set_field(&pllctl, PLLCTL_FD, 16 - 2);
1285                 set_field(&pllctl, PLLCTL_RD, 1 - 1);
1286         } else { /* 44100 */
1287                 set_field(&pllctl, PLLCTL_FD, 147 - 2);
1288                 set_field(&pllctl, PLLCTL_RD, 10 - 1);
1289         }
1290         hw_write_20kx(hw, PLL_CTL, pllctl);
1291         mdelay(40);
1292         for (i = 0; i < 1000; i++) {
1293                 pllstat = hw_read_20kx(hw, PLL_STAT);
1294                 if (get_field(pllstat, PLLSTAT_PD))
1295                         continue;
1296
1297                 if (get_field(pllstat, PLLSTAT_B) !=
1298                                         get_field(pllctl, PLLCTL_B))
1299                         continue;
1300
1301                 if (get_field(pllstat, PLLSTAT_CCS) !=
1302                                         get_field(pllctl, PLLCTL_SRC))
1303                         continue;
1304
1305                 if (get_field(pllstat, PLLSTAT_CRD) !=
1306                                         get_field(pllctl, PLLCTL_RD))
1307                         continue;
1308
1309                 if (get_field(pllstat, PLLSTAT_CFD) !=
1310                                         get_field(pllctl, PLLCTL_FD))
1311                         continue;
1312
1313                 break;
1314         }
1315         if (i >= 1000) {
1316                 printk(KERN_ALERT "PLL initialization failed!!!\n");
1317                 return -EBUSY;
1318         }
1319
1320         return 0;
1321 }
1322
1323 static int hw_auto_init(struct hw *hw)
1324 {
1325         unsigned int gctl;
1326         int i;
1327
1328         gctl = hw_read_20kx(hw, GLOBAL_CNTL_GCTL);
1329         set_field(&gctl, GCTL_AIE, 0);
1330         hw_write_20kx(hw, GLOBAL_CNTL_GCTL, gctl);
1331         set_field(&gctl, GCTL_AIE, 1);
1332         hw_write_20kx(hw, GLOBAL_CNTL_GCTL, gctl);
1333         mdelay(10);
1334         for (i = 0; i < 400000; i++) {
1335                 gctl = hw_read_20kx(hw, GLOBAL_CNTL_GCTL);
1336                 if (get_field(gctl, GCTL_AID))
1337                         break;
1338         }
1339         if (!get_field(gctl, GCTL_AID)) {
1340                 printk(KERN_ALERT "Card Auto-init failed!!!\n");
1341                 return -EBUSY;
1342         }
1343
1344         return 0;
1345 }
1346
1347 /* DAC operations */
1348
1349 #define CS4382_MC1              0x1
1350 #define CS4382_MC2              0x2
1351 #define CS4382_MC3              0x3
1352 #define CS4382_FC               0x4
1353 #define CS4382_IC               0x5
1354 #define CS4382_XC1              0x6
1355 #define CS4382_VCA1             0x7
1356 #define CS4382_VCB1             0x8
1357 #define CS4382_XC2              0x9
1358 #define CS4382_VCA2             0xA
1359 #define CS4382_VCB2             0xB
1360 #define CS4382_XC3              0xC
1361 #define CS4382_VCA3             0xD
1362 #define CS4382_VCB3             0xE
1363 #define CS4382_XC4              0xF
1364 #define CS4382_VCA4             0x10
1365 #define CS4382_VCB4             0x11
1366 #define CS4382_CREV             0x12
1367
1368 /* I2C status */
1369 #define STATE_LOCKED            0x00
1370 #define STATE_UNLOCKED          0xAA
1371 #define DATA_READY              0x800000    /* Used with I2C_IF_STATUS */
1372 #define DATA_ABORT              0x10000     /* Used with I2C_IF_STATUS */
1373
1374 #define I2C_STATUS_DCM  0x00000001
1375 #define I2C_STATUS_BC   0x00000006
1376 #define I2C_STATUS_APD  0x00000008
1377 #define I2C_STATUS_AB   0x00010000
1378 #define I2C_STATUS_DR   0x00800000
1379
1380 #define I2C_ADDRESS_PTAD        0x0000FFFF
1381 #define I2C_ADDRESS_SLAD        0x007F0000
1382
1383 struct REGS_CS4382 {
1384         u32 dwModeControl_1;
1385         u32 dwModeControl_2;
1386         u32 dwModeControl_3;
1387
1388         u32 dwFilterControl;
1389         u32 dwInvertControl;
1390
1391         u32 dwMixControl_P1;
1392         u32 dwVolControl_A1;
1393         u32 dwVolControl_B1;
1394
1395         u32 dwMixControl_P2;
1396         u32 dwVolControl_A2;
1397         u32 dwVolControl_B2;
1398
1399         u32 dwMixControl_P3;
1400         u32 dwVolControl_A3;
1401         u32 dwVolControl_B3;
1402
1403         u32 dwMixControl_P4;
1404         u32 dwVolControl_A4;
1405         u32 dwVolControl_B4;
1406 };
1407
1408 static u8 m_bAddressSize, m_bDataSize, m_bDeviceID;
1409
1410 static int I2CUnlockFullAccess(struct hw *hw)
1411 {
1412         u8 UnlockKeySequence_FLASH_FULLACCESS_MODE[2] =  {0xB3, 0xD4};
1413
1414         /* Send keys for forced BIOS mode */
1415         hw_write_20kx(hw, I2C_IF_WLOCK,
1416                         UnlockKeySequence_FLASH_FULLACCESS_MODE[0]);
1417         hw_write_20kx(hw, I2C_IF_WLOCK,
1418                         UnlockKeySequence_FLASH_FULLACCESS_MODE[1]);
1419         /* Check whether the chip is unlocked */
1420         if (hw_read_20kx(hw, I2C_IF_WLOCK) == STATE_UNLOCKED)
1421                 return 0;
1422
1423         return -1;
1424 }
1425
1426 static int I2CLockChip(struct hw *hw)
1427 {
1428         /* Write twice */
1429         hw_write_20kx(hw, I2C_IF_WLOCK, STATE_LOCKED);
1430         hw_write_20kx(hw, I2C_IF_WLOCK, STATE_LOCKED);
1431         if (hw_read_20kx(hw, I2C_IF_WLOCK) == STATE_LOCKED)
1432                 return 0;
1433
1434         return -1;
1435 }
1436
1437 static int I2CInit(struct hw *hw, u8 bDeviceID, u8 bAddressSize, u8 bDataSize)
1438 {
1439         int err = 0;
1440         unsigned int RegI2CStatus;
1441         unsigned int RegI2CAddress;
1442
1443         err = I2CUnlockFullAccess(hw);
1444         if (err < 0)
1445                 return err;
1446
1447         m_bAddressSize = bAddressSize;
1448         m_bDataSize = bDataSize;
1449         m_bDeviceID = bDeviceID;
1450
1451         RegI2CAddress = 0;
1452         set_field(&RegI2CAddress, I2C_ADDRESS_SLAD, bDeviceID);
1453
1454         hw_write_20kx(hw, I2C_IF_ADDRESS, RegI2CAddress);
1455
1456         RegI2CStatus = hw_read_20kx(hw, I2C_IF_STATUS);
1457
1458         set_field(&RegI2CStatus, I2C_STATUS_DCM, 1); /* Direct control mode */
1459
1460         hw_write_20kx(hw, I2C_IF_STATUS, RegI2CStatus);
1461
1462         return 0;
1463 }
1464
1465 static int I2CUninit(struct hw *hw)
1466 {
1467         unsigned int RegI2CStatus;
1468         unsigned int RegI2CAddress;
1469
1470         RegI2CAddress = 0;
1471         set_field(&RegI2CAddress, I2C_ADDRESS_SLAD, 0x57); /* I2C id */
1472
1473         hw_write_20kx(hw, I2C_IF_ADDRESS, RegI2CAddress);
1474
1475         RegI2CStatus = hw_read_20kx(hw, I2C_IF_STATUS);
1476
1477         set_field(&RegI2CStatus, I2C_STATUS_DCM, 0); /* I2C mode */
1478
1479         hw_write_20kx(hw, I2C_IF_STATUS, RegI2CStatus);
1480
1481         return I2CLockChip(hw);
1482 }
1483
1484 static int I2CWaitDataReady(struct hw *hw)
1485 {
1486         int i = 0x400000;
1487         unsigned int ret = 0;
1488
1489         do {
1490                 ret = hw_read_20kx(hw, I2C_IF_STATUS);
1491         } while ((!(ret & DATA_READY)) && --i);
1492
1493         return i;
1494 }
1495
1496 static int I2CRead(struct hw *hw, u16 wAddress, u32 *pdwData)
1497 {
1498         unsigned int RegI2CStatus;
1499
1500         RegI2CStatus = hw_read_20kx(hw, I2C_IF_STATUS);
1501         set_field(&RegI2CStatus, I2C_STATUS_BC,
1502                         (4 == m_bAddressSize) ? 0 : m_bAddressSize);
1503         hw_write_20kx(hw, I2C_IF_STATUS, RegI2CStatus);
1504         if (!I2CWaitDataReady(hw))
1505                 return -1;
1506
1507         hw_write_20kx(hw, I2C_IF_WDATA, (u32)wAddress);
1508         if (!I2CWaitDataReady(hw))
1509                 return -1;
1510
1511         /* Force a read operation */
1512         hw_write_20kx(hw, I2C_IF_RDATA, 0);
1513         if (!I2CWaitDataReady(hw))
1514                 return -1;
1515
1516         *pdwData = hw_read_20kx(hw, I2C_IF_RDATA);
1517
1518         return 0;
1519 }
1520
1521 static int I2CWrite(struct hw *hw, u16 wAddress, u32 dwData)
1522 {
1523         unsigned int dwI2CData = (dwData << (m_bAddressSize * 8)) | wAddress;
1524         unsigned int RegI2CStatus;
1525
1526         RegI2CStatus = hw_read_20kx(hw, I2C_IF_STATUS);
1527
1528         set_field(&RegI2CStatus, I2C_STATUS_BC,
1529                   (4 == (m_bAddressSize + m_bDataSize)) ?
1530                   0 : (m_bAddressSize + m_bDataSize));
1531
1532         hw_write_20kx(hw, I2C_IF_STATUS, RegI2CStatus);
1533         I2CWaitDataReady(hw);
1534         /* Dummy write to trigger the write oprtation */
1535         hw_write_20kx(hw, I2C_IF_WDATA, 0);
1536         I2CWaitDataReady(hw);
1537
1538         /* This is the real data */
1539         hw_write_20kx(hw, I2C_IF_WDATA, dwI2CData);
1540         I2CWaitDataReady(hw);
1541
1542         return 0;
1543 }
1544
1545 static int hw_dac_init(struct hw *hw, const struct dac_conf *info)
1546 {
1547         int err = 0;
1548         u32 dwData = 0;
1549         int i = 0;
1550         struct REGS_CS4382 cs4382_Read = {0};
1551         struct REGS_CS4382 cs4382_Def = {
1552                                    0x00000001,  /* Mode Control 1 */
1553                                    0x00000000,  /* Mode Control 2 */
1554                                    0x00000084,  /* Mode Control 3 */
1555                                    0x00000000,  /* Filter Control */
1556                                    0x00000000,  /* Invert Control */
1557                                    0x00000024,  /* Mixing Control Pair 1 */
1558                                    0x00000000,  /* Vol Control A1 */
1559                                    0x00000000,  /* Vol Control B1 */
1560                                    0x00000024,  /* Mixing Control Pair 2 */
1561                                    0x00000000,  /* Vol Control A2 */
1562                                    0x00000000,  /* Vol Control B2 */
1563                                    0x00000024,  /* Mixing Control Pair 3 */
1564                                    0x00000000,  /* Vol Control A3 */
1565                                    0x00000000,  /* Vol Control B3 */
1566                                    0x00000024,  /* Mixing Control Pair 4 */
1567                                    0x00000000,  /* Vol Control A4 */
1568                                    0x00000000   /* Vol Control B4 */
1569                                  };
1570
1571         /* Set DAC reset bit as output */
1572         dwData = hw_read_20kx(hw, GPIO_CTRL);
1573         dwData |= 0x02;
1574         hw_write_20kx(hw, GPIO_CTRL, dwData);
1575
1576         err = I2CInit(hw, 0x18, 1, 1);
1577         if (err < 0)
1578                 goto End;
1579
1580         for (i = 0; i < 2; i++) {
1581                 /* Reset DAC twice just in-case the chip
1582                  * didn't initialized properly */
1583                 dwData = hw_read_20kx(hw, GPIO_DATA);
1584                 /* GPIO data bit 1 */
1585                 dwData &= 0xFFFFFFFD;
1586                 hw_write_20kx(hw, GPIO_DATA, dwData);
1587                 mdelay(10);
1588                 dwData |= 0x2;
1589                 hw_write_20kx(hw, GPIO_DATA, dwData);
1590                 mdelay(50);
1591
1592                 /* Reset the 2nd time */
1593                 dwData &= 0xFFFFFFFD;
1594                 hw_write_20kx(hw, GPIO_DATA, dwData);
1595                 mdelay(10);
1596                 dwData |= 0x2;
1597                 hw_write_20kx(hw, GPIO_DATA, dwData);
1598                 mdelay(50);
1599
1600                 if (I2CRead(hw, CS4382_MC1,  &cs4382_Read.dwModeControl_1))
1601                         continue;
1602
1603                 if (I2CRead(hw, CS4382_MC2,  &cs4382_Read.dwModeControl_2))
1604                         continue;
1605
1606                 if (I2CRead(hw, CS4382_MC3,  &cs4382_Read.dwModeControl_3))
1607                         continue;
1608
1609                 if (I2CRead(hw, CS4382_FC,   &cs4382_Read.dwFilterControl))
1610                         continue;
1611
1612                 if (I2CRead(hw, CS4382_IC,   &cs4382_Read.dwInvertControl))
1613                         continue;
1614
1615                 if (I2CRead(hw, CS4382_XC1,  &cs4382_Read.dwMixControl_P1))
1616                         continue;
1617
1618                 if (I2CRead(hw, CS4382_VCA1, &cs4382_Read.dwVolControl_A1))
1619                         continue;
1620
1621                 if (I2CRead(hw, CS4382_VCB1, &cs4382_Read.dwVolControl_B1))
1622                         continue;
1623
1624                 if (I2CRead(hw, CS4382_XC2,  &cs4382_Read.dwMixControl_P2))
1625                         continue;
1626
1627                 if (I2CRead(hw, CS4382_VCA2, &cs4382_Read.dwVolControl_A2))
1628                         continue;
1629
1630                 if (I2CRead(hw, CS4382_VCB2, &cs4382_Read.dwVolControl_B2))
1631                         continue;
1632
1633                 if (I2CRead(hw, CS4382_XC3,  &cs4382_Read.dwMixControl_P3))
1634                         continue;
1635
1636                 if (I2CRead(hw, CS4382_VCA3, &cs4382_Read.dwVolControl_A3))
1637                         continue;
1638
1639                 if (I2CRead(hw, CS4382_VCB3, &cs4382_Read.dwVolControl_B3))
1640                         continue;
1641
1642                 if (I2CRead(hw, CS4382_XC4,  &cs4382_Read.dwMixControl_P4))
1643                         continue;
1644
1645                 if (I2CRead(hw, CS4382_VCA4, &cs4382_Read.dwVolControl_A4))
1646                         continue;
1647
1648                 if (I2CRead(hw, CS4382_VCB4, &cs4382_Read.dwVolControl_B4))
1649                         continue;
1650
1651                 if (memcmp(&cs4382_Read, &cs4382_Def,
1652                                                 sizeof(struct REGS_CS4382)))
1653                         continue;
1654                 else
1655                         break;
1656         }
1657
1658         if (i >= 2)
1659                 goto End;
1660
1661         /* Note: Every I2C write must have some delay.
1662          * This is not a requirement but the delay works here... */
1663         I2CWrite(hw, CS4382_MC1, 0x80);
1664         I2CWrite(hw, CS4382_MC2, 0x10);
1665         if (1 == info->msr) {
1666                 I2CWrite(hw, CS4382_XC1, 0x24);
1667                 I2CWrite(hw, CS4382_XC2, 0x24);
1668                 I2CWrite(hw, CS4382_XC3, 0x24);
1669                 I2CWrite(hw, CS4382_XC4, 0x24);
1670         } else if (2 == info->msr) {
1671                 I2CWrite(hw, CS4382_XC1, 0x25);
1672                 I2CWrite(hw, CS4382_XC2, 0x25);
1673                 I2CWrite(hw, CS4382_XC3, 0x25);
1674                 I2CWrite(hw, CS4382_XC4, 0x25);
1675         } else {
1676                 I2CWrite(hw, CS4382_XC1, 0x26);
1677                 I2CWrite(hw, CS4382_XC2, 0x26);
1678                 I2CWrite(hw, CS4382_XC3, 0x26);
1679                 I2CWrite(hw, CS4382_XC4, 0x26);
1680         }
1681
1682         return 0;
1683 End:
1684
1685         I2CUninit(hw);
1686         return -1;
1687 }
1688
1689 /* ADC operations */
1690 #define MAKE_WM8775_ADDR(addr, data)    (u32)(((addr<<1)&0xFE)|((data>>8)&0x1))
1691 #define MAKE_WM8775_DATA(data)  (u32)(data&0xFF)
1692
1693 #define WM8775_IC       0x0B
1694 #define WM8775_MMC      0x0C
1695 #define WM8775_AADCL    0x0E
1696 #define WM8775_AADCR    0x0F
1697 #define WM8775_ADCMC    0x15
1698 #define WM8775_RESET    0x17
1699
1700 static int hw_is_adc_input_selected(struct hw *hw, enum ADCSRC type)
1701 {
1702         u32 data = 0;
1703
1704         data = hw_read_20kx(hw, GPIO_DATA);
1705         switch (type) {
1706         case ADC_MICIN:
1707                 data = (data & (0x1 << 14)) ? 1 : 0;
1708                 break;
1709         case ADC_LINEIN:
1710                 data = (data & (0x1 << 14)) ? 0 : 1;
1711                 break;
1712         default:
1713                 data = 0;
1714         }
1715         return data;
1716 }
1717
1718 static int hw_adc_input_select(struct hw *hw, enum ADCSRC type)
1719 {
1720         u32 data = 0;
1721
1722         data = hw_read_20kx(hw, GPIO_DATA);
1723         switch (type) {
1724         case ADC_MICIN:
1725                 data |= (0x1 << 14);
1726                 hw_write_20kx(hw, GPIO_DATA, data);
1727                 I2CWrite(hw, MAKE_WM8775_ADDR(WM8775_ADCMC, 0x101),
1728                                 MAKE_WM8775_DATA(0x101)); /* Mic-in */
1729                 I2CWrite(hw, MAKE_WM8775_ADDR(WM8775_AADCL, 0xE7),
1730                                 MAKE_WM8775_DATA(0xE7)); /* +12dB boost */
1731                 I2CWrite(hw, MAKE_WM8775_ADDR(WM8775_AADCR, 0xE7),
1732                                 MAKE_WM8775_DATA(0xE7)); /* +12dB boost */
1733                 break;
1734         case ADC_LINEIN:
1735                 data &= ~(0x1 << 14);
1736                 hw_write_20kx(hw, GPIO_DATA, data);
1737                 I2CWrite(hw, MAKE_WM8775_ADDR(WM8775_ADCMC, 0x102),
1738                                 MAKE_WM8775_DATA(0x102)); /* Line-in */
1739                 I2CWrite(hw, MAKE_WM8775_ADDR(WM8775_AADCL, 0xCF),
1740                                 MAKE_WM8775_DATA(0xCF)); /* No boost */
1741                 I2CWrite(hw, MAKE_WM8775_ADDR(WM8775_AADCR, 0xCF),
1742                                 MAKE_WM8775_DATA(0xCF)); /* No boost */
1743                 break;
1744         default:
1745                 break;
1746         }
1747
1748         return 0;
1749 }
1750
1751 static int hw_adc_init(struct hw *hw, const struct adc_conf *info)
1752 {
1753         int err = 0;
1754         u32 dwMux = 2, dwData = 0, dwCtl = 0;
1755
1756         /*  Set ADC reset bit as output */
1757         dwData = hw_read_20kx(hw, GPIO_CTRL);
1758         dwData |= (0x1 << 15);
1759         hw_write_20kx(hw, GPIO_CTRL, dwData);
1760
1761         /* Initialize I2C */
1762         err = I2CInit(hw, 0x1A, 1, 1);
1763         if (err < 0) {
1764                 printk(KERN_ALERT "Failure to acquire I2C!!!\n");
1765                 goto error;
1766         }
1767
1768         /* Make ADC in normal operation */
1769         dwData = hw_read_20kx(hw, GPIO_DATA);
1770         dwData &= ~(0x1 << 15);
1771         mdelay(10);
1772         dwData |= (0x1 << 15);
1773         hw_write_20kx(hw, GPIO_DATA, dwData);
1774         mdelay(50);
1775
1776         /* Set the master mode (256fs) */
1777         if (1 == info->msr) {
1778                 I2CWrite(hw, MAKE_WM8775_ADDR(WM8775_MMC, 0x02),
1779                                                 MAKE_WM8775_DATA(0x02));
1780         } else if (2 == info->msr) {
1781                 I2CWrite(hw, MAKE_WM8775_ADDR(WM8775_MMC, 0x0A),
1782                                                 MAKE_WM8775_DATA(0x0A));
1783         } else {
1784                 printk(KERN_ALERT "Invalid master sampling "
1785                                   "rate (msr %d)!!!\n", info->msr);
1786                 err = -EINVAL;
1787                 goto error;
1788         }
1789
1790         /* Configure GPIO bit 14 change to line-in/mic-in */
1791         dwCtl = hw_read_20kx(hw, GPIO_CTRL);
1792         dwCtl |= 0x1<<14;
1793         hw_write_20kx(hw, GPIO_CTRL, dwCtl);
1794
1795         /* Check using Mic-in or Line-in */
1796         dwData = hw_read_20kx(hw, GPIO_DATA);
1797
1798         if (dwMux == 1) {
1799                 /* Configures GPIO data to select Mic-in */
1800                 dwData |= 0x1<<14;
1801                 hw_write_20kx(hw, GPIO_DATA, dwData);
1802
1803                 I2CWrite(hw, MAKE_WM8775_ADDR(WM8775_ADCMC, 0x101),
1804                                 MAKE_WM8775_DATA(0x101)); /* Mic-in */
1805                 I2CWrite(hw, MAKE_WM8775_ADDR(WM8775_AADCL, 0xE7),
1806                                 MAKE_WM8775_DATA(0xE7)); /* +12dB boost */
1807                 I2CWrite(hw, MAKE_WM8775_ADDR(WM8775_AADCR, 0xE7),
1808                                 MAKE_WM8775_DATA(0xE7)); /* +12dB boost */
1809         } else if (dwMux == 2) {
1810                 /* Configures GPIO data to select Line-in */
1811                 dwData &= ~(0x1<<14);
1812                 hw_write_20kx(hw, GPIO_DATA, dwData);
1813
1814                 /* Setup ADC */
1815                 I2CWrite(hw, MAKE_WM8775_ADDR(WM8775_ADCMC, 0x102),
1816                                 MAKE_WM8775_DATA(0x102)); /* Line-in */
1817                 I2CWrite(hw, MAKE_WM8775_ADDR(WM8775_AADCL, 0xCF),
1818                                 MAKE_WM8775_DATA(0xCF)); /* No boost */
1819                 I2CWrite(hw, MAKE_WM8775_ADDR(WM8775_AADCR, 0xCF),
1820                                 MAKE_WM8775_DATA(0xCF)); /* No boost */
1821         } else {
1822                 printk(KERN_ALERT "ERROR!!! Invalid input mux!!!\n");
1823                 err = -EINVAL;
1824                 goto error;
1825         }
1826
1827         return 0;
1828
1829 error:
1830         I2CUninit(hw);
1831         return err;
1832 }
1833
1834 static int hw_have_digit_io_switch(struct hw *hw)
1835 {
1836         return 0;
1837 }
1838
1839 static int hw_card_start(struct hw *hw)
1840 {
1841         int err = 0;
1842         struct pci_dev *pci = hw->pci;
1843         unsigned int gctl;
1844         unsigned int dma_mask = 0;
1845
1846         err = pci_enable_device(pci);
1847         if (err < 0)
1848                 return err;
1849
1850         /* Set DMA transfer mask */
1851         dma_mask = CT_XFI_DMA_MASK;
1852         if (pci_set_dma_mask(pci, dma_mask) < 0 ||
1853             pci_set_consistent_dma_mask(pci, dma_mask) < 0) {
1854                 printk(KERN_ERR "architecture does not support PCI "
1855                 "busmaster DMA with mask 0x%x\n", dma_mask);
1856                 err = -ENXIO;
1857                 goto error1;
1858         }
1859
1860         err = pci_request_regions(pci, "XFi");
1861         if (err < 0)
1862                 goto error1;
1863
1864         hw->io_base = pci_resource_start(hw->pci, 2);
1865         hw->mem_base = (unsigned long)ioremap(hw->io_base,
1866                                         pci_resource_len(hw->pci, 2));
1867         if (NULL == (void *)hw->mem_base) {
1868                 err = -ENOENT;
1869                 goto error2;
1870         }
1871
1872         /* Switch to 20k2 mode from UAA mode. */
1873         gctl = hw_read_20kx(hw, GLOBAL_CNTL_GCTL);
1874         set_field(&gctl, GCTL_UAA, 0);
1875         hw_write_20kx(hw, GLOBAL_CNTL_GCTL, gctl);
1876
1877         /*if ((err = request_irq(pci->irq, ct_atc_interrupt, IRQF_SHARED,
1878                                 atc->chip_details->nm_card, hw))) {
1879                 goto error3;
1880         }
1881         hw->irq = pci->irq;
1882         */
1883
1884         pci_set_master(pci);
1885
1886         return 0;
1887
1888 /*error3:
1889         iounmap((void *)hw->mem_base);
1890         hw->mem_base = (unsigned long)NULL;*/
1891 error2:
1892         pci_release_regions(pci);
1893         hw->io_base = 0;
1894 error1:
1895         pci_disable_device(pci);
1896         return err;
1897 }
1898
1899 static int hw_card_stop(struct hw *hw)
1900 {
1901         /* TODO: Disable interrupt and so on... */
1902         return 0;
1903 }
1904
1905 static int hw_card_shutdown(struct hw *hw)
1906 {
1907         if (hw->irq >= 0)
1908                 free_irq(hw->irq, hw);
1909
1910         hw->irq = -1;
1911
1912         if (NULL != ((void *)hw->mem_base))
1913                 iounmap((void *)hw->mem_base);
1914
1915         hw->mem_base = (unsigned long)NULL;
1916
1917         if (hw->io_base)
1918                 pci_release_regions(hw->pci);
1919
1920         hw->io_base = 0;
1921
1922         pci_disable_device(hw->pci);
1923
1924         return 0;
1925 }
1926
1927 static int hw_card_init(struct hw *hw, struct card_conf *info)
1928 {
1929         int err;
1930         unsigned int gctl;
1931         u32 data = 0;
1932         struct dac_conf dac_info = {0};
1933         struct adc_conf adc_info = {0};
1934         struct daio_conf daio_info = {0};
1935         struct trn_conf trn_info = {0};
1936
1937         /* Get PCI io port/memory base address and
1938          * do 20kx core switch if needed. */
1939         if (!hw->io_base) {
1940                 err = hw_card_start(hw);
1941                 if (err)
1942                         return err;
1943         }
1944
1945         /* PLL init */
1946         err = hw_pll_init(hw, info->rsr);
1947         if (err < 0)
1948                 return err;
1949
1950         /* kick off auto-init */
1951         err = hw_auto_init(hw);
1952         if (err < 0)
1953                 return err;
1954
1955         gctl = hw_read_20kx(hw, GLOBAL_CNTL_GCTL);
1956         set_field(&gctl, GCTL_DBP, 1);
1957         set_field(&gctl, GCTL_TBP, 1);
1958         set_field(&gctl, GCTL_FBP, 1);
1959         set_field(&gctl, GCTL_DPC, 0);
1960         hw_write_20kx(hw, GLOBAL_CNTL_GCTL, gctl);
1961
1962         /* Reset all global pending interrupts */
1963         hw_write_20kx(hw, INTERRUPT_GIE, 0);
1964         /* Reset all SRC pending interrupts */
1965         hw_write_20kx(hw, SRC_IP, 0);
1966
1967         /* TODO: detect the card ID and configure GPIO accordingly. */
1968         /* Configures GPIO (0xD802 0x98028) */
1969         /*hw_write_20kx(hw, GPIO_CTRL, 0x7F07);*/
1970         /* Configures GPIO (SB0880) */
1971         /*hw_write_20kx(hw, GPIO_CTRL, 0xFF07);*/
1972         hw_write_20kx(hw, GPIO_CTRL, 0xD802);
1973
1974         /* Enable audio ring */
1975         hw_write_20kx(hw, MIXER_AR_ENABLE, 0x01);
1976
1977         trn_info.vm_pgt_phys = info->vm_pgt_phys;
1978         err = hw_trn_init(hw, &trn_info);
1979         if (err < 0)
1980                 return err;
1981
1982         daio_info.msr = info->msr;
1983         err = hw_daio_init(hw, &daio_info);
1984         if (err < 0)
1985                 return err;
1986
1987         dac_info.msr = info->msr;
1988         err = hw_dac_init(hw, &dac_info);
1989         if (err < 0)
1990                 return err;
1991
1992         adc_info.msr = info->msr;
1993         adc_info.input = ADC_LINEIN;
1994         adc_info.mic20db = 0;
1995         err = hw_adc_init(hw, &adc_info);
1996         if (err < 0)
1997                 return err;
1998
1999         data = hw_read_20kx(hw, SRC_MCTL);
2000         data |= 0x1; /* Enables input from the audio ring */
2001         hw_write_20kx(hw, SRC_MCTL, data);
2002
2003         return 0;
2004 }
2005
2006 static u32 hw_read_20kx(struct hw *hw, u32 reg)
2007 {
2008         return readl((void *)(hw->mem_base + reg));
2009 }
2010
2011 static void hw_write_20kx(struct hw *hw, u32 reg, u32 data)
2012 {
2013         writel(data, (void *)(hw->mem_base + reg));
2014 }
2015
2016 int create_20k2_hw_obj(struct hw **rhw)
2017 {
2018         struct hw *hw;
2019
2020         *rhw = NULL;
2021         hw = kzalloc(sizeof(*hw), GFP_KERNEL);
2022         if (NULL == hw)
2023                 return -ENOMEM;
2024
2025         hw->io_base = 0;
2026         hw->mem_base = (unsigned long)NULL;
2027         hw->irq = -1;
2028
2029         hw->card_init = hw_card_init;
2030         hw->card_stop = hw_card_stop;
2031         hw->pll_init = hw_pll_init;
2032         hw->is_adc_source_selected = hw_is_adc_input_selected;
2033         hw->select_adc_source = hw_adc_input_select;
2034         hw->have_digit_io_switch = hw_have_digit_io_switch;
2035
2036         hw->src_rsc_get_ctrl_blk = src_get_rsc_ctrl_blk;
2037         hw->src_rsc_put_ctrl_blk = src_put_rsc_ctrl_blk;
2038         hw->src_mgr_get_ctrl_blk = src_mgr_get_ctrl_blk;
2039         hw->src_mgr_put_ctrl_blk = src_mgr_put_ctrl_blk;
2040         hw->src_set_state = src_set_state;
2041         hw->src_set_bm = src_set_bm;
2042         hw->src_set_rsr = src_set_rsr;
2043         hw->src_set_sf = src_set_sf;
2044         hw->src_set_wr = src_set_wr;
2045         hw->src_set_pm = src_set_pm;
2046         hw->src_set_rom = src_set_rom;
2047         hw->src_set_vo = src_set_vo;
2048         hw->src_set_st = src_set_st;
2049         hw->src_set_ie = src_set_ie;
2050         hw->src_set_ilsz = src_set_ilsz;
2051         hw->src_set_bp = src_set_bp;
2052         hw->src_set_cisz = src_set_cisz;
2053         hw->src_set_ca = src_set_ca;
2054         hw->src_set_sa = src_set_sa;
2055         hw->src_set_la = src_set_la;
2056         hw->src_set_pitch = src_set_pitch;
2057         hw->src_set_dirty = src_set_dirty;
2058         hw->src_set_clear_zbufs = src_set_clear_zbufs;
2059         hw->src_set_dirty_all = src_set_dirty_all;
2060         hw->src_commit_write = src_commit_write;
2061         hw->src_get_ca = src_get_ca;
2062         hw->src_get_dirty = src_get_dirty;
2063         hw->src_dirty_conj_mask = src_dirty_conj_mask;
2064         hw->src_mgr_enbs_src = src_mgr_enbs_src;
2065         hw->src_mgr_enb_src = src_mgr_enb_src;
2066         hw->src_mgr_dsb_src = src_mgr_dsb_src;
2067         hw->src_mgr_commit_write = src_mgr_commit_write;
2068
2069         hw->srcimp_mgr_get_ctrl_blk = srcimp_mgr_get_ctrl_blk;
2070         hw->srcimp_mgr_put_ctrl_blk = srcimp_mgr_put_ctrl_blk;
2071         hw->srcimp_mgr_set_imaparc = srcimp_mgr_set_imaparc;
2072         hw->srcimp_mgr_set_imapuser = srcimp_mgr_set_imapuser;
2073         hw->srcimp_mgr_set_imapnxt = srcimp_mgr_set_imapnxt;
2074         hw->srcimp_mgr_set_imapaddr = srcimp_mgr_set_imapaddr;
2075         hw->srcimp_mgr_commit_write = srcimp_mgr_commit_write;
2076
2077         hw->amixer_rsc_get_ctrl_blk = amixer_rsc_get_ctrl_blk;
2078         hw->amixer_rsc_put_ctrl_blk = amixer_rsc_put_ctrl_blk;
2079         hw->amixer_mgr_get_ctrl_blk = amixer_mgr_get_ctrl_blk;
2080         hw->amixer_mgr_put_ctrl_blk = amixer_mgr_put_ctrl_blk;
2081         hw->amixer_set_mode = amixer_set_mode;
2082         hw->amixer_set_iv = amixer_set_iv;
2083         hw->amixer_set_x = amixer_set_x;
2084         hw->amixer_set_y = amixer_set_y;
2085         hw->amixer_set_sadr = amixer_set_sadr;
2086         hw->amixer_set_se = amixer_set_se;
2087         hw->amixer_set_dirty = amixer_set_dirty;
2088         hw->amixer_set_dirty_all = amixer_set_dirty_all;
2089         hw->amixer_commit_write = amixer_commit_write;
2090         hw->amixer_get_y = amixer_get_y;
2091         hw->amixer_get_dirty = amixer_get_dirty;
2092
2093         hw->dai_get_ctrl_blk = dai_get_ctrl_blk;
2094         hw->dai_put_ctrl_blk = dai_put_ctrl_blk;
2095         hw->dai_srt_set_srco = dai_srt_set_srco;
2096         hw->dai_srt_set_srcm = dai_srt_set_srcm;
2097         hw->dai_srt_set_rsr = dai_srt_set_rsr;
2098         hw->dai_srt_set_drat = dai_srt_set_drat;
2099         hw->dai_srt_set_ec = dai_srt_set_ec;
2100         hw->dai_srt_set_et = dai_srt_set_et;
2101         hw->dai_commit_write = dai_commit_write;
2102
2103         hw->dao_get_ctrl_blk = dao_get_ctrl_blk;
2104         hw->dao_put_ctrl_blk = dao_put_ctrl_blk;
2105         hw->dao_set_spos = dao_set_spos;
2106         hw->dao_commit_write = dao_commit_write;
2107         hw->dao_get_spos = dao_get_spos;
2108
2109         hw->daio_mgr_get_ctrl_blk = daio_mgr_get_ctrl_blk;
2110         hw->daio_mgr_put_ctrl_blk = daio_mgr_put_ctrl_blk;
2111         hw->daio_mgr_enb_dai = daio_mgr_enb_dai;
2112         hw->daio_mgr_dsb_dai = daio_mgr_dsb_dai;
2113         hw->daio_mgr_enb_dao = daio_mgr_enb_dao;
2114         hw->daio_mgr_dsb_dao = daio_mgr_dsb_dao;
2115         hw->daio_mgr_dao_init = daio_mgr_dao_init;
2116         hw->daio_mgr_set_imaparc = daio_mgr_set_imaparc;
2117         hw->daio_mgr_set_imapnxt = daio_mgr_set_imapnxt;
2118         hw->daio_mgr_set_imapaddr = daio_mgr_set_imapaddr;
2119         hw->daio_mgr_commit_write = daio_mgr_commit_write;
2120
2121         *rhw = hw;
2122
2123         return 0;
2124 }
2125
2126 int destroy_20k2_hw_obj(struct hw *hw)
2127 {
2128         if (hw->io_base)
2129                 hw_card_shutdown(hw);
2130
2131         kfree(hw);
2132         return 0;
2133 }