mv643xx_eth: Move ethernet register definitions into private header
[linux-2.6.git] / include / linux / mv643xx.h
1 /*
2  * mv643xx.h - MV-643XX Internal registers definition file.
3  *
4  * Copyright 2002 Momentum Computer, Inc.
5  *      Author: Matthew Dharm <mdharm@momenco.com>
6  * Copyright 2002 GALILEO TECHNOLOGY, LTD. 
7  *
8  * This program is free software; you can redistribute  it and/or modify it
9  * under  the terms of  the GNU General  Public License as published by the
10  * Free Software Foundation;  either version 2 of the  License, or (at your
11  * option) any later version.
12  */
13 #ifndef __ASM_MV643XX_H
14 #define __ASM_MV643XX_H
15
16 #include <asm/types.h>
17 #include <linux/mv643xx_eth.h>
18
19 /****************************************/
20 /* Processor Address Space              */
21 /****************************************/
22
23 /* DDR SDRAM BAR and size registers */
24
25 #define MV64340_CS_0_BASE_ADDR                                      0x008
26 #define MV64340_CS_0_SIZE                                           0x010
27 #define MV64340_CS_1_BASE_ADDR                                      0x208
28 #define MV64340_CS_1_SIZE                                           0x210
29 #define MV64340_CS_2_BASE_ADDR                                      0x018
30 #define MV64340_CS_2_SIZE                                           0x020
31 #define MV64340_CS_3_BASE_ADDR                                      0x218
32 #define MV64340_CS_3_SIZE                                           0x220
33
34 /* Devices BAR and size registers */
35
36 #define MV64340_DEV_CS0_BASE_ADDR                                   0x028
37 #define MV64340_DEV_CS0_SIZE                                        0x030
38 #define MV64340_DEV_CS1_BASE_ADDR                                   0x228
39 #define MV64340_DEV_CS1_SIZE                                        0x230
40 #define MV64340_DEV_CS2_BASE_ADDR                                   0x248
41 #define MV64340_DEV_CS2_SIZE                                        0x250
42 #define MV64340_DEV_CS3_BASE_ADDR                                   0x038
43 #define MV64340_DEV_CS3_SIZE                                        0x040
44 #define MV64340_BOOTCS_BASE_ADDR                                    0x238
45 #define MV64340_BOOTCS_SIZE                                         0x240
46
47 /* PCI 0 BAR and size registers */
48
49 #define MV64340_PCI_0_IO_BASE_ADDR                                  0x048
50 #define MV64340_PCI_0_IO_SIZE                                       0x050
51 #define MV64340_PCI_0_MEMORY0_BASE_ADDR                             0x058
52 #define MV64340_PCI_0_MEMORY0_SIZE                                  0x060
53 #define MV64340_PCI_0_MEMORY1_BASE_ADDR                             0x080
54 #define MV64340_PCI_0_MEMORY1_SIZE                                  0x088
55 #define MV64340_PCI_0_MEMORY2_BASE_ADDR                             0x258
56 #define MV64340_PCI_0_MEMORY2_SIZE                                  0x260
57 #define MV64340_PCI_0_MEMORY3_BASE_ADDR                             0x280
58 #define MV64340_PCI_0_MEMORY3_SIZE                                  0x288
59
60 /* PCI 1 BAR and size registers */
61 #define MV64340_PCI_1_IO_BASE_ADDR                                  0x090
62 #define MV64340_PCI_1_IO_SIZE                                       0x098
63 #define MV64340_PCI_1_MEMORY0_BASE_ADDR                             0x0a0
64 #define MV64340_PCI_1_MEMORY0_SIZE                                  0x0a8
65 #define MV64340_PCI_1_MEMORY1_BASE_ADDR                             0x0b0
66 #define MV64340_PCI_1_MEMORY1_SIZE                                  0x0b8
67 #define MV64340_PCI_1_MEMORY2_BASE_ADDR                             0x2a0
68 #define MV64340_PCI_1_MEMORY2_SIZE                                  0x2a8
69 #define MV64340_PCI_1_MEMORY3_BASE_ADDR                             0x2b0
70 #define MV64340_PCI_1_MEMORY3_SIZE                                  0x2b8
71
72 /* SRAM base address */
73 #define MV64340_INTEGRATED_SRAM_BASE_ADDR                           0x268
74
75 /* internal registers space base address */
76 #define MV64340_INTERNAL_SPACE_BASE_ADDR                            0x068
77
78 /* Enables the CS , DEV_CS , PCI 0 and PCI 1 
79    windows above */
80 #define MV64340_BASE_ADDR_ENABLE                                    0x278
81
82 /****************************************/
83 /* PCI remap registers                  */
84 /****************************************/
85       /* PCI 0 */
86 #define MV64340_PCI_0_IO_ADDR_REMAP                                 0x0f0
87 #define MV64340_PCI_0_MEMORY0_LOW_ADDR_REMAP                        0x0f8
88 #define MV64340_PCI_0_MEMORY0_HIGH_ADDR_REMAP                       0x320
89 #define MV64340_PCI_0_MEMORY1_LOW_ADDR_REMAP                        0x100
90 #define MV64340_PCI_0_MEMORY1_HIGH_ADDR_REMAP                       0x328
91 #define MV64340_PCI_0_MEMORY2_LOW_ADDR_REMAP                        0x2f8
92 #define MV64340_PCI_0_MEMORY2_HIGH_ADDR_REMAP                       0x330
93 #define MV64340_PCI_0_MEMORY3_LOW_ADDR_REMAP                        0x300
94 #define MV64340_PCI_0_MEMORY3_HIGH_ADDR_REMAP                       0x338
95       /* PCI 1 */
96 #define MV64340_PCI_1_IO_ADDR_REMAP                                 0x108
97 #define MV64340_PCI_1_MEMORY0_LOW_ADDR_REMAP                        0x110
98 #define MV64340_PCI_1_MEMORY0_HIGH_ADDR_REMAP                       0x340
99 #define MV64340_PCI_1_MEMORY1_LOW_ADDR_REMAP                        0x118
100 #define MV64340_PCI_1_MEMORY1_HIGH_ADDR_REMAP                       0x348
101 #define MV64340_PCI_1_MEMORY2_LOW_ADDR_REMAP                        0x310
102 #define MV64340_PCI_1_MEMORY2_HIGH_ADDR_REMAP                       0x350
103 #define MV64340_PCI_1_MEMORY3_LOW_ADDR_REMAP                        0x318
104 #define MV64340_PCI_1_MEMORY3_HIGH_ADDR_REMAP                       0x358
105  
106 #define MV64340_CPU_PCI_0_HEADERS_RETARGET_CONTROL                  0x3b0
107 #define MV64340_CPU_PCI_0_HEADERS_RETARGET_BASE                     0x3b8
108 #define MV64340_CPU_PCI_1_HEADERS_RETARGET_CONTROL                  0x3c0
109 #define MV64340_CPU_PCI_1_HEADERS_RETARGET_BASE                     0x3c8
110 #define MV64340_CPU_GE_HEADERS_RETARGET_CONTROL                     0x3d0
111 #define MV64340_CPU_GE_HEADERS_RETARGET_BASE                        0x3d8
112 #define MV64340_CPU_IDMA_HEADERS_RETARGET_CONTROL                   0x3e0
113 #define MV64340_CPU_IDMA_HEADERS_RETARGET_BASE                      0x3e8
114
115 /****************************************/
116 /*         CPU Control Registers        */
117 /****************************************/
118
119 #define MV64340_CPU_CONFIG                                          0x000
120 #define MV64340_CPU_MODE                                            0x120
121 #define MV64340_CPU_MASTER_CONTROL                                  0x160
122 #define MV64340_CPU_CROSS_BAR_CONTROL_LOW                           0x150
123 #define MV64340_CPU_CROSS_BAR_CONTROL_HIGH                          0x158
124 #define MV64340_CPU_CROSS_BAR_TIMEOUT                               0x168
125
126 /****************************************/
127 /* SMP RegisterS                        */
128 /****************************************/
129
130 #define MV64340_SMP_WHO_AM_I                                        0x200
131 #define MV64340_SMP_CPU0_DOORBELL                                   0x214
132 #define MV64340_SMP_CPU0_DOORBELL_CLEAR                             0x21C
133 #define MV64340_SMP_CPU1_DOORBELL                                   0x224
134 #define MV64340_SMP_CPU1_DOORBELL_CLEAR                             0x22C
135 #define MV64340_SMP_CPU0_DOORBELL_MASK                              0x234
136 #define MV64340_SMP_CPU1_DOORBELL_MASK                              0x23C
137 #define MV64340_SMP_SEMAPHOR0                                       0x244
138 #define MV64340_SMP_SEMAPHOR1                                       0x24c
139 #define MV64340_SMP_SEMAPHOR2                                       0x254
140 #define MV64340_SMP_SEMAPHOR3                                       0x25c
141 #define MV64340_SMP_SEMAPHOR4                                       0x264
142 #define MV64340_SMP_SEMAPHOR5                                       0x26c
143 #define MV64340_SMP_SEMAPHOR6                                       0x274
144 #define MV64340_SMP_SEMAPHOR7                                       0x27c
145
146 /****************************************/
147 /*  CPU Sync Barrier Register           */
148 /****************************************/
149
150 #define MV64340_CPU_0_SYNC_BARRIER_TRIGGER                          0x0c0
151 #define MV64340_CPU_0_SYNC_BARRIER_VIRTUAL                          0x0c8
152 #define MV64340_CPU_1_SYNC_BARRIER_TRIGGER                          0x0d0
153 #define MV64340_CPU_1_SYNC_BARRIER_VIRTUAL                          0x0d8
154
155 /****************************************/
156 /* CPU Access Protect                   */
157 /****************************************/
158
159 #define MV64340_CPU_PROTECT_WINDOW_0_BASE_ADDR                      0x180
160 #define MV64340_CPU_PROTECT_WINDOW_0_SIZE                           0x188
161 #define MV64340_CPU_PROTECT_WINDOW_1_BASE_ADDR                      0x190
162 #define MV64340_CPU_PROTECT_WINDOW_1_SIZE                           0x198
163 #define MV64340_CPU_PROTECT_WINDOW_2_BASE_ADDR                      0x1a0
164 #define MV64340_CPU_PROTECT_WINDOW_2_SIZE                           0x1a8
165 #define MV64340_CPU_PROTECT_WINDOW_3_BASE_ADDR                      0x1b0
166 #define MV64340_CPU_PROTECT_WINDOW_3_SIZE                           0x1b8
167
168
169 /****************************************/
170 /*          CPU Error Report            */
171 /****************************************/
172
173 #define MV64340_CPU_ERROR_ADDR_LOW                                  0x070
174 #define MV64340_CPU_ERROR_ADDR_HIGH                                 0x078
175 #define MV64340_CPU_ERROR_DATA_LOW                                  0x128
176 #define MV64340_CPU_ERROR_DATA_HIGH                                 0x130
177 #define MV64340_CPU_ERROR_PARITY                                    0x138
178 #define MV64340_CPU_ERROR_CAUSE                                     0x140
179 #define MV64340_CPU_ERROR_MASK                                      0x148
180
181 /****************************************/
182 /*      CPU Interface Debug Registers   */
183 /****************************************/
184
185 #define MV64340_PUNIT_SLAVE_DEBUG_LOW                               0x360
186 #define MV64340_PUNIT_SLAVE_DEBUG_HIGH                              0x368
187 #define MV64340_PUNIT_MASTER_DEBUG_LOW                              0x370
188 #define MV64340_PUNIT_MASTER_DEBUG_HIGH                             0x378
189 #define MV64340_PUNIT_MMASK                                         0x3e4
190
191 /****************************************/
192 /*  Integrated SRAM Registers           */
193 /****************************************/
194
195 #define MV64340_SRAM_CONFIG                                         0x380
196 #define MV64340_SRAM_TEST_MODE                                      0X3F4
197 #define MV64340_SRAM_ERROR_CAUSE                                    0x388
198 #define MV64340_SRAM_ERROR_ADDR                                     0x390
199 #define MV64340_SRAM_ERROR_ADDR_HIGH                                0X3F8
200 #define MV64340_SRAM_ERROR_DATA_LOW                                 0x398
201 #define MV64340_SRAM_ERROR_DATA_HIGH                                0x3a0
202 #define MV64340_SRAM_ERROR_DATA_PARITY                              0x3a8
203
204 /****************************************/
205 /* SDRAM Configuration                  */
206 /****************************************/
207
208 #define MV64340_SDRAM_CONFIG                                        0x1400
209 #define MV64340_D_UNIT_CONTROL_LOW                                  0x1404
210 #define MV64340_D_UNIT_CONTROL_HIGH                                 0x1424
211 #define MV64340_SDRAM_TIMING_CONTROL_LOW                            0x1408
212 #define MV64340_SDRAM_TIMING_CONTROL_HIGH                           0x140c
213 #define MV64340_SDRAM_ADDR_CONTROL                                  0x1410
214 #define MV64340_SDRAM_OPEN_PAGES_CONTROL                            0x1414
215 #define MV64340_SDRAM_OPERATION                                     0x1418
216 #define MV64340_SDRAM_MODE                                          0x141c
217 #define MV64340_EXTENDED_DRAM_MODE                                  0x1420
218 #define MV64340_SDRAM_CROSS_BAR_CONTROL_LOW                         0x1430
219 #define MV64340_SDRAM_CROSS_BAR_CONTROL_HIGH                        0x1434
220 #define MV64340_SDRAM_CROSS_BAR_TIMEOUT                             0x1438
221 #define MV64340_SDRAM_ADDR_CTRL_PADS_CALIBRATION                    0x14c0
222 #define MV64340_SDRAM_DATA_PADS_CALIBRATION                         0x14c4
223
224 /****************************************/
225 /* SDRAM Error Report                   */
226 /****************************************/
227
228 #define MV64340_SDRAM_ERROR_DATA_LOW                                0x1444
229 #define MV64340_SDRAM_ERROR_DATA_HIGH                               0x1440
230 #define MV64340_SDRAM_ERROR_ADDR                                    0x1450
231 #define MV64340_SDRAM_RECEIVED_ECC                                  0x1448
232 #define MV64340_SDRAM_CALCULATED_ECC                                0x144c
233 #define MV64340_SDRAM_ECC_CONTROL                                   0x1454
234 #define MV64340_SDRAM_ECC_ERROR_COUNTER                             0x1458
235
236 /******************************************/
237 /*  Controlled Delay Line (CDL) Registers */
238 /******************************************/
239
240 #define MV64340_DFCDL_CONFIG0                                       0x1480
241 #define MV64340_DFCDL_CONFIG1                                       0x1484
242 #define MV64340_DLL_WRITE                                           0x1488
243 #define MV64340_DLL_READ                                            0x148c
244 #define MV64340_SRAM_ADDR                                           0x1490
245 #define MV64340_SRAM_DATA0                                          0x1494
246 #define MV64340_SRAM_DATA1                                          0x1498
247 #define MV64340_SRAM_DATA2                                          0x149c
248 #define MV64340_DFCL_PROBE                                          0x14a0
249
250 /******************************************/
251 /*   Debug Registers                      */
252 /******************************************/
253
254 #define MV64340_DUNIT_DEBUG_LOW                                     0x1460
255 #define MV64340_DUNIT_DEBUG_HIGH                                    0x1464
256 #define MV64340_DUNIT_MMASK                                         0X1b40
257
258 /****************************************/
259 /* Device Parameters                    */
260 /****************************************/
261
262 #define MV64340_DEVICE_BANK0_PARAMETERS                             0x45c
263 #define MV64340_DEVICE_BANK1_PARAMETERS                             0x460
264 #define MV64340_DEVICE_BANK2_PARAMETERS                             0x464
265 #define MV64340_DEVICE_BANK3_PARAMETERS                             0x468
266 #define MV64340_DEVICE_BOOT_BANK_PARAMETERS                         0x46c
267 #define MV64340_DEVICE_INTERFACE_CONTROL                            0x4c0
268 #define MV64340_DEVICE_INTERFACE_CROSS_BAR_CONTROL_LOW              0x4c8
269 #define MV64340_DEVICE_INTERFACE_CROSS_BAR_CONTROL_HIGH             0x4cc
270 #define MV64340_DEVICE_INTERFACE_CROSS_BAR_TIMEOUT                  0x4c4
271
272 /****************************************/
273 /* Device interrupt registers           */
274 /****************************************/
275
276 #define MV64340_DEVICE_INTERRUPT_CAUSE                              0x4d0
277 #define MV64340_DEVICE_INTERRUPT_MASK                               0x4d4
278 #define MV64340_DEVICE_ERROR_ADDR                                   0x4d8
279 #define MV64340_DEVICE_ERROR_DATA                                   0x4dc
280 #define MV64340_DEVICE_ERROR_PARITY                                 0x4e0
281
282 /****************************************/
283 /* Device debug registers               */
284 /****************************************/
285
286 #define MV64340_DEVICE_DEBUG_LOW                                    0x4e4
287 #define MV64340_DEVICE_DEBUG_HIGH                                   0x4e8
288 #define MV64340_RUNIT_MMASK                                         0x4f0
289
290 /****************************************/
291 /* PCI Slave Address Decoding registers */
292 /****************************************/
293
294 #define MV64340_PCI_0_CS_0_BANK_SIZE                                0xc08
295 #define MV64340_PCI_1_CS_0_BANK_SIZE                                0xc88
296 #define MV64340_PCI_0_CS_1_BANK_SIZE                                0xd08
297 #define MV64340_PCI_1_CS_1_BANK_SIZE                                0xd88
298 #define MV64340_PCI_0_CS_2_BANK_SIZE                                0xc0c
299 #define MV64340_PCI_1_CS_2_BANK_SIZE                                0xc8c
300 #define MV64340_PCI_0_CS_3_BANK_SIZE                                0xd0c
301 #define MV64340_PCI_1_CS_3_BANK_SIZE                                0xd8c
302 #define MV64340_PCI_0_DEVCS_0_BANK_SIZE                             0xc10
303 #define MV64340_PCI_1_DEVCS_0_BANK_SIZE                             0xc90
304 #define MV64340_PCI_0_DEVCS_1_BANK_SIZE                             0xd10
305 #define MV64340_PCI_1_DEVCS_1_BANK_SIZE                             0xd90
306 #define MV64340_PCI_0_DEVCS_2_BANK_SIZE                             0xd18
307 #define MV64340_PCI_1_DEVCS_2_BANK_SIZE                             0xd98
308 #define MV64340_PCI_0_DEVCS_3_BANK_SIZE                             0xc14
309 #define MV64340_PCI_1_DEVCS_3_BANK_SIZE                             0xc94
310 #define MV64340_PCI_0_DEVCS_BOOT_BANK_SIZE                          0xd14
311 #define MV64340_PCI_1_DEVCS_BOOT_BANK_SIZE                          0xd94
312 #define MV64340_PCI_0_P2P_MEM0_BAR_SIZE                             0xd1c
313 #define MV64340_PCI_1_P2P_MEM0_BAR_SIZE                             0xd9c
314 #define MV64340_PCI_0_P2P_MEM1_BAR_SIZE                             0xd20
315 #define MV64340_PCI_1_P2P_MEM1_BAR_SIZE                             0xda0
316 #define MV64340_PCI_0_P2P_I_O_BAR_SIZE                              0xd24
317 #define MV64340_PCI_1_P2P_I_O_BAR_SIZE                              0xda4
318 #define MV64340_PCI_0_CPU_BAR_SIZE                                  0xd28
319 #define MV64340_PCI_1_CPU_BAR_SIZE                                  0xda8
320 #define MV64340_PCI_0_INTERNAL_SRAM_BAR_SIZE                        0xe00
321 #define MV64340_PCI_1_INTERNAL_SRAM_BAR_SIZE                        0xe80
322 #define MV64340_PCI_0_EXPANSION_ROM_BAR_SIZE                        0xd2c
323 #define MV64340_PCI_1_EXPANSION_ROM_BAR_SIZE                        0xd9c
324 #define MV64340_PCI_0_BASE_ADDR_REG_ENABLE                          0xc3c
325 #define MV64340_PCI_1_BASE_ADDR_REG_ENABLE                          0xcbc
326 #define MV64340_PCI_0_CS_0_BASE_ADDR_REMAP                          0xc48
327 #define MV64340_PCI_1_CS_0_BASE_ADDR_REMAP                          0xcc8
328 #define MV64340_PCI_0_CS_1_BASE_ADDR_REMAP                          0xd48
329 #define MV64340_PCI_1_CS_1_BASE_ADDR_REMAP                          0xdc8
330 #define MV64340_PCI_0_CS_2_BASE_ADDR_REMAP                          0xc4c
331 #define MV64340_PCI_1_CS_2_BASE_ADDR_REMAP                          0xccc
332 #define MV64340_PCI_0_CS_3_BASE_ADDR_REMAP                          0xd4c
333 #define MV64340_PCI_1_CS_3_BASE_ADDR_REMAP                          0xdcc
334 #define MV64340_PCI_0_CS_0_BASE_HIGH_ADDR_REMAP                     0xF04
335 #define MV64340_PCI_1_CS_0_BASE_HIGH_ADDR_REMAP                     0xF84
336 #define MV64340_PCI_0_CS_1_BASE_HIGH_ADDR_REMAP                     0xF08
337 #define MV64340_PCI_1_CS_1_BASE_HIGH_ADDR_REMAP                     0xF88
338 #define MV64340_PCI_0_CS_2_BASE_HIGH_ADDR_REMAP                     0xF0C
339 #define MV64340_PCI_1_CS_2_BASE_HIGH_ADDR_REMAP                     0xF8C
340 #define MV64340_PCI_0_CS_3_BASE_HIGH_ADDR_REMAP                     0xF10
341 #define MV64340_PCI_1_CS_3_BASE_HIGH_ADDR_REMAP                     0xF90
342 #define MV64340_PCI_0_DEVCS_0_BASE_ADDR_REMAP                       0xc50
343 #define MV64340_PCI_1_DEVCS_0_BASE_ADDR_REMAP                       0xcd0
344 #define MV64340_PCI_0_DEVCS_1_BASE_ADDR_REMAP                       0xd50
345 #define MV64340_PCI_1_DEVCS_1_BASE_ADDR_REMAP                       0xdd0
346 #define MV64340_PCI_0_DEVCS_2_BASE_ADDR_REMAP                       0xd58
347 #define MV64340_PCI_1_DEVCS_2_BASE_ADDR_REMAP                       0xdd8
348 #define MV64340_PCI_0_DEVCS_3_BASE_ADDR_REMAP                       0xc54
349 #define MV64340_PCI_1_DEVCS_3_BASE_ADDR_REMAP                       0xcd4
350 #define MV64340_PCI_0_DEVCS_BOOTCS_BASE_ADDR_REMAP                  0xd54
351 #define MV64340_PCI_1_DEVCS_BOOTCS_BASE_ADDR_REMAP                  0xdd4
352 #define MV64340_PCI_0_P2P_MEM0_BASE_ADDR_REMAP_LOW                  0xd5c
353 #define MV64340_PCI_1_P2P_MEM0_BASE_ADDR_REMAP_LOW                  0xddc
354 #define MV64340_PCI_0_P2P_MEM0_BASE_ADDR_REMAP_HIGH                 0xd60
355 #define MV64340_PCI_1_P2P_MEM0_BASE_ADDR_REMAP_HIGH                 0xde0
356 #define MV64340_PCI_0_P2P_MEM1_BASE_ADDR_REMAP_LOW                  0xd64
357 #define MV64340_PCI_1_P2P_MEM1_BASE_ADDR_REMAP_LOW                  0xde4
358 #define MV64340_PCI_0_P2P_MEM1_BASE_ADDR_REMAP_HIGH                 0xd68
359 #define MV64340_PCI_1_P2P_MEM1_BASE_ADDR_REMAP_HIGH                 0xde8
360 #define MV64340_PCI_0_P2P_I_O_BASE_ADDR_REMAP                       0xd6c
361 #define MV64340_PCI_1_P2P_I_O_BASE_ADDR_REMAP                       0xdec 
362 #define MV64340_PCI_0_CPU_BASE_ADDR_REMAP_LOW                       0xd70
363 #define MV64340_PCI_1_CPU_BASE_ADDR_REMAP_LOW                       0xdf0
364 #define MV64340_PCI_0_CPU_BASE_ADDR_REMAP_HIGH                      0xd74
365 #define MV64340_PCI_1_CPU_BASE_ADDR_REMAP_HIGH                      0xdf4
366 #define MV64340_PCI_0_INTEGRATED_SRAM_BASE_ADDR_REMAP               0xf00
367 #define MV64340_PCI_1_INTEGRATED_SRAM_BASE_ADDR_REMAP               0xf80
368 #define MV64340_PCI_0_EXPANSION_ROM_BASE_ADDR_REMAP                 0xf38
369 #define MV64340_PCI_1_EXPANSION_ROM_BASE_ADDR_REMAP                 0xfb8
370 #define MV64340_PCI_0_ADDR_DECODE_CONTROL                           0xd3c
371 #define MV64340_PCI_1_ADDR_DECODE_CONTROL                           0xdbc
372 #define MV64340_PCI_0_HEADERS_RETARGET_CONTROL                      0xF40
373 #define MV64340_PCI_1_HEADERS_RETARGET_CONTROL                      0xFc0
374 #define MV64340_PCI_0_HEADERS_RETARGET_BASE                         0xF44
375 #define MV64340_PCI_1_HEADERS_RETARGET_BASE                         0xFc4
376 #define MV64340_PCI_0_HEADERS_RETARGET_HIGH                         0xF48
377 #define MV64340_PCI_1_HEADERS_RETARGET_HIGH                         0xFc8
378
379 /***********************************/
380 /*   PCI Control Register Map      */
381 /***********************************/
382
383 #define MV64340_PCI_0_DLL_STATUS_AND_COMMAND                        0x1d20
384 #define MV64340_PCI_1_DLL_STATUS_AND_COMMAND                        0x1da0
385 #define MV64340_PCI_0_MPP_PADS_DRIVE_CONTROL                        0x1d1C
386 #define MV64340_PCI_1_MPP_PADS_DRIVE_CONTROL                        0x1d9C
387 #define MV64340_PCI_0_COMMAND                                       0xc00
388 #define MV64340_PCI_1_COMMAND                                       0xc80
389 #define MV64340_PCI_0_MODE                                          0xd00
390 #define MV64340_PCI_1_MODE                                          0xd80
391 #define MV64340_PCI_0_RETRY                                         0xc04
392 #define MV64340_PCI_1_RETRY                                         0xc84
393 #define MV64340_PCI_0_READ_BUFFER_DISCARD_TIMER                     0xd04
394 #define MV64340_PCI_1_READ_BUFFER_DISCARD_TIMER                     0xd84
395 #define MV64340_PCI_0_MSI_TRIGGER_TIMER                             0xc38
396 #define MV64340_PCI_1_MSI_TRIGGER_TIMER                             0xcb8
397 #define MV64340_PCI_0_ARBITER_CONTROL                               0x1d00
398 #define MV64340_PCI_1_ARBITER_CONTROL                               0x1d80
399 #define MV64340_PCI_0_CROSS_BAR_CONTROL_LOW                         0x1d08
400 #define MV64340_PCI_1_CROSS_BAR_CONTROL_LOW                         0x1d88
401 #define MV64340_PCI_0_CROSS_BAR_CONTROL_HIGH                        0x1d0c
402 #define MV64340_PCI_1_CROSS_BAR_CONTROL_HIGH                        0x1d8c
403 #define MV64340_PCI_0_CROSS_BAR_TIMEOUT                             0x1d04
404 #define MV64340_PCI_1_CROSS_BAR_TIMEOUT                             0x1d84
405 #define MV64340_PCI_0_SYNC_BARRIER_TRIGGER_REG                      0x1D18
406 #define MV64340_PCI_1_SYNC_BARRIER_TRIGGER_REG                      0x1D98
407 #define MV64340_PCI_0_SYNC_BARRIER_VIRTUAL_REG                      0x1d10
408 #define MV64340_PCI_1_SYNC_BARRIER_VIRTUAL_REG                      0x1d90
409 #define MV64340_PCI_0_P2P_CONFIG                                    0x1d14
410 #define MV64340_PCI_1_P2P_CONFIG                                    0x1d94
411
412 #define MV64340_PCI_0_ACCESS_CONTROL_BASE_0_LOW                     0x1e00
413 #define MV64340_PCI_0_ACCESS_CONTROL_BASE_0_HIGH                    0x1e04
414 #define MV64340_PCI_0_ACCESS_CONTROL_SIZE_0                         0x1e08
415 #define MV64340_PCI_0_ACCESS_CONTROL_BASE_1_LOW                     0x1e10
416 #define MV64340_PCI_0_ACCESS_CONTROL_BASE_1_HIGH                    0x1e14
417 #define MV64340_PCI_0_ACCESS_CONTROL_SIZE_1                         0x1e18
418 #define MV64340_PCI_0_ACCESS_CONTROL_BASE_2_LOW                     0x1e20
419 #define MV64340_PCI_0_ACCESS_CONTROL_BASE_2_HIGH                    0x1e24
420 #define MV64340_PCI_0_ACCESS_CONTROL_SIZE_2                         0x1e28
421 #define MV64340_PCI_0_ACCESS_CONTROL_BASE_3_LOW                     0x1e30
422 #define MV64340_PCI_0_ACCESS_CONTROL_BASE_3_HIGH                    0x1e34
423 #define MV64340_PCI_0_ACCESS_CONTROL_SIZE_3                         0x1e38
424 #define MV64340_PCI_0_ACCESS_CONTROL_BASE_4_LOW                     0x1e40
425 #define MV64340_PCI_0_ACCESS_CONTROL_BASE_4_HIGH                    0x1e44
426 #define MV64340_PCI_0_ACCESS_CONTROL_SIZE_4                         0x1e48
427 #define MV64340_PCI_0_ACCESS_CONTROL_BASE_5_LOW                     0x1e50
428 #define MV64340_PCI_0_ACCESS_CONTROL_BASE_5_HIGH                    0x1e54
429 #define MV64340_PCI_0_ACCESS_CONTROL_SIZE_5                         0x1e58
430
431 #define MV64340_PCI_1_ACCESS_CONTROL_BASE_0_LOW                     0x1e80
432 #define MV64340_PCI_1_ACCESS_CONTROL_BASE_0_HIGH                    0x1e84
433 #define MV64340_PCI_1_ACCESS_CONTROL_SIZE_0                         0x1e88
434 #define MV64340_PCI_1_ACCESS_CONTROL_BASE_1_LOW                     0x1e90
435 #define MV64340_PCI_1_ACCESS_CONTROL_BASE_1_HIGH                    0x1e94
436 #define MV64340_PCI_1_ACCESS_CONTROL_SIZE_1                         0x1e98
437 #define MV64340_PCI_1_ACCESS_CONTROL_BASE_2_LOW                     0x1ea0
438 #define MV64340_PCI_1_ACCESS_CONTROL_BASE_2_HIGH                    0x1ea4
439 #define MV64340_PCI_1_ACCESS_CONTROL_SIZE_2                         0x1ea8
440 #define MV64340_PCI_1_ACCESS_CONTROL_BASE_3_LOW                     0x1eb0
441 #define MV64340_PCI_1_ACCESS_CONTROL_BASE_3_HIGH                    0x1eb4
442 #define MV64340_PCI_1_ACCESS_CONTROL_SIZE_3                         0x1eb8
443 #define MV64340_PCI_1_ACCESS_CONTROL_BASE_4_LOW                     0x1ec0
444 #define MV64340_PCI_1_ACCESS_CONTROL_BASE_4_HIGH                    0x1ec4
445 #define MV64340_PCI_1_ACCESS_CONTROL_SIZE_4                         0x1ec8
446 #define MV64340_PCI_1_ACCESS_CONTROL_BASE_5_LOW                     0x1ed0
447 #define MV64340_PCI_1_ACCESS_CONTROL_BASE_5_HIGH                    0x1ed4
448 #define MV64340_PCI_1_ACCESS_CONTROL_SIZE_5                         0x1ed8
449
450 /****************************************/
451 /*   PCI Configuration Access Registers */
452 /****************************************/
453
454 #define MV64340_PCI_0_CONFIG_ADDR                                   0xcf8
455 #define MV64340_PCI_0_CONFIG_DATA_VIRTUAL_REG                       0xcfc
456 #define MV64340_PCI_1_CONFIG_ADDR                                   0xc78
457 #define MV64340_PCI_1_CONFIG_DATA_VIRTUAL_REG                       0xc7c
458 #define MV64340_PCI_0_INTERRUPT_ACKNOWLEDGE_VIRTUAL_REG             0xc34
459 #define MV64340_PCI_1_INTERRUPT_ACKNOWLEDGE_VIRTUAL_REG             0xcb4
460
461 /****************************************/
462 /*   PCI Error Report Registers         */
463 /****************************************/
464
465 #define MV64340_PCI_0_SERR_MASK                                     0xc28
466 #define MV64340_PCI_1_SERR_MASK                                     0xca8
467 #define MV64340_PCI_0_ERROR_ADDR_LOW                                0x1d40
468 #define MV64340_PCI_1_ERROR_ADDR_LOW                                0x1dc0
469 #define MV64340_PCI_0_ERROR_ADDR_HIGH                               0x1d44
470 #define MV64340_PCI_1_ERROR_ADDR_HIGH                               0x1dc4
471 #define MV64340_PCI_0_ERROR_ATTRIBUTE                               0x1d48
472 #define MV64340_PCI_1_ERROR_ATTRIBUTE                               0x1dc8
473 #define MV64340_PCI_0_ERROR_COMMAND                                 0x1d50
474 #define MV64340_PCI_1_ERROR_COMMAND                                 0x1dd0
475 #define MV64340_PCI_0_ERROR_CAUSE                                   0x1d58
476 #define MV64340_PCI_1_ERROR_CAUSE                                   0x1dd8
477 #define MV64340_PCI_0_ERROR_MASK                                    0x1d5c
478 #define MV64340_PCI_1_ERROR_MASK                                    0x1ddc
479
480 /****************************************/
481 /*   PCI Debug Registers                */
482 /****************************************/
483
484 #define MV64340_PCI_0_MMASK                                         0X1D24
485 #define MV64340_PCI_1_MMASK                                         0X1DA4
486
487 /*********************************************/
488 /* PCI Configuration, Function 0, Registers  */
489 /*********************************************/
490
491 #define MV64340_PCI_DEVICE_AND_VENDOR_ID                            0x000
492 #define MV64340_PCI_STATUS_AND_COMMAND                              0x004
493 #define MV64340_PCI_CLASS_CODE_AND_REVISION_ID                      0x008
494 #define MV64340_PCI_BIST_HEADER_TYPE_LATENCY_TIMER_CACHE_LINE       0x00C
495
496 #define MV64340_PCI_SCS_0_BASE_ADDR_LOW                             0x010
497 #define MV64340_PCI_SCS_0_BASE_ADDR_HIGH                            0x014
498 #define MV64340_PCI_SCS_1_BASE_ADDR_LOW                             0x018
499 #define MV64340_PCI_SCS_1_BASE_ADDR_HIGH                            0x01C
500 #define MV64340_PCI_INTERNAL_REG_MEM_MAPPED_BASE_ADDR_LOW           0x020
501 #define MV64340_PCI_INTERNAL_REG_MEM_MAPPED_BASE_ADDR_HIGH          0x024
502 #define MV64340_PCI_SUBSYSTEM_ID_AND_SUBSYSTEM_VENDOR_ID            0x02c
503 #define MV64340_PCI_EXPANSION_ROM_BASE_ADDR_REG                     0x030
504 #define MV64340_PCI_CAPABILTY_LIST_POINTER                          0x034
505 #define MV64340_PCI_INTERRUPT_PIN_AND_LINE                          0x03C
506        /* capability list */
507 #define MV64340_PCI_POWER_MANAGEMENT_CAPABILITY                     0x040
508 #define MV64340_PCI_POWER_MANAGEMENT_STATUS_AND_CONTROL             0x044
509 #define MV64340_PCI_VPD_ADDR                                        0x048
510 #define MV64340_PCI_VPD_DATA                                        0x04c
511 #define MV64340_PCI_MSI_MESSAGE_CONTROL                             0x050
512 #define MV64340_PCI_MSI_MESSAGE_ADDR                                0x054
513 #define MV64340_PCI_MSI_MESSAGE_UPPER_ADDR                          0x058
514 #define MV64340_PCI_MSI_MESSAGE_DATA                                0x05c
515 #define MV64340_PCI_X_COMMAND                                       0x060
516 #define MV64340_PCI_X_STATUS                                        0x064
517 #define MV64340_PCI_COMPACT_PCI_HOT_SWAP                            0x068
518
519 /***********************************************/
520 /*   PCI Configuration, Function 1, Registers  */
521 /***********************************************/
522
523 #define MV64340_PCI_SCS_2_BASE_ADDR_LOW                             0x110
524 #define MV64340_PCI_SCS_2_BASE_ADDR_HIGH                            0x114
525 #define MV64340_PCI_SCS_3_BASE_ADDR_LOW                             0x118
526 #define MV64340_PCI_SCS_3_BASE_ADDR_HIGH                            0x11c
527 #define MV64340_PCI_INTERNAL_SRAM_BASE_ADDR_LOW                     0x120
528 #define MV64340_PCI_INTERNAL_SRAM_BASE_ADDR_HIGH                    0x124
529
530 /***********************************************/
531 /*  PCI Configuration, Function 2, Registers   */
532 /***********************************************/
533
534 #define MV64340_PCI_DEVCS_0_BASE_ADDR_LOW                           0x210
535 #define MV64340_PCI_DEVCS_0_BASE_ADDR_HIGH                          0x214
536 #define MV64340_PCI_DEVCS_1_BASE_ADDR_LOW                           0x218
537 #define MV64340_PCI_DEVCS_1_BASE_ADDR_HIGH                          0x21c
538 #define MV64340_PCI_DEVCS_2_BASE_ADDR_LOW                           0x220
539 #define MV64340_PCI_DEVCS_2_BASE_ADDR_HIGH                          0x224
540
541 /***********************************************/
542 /*  PCI Configuration, Function 3, Registers   */
543 /***********************************************/
544
545 #define MV64340_PCI_DEVCS_3_BASE_ADDR_LOW                           0x310
546 #define MV64340_PCI_DEVCS_3_BASE_ADDR_HIGH                          0x314
547 #define MV64340_PCI_BOOT_CS_BASE_ADDR_LOW                           0x318
548 #define MV64340_PCI_BOOT_CS_BASE_ADDR_HIGH                          0x31c
549 #define MV64340_PCI_CPU_BASE_ADDR_LOW                               0x220
550 #define MV64340_PCI_CPU_BASE_ADDR_HIGH                              0x224
551
552 /***********************************************/
553 /*  PCI Configuration, Function 4, Registers   */
554 /***********************************************/
555
556 #define MV64340_PCI_P2P_MEM0_BASE_ADDR_LOW                          0x410
557 #define MV64340_PCI_P2P_MEM0_BASE_ADDR_HIGH                         0x414
558 #define MV64340_PCI_P2P_MEM1_BASE_ADDR_LOW                          0x418
559 #define MV64340_PCI_P2P_MEM1_BASE_ADDR_HIGH                         0x41c
560 #define MV64340_PCI_P2P_I_O_BASE_ADDR                               0x420
561 #define MV64340_PCI_INTERNAL_REGS_I_O_MAPPED_BASE_ADDR              0x424
562
563 /****************************************/
564 /* Messaging Unit Registers (I20)       */
565 /****************************************/
566
567 #define MV64340_I2O_INBOUND_MESSAGE_REG0_PCI_0_SIDE                 0x010
568 #define MV64340_I2O_INBOUND_MESSAGE_REG1_PCI_0_SIDE                 0x014
569 #define MV64340_I2O_OUTBOUND_MESSAGE_REG0_PCI_0_SIDE                0x018
570 #define MV64340_I2O_OUTBOUND_MESSAGE_REG1_PCI_0_SIDE                0x01C
571 #define MV64340_I2O_INBOUND_DOORBELL_REG_PCI_0_SIDE                 0x020
572 #define MV64340_I2O_INBOUND_INTERRUPT_CAUSE_REG_PCI_0_SIDE          0x024
573 #define MV64340_I2O_INBOUND_INTERRUPT_MASK_REG_PCI_0_SIDE           0x028
574 #define MV64340_I2O_OUTBOUND_DOORBELL_REG_PCI_0_SIDE                0x02C
575 #define MV64340_I2O_OUTBOUND_INTERRUPT_CAUSE_REG_PCI_0_SIDE         0x030
576 #define MV64340_I2O_OUTBOUND_INTERRUPT_MASK_REG_PCI_0_SIDE          0x034
577 #define MV64340_I2O_INBOUND_QUEUE_PORT_VIRTUAL_REG_PCI_0_SIDE       0x040
578 #define MV64340_I2O_OUTBOUND_QUEUE_PORT_VIRTUAL_REG_PCI_0_SIDE      0x044
579 #define MV64340_I2O_QUEUE_CONTROL_REG_PCI_0_SIDE                    0x050
580 #define MV64340_I2O_QUEUE_BASE_ADDR_REG_PCI_0_SIDE                  0x054
581 #define MV64340_I2O_INBOUND_FREE_HEAD_POINTER_REG_PCI_0_SIDE        0x060
582 #define MV64340_I2O_INBOUND_FREE_TAIL_POINTER_REG_PCI_0_SIDE        0x064
583 #define MV64340_I2O_INBOUND_POST_HEAD_POINTER_REG_PCI_0_SIDE        0x068
584 #define MV64340_I2O_INBOUND_POST_TAIL_POINTER_REG_PCI_0_SIDE        0x06C
585 #define MV64340_I2O_OUTBOUND_FREE_HEAD_POINTER_REG_PCI_0_SIDE       0x070
586 #define MV64340_I2O_OUTBOUND_FREE_TAIL_POINTER_REG_PCI_0_SIDE       0x074
587 #define MV64340_I2O_OUTBOUND_POST_HEAD_POINTER_REG_PCI_0_SIDE       0x0F8
588 #define MV64340_I2O_OUTBOUND_POST_TAIL_POINTER_REG_PCI_0_SIDE       0x0FC
589
590 #define MV64340_I2O_INBOUND_MESSAGE_REG0_PCI_1_SIDE                 0x090
591 #define MV64340_I2O_INBOUND_MESSAGE_REG1_PCI_1_SIDE                 0x094
592 #define MV64340_I2O_OUTBOUND_MESSAGE_REG0_PCI_1_SIDE                0x098
593 #define MV64340_I2O_OUTBOUND_MESSAGE_REG1_PCI_1_SIDE                0x09C
594 #define MV64340_I2O_INBOUND_DOORBELL_REG_PCI_1_SIDE                 0x0A0
595 #define MV64340_I2O_INBOUND_INTERRUPT_CAUSE_REG_PCI_1_SIDE          0x0A4
596 #define MV64340_I2O_INBOUND_INTERRUPT_MASK_REG_PCI_1_SIDE           0x0A8
597 #define MV64340_I2O_OUTBOUND_DOORBELL_REG_PCI_1_SIDE                0x0AC
598 #define MV64340_I2O_OUTBOUND_INTERRUPT_CAUSE_REG_PCI_1_SIDE         0x0B0
599 #define MV64340_I2O_OUTBOUND_INTERRUPT_MASK_REG_PCI_1_SIDE          0x0B4
600 #define MV64340_I2O_INBOUND_QUEUE_PORT_VIRTUAL_REG_PCI_1_SIDE       0x0C0
601 #define MV64340_I2O_OUTBOUND_QUEUE_PORT_VIRTUAL_REG_PCI_1_SIDE      0x0C4
602 #define MV64340_I2O_QUEUE_CONTROL_REG_PCI_1_SIDE                    0x0D0
603 #define MV64340_I2O_QUEUE_BASE_ADDR_REG_PCI_1_SIDE                  0x0D4
604 #define MV64340_I2O_INBOUND_FREE_HEAD_POINTER_REG_PCI_1_SIDE        0x0E0
605 #define MV64340_I2O_INBOUND_FREE_TAIL_POINTER_REG_PCI_1_SIDE        0x0E4
606 #define MV64340_I2O_INBOUND_POST_HEAD_POINTER_REG_PCI_1_SIDE        0x0E8
607 #define MV64340_I2O_INBOUND_POST_TAIL_POINTER_REG_PCI_1_SIDE        0x0EC
608 #define MV64340_I2O_OUTBOUND_FREE_HEAD_POINTER_REG_PCI_1_SIDE       0x0F0
609 #define MV64340_I2O_OUTBOUND_FREE_TAIL_POINTER_REG_PCI_1_SIDE       0x0F4
610 #define MV64340_I2O_OUTBOUND_POST_HEAD_POINTER_REG_PCI_1_SIDE       0x078
611 #define MV64340_I2O_OUTBOUND_POST_TAIL_POINTER_REG_PCI_1_SIDE       0x07C
612
613 #define MV64340_I2O_INBOUND_MESSAGE_REG0_CPU0_SIDE                  0x1C10
614 #define MV64340_I2O_INBOUND_MESSAGE_REG1_CPU0_SIDE                  0x1C14
615 #define MV64340_I2O_OUTBOUND_MESSAGE_REG0_CPU0_SIDE                 0x1C18
616 #define MV64340_I2O_OUTBOUND_MESSAGE_REG1_CPU0_SIDE                 0x1C1C
617 #define MV64340_I2O_INBOUND_DOORBELL_REG_CPU0_SIDE                  0x1C20
618 #define MV64340_I2O_INBOUND_INTERRUPT_CAUSE_REG_CPU0_SIDE           0x1C24
619 #define MV64340_I2O_INBOUND_INTERRUPT_MASK_REG_CPU0_SIDE            0x1C28
620 #define MV64340_I2O_OUTBOUND_DOORBELL_REG_CPU0_SIDE                 0x1C2C
621 #define MV64340_I2O_OUTBOUND_INTERRUPT_CAUSE_REG_CPU0_SIDE          0x1C30
622 #define MV64340_I2O_OUTBOUND_INTERRUPT_MASK_REG_CPU0_SIDE           0x1C34
623 #define MV64340_I2O_INBOUND_QUEUE_PORT_VIRTUAL_REG_CPU0_SIDE        0x1C40
624 #define MV64340_I2O_OUTBOUND_QUEUE_PORT_VIRTUAL_REG_CPU0_SIDE       0x1C44
625 #define MV64340_I2O_QUEUE_CONTROL_REG_CPU0_SIDE                     0x1C50
626 #define MV64340_I2O_QUEUE_BASE_ADDR_REG_CPU0_SIDE                   0x1C54
627 #define MV64340_I2O_INBOUND_FREE_HEAD_POINTER_REG_CPU0_SIDE         0x1C60
628 #define MV64340_I2O_INBOUND_FREE_TAIL_POINTER_REG_CPU0_SIDE         0x1C64
629 #define MV64340_I2O_INBOUND_POST_HEAD_POINTER_REG_CPU0_SIDE         0x1C68
630 #define MV64340_I2O_INBOUND_POST_TAIL_POINTER_REG_CPU0_SIDE         0x1C6C
631 #define MV64340_I2O_OUTBOUND_FREE_HEAD_POINTER_REG_CPU0_SIDE        0x1C70
632 #define MV64340_I2O_OUTBOUND_FREE_TAIL_POINTER_REG_CPU0_SIDE        0x1C74
633 #define MV64340_I2O_OUTBOUND_POST_HEAD_POINTER_REG_CPU0_SIDE        0x1CF8
634 #define MV64340_I2O_OUTBOUND_POST_TAIL_POINTER_REG_CPU0_SIDE        0x1CFC
635 #define MV64340_I2O_INBOUND_MESSAGE_REG0_CPU1_SIDE                  0x1C90
636 #define MV64340_I2O_INBOUND_MESSAGE_REG1_CPU1_SIDE                  0x1C94
637 #define MV64340_I2O_OUTBOUND_MESSAGE_REG0_CPU1_SIDE                 0x1C98
638 #define MV64340_I2O_OUTBOUND_MESSAGE_REG1_CPU1_SIDE                 0x1C9C
639 #define MV64340_I2O_INBOUND_DOORBELL_REG_CPU1_SIDE                  0x1CA0
640 #define MV64340_I2O_INBOUND_INTERRUPT_CAUSE_REG_CPU1_SIDE           0x1CA4
641 #define MV64340_I2O_INBOUND_INTERRUPT_MASK_REG_CPU1_SIDE            0x1CA8
642 #define MV64340_I2O_OUTBOUND_DOORBELL_REG_CPU1_SIDE                 0x1CAC
643 #define MV64340_I2O_OUTBOUND_INTERRUPT_CAUSE_REG_CPU1_SIDE          0x1CB0
644 #define MV64340_I2O_OUTBOUND_INTERRUPT_MASK_REG_CPU1_SIDE           0x1CB4
645 #define MV64340_I2O_INBOUND_QUEUE_PORT_VIRTUAL_REG_CPU1_SIDE        0x1CC0
646 #define MV64340_I2O_OUTBOUND_QUEUE_PORT_VIRTUAL_REG_CPU1_SIDE       0x1CC4
647 #define MV64340_I2O_QUEUE_CONTROL_REG_CPU1_SIDE                     0x1CD0
648 #define MV64340_I2O_QUEUE_BASE_ADDR_REG_CPU1_SIDE                   0x1CD4
649 #define MV64340_I2O_INBOUND_FREE_HEAD_POINTER_REG_CPU1_SIDE         0x1CE0
650 #define MV64340_I2O_INBOUND_FREE_TAIL_POINTER_REG_CPU1_SIDE         0x1CE4
651 #define MV64340_I2O_INBOUND_POST_HEAD_POINTER_REG_CPU1_SIDE         0x1CE8
652 #define MV64340_I2O_INBOUND_POST_TAIL_POINTER_REG_CPU1_SIDE         0x1CEC
653 #define MV64340_I2O_OUTBOUND_FREE_HEAD_POINTER_REG_CPU1_SIDE        0x1CF0
654 #define MV64340_I2O_OUTBOUND_FREE_TAIL_POINTER_REG_CPU1_SIDE        0x1CF4
655 #define MV64340_I2O_OUTBOUND_POST_HEAD_POINTER_REG_CPU1_SIDE        0x1C78
656 #define MV64340_I2O_OUTBOUND_POST_TAIL_POINTER_REG_CPU1_SIDE        0x1C7C
657
658 /****************************************/
659 /*        Ethernet Unit Registers               */
660 /****************************************/
661
662 /*******************************************/
663 /*          CUNIT  Registers               */
664 /*******************************************/
665
666          /* Address Decoding Register Map */
667            
668 #define MV64340_CUNIT_BASE_ADDR_REG0                                0xf200
669 #define MV64340_CUNIT_BASE_ADDR_REG1                                0xf208
670 #define MV64340_CUNIT_BASE_ADDR_REG2                                0xf210
671 #define MV64340_CUNIT_BASE_ADDR_REG3                                0xf218
672 #define MV64340_CUNIT_SIZE0                                         0xf204
673 #define MV64340_CUNIT_SIZE1                                         0xf20c
674 #define MV64340_CUNIT_SIZE2                                         0xf214
675 #define MV64340_CUNIT_SIZE3                                         0xf21c
676 #define MV64340_CUNIT_HIGH_ADDR_REMAP_REG0                          0xf240
677 #define MV64340_CUNIT_HIGH_ADDR_REMAP_REG1                          0xf244
678 #define MV64340_CUNIT_BASE_ADDR_ENABLE_REG                          0xf250
679 #define MV64340_MPSC0_ACCESS_PROTECTION_REG                         0xf254
680 #define MV64340_MPSC1_ACCESS_PROTECTION_REG                         0xf258
681 #define MV64340_CUNIT_INTERNAL_SPACE_BASE_ADDR_REG                  0xf25C
682
683         /*  Error Report Registers  */
684
685 #define MV64340_CUNIT_INTERRUPT_CAUSE_REG                           0xf310
686 #define MV64340_CUNIT_INTERRUPT_MASK_REG                            0xf314
687 #define MV64340_CUNIT_ERROR_ADDR                                    0xf318
688
689         /*  Cunit Control Registers */
690
691 #define MV64340_CUNIT_ARBITER_CONTROL_REG                           0xf300
692 #define MV64340_CUNIT_CONFIG_REG                                    0xb40c
693 #define MV64340_CUNIT_CRROSBAR_TIMEOUT_REG                          0xf304
694
695         /*  Cunit Debug Registers   */
696
697 #define MV64340_CUNIT_DEBUG_LOW                                     0xf340
698 #define MV64340_CUNIT_DEBUG_HIGH                                    0xf344
699 #define MV64340_CUNIT_MMASK                                         0xf380
700
701         /*  MPSCs Clocks Routing Registers  */
702
703 #define MV64340_MPSC_ROUTING_REG                                    0xb400
704 #define MV64340_MPSC_RX_CLOCK_ROUTING_REG                           0xb404
705 #define MV64340_MPSC_TX_CLOCK_ROUTING_REG                           0xb408
706
707         /*  MPSCs Interrupts Registers    */
708
709 #define MV64340_MPSC_CAUSE_REG(port)                               (0xb804 + (port<<3))
710 #define MV64340_MPSC_MASK_REG(port)                                (0xb884 + (port<<3))
711  
712 #define MV64340_MPSC_MAIN_CONFIG_LOW(port)                         (0x8000 + (port<<12))
713 #define MV64340_MPSC_MAIN_CONFIG_HIGH(port)                        (0x8004 + (port<<12))    
714 #define MV64340_MPSC_PROTOCOL_CONFIG(port)                         (0x8008 + (port<<12))    
715 #define MV64340_MPSC_CHANNEL_REG1(port)                            (0x800c + (port<<12))    
716 #define MV64340_MPSC_CHANNEL_REG2(port)                            (0x8010 + (port<<12))    
717 #define MV64340_MPSC_CHANNEL_REG3(port)                            (0x8014 + (port<<12))    
718 #define MV64340_MPSC_CHANNEL_REG4(port)                            (0x8018 + (port<<12))    
719 #define MV64340_MPSC_CHANNEL_REG5(port)                            (0x801c + (port<<12))    
720 #define MV64340_MPSC_CHANNEL_REG6(port)                            (0x8020 + (port<<12))    
721 #define MV64340_MPSC_CHANNEL_REG7(port)                            (0x8024 + (port<<12))    
722 #define MV64340_MPSC_CHANNEL_REG8(port)                            (0x8028 + (port<<12))    
723 #define MV64340_MPSC_CHANNEL_REG9(port)                            (0x802c + (port<<12))    
724 #define MV64340_MPSC_CHANNEL_REG10(port)                           (0x8030 + (port<<12))    
725         
726         /*  MPSC0 Registers      */
727
728
729 /***************************************/
730 /*          SDMA Registers             */
731 /***************************************/
732
733 #define MV64340_SDMA_CONFIG_REG(channel)                        (0x4000 + (channel<<13))        
734 #define MV64340_SDMA_COMMAND_REG(channel)                       (0x4008 + (channel<<13))        
735 #define MV64340_SDMA_CURRENT_RX_DESCRIPTOR_POINTER(channel)     (0x4810 + (channel<<13))        
736 #define MV64340_SDMA_CURRENT_TX_DESCRIPTOR_POINTER(channel)     (0x4c10 + (channel<<13))        
737 #define MV64340_SDMA_FIRST_TX_DESCRIPTOR_POINTER(channel)       (0x4c14 + (channel<<13)) 
738
739 #define MV64340_SDMA_CAUSE_REG                                      0xb800
740 #define MV64340_SDMA_MASK_REG                                       0xb880
741          
742 /* BRG Interrupts */
743
744 #define MV64340_BRG_CONFIG_REG(brg)                              (0xb200 + (brg<<3))
745 #define MV64340_BRG_BAUDE_TUNING_REG(brg)                        (0xb208 + (brg<<3))
746 #define MV64340_BRG_CAUSE_REG                                       0xb834
747 #define MV64340_BRG_MASK_REG                                        0xb8b4
748
749 /****************************************/
750 /* DMA Channel Control                  */
751 /****************************************/
752
753 #define MV64340_DMA_CHANNEL0_CONTROL                                0x840
754 #define MV64340_DMA_CHANNEL0_CONTROL_HIGH                           0x880
755 #define MV64340_DMA_CHANNEL1_CONTROL                                0x844
756 #define MV64340_DMA_CHANNEL1_CONTROL_HIGH                           0x884
757 #define MV64340_DMA_CHANNEL2_CONTROL                                0x848
758 #define MV64340_DMA_CHANNEL2_CONTROL_HIGH                           0x888
759 #define MV64340_DMA_CHANNEL3_CONTROL                                0x84C
760 #define MV64340_DMA_CHANNEL3_CONTROL_HIGH                           0x88C
761
762
763 /****************************************/
764 /*           IDMA Registers             */
765 /****************************************/
766
767 #define MV64340_DMA_CHANNEL0_BYTE_COUNT                             0x800
768 #define MV64340_DMA_CHANNEL1_BYTE_COUNT                             0x804
769 #define MV64340_DMA_CHANNEL2_BYTE_COUNT                             0x808
770 #define MV64340_DMA_CHANNEL3_BYTE_COUNT                             0x80C
771 #define MV64340_DMA_CHANNEL0_SOURCE_ADDR                            0x810
772 #define MV64340_DMA_CHANNEL1_SOURCE_ADDR                            0x814
773 #define MV64340_DMA_CHANNEL2_SOURCE_ADDR                            0x818
774 #define MV64340_DMA_CHANNEL3_SOURCE_ADDR                            0x81c
775 #define MV64340_DMA_CHANNEL0_DESTINATION_ADDR                       0x820
776 #define MV64340_DMA_CHANNEL1_DESTINATION_ADDR                       0x824
777 #define MV64340_DMA_CHANNEL2_DESTINATION_ADDR                       0x828
778 #define MV64340_DMA_CHANNEL3_DESTINATION_ADDR                       0x82C
779 #define MV64340_DMA_CHANNEL0_NEXT_DESCRIPTOR_POINTER                0x830
780 #define MV64340_DMA_CHANNEL1_NEXT_DESCRIPTOR_POINTER                0x834
781 #define MV64340_DMA_CHANNEL2_NEXT_DESCRIPTOR_POINTER                0x838
782 #define MV64340_DMA_CHANNEL3_NEXT_DESCRIPTOR_POINTER                0x83C
783 #define MV64340_DMA_CHANNEL0_CURRENT_DESCRIPTOR_POINTER             0x870
784 #define MV64340_DMA_CHANNEL1_CURRENT_DESCRIPTOR_POINTER             0x874
785 #define MV64340_DMA_CHANNEL2_CURRENT_DESCRIPTOR_POINTER             0x878
786 #define MV64340_DMA_CHANNEL3_CURRENT_DESCRIPTOR_POINTER             0x87C
787
788  /*  IDMA Address Decoding Base Address Registers  */
789  
790 #define MV64340_DMA_BASE_ADDR_REG0                                  0xa00
791 #define MV64340_DMA_BASE_ADDR_REG1                                  0xa08
792 #define MV64340_DMA_BASE_ADDR_REG2                                  0xa10
793 #define MV64340_DMA_BASE_ADDR_REG3                                  0xa18
794 #define MV64340_DMA_BASE_ADDR_REG4                                  0xa20
795 #define MV64340_DMA_BASE_ADDR_REG5                                  0xa28
796 #define MV64340_DMA_BASE_ADDR_REG6                                  0xa30
797 #define MV64340_DMA_BASE_ADDR_REG7                                  0xa38
798  
799  /*  IDMA Address Decoding Size Address Register   */
800  
801 #define MV64340_DMA_SIZE_REG0                                       0xa04
802 #define MV64340_DMA_SIZE_REG1                                       0xa0c
803 #define MV64340_DMA_SIZE_REG2                                       0xa14
804 #define MV64340_DMA_SIZE_REG3                                       0xa1c
805 #define MV64340_DMA_SIZE_REG4                                       0xa24
806 #define MV64340_DMA_SIZE_REG5                                       0xa2c
807 #define MV64340_DMA_SIZE_REG6                                       0xa34
808 #define MV64340_DMA_SIZE_REG7                                       0xa3C
809
810  /* IDMA Address Decoding High Address Remap and Access 
811                   Protection Registers                    */
812                   
813 #define MV64340_DMA_HIGH_ADDR_REMAP_REG0                            0xa60
814 #define MV64340_DMA_HIGH_ADDR_REMAP_REG1                            0xa64
815 #define MV64340_DMA_HIGH_ADDR_REMAP_REG2                            0xa68
816 #define MV64340_DMA_HIGH_ADDR_REMAP_REG3                            0xa6C
817 #define MV64340_DMA_BASE_ADDR_ENABLE_REG                            0xa80
818 #define MV64340_DMA_CHANNEL0_ACCESS_PROTECTION_REG                  0xa70
819 #define MV64340_DMA_CHANNEL1_ACCESS_PROTECTION_REG                  0xa74
820 #define MV64340_DMA_CHANNEL2_ACCESS_PROTECTION_REG                  0xa78
821 #define MV64340_DMA_CHANNEL3_ACCESS_PROTECTION_REG                  0xa7c
822 #define MV64340_DMA_ARBITER_CONTROL                                 0x860
823 #define MV64340_DMA_CROSS_BAR_TIMEOUT                               0x8d0
824
825  /*  IDMA Headers Retarget Registers   */
826
827 #define MV64340_DMA_HEADERS_RETARGET_CONTROL                        0xa84
828 #define MV64340_DMA_HEADERS_RETARGET_BASE                           0xa88
829
830  /*  IDMA Interrupt Register  */
831
832 #define MV64340_DMA_INTERRUPT_CAUSE_REG                             0x8c0
833 #define MV64340_DMA_INTERRUPT_CAUSE_MASK                            0x8c4
834 #define MV64340_DMA_ERROR_ADDR                                      0x8c8
835 #define MV64340_DMA_ERROR_SELECT                                    0x8cc
836
837  /*  IDMA Debug Register ( for internal use )    */
838
839 #define MV64340_DMA_DEBUG_LOW                                       0x8e0
840 #define MV64340_DMA_DEBUG_HIGH                                      0x8e4
841 #define MV64340_DMA_SPARE                                           0xA8C
842
843 /****************************************/
844 /* Timer_Counter                        */
845 /****************************************/
846
847 #define MV64340_TIMER_COUNTER0                                      0x850
848 #define MV64340_TIMER_COUNTER1                                      0x854
849 #define MV64340_TIMER_COUNTER2                                      0x858
850 #define MV64340_TIMER_COUNTER3                                      0x85C
851 #define MV64340_TIMER_COUNTER_0_3_CONTROL                           0x864
852 #define MV64340_TIMER_COUNTER_0_3_INTERRUPT_CAUSE                   0x868
853 #define MV64340_TIMER_COUNTER_0_3_INTERRUPT_MASK                    0x86c
854
855 /****************************************/
856 /*         Watchdog registers           */
857 /****************************************/
858
859 #define MV64340_WATCHDOG_CONFIG_REG                                 0xb410
860 #define MV64340_WATCHDOG_VALUE_REG                                  0xb414
861
862 /****************************************/
863 /* I2C Registers                        */
864 /****************************************/
865
866 #define MV64XXX_I2C_CTLR_NAME                                   "mv64xxx_i2c"
867 #define MV64XXX_I2C_OFFSET                                          0xc000
868 #define MV64XXX_I2C_REG_BLOCK_SIZE                                  0x0020
869
870 /****************************************/
871 /* GPP Interface Registers              */
872 /****************************************/
873
874 #define MV64340_GPP_IO_CONTROL                                      0xf100
875 #define MV64340_GPP_LEVEL_CONTROL                                   0xf110
876 #define MV64340_GPP_VALUE                                           0xf104
877 #define MV64340_GPP_INTERRUPT_CAUSE                                 0xf108
878 #define MV64340_GPP_INTERRUPT_MASK0                                 0xf10c
879 #define MV64340_GPP_INTERRUPT_MASK1                                 0xf114
880 #define MV64340_GPP_VALUE_SET                                       0xf118
881 #define MV64340_GPP_VALUE_CLEAR                                     0xf11c
882
883 /****************************************/
884 /* Interrupt Controller Registers       */
885 /****************************************/
886
887 /****************************************/
888 /* Interrupts                           */
889 /****************************************/
890
891 #define MV64340_MAIN_INTERRUPT_CAUSE_LOW                            0x004
892 #define MV64340_MAIN_INTERRUPT_CAUSE_HIGH                           0x00c
893 #define MV64340_CPU_INTERRUPT0_MASK_LOW                             0x014
894 #define MV64340_CPU_INTERRUPT0_MASK_HIGH                            0x01c
895 #define MV64340_CPU_INTERRUPT0_SELECT_CAUSE                         0x024
896 #define MV64340_CPU_INTERRUPT1_MASK_LOW                             0x034
897 #define MV64340_CPU_INTERRUPT1_MASK_HIGH                            0x03c
898 #define MV64340_CPU_INTERRUPT1_SELECT_CAUSE                         0x044
899 #define MV64340_INTERRUPT0_MASK_0_LOW                               0x054
900 #define MV64340_INTERRUPT0_MASK_0_HIGH                              0x05c
901 #define MV64340_INTERRUPT0_SELECT_CAUSE                             0x064
902 #define MV64340_INTERRUPT1_MASK_0_LOW                               0x074
903 #define MV64340_INTERRUPT1_MASK_0_HIGH                              0x07c
904 #define MV64340_INTERRUPT1_SELECT_CAUSE                             0x084
905
906 /****************************************/
907 /*      MPP Interface Registers         */
908 /****************************************/
909
910 #define MV64340_MPP_CONTROL0                                        0xf000
911 #define MV64340_MPP_CONTROL1                                        0xf004
912 #define MV64340_MPP_CONTROL2                                        0xf008
913 #define MV64340_MPP_CONTROL3                                        0xf00c
914
915 /****************************************/
916 /*    Serial Initialization registers   */
917 /****************************************/
918
919 #define MV64340_SERIAL_INIT_LAST_DATA                               0xf324
920 #define MV64340_SERIAL_INIT_CONTROL                                 0xf328
921 #define MV64340_SERIAL_INIT_STATUS                                  0xf32c
922
923 extern void mv64340_irq_init(unsigned int base);
924
925 /* MPSC Platform Device, Driver Data (Shared register regions) */
926 #define MPSC_SHARED_NAME                "mpsc_shared"
927
928 #define MPSC_ROUTING_BASE_ORDER         0
929 #define MPSC_SDMA_INTR_BASE_ORDER       1
930
931 #define MPSC_ROUTING_REG_BLOCK_SIZE     0x000c
932 #define MPSC_SDMA_INTR_REG_BLOCK_SIZE   0x0084
933
934 struct mpsc_shared_pdata {
935         u32     mrr_val;
936         u32     rcrr_val;
937         u32     tcrr_val;
938         u32     intr_cause_val;
939         u32     intr_mask_val;
940 };
941
942 /* MPSC Platform Device, Driver Data */
943 #define MPSC_CTLR_NAME                  "mpsc"
944
945 #define MPSC_BASE_ORDER                 0
946 #define MPSC_SDMA_BASE_ORDER            1
947 #define MPSC_BRG_BASE_ORDER             2
948
949 #define MPSC_REG_BLOCK_SIZE             0x0038
950 #define MPSC_SDMA_REG_BLOCK_SIZE        0x0c18
951 #define MPSC_BRG_REG_BLOCK_SIZE         0x0008
952
953 struct mpsc_pdata {
954         u8      mirror_regs;
955         u8      cache_mgmt;
956         u8      max_idle;
957         int     default_baud;
958         int     default_bits;
959         int     default_parity;
960         int     default_flow;
961         u32     chr_1_val;
962         u32     chr_2_val;
963         u32     chr_10_val;
964         u32     mpcr_val;
965         u32     bcr_val;
966         u8      brg_can_tune;
967         u8      brg_clk_src;
968         u32     brg_clk_freq;
969 };
970
971 /* i2c Platform Device, Driver Data */
972 struct mv64xxx_i2c_pdata {
973         u32     freq_m;
974         u32     freq_n;
975         u32     timeout;        /* In milliseconds */
976         u32     retries;
977 };
978
979 /* Watchdog Platform Device, Driver Data */
980 #define MV64x60_WDT_NAME                        "mv64x60_wdt"
981
982 struct mv64x60_wdt_pdata {
983         int     timeout;        /* watchdog expiry in seconds, default 10 */
984         int     bus_clk;        /* bus clock in MHz, default 133 */
985 };
986
987 #endif /* __ASM_MV643XX_H */