regulator: Add WM8350 regulator support
[linux-2.6.git] / include / linux / mfd / wm8350 / pmic.h
1 /*
2  * pmic.h  --  Power Managment Driver for Wolfson WM8350 PMIC
3  *
4  * Copyright 2007 Wolfson Microelectronics PLC
5  *
6  *  This program is free software; you can redistribute  it and/or modify it
7  *  under  the terms of  the GNU General  Public License as published by the
8  *  Free Software Foundation;  either version 2 of the  License, or (at your
9  *  option) any later version.
10  *
11  */
12
13 #ifndef __LINUX_MFD_WM8350_PMIC_H
14 #define __LINUX_MFD_WM8350_PMIC_H
15
16 /*
17  * Register values.
18  */
19
20 #define WM8350_CURRENT_SINK_DRIVER_A            0xAC
21 #define WM8350_CSA_FLASH_CONTROL                0xAD
22 #define WM8350_CURRENT_SINK_DRIVER_B            0xAE
23 #define WM8350_CSB_FLASH_CONTROL                0xAF
24 #define WM8350_DCDC_LDO_REQUESTED               0xB0
25 #define WM8350_DCDC_ACTIVE_OPTIONS              0xB1
26 #define WM8350_DCDC_SLEEP_OPTIONS               0xB2
27 #define WM8350_POWER_CHECK_COMPARATOR           0xB3
28 #define WM8350_DCDC1_CONTROL                    0xB4
29 #define WM8350_DCDC1_TIMEOUTS                   0xB5
30 #define WM8350_DCDC1_LOW_POWER                  0xB6
31 #define WM8350_DCDC2_CONTROL                    0xB7
32 #define WM8350_DCDC2_TIMEOUTS                   0xB8
33 #define WM8350_DCDC3_CONTROL                    0xBA
34 #define WM8350_DCDC3_TIMEOUTS                   0xBB
35 #define WM8350_DCDC3_LOW_POWER                  0xBC
36 #define WM8350_DCDC4_CONTROL                    0xBD
37 #define WM8350_DCDC4_TIMEOUTS                   0xBE
38 #define WM8350_DCDC4_LOW_POWER                  0xBF
39 #define WM8350_DCDC5_CONTROL                    0xC0
40 #define WM8350_DCDC5_TIMEOUTS                   0xC1
41 #define WM8350_DCDC6_CONTROL                    0xC3
42 #define WM8350_DCDC6_TIMEOUTS                   0xC4
43 #define WM8350_DCDC6_LOW_POWER                  0xC5
44 #define WM8350_LIMIT_SWITCH_CONTROL             0xC7
45 #define WM8350_LDO1_CONTROL                     0xC8
46 #define WM8350_LDO1_TIMEOUTS                    0xC9
47 #define WM8350_LDO1_LOW_POWER                   0xCA
48 #define WM8350_LDO2_CONTROL                     0xCB
49 #define WM8350_LDO2_TIMEOUTS                    0xCC
50 #define WM8350_LDO2_LOW_POWER                   0xCD
51 #define WM8350_LDO3_CONTROL                     0xCE
52 #define WM8350_LDO3_TIMEOUTS                    0xCF
53 #define WM8350_LDO3_LOW_POWER                   0xD0
54 #define WM8350_LDO4_CONTROL                     0xD1
55 #define WM8350_LDO4_TIMEOUTS                    0xD2
56 #define WM8350_LDO4_LOW_POWER                   0xD3
57 #define WM8350_VCC_FAULT_MASKS                  0xD7
58 #define WM8350_MAIN_BANDGAP_CONTROL             0xD8
59 #define WM8350_OSC_CONTROL                      0xD9
60 #define WM8350_RTC_TICK_CONTROL                 0xDA
61 #define WM8350_SECURITY                         0xDB
62 #define WM8350_RAM_BIST_1                       0xDC
63 #define WM8350_DCDC_LDO_STATUS                  0xE1
64 #define WM8350_GPIO_PIN_STATUS                  0xE6
65
66 #define WM8350_DCDC1_FORCE_PWM                  0xF8
67 #define WM8350_DCDC3_FORCE_PWM                  0xFA
68 #define WM8350_DCDC4_FORCE_PWM                  0xFB
69 #define WM8350_DCDC6_FORCE_PWM                  0xFD
70
71 /*
72  * R172 (0xAC) - Current Sink Driver A
73  */
74 #define WM8350_CS1_HIB_MODE                     0x1000
75 #define WM8350_CS1_HIB_MODE_MASK                0x1000
76 #define WM8350_CS1_HIB_MODE_SHIFT                   12
77 #define WM8350_CS1_ISEL_MASK                    0x003F
78 #define WM8350_CS1_ISEL_SHIFT                        0
79
80 /* Bit values for R172 (0xAC) */
81 #define WM8350_CS1_HIB_MODE_DISABLE                  0
82 #define WM8350_CS1_HIB_MODE_LEAVE                    1
83
84 #define WM8350_CS1_ISEL_220M                      0x3F
85
86 /*
87  * R173 (0xAD) - CSA Flash control
88  */
89 #define WM8350_CS1_FLASH_MODE                   0x8000
90 #define WM8350_CS1_TRIGSRC                      0x4000
91 #define WM8350_CS1_DRIVE                        0x2000
92 #define WM8350_CS1_FLASH_DUR_MASK               0x0300
93 #define WM8350_CS1_OFF_RAMP_MASK                0x0030
94 #define WM8350_CS1_ON_RAMP_MASK                 0x0003
95
96 /*
97  * R174 (0xAE) - Current Sink Driver B
98  */
99 #define WM8350_CS2_HIB_MODE                     0x1000
100 #define WM8350_CS2_ISEL_MASK                    0x003F
101
102 /*
103  * R175 (0xAF) - CSB Flash control
104  */
105 #define WM8350_CS2_FLASH_MODE                   0x8000
106 #define WM8350_CS2_TRIGSRC                      0x4000
107 #define WM8350_CS2_DRIVE                        0x2000
108 #define WM8350_CS2_FLASH_DUR_MASK               0x0300
109 #define WM8350_CS2_OFF_RAMP_MASK                0x0030
110 #define WM8350_CS2_ON_RAMP_MASK                 0x0003
111
112 /*
113  * R176 (0xB0) - DCDC/LDO requested
114  */
115 #define WM8350_LS_ENA                           0x8000
116 #define WM8350_LDO4_ENA                         0x0800
117 #define WM8350_LDO3_ENA                         0x0400
118 #define WM8350_LDO2_ENA                         0x0200
119 #define WM8350_LDO1_ENA                         0x0100
120 #define WM8350_DC6_ENA                          0x0020
121 #define WM8350_DC5_ENA                          0x0010
122 #define WM8350_DC4_ENA                          0x0008
123 #define WM8350_DC3_ENA                          0x0004
124 #define WM8350_DC2_ENA                          0x0002
125 #define WM8350_DC1_ENA                          0x0001
126
127 /*
128  * R177 (0xB1) - DCDC Active options
129  */
130 #define WM8350_PUTO_MASK                        0x3000
131 #define WM8350_PWRUP_DELAY_MASK                 0x0300
132 #define WM8350_DC6_ACTIVE                       0x0020
133 #define WM8350_DC4_ACTIVE                       0x0008
134 #define WM8350_DC3_ACTIVE                       0x0004
135 #define WM8350_DC1_ACTIVE                       0x0001
136
137 /*
138  * R178 (0xB2) - DCDC Sleep options
139  */
140 #define WM8350_DC6_SLEEP                        0x0020
141 #define WM8350_DC4_SLEEP                        0x0008
142 #define WM8350_DC3_SLEEP                        0x0004
143 #define WM8350_DC1_SLEEP                        0x0001
144
145 /*
146  * R179 (0xB3) - Power-check comparator
147  */
148 #define WM8350_PCCMP_ERRACT                     0x4000
149 #define WM8350_PCCMP_RAIL                       0x0100
150 #define WM8350_PCCMP_OFF_THR_MASK               0x0070
151 #define WM8350_PCCMP_ON_THR_MASK                0x0007
152
153 /*
154  * R180 (0xB4) - DCDC1 Control
155  */
156 #define WM8350_DC1_OPFLT                        0x0400
157 #define WM8350_DC1_VSEL_MASK                    0x007F
158 #define WM8350_DC1_VSEL_SHIFT                        0
159
160 /*
161  * R181 (0xB5) - DCDC1 Timeouts
162  */
163 #define WM8350_DC1_ERRACT_MASK                  0xC000
164 #define WM8350_DC1_ERRACT_SHIFT                     14
165 #define WM8350_DC1_ENSLOT_MASK                  0x3C00
166 #define WM8350_DC1_ENSLOT_SHIFT                     10
167 #define WM8350_DC1_SDSLOT_MASK                  0x03C0
168 #define WM8350_DC1_UVTO_MASK                    0x0030
169 #define WM8350_DC1_SDSLOT_SHIFT                      6
170
171 /* Bit values for R181 (0xB5) */
172 #define WM8350_DC1_ERRACT_NONE                       0
173 #define WM8350_DC1_ERRACT_SHUTDOWN_CONV              1
174 #define WM8350_DC1_ERRACT_SHUTDOWN_SYS               2
175
176 /*
177  * R182 (0xB6) - DCDC1 Low Power
178  */
179 #define WM8350_DC1_HIB_MODE_MASK                0x7000
180 #define WM8350_DC1_HIB_TRIG_MASK                0x0300
181 #define WM8350_DC1_VIMG_MASK                    0x007F
182
183 /*
184  * R183 (0xB7) - DCDC2 Control
185  */
186 #define WM8350_DC2_MODE                         0x4000
187 #define WM8350_DC2_MODE_MASK                    0x4000
188 #define WM8350_DC2_MODE_SHIFT                       14
189 #define WM8350_DC2_HIB_MODE                     0x1000
190 #define WM8350_DC2_HIB_MODE_MASK                0x1000
191 #define WM8350_DC2_HIB_MODE_SHIFT                   12
192 #define WM8350_DC2_HIB_TRIG_MASK                0x0300
193 #define WM8350_DC2_HIB_TRIG_SHIFT                    8
194 #define WM8350_DC2_ILIM                         0x0040
195 #define WM8350_DC2_ILIM_MASK                    0x0040
196 #define WM8350_DC2_ILIM_SHIFT                        6
197 #define WM8350_DC2_RMP_MASK                     0x0018
198 #define WM8350_DC2_RMP_SHIFT                         3
199 #define WM8350_DC2_FBSRC_MASK                   0x0003
200 #define WM8350_DC2_FBSRC_SHIFT                       0
201
202 /* Bit values for R183 (0xB7) */
203 #define WM8350_DC2_MODE_BOOST                        0
204 #define WM8350_DC2_MODE_SWITCH                       1
205
206 #define WM8350_DC2_HIB_MODE_ACTIVE                   1
207 #define WM8350_DC2_HIB_MODE_DISABLE                  0
208
209 #define WM8350_DC2_HIB_TRIG_NONE                     0
210 #define WM8350_DC2_HIB_TRIG_LPWR1                    1
211 #define WM8350_DC2_HIB_TRIG_LPWR2                    2
212 #define WM8350_DC2_HIB_TRIG_LPWR3                    3
213
214 #define WM8350_DC2_ILIM_HIGH                         0
215 #define WM8350_DC2_ILIM_LOW                          1
216
217 #define WM8350_DC2_RMP_30V                           0
218 #define WM8350_DC2_RMP_20V                           1
219 #define WM8350_DC2_RMP_10V                           2
220 #define WM8350_DC2_RMP_5V                            3
221
222 #define WM8350_DC2_FBSRC_FB2                         0
223 #define WM8350_DC2_FBSRC_ISINKA                      1
224 #define WM8350_DC2_FBSRC_ISINKB                      2
225 #define WM8350_DC2_FBSRC_USB                         3
226
227 /*
228  * R184 (0xB8) - DCDC2 Timeouts
229  */
230 #define WM8350_DC2_ERRACT_MASK                  0xC000
231 #define WM8350_DC2_ERRACT_SHIFT                     14
232 #define WM8350_DC2_ENSLOT_MASK                  0x3C00
233 #define WM8350_DC2_ENSLOT_SHIFT                     10
234 #define WM8350_DC2_SDSLOT_MASK                  0x03C0
235 #define WM8350_DC2_UVTO_MASK                    0x0030
236
237 /* Bit values for R184 (0xB8) */
238 #define WM8350_DC2_ERRACT_NONE                       0
239 #define WM8350_DC2_ERRACT_SHUTDOWN_CONV              1
240 #define WM8350_DC2_ERRACT_SHUTDOWN_SYS               2
241
242 /*
243  * R186 (0xBA) - DCDC3 Control
244  */
245 #define WM8350_DC3_OPFLT                        0x0400
246 #define WM8350_DC3_VSEL_MASK                    0x007F
247 #define WM8350_DC3_VSEL_SHIFT                        0
248
249 /*
250  * R187 (0xBB) - DCDC3 Timeouts
251  */
252 #define WM8350_DC3_ERRACT_MASK                  0xC000
253 #define WM8350_DC3_ERRACT_SHIFT                     14
254 #define WM8350_DC3_ENSLOT_MASK                  0x3C00
255 #define WM8350_DC3_ENSLOT_SHIFT                     10
256 #define WM8350_DC3_SDSLOT_MASK                  0x03C0
257 #define WM8350_DC3_UVTO_MASK                    0x0030
258 #define WM8350_DC3_SDSLOT_SHIFT                      6
259
260 /* Bit values for R187 (0xBB) */
261 #define WM8350_DC3_ERRACT_NONE                       0
262 #define WM8350_DC3_ERRACT_SHUTDOWN_CONV              1
263 #define WM8350_DC3_ERRACT_SHUTDOWN_SYS               2
264 /*
265  * R188 (0xBC) - DCDC3 Low Power
266  */
267 #define WM8350_DC3_HIB_MODE_MASK                0x7000
268 #define WM8350_DC3_HIB_TRIG_MASK                0x0300
269 #define WM8350_DC3_VIMG_MASK                    0x007F
270
271 /*
272  * R189 (0xBD) - DCDC4 Control
273  */
274 #define WM8350_DC4_OPFLT                        0x0400
275 #define WM8350_DC4_VSEL_MASK                    0x007F
276 #define WM8350_DC4_VSEL_SHIFT                        0
277
278 /*
279  * R190 (0xBE) - DCDC4 Timeouts
280  */
281 #define WM8350_DC4_ERRACT_MASK                  0xC000
282 #define WM8350_DC4_ERRACT_SHIFT                     14
283 #define WM8350_DC4_ENSLOT_MASK                  0x3C00
284 #define WM8350_DC4_ENSLOT_SHIFT                     10
285 #define WM8350_DC4_SDSLOT_MASK                  0x03C0
286 #define WM8350_DC4_UVTO_MASK                    0x0030
287 #define WM8350_DC4_SDSLOT_SHIFT                      6
288
289 /* Bit values for R190 (0xBE) */
290 #define WM8350_DC4_ERRACT_NONE                       0
291 #define WM8350_DC4_ERRACT_SHUTDOWN_CONV              1
292 #define WM8350_DC4_ERRACT_SHUTDOWN_SYS               2
293
294 /*
295  * R191 (0xBF) - DCDC4 Low Power
296  */
297 #define WM8350_DC4_HIB_MODE_MASK                0x7000
298 #define WM8350_DC4_HIB_TRIG_MASK                0x0300
299 #define WM8350_DC4_VIMG_MASK                    0x007F
300
301 /*
302  * R192 (0xC0) - DCDC5 Control
303  */
304 #define WM8350_DC5_MODE                         0x4000
305 #define WM8350_DC5_MODE_MASK                    0x4000
306 #define WM8350_DC5_MODE_SHIFT                       14
307 #define WM8350_DC5_HIB_MODE                     0x1000
308 #define WM8350_DC5_HIB_MODE_MASK                0x1000
309 #define WM8350_DC5_HIB_MODE_SHIFT                   12
310 #define WM8350_DC5_HIB_TRIG_MASK                0x0300
311 #define WM8350_DC5_HIB_TRIG_SHIFT                    8
312 #define WM8350_DC5_ILIM                         0x0040
313 #define WM8350_DC5_ILIM_MASK                    0x0040
314 #define WM8350_DC5_ILIM_SHIFT                        6
315 #define WM8350_DC5_RMP_MASK                     0x0018
316 #define WM8350_DC5_RMP_SHIFT                         3
317 #define WM8350_DC5_FBSRC_MASK                   0x0003
318 #define WM8350_DC5_FBSRC_SHIFT                       0
319
320 /* Bit values for R192 (0xC0) */
321 #define WM8350_DC5_MODE_BOOST                        0
322 #define WM8350_DC5_MODE_SWITCH                       1
323
324 #define WM8350_DC5_HIB_MODE_ACTIVE                   1
325 #define WM8350_DC5_HIB_MODE_DISABLE                  0
326
327 #define WM8350_DC5_HIB_TRIG_NONE                     0
328 #define WM8350_DC5_HIB_TRIG_LPWR1                    1
329 #define WM8350_DC5_HIB_TRIG_LPWR2                    2
330 #define WM8350_DC5_HIB_TRIG_LPWR3                    3
331
332 #define WM8350_DC5_ILIM_HIGH                         0
333 #define WM8350_DC5_ILIM_LOW                          1
334
335 #define WM8350_DC5_RMP_30V                           0
336 #define WM8350_DC5_RMP_20V                           1
337 #define WM8350_DC5_RMP_10V                           2
338 #define WM8350_DC5_RMP_5V                            3
339
340 #define WM8350_DC5_FBSRC_FB2                         0
341 #define WM8350_DC5_FBSRC_ISINKA                      1
342 #define WM8350_DC5_FBSRC_ISINKB                      2
343 #define WM8350_DC5_FBSRC_USB                         3
344
345 /*
346  * R193 (0xC1) - DCDC5 Timeouts
347  */
348 #define WM8350_DC5_ERRACT_MASK                  0xC000
349 #define WM8350_DC5_ERRACT_SHIFT                     14
350 #define WM8350_DC5_ENSLOT_MASK                  0x3C00
351 #define WM8350_DC5_ENSLOT_SHIFT                     10
352 #define WM8350_DC5_SDSLOT_MASK                  0x03C0
353 #define WM8350_DC5_UVTO_MASK                    0x0030
354 #define WM8350_DC5_SDSLOT_SHIFT                      6
355
356 /* Bit values for R193 (0xC1) */
357 #define WM8350_DC5_ERRACT_NONE                       0
358 #define WM8350_DC5_ERRACT_SHUTDOWN_CONV              1
359 #define WM8350_DC5_ERRACT_SHUTDOWN_SYS               2
360
361 /*
362  * R195 (0xC3) - DCDC6 Control
363  */
364 #define WM8350_DC6_OPFLT                        0x0400
365 #define WM8350_DC6_VSEL_MASK                    0x007F
366 #define WM8350_DC6_VSEL_SHIFT                        0
367
368 /*
369  * R196 (0xC4) - DCDC6 Timeouts
370  */
371 #define WM8350_DC6_ERRACT_MASK                  0xC000
372 #define WM8350_DC6_ERRACT_SHIFT                     14
373 #define WM8350_DC6_ENSLOT_MASK                  0x3C00
374 #define WM8350_DC6_ENSLOT_SHIFT                     10
375 #define WM8350_DC6_SDSLOT_MASK                  0x03C0
376 #define WM8350_DC6_UVTO_MASK                    0x0030
377 #define WM8350_DC6_SDSLOT_SHIFT                      6
378
379 /* Bit values for R196 (0xC4) */
380 #define WM8350_DC6_ERRACT_NONE                       0
381 #define WM8350_DC6_ERRACT_SHUTDOWN_CONV              1
382 #define WM8350_DC6_ERRACT_SHUTDOWN_SYS               2
383
384 /*
385  * R197 (0xC5) - DCDC6 Low Power
386  */
387 #define WM8350_DC6_HIB_MODE_MASK                0x7000
388 #define WM8350_DC6_HIB_TRIG_MASK                0x0300
389 #define WM8350_DC6_VIMG_MASK                    0x007F
390
391 /*
392  * R199 (0xC7) - Limit Switch Control
393  */
394 #define WM8350_LS_ERRACT_MASK                   0xC000
395 #define WM8350_LS_ERRACT_SHIFT                      14
396 #define WM8350_LS_ENSLOT_MASK                   0x3C00
397 #define WM8350_LS_ENSLOT_SHIFT                      10
398 #define WM8350_LS_SDSLOT_MASK                   0x03C0
399 #define WM8350_LS_SDSLOT_SHIFT                       6
400 #define WM8350_LS_HIB_MODE                      0x0010
401 #define WM8350_LS_HIB_MODE_MASK                 0x0010
402 #define WM8350_LS_HIB_MODE_SHIFT                     4
403 #define WM8350_LS_HIB_PROT                      0x0002
404 #define WM8350_LS_HIB_PROT_MASK                 0x0002
405 #define WM8350_LS_HIB_PROT_SHIFT                     1
406 #define WM8350_LS_PROT                          0x0001
407 #define WM8350_LS_PROT_MASK                     0x0001
408 #define WM8350_LS_PROT_SHIFT                         0
409
410 /* Bit values for R199 (0xC7) */
411 #define WM8350_LS_ERRACT_NONE                       0
412 #define WM8350_LS_ERRACT_SHUTDOWN_CONV              1
413 #define WM8350_LS_ERRACT_SHUTDOWN_SYS               2
414
415 /*
416  * R200 (0xC8) - LDO1 Control
417  */
418 #define WM8350_LDO1_SWI                         0x4000
419 #define WM8350_LDO1_OPFLT                       0x0400
420 #define WM8350_LDO1_VSEL_MASK                   0x001F
421 #define WM8350_LDO1_VSEL_SHIFT                       0
422
423 /*
424  * R201 (0xC9) - LDO1 Timeouts
425  */
426 #define WM8350_LDO1_ERRACT_MASK                 0xC000
427 #define WM8350_LDO1_ERRACT_SHIFT                    14
428 #define WM8350_LDO1_ENSLOT_MASK                 0x3C00
429 #define WM8350_LDO1_ENSLOT_SHIFT                    10
430 #define WM8350_LDO1_SDSLOT_MASK                 0x03C0
431 #define WM8350_LDO1_UVTO_MASK                   0x0030
432 #define WM8350_LDO1_SDSLOT_SHIFT                     6
433
434 /* Bit values for R201 (0xC9) */
435 #define WM8350_LDO1_ERRACT_NONE                       0
436 #define WM8350_LDO1_ERRACT_SHUTDOWN_CONV              1
437 #define WM8350_LDO1_ERRACT_SHUTDOWN_SYS               2
438
439 /*
440  * R202 (0xCA) - LDO1 Low Power
441  */
442 #define WM8350_LDO1_HIB_MODE_MASK               0x3000
443 #define WM8350_LDO1_HIB_TRIG_MASK               0x0300
444 #define WM8350_LDO1_VIMG_MASK                   0x001F
445 #define WM8350_LDO1_HIB_MODE_DIS                (0x1 << 12)
446
447
448 /*
449  * R203 (0xCB) - LDO2 Control
450  */
451 #define WM8350_LDO2_SWI                         0x4000
452 #define WM8350_LDO2_OPFLT                       0x0400
453 #define WM8350_LDO2_VSEL_MASK                   0x001F
454 #define WM8350_LDO2_VSEL_SHIFT                       0
455
456 /*
457  * R204 (0xCC) - LDO2 Timeouts
458  */
459 #define WM8350_LDO2_ERRACT_MASK                 0xC000
460 #define WM8350_LDO2_ERRACT_SHIFT                    14
461 #define WM8350_LDO2_ENSLOT_MASK                 0x3C00
462 #define WM8350_LDO2_ENSLOT_SHIFT                    10
463 #define WM8350_LDO2_SDSLOT_MASK                 0x03C0
464 #define WM8350_LDO2_SDSLOT_SHIFT                     6
465
466 /* Bit values for R204 (0xCC) */
467 #define WM8350_LDO2_ERRACT_NONE                       0
468 #define WM8350_LDO2_ERRACT_SHUTDOWN_CONV              1
469 #define WM8350_LDO2_ERRACT_SHUTDOWN_SYS               2
470
471 /*
472  * R205 (0xCD) - LDO2 Low Power
473  */
474 #define WM8350_LDO2_HIB_MODE_MASK               0x3000
475 #define WM8350_LDO2_HIB_TRIG_MASK               0x0300
476 #define WM8350_LDO2_VIMG_MASK                   0x001F
477
478 /*
479  * R206 (0xCE) - LDO3 Control
480  */
481 #define WM8350_LDO3_SWI                         0x4000
482 #define WM8350_LDO3_OPFLT                       0x0400
483 #define WM8350_LDO3_VSEL_MASK                   0x001F
484 #define WM8350_LDO3_VSEL_SHIFT                       0
485
486 /*
487  * R207 (0xCF) - LDO3 Timeouts
488  */
489 #define WM8350_LDO3_ERRACT_MASK                 0xC000
490 #define WM8350_LDO3_ERRACT_SHIFT                    14
491 #define WM8350_LDO3_ENSLOT_MASK                 0x3C00
492 #define WM8350_LDO3_ENSLOT_SHIFT                    10
493 #define WM8350_LDO3_SDSLOT_MASK                 0x03C0
494 #define WM8350_LDO3_UVTO_MASK                   0x0030
495 #define WM8350_LDO3_SDSLOT_SHIFT                     6
496
497 /* Bit values for R207 (0xCF) */
498 #define WM8350_LDO3_ERRACT_NONE                       0
499 #define WM8350_LDO3_ERRACT_SHUTDOWN_CONV              1
500 #define WM8350_LDO3_ERRACT_SHUTDOWN_SYS               2
501
502 /*
503  * R208 (0xD0) - LDO3 Low Power
504  */
505 #define WM8350_LDO3_HIB_MODE_MASK               0x3000
506 #define WM8350_LDO3_HIB_TRIG_MASK               0x0300
507 #define WM8350_LDO3_VIMG_MASK                   0x001F
508
509 /*
510  * R209 (0xD1) - LDO4 Control
511  */
512 #define WM8350_LDO4_SWI                         0x4000
513 #define WM8350_LDO4_OPFLT                       0x0400
514 #define WM8350_LDO4_VSEL_MASK                   0x001F
515 #define WM8350_LDO4_VSEL_SHIFT                       0
516
517 /*
518  * R210 (0xD2) - LDO4 Timeouts
519  */
520 #define WM8350_LDO4_ERRACT_MASK                 0xC000
521 #define WM8350_LDO4_ERRACT_SHIFT                    14
522 #define WM8350_LDO4_ENSLOT_MASK                 0x3C00
523 #define WM8350_LDO4_ENSLOT_SHIFT                    10
524 #define WM8350_LDO4_SDSLOT_MASK                 0x03C0
525 #define WM8350_LDO4_UVTO_MASK                   0x0030
526 #define WM8350_LDO4_SDSLOT_SHIFT                     6
527
528 /* Bit values for R210 (0xD2) */
529 #define WM8350_LDO4_ERRACT_NONE                       0
530 #define WM8350_LDO4_ERRACT_SHUTDOWN_CONV              1
531 #define WM8350_LDO4_ERRACT_SHUTDOWN_SYS               2
532
533 /*
534  * R211 (0xD3) - LDO4 Low Power
535  */
536 #define WM8350_LDO4_HIB_MODE_MASK               0x3000
537 #define WM8350_LDO4_HIB_TRIG_MASK               0x0300
538 #define WM8350_LDO4_VIMG_MASK                   0x001F
539
540 /*
541  * R215 (0xD7) - VCC_FAULT Masks
542  */
543 #define WM8350_LS_FAULT                         0x8000
544 #define WM8350_LDO4_FAULT                       0x0800
545 #define WM8350_LDO3_FAULT                       0x0400
546 #define WM8350_LDO2_FAULT                       0x0200
547 #define WM8350_LDO1_FAULT                       0x0100
548 #define WM8350_DC6_FAULT                        0x0020
549 #define WM8350_DC5_FAULT                        0x0010
550 #define WM8350_DC4_FAULT                        0x0008
551 #define WM8350_DC3_FAULT                        0x0004
552 #define WM8350_DC2_FAULT                        0x0002
553 #define WM8350_DC1_FAULT                        0x0001
554
555 /*
556  * R216 (0xD8) - Main Bandgap Control
557  */
558 #define WM8350_MBG_LOAD_FUSES                   0x8000
559 #define WM8350_MBG_FUSE_WPREP                   0x4000
560 #define WM8350_MBG_FUSE_WRITE                   0x2000
561 #define WM8350_MBG_FUSE_TRIM_MASK               0x1F00
562 #define WM8350_MBG_TRIM_SRC                     0x0020
563 #define WM8350_MBG_USER_TRIM_MASK               0x001F
564
565 /*
566  * R217 (0xD9) - OSC Control
567  */
568 #define WM8350_OSC_LOAD_FUSES                   0x8000
569 #define WM8350_OSC_FUSE_WPREP                   0x4000
570 #define WM8350_OSC_FUSE_WRITE                   0x2000
571 #define WM8350_OSC_FUSE_TRIM_MASK               0x0F00
572 #define WM8350_OSC_TRIM_SRC                     0x0020
573 #define WM8350_OSC_USER_TRIM_MASK               0x000F
574
575 /*
576  * R248 (0xF8) - DCDC1 Force PWM
577  */
578 #define WM8350_DCDC1_FORCE_PWM_ENA              0x0010
579
580 /*
581  * R250 (0xFA) - DCDC3 Force PWM
582  */
583 #define WM8350_DCDC3_FORCE_PWM_ENA              0x0010
584
585 /*
586  * R251 (0xFB) - DCDC4 Force PWM
587  */
588 #define WM8350_DCDC4_FORCE_PWM_ENA              0x0010
589
590 /*
591  * R253 (0xFD) - DCDC1 Force PWM
592  */
593 #define WM8350_DCDC6_FORCE_PWM_ENA              0x0010
594
595 /*
596  * DCDC's
597  */
598 #define WM8350_DCDC_1                           0
599 #define WM8350_DCDC_2                           1
600 #define WM8350_DCDC_3                           2
601 #define WM8350_DCDC_4                           3
602 #define WM8350_DCDC_5                           4
603 #define WM8350_DCDC_6                           5
604
605 /* DCDC modes */
606 #define WM8350_DCDC_ACTIVE_STANDBY              0
607 #define WM8350_DCDC_ACTIVE_PULSE                1
608 #define WM8350_DCDC_SLEEP_NORMAL                0
609 #define WM8350_DCDC_SLEEP_LOW                   1
610
611 /* DCDC Low power (Hibernate) mode */
612 #define WM8350_DCDC_HIB_MODE_CUR                (0 << 12)
613 #define WM8350_DCDC_HIB_MODE_IMAGE              (1 << 12)
614 #define WM8350_DCDC_HIB_MODE_STANDBY            (2 << 12)
615 #define WM8350_DCDC_HIB_MODE_LDO                (4 << 12)
616 #define WM8350_DCDC_HIB_MODE_LDO_IM             (5 << 12)
617 #define WM8350_DCDC_HIB_MODE_DIS                (7 << 12)
618 #define WM8350_DCDC_HIB_MODE_MASK               (7 << 12)
619
620 /* DCDC Low Power (Hibernate) signal */
621 #define WM8350_DCDC_HIB_SIG_REG                 (0 << 8)
622 #define WM8350_DCDC_HIB_SIG_LPWR1               (1 << 8)
623 #define WM8350_DCDC_HIB_SIG_LPWR2               (2 << 8)
624 #define WM8350_DCDC_HIB_SIG_LPWR3               (3 << 8)
625
626 /* LDO Low power (Hibernate) mode */
627 #define WM8350_LDO_HIB_MODE_IMAGE               (0 << 0)
628 #define WM8350_LDO_HIB_MODE_DIS                 (1 << 0)
629
630 /* LDO Low Power (Hibernate) signal */
631 #define WM8350_LDO_HIB_SIG_REG                  (0 << 8)
632 #define WM8350_LDO_HIB_SIG_LPWR1                (1 << 8)
633 #define WM8350_LDO_HIB_SIG_LPWR2                (2 << 8)
634 #define WM8350_LDO_HIB_SIG_LPWR3                (3 << 8)
635
636 /*
637  * LDOs
638  */
639 #define WM8350_LDO_1                            6
640 #define WM8350_LDO_2                            7
641 #define WM8350_LDO_3                            8
642 #define WM8350_LDO_4                            9
643
644 /*
645  * ISINKs
646  */
647 #define WM8350_ISINK_A                          10
648 #define WM8350_ISINK_B                          11
649
650 #define WM8350_ISINK_MODE_BOOST                 0
651 #define WM8350_ISINK_MODE_SWITCH                1
652 #define WM8350_ISINK_ILIM_NORMAL                0
653 #define WM8350_ISINK_ILIM_LOW                   1
654
655 #define WM8350_ISINK_FLASH_DISABLE              0
656 #define WM8350_ISINK_FLASH_ENABLE               1
657 #define WM8350_ISINK_FLASH_TRIG_BIT             0
658 #define WM8350_ISINK_FLASH_TRIG_GPIO            1
659 #define WM8350_ISINK_FLASH_MODE_EN              (1 << 13)
660 #define WM8350_ISINK_FLASH_MODE_DIS             (0 << 13)
661 #define WM8350_ISINK_FLASH_DUR_32MS             (0 << 8)
662 #define WM8350_ISINK_FLASH_DUR_64MS             (1 << 8)
663 #define WM8350_ISINK_FLASH_DUR_96MS             (2 << 8)
664 #define WM8350_ISINK_FLASH_DUR_1024MS           (3 << 8)
665 #define WM8350_ISINK_FLASH_ON_INSTANT           (0 << 4)
666 #define WM8350_ISINK_FLASH_ON_0_25S             (1 << 4)
667 #define WM8350_ISINK_FLASH_ON_0_50S             (2 << 4)
668 #define WM8350_ISINK_FLASH_ON_1_00S             (3 << 4)
669 #define WM8350_ISINK_FLASH_ON_1_95S             (1 << 4)
670 #define WM8350_ISINK_FLASH_ON_3_91S             (2 << 4)
671 #define WM8350_ISINK_FLASH_ON_7_80S             (3 << 4)
672 #define WM8350_ISINK_FLASH_OFF_INSTANT          (0 << 0)
673 #define WM8350_ISINK_FLASH_OFF_0_25S            (1 << 0)
674 #define WM8350_ISINK_FLASH_OFF_0_50S            (2 << 0)
675 #define WM8350_ISINK_FLASH_OFF_1_00S            (3 << 0)
676 #define WM8350_ISINK_FLASH_OFF_1_95S            (1 << 0)
677 #define WM8350_ISINK_FLASH_OFF_3_91S            (2 << 0)
678 #define WM8350_ISINK_FLASH_OFF_7_80S            (3 << 0)
679
680 /*
681  * Regulator Interrupts.
682  */
683 #define WM8350_IRQ_CS1                          13
684 #define WM8350_IRQ_CS2                          14
685 #define WM8350_IRQ_UV_LDO4                      25
686 #define WM8350_IRQ_UV_LDO3                      26
687 #define WM8350_IRQ_UV_LDO2                      27
688 #define WM8350_IRQ_UV_LDO1                      28
689 #define WM8350_IRQ_UV_DC6                       29
690 #define WM8350_IRQ_UV_DC5                       30
691 #define WM8350_IRQ_UV_DC4                       31
692 #define WM8350_IRQ_UV_DC3                       32
693 #define WM8350_IRQ_UV_DC2                       33
694 #define WM8350_IRQ_UV_DC1                       34
695 #define WM8350_IRQ_OC_LS                        35
696
697 #define NUM_WM8350_REGULATORS                   12
698
699 struct wm8350;
700 struct platform_device;
701 struct regulator_init_data;
702
703 struct wm8350_pmic {
704         /* ISINK to DCDC mapping */
705         int isink_A_dcdc;
706         int isink_B_dcdc;
707
708         /* hibernate configs */
709         u16 dcdc1_hib_mode;
710         u16 dcdc3_hib_mode;
711         u16 dcdc4_hib_mode;
712         u16 dcdc6_hib_mode;
713
714         /* regulator devices */
715         struct platform_device *pdev[NUM_WM8350_REGULATORS];
716 };
717
718 int wm8350_register_regulator(struct wm8350 *wm8350, int reg,
719                               struct regulator_init_data *initdata);
720
721 /*
722  * Additional DCDC control not supported via regulator API
723  */
724 int wm8350_dcdc_set_slot(struct wm8350 *wm8350, int dcdc, u16 start,
725                          u16 stop, u16 fault);
726 int wm8350_dcdc25_set_mode(struct wm8350 *wm8350, int dcdc, u16 mode,
727                            u16 ilim, u16 ramp, u16 feedback);
728
729 /*
730  * Additional LDO control not supported via regulator API
731  */
732 int wm8350_ldo_set_slot(struct wm8350 *wm8350, int ldo, u16 start, u16 stop);
733
734 /*
735  * Additional ISINK control not supported via regulator API
736  */
737 int wm8350_isink_set_flash(struct wm8350 *wm8350, int isink, u16 mode,
738                            u16 trigger, u16 duration, u16 on_ramp,
739                            u16 off_ramp, u16 drive);
740
741 #endif