[SPARC64]: Sanitize %pstate writes for sun4v.
[linux-2.6.git] / include / asm-sparc64 / cpudata.h
1 /* cpudata.h: Per-cpu parameters.
2  *
3  * Copyright (C) 2003, 2005, 2006 David S. Miller (davem@davemloft.net)
4  */
5
6 #ifndef _SPARC64_CPUDATA_H
7 #define _SPARC64_CPUDATA_H
8
9 #ifndef __ASSEMBLY__
10
11 #include <linux/percpu.h>
12 #include <linux/threads.h>
13
14 typedef struct {
15         /* Dcache line 1 */
16         unsigned int    __softirq_pending; /* must be 1st, see rtrap.S */
17         unsigned int    multiplier;
18         unsigned int    counter;
19         unsigned int    idle_volume;
20         unsigned long   clock_tick;     /* %tick's per second */
21         unsigned long   udelay_val;
22
23         /* Dcache line 2, rarely used */
24         unsigned int    dcache_size;
25         unsigned int    dcache_line_size;
26         unsigned int    icache_size;
27         unsigned int    icache_line_size;
28         unsigned int    ecache_size;
29         unsigned int    ecache_line_size;
30         unsigned int    __pad3;
31         unsigned int    __pad4;
32 } cpuinfo_sparc;
33
34 DECLARE_PER_CPU(cpuinfo_sparc, __cpu_data);
35 #define cpu_data(__cpu)         per_cpu(__cpu_data, (__cpu))
36 #define local_cpu_data()        __get_cpu_var(__cpu_data)
37
38 /* Trap handling code needs to get at a few critical values upon
39  * trap entry and to process TSB misses.  These cannot be in the
40  * per_cpu() area as we really need to lock them into the TLB and
41  * thus make them part of the main kernel image.  As a result we
42  * try to make this as small as possible.
43  *
44  * This is padded out and aligned to 64-bytes to avoid false sharing
45  * on SMP.
46  */
47
48 /* If you modify the size of this structure, please update
49  * TRAP_BLOCK_SZ_SHIFT below.
50  */
51 struct thread_info;
52 struct trap_per_cpu {
53 /* D-cache line 1 */
54         struct thread_info      *thread;
55         unsigned long           pgd_paddr;
56         unsigned long           __pad1[2];
57
58 /* D-cache line 2 */
59         unsigned long           __pad2[4];
60 } __attribute__((aligned(64)));
61 extern struct trap_per_cpu trap_block[NR_CPUS];
62 extern void init_cur_cpu_trap(void);
63 extern void setup_tba(void);
64
65 #ifdef CONFIG_SMP
66 struct cpuid_patch_entry {
67         unsigned int    addr;
68         unsigned int    cheetah_safari[4];
69         unsigned int    cheetah_jbus[4];
70         unsigned int    starfire[4];
71         unsigned int    sun4v[4];
72 };
73 extern struct cpuid_patch_entry __cpuid_patch, __cpuid_patch_end;
74 #endif
75
76 struct gl_1insn_patch_entry {
77         unsigned int    addr;
78         unsigned int    insn;
79 };
80 extern struct gl_1insn_patch_entry __gl_1insn_patch, __gl_1insn_patch_end;
81
82 struct gl_2insn_patch_entry {
83         unsigned int    addr;
84         unsigned int    insns[2];
85 };
86 extern struct gl_2insn_patch_entry __gl_2insn_patch, __gl_2insn_patch_end;
87 #endif /* !(__ASSEMBLY__) */
88
89 #define TRAP_PER_CPU_THREAD     0x00
90 #define TRAP_PER_CPU_PGD_PADDR  0x08
91
92 #define TRAP_BLOCK_SZ_SHIFT     6
93
94 #include <asm/scratchpad.h>
95
96 #ifdef CONFIG_SMP
97
98 #define __GET_CPUID(REG)                                \
99         /* Spitfire implementation (default). */        \
100 661:    ldxa            [%g0] ASI_UPA_CONFIG, REG;      \
101         srlx            REG, 17, REG;                   \
102          and            REG, 0x1f, REG;                 \
103         nop;                                            \
104         .section        .cpuid_patch, "ax";             \
105         /* Instruction location. */                     \
106         .word           661b;                           \
107         /* Cheetah Safari implementation. */            \
108         ldxa            [%g0] ASI_SAFARI_CONFIG, REG;   \
109         srlx            REG, 17, REG;                   \
110         and             REG, 0x3ff, REG;                \
111         nop;                                            \
112         /* Cheetah JBUS implementation. */              \
113         ldxa            [%g0] ASI_JBUS_CONFIG, REG;     \
114         srlx            REG, 17, REG;                   \
115         and             REG, 0x1f, REG;                 \
116         nop;                                            \
117         /* Starfire implementation. */                  \
118         sethi           %hi(0x1fff40000d0 >> 9), REG;   \
119         sllx            REG, 9, REG;                    \
120         or              REG, 0xd0, REG;                 \
121         lduwa           [REG] ASI_PHYS_BYPASS_EC_E, REG;\
122         /* sun4v implementation. */                     \
123         mov             SCRATCHPAD_CPUID, REG;          \
124         nop;                                            \
125         ldxa            [REG] ASI_SCRATCHPAD, REG;      \
126         nop;                                            \
127         .previous;
128
129 /* Clobbers TMP, current address space PGD phys address into DEST.  */
130 #define TRAP_LOAD_PGD_PHYS(DEST, TMP)           \
131         __GET_CPUID(TMP)                        \
132         sethi   %hi(trap_block), DEST;          \
133         sllx    TMP, TRAP_BLOCK_SZ_SHIFT, TMP;  \
134         or      DEST, %lo(trap_block), DEST;    \
135         add     DEST, TMP, DEST;                \
136         ldx     [DEST + TRAP_PER_CPU_PGD_PADDR], DEST;
137
138 /* Clobbers TMP, loads local processor's IRQ work area into DEST.  */
139 #define TRAP_LOAD_IRQ_WORK(DEST, TMP)           \
140         __GET_CPUID(TMP)                        \
141         sethi   %hi(__irq_work), DEST;          \
142         sllx    TMP, 6, TMP;                    \
143         or      DEST, %lo(__irq_work), DEST;    \
144         add     DEST, TMP, DEST;
145
146 /* Clobbers TMP, loads DEST with current thread info pointer.  */
147 #define TRAP_LOAD_THREAD_REG(DEST, TMP)         \
148         __GET_CPUID(TMP)                        \
149         sethi   %hi(trap_block), DEST;          \
150         sllx    TMP, TRAP_BLOCK_SZ_SHIFT, TMP;  \
151         or      DEST, %lo(trap_block), DEST;    \
152         ldx     [DEST + TMP], DEST;
153
154 /* Given the current thread info pointer in THR, load the per-cpu
155  * area base of the current processor into DEST.  REG1, REG2, and REG3 are
156  * clobbered.
157  *
158  * You absolutely cannot use DEST as a temporary in this code.  The
159  * reason is that traps can happen during execution, and return from
160  * trap will load the fully resolved DEST per-cpu base.  This can corrupt
161  * the calculations done by the macro mid-stream.
162  */
163 #define LOAD_PER_CPU_BASE(DEST, THR, REG1, REG2, REG3)  \
164         ldub    [THR + TI_CPU], REG1;                   \
165         sethi   %hi(__per_cpu_shift), REG3;             \
166         sethi   %hi(__per_cpu_base), REG2;              \
167         ldx     [REG3 + %lo(__per_cpu_shift)], REG3;    \
168         ldx     [REG2 + %lo(__per_cpu_base)], REG2;     \
169         sllx    REG1, REG3, REG3;                       \
170         add     REG3, REG2, DEST;
171
172 #else
173
174 /* Uniprocessor versions, we know the cpuid is zero.  */
175 #define TRAP_LOAD_PGD_PHYS(DEST, TMP)           \
176         sethi   %hi(trap_block), DEST;          \
177         or      DEST, %lo(trap_block), DEST;    \
178         ldx     [DEST + TRAP_PER_CPU_PGD_PADDR], DEST;
179
180 #define TRAP_LOAD_IRQ_WORK(DEST, TMP)           \
181         sethi   %hi(__irq_work), DEST;          \
182         or      DEST, %lo(__irq_work), DEST;
183
184 #define TRAP_LOAD_THREAD_REG(DEST, TMP)         \
185         sethi   %hi(trap_block), DEST;          \
186         ldx     [DEST + %lo(trap_block)], DEST;
187
188 /* No per-cpu areas on uniprocessor, so no need to load DEST.  */
189 #define LOAD_PER_CPU_BASE(DEST, THR, REG1, REG2, REG3)
190
191 #endif /* !(CONFIG_SMP) */
192
193 #endif /* _SPARC64_CPUDATA_H */