[POWERPC] Celleb: consolidate spu management ops
[linux-2.6.git] / include / asm-powerpc / spu.h
1 /*
2  * SPU core / file system interface and HW structures
3  *
4  * (C) Copyright IBM Deutschland Entwicklung GmbH 2005
5  *
6  * Author: Arnd Bergmann <arndb@de.ibm.com>
7  *
8  * This program is free software; you can redistribute it and/or modify
9  * it under the terms of the GNU General Public License as published by
10  * the Free Software Foundation; either version 2, or (at your option)
11  * any later version.
12  *
13  * This program is distributed in the hope that it will be useful,
14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16  * GNU General Public License for more details.
17  *
18  * You should have received a copy of the GNU General Public License
19  * along with this program; if not, write to the Free Software
20  * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
21  */
22
23 #ifndef _SPU_H
24 #define _SPU_H
25 #ifdef __KERNEL__
26
27 #include <linux/workqueue.h>
28 #include <linux/sysdev.h>
29
30 #define LS_SIZE (256 * 1024)
31 #define LS_ADDR_MASK (LS_SIZE - 1)
32
33 #define MFC_PUT_CMD             0x20
34 #define MFC_PUTS_CMD            0x28
35 #define MFC_PUTR_CMD            0x30
36 #define MFC_PUTF_CMD            0x22
37 #define MFC_PUTB_CMD            0x21
38 #define MFC_PUTFS_CMD           0x2A
39 #define MFC_PUTBS_CMD           0x29
40 #define MFC_PUTRF_CMD           0x32
41 #define MFC_PUTRB_CMD           0x31
42 #define MFC_PUTL_CMD            0x24
43 #define MFC_PUTRL_CMD           0x34
44 #define MFC_PUTLF_CMD           0x26
45 #define MFC_PUTLB_CMD           0x25
46 #define MFC_PUTRLF_CMD          0x36
47 #define MFC_PUTRLB_CMD          0x35
48
49 #define MFC_GET_CMD             0x40
50 #define MFC_GETS_CMD            0x48
51 #define MFC_GETF_CMD            0x42
52 #define MFC_GETB_CMD            0x41
53 #define MFC_GETFS_CMD           0x4A
54 #define MFC_GETBS_CMD           0x49
55 #define MFC_GETL_CMD            0x44
56 #define MFC_GETLF_CMD           0x46
57 #define MFC_GETLB_CMD           0x45
58
59 #define MFC_SDCRT_CMD           0x80
60 #define MFC_SDCRTST_CMD         0x81
61 #define MFC_SDCRZ_CMD           0x89
62 #define MFC_SDCRS_CMD           0x8D
63 #define MFC_SDCRF_CMD           0x8F
64
65 #define MFC_GETLLAR_CMD         0xD0
66 #define MFC_PUTLLC_CMD          0xB4
67 #define MFC_PUTLLUC_CMD         0xB0
68 #define MFC_PUTQLLUC_CMD        0xB8
69 #define MFC_SNDSIG_CMD          0xA0
70 #define MFC_SNDSIGB_CMD         0xA1
71 #define MFC_SNDSIGF_CMD         0xA2
72 #define MFC_BARRIER_CMD         0xC0
73 #define MFC_EIEIO_CMD           0xC8
74 #define MFC_SYNC_CMD            0xCC
75
76 #define MFC_MIN_DMA_SIZE_SHIFT  4       /* 16 bytes */
77 #define MFC_MAX_DMA_SIZE_SHIFT  14      /* 16384 bytes */
78 #define MFC_MIN_DMA_SIZE        (1 << MFC_MIN_DMA_SIZE_SHIFT)
79 #define MFC_MAX_DMA_SIZE        (1 << MFC_MAX_DMA_SIZE_SHIFT)
80 #define MFC_MIN_DMA_SIZE_MASK   (MFC_MIN_DMA_SIZE - 1)
81 #define MFC_MAX_DMA_SIZE_MASK   (MFC_MAX_DMA_SIZE - 1)
82 #define MFC_MIN_DMA_LIST_SIZE   0x0008  /*   8 bytes */
83 #define MFC_MAX_DMA_LIST_SIZE   0x4000  /* 16K bytes */
84
85 #define MFC_TAGID_TO_TAGMASK(tag_id)  (1 << (tag_id & 0x1F))
86
87 /* Events for Channels 0-2 */
88 #define MFC_DMA_TAG_STATUS_UPDATE_EVENT     0x00000001
89 #define MFC_DMA_TAG_CMD_STALL_NOTIFY_EVENT  0x00000002
90 #define MFC_DMA_QUEUE_AVAILABLE_EVENT       0x00000008
91 #define MFC_SPU_MAILBOX_WRITTEN_EVENT       0x00000010
92 #define MFC_DECREMENTER_EVENT               0x00000020
93 #define MFC_PU_INT_MAILBOX_AVAILABLE_EVENT  0x00000040
94 #define MFC_PU_MAILBOX_AVAILABLE_EVENT      0x00000080
95 #define MFC_SIGNAL_2_EVENT                  0x00000100
96 #define MFC_SIGNAL_1_EVENT                  0x00000200
97 #define MFC_LLR_LOST_EVENT                  0x00000400
98 #define MFC_PRIV_ATTN_EVENT                 0x00000800
99 #define MFC_MULTI_SRC_EVENT                 0x00001000
100
101 /* Flags indicating progress during context switch. */
102 #define SPU_CONTEXT_SWITCH_PENDING      0UL
103 #define SPU_CONTEXT_SWITCH_ACTIVE       1UL
104
105 struct spu_context;
106 struct spu_runqueue;
107 struct device_node;
108
109 struct spu {
110         const char *name;
111         unsigned long local_store_phys;
112         u8 *local_store;
113         unsigned long problem_phys;
114         struct spu_problem __iomem *problem;
115         struct spu_priv2 __iomem *priv2;
116         struct list_head list;
117         struct list_head sched_list;
118         struct list_head full_list;
119         int number;
120         unsigned int irqs[3];
121         u32 node;
122         u64 flags;
123         u64 dar;
124         u64 dsisr;
125         size_t ls_size;
126         unsigned int slb_replace;
127         struct mm_struct *mm;
128         struct spu_context *ctx;
129         struct spu_runqueue *rq;
130         unsigned long long timestamp;
131         pid_t pid;
132         int prio;
133         int class_0_pending;
134         spinlock_t register_lock;
135
136         void (* wbox_callback)(struct spu *spu);
137         void (* ibox_callback)(struct spu *spu);
138         void (* stop_callback)(struct spu *spu);
139         void (* mfc_callback)(struct spu *spu);
140         void (* dma_callback)(struct spu *spu, int type);
141
142         char irq_c0[8];
143         char irq_c1[8];
144         char irq_c2[8];
145
146         u64 spe_id;
147
148         void* pdata; /* platform private data */
149
150         /* of based platforms only */
151         struct device_node *devnode;
152
153         /* native only */
154         struct spu_priv1 __iomem *priv1;
155
156         /* beat only */
157         u64 shadow_int_mask_RW[3];
158
159         struct sys_device sysdev;
160 };
161
162 struct spu *spu_alloc(void);
163 struct spu *spu_alloc_node(int node);
164 void spu_free(struct spu *spu);
165 int spu_irq_class_0_bottom(struct spu *spu);
166 int spu_irq_class_1_bottom(struct spu *spu);
167 void spu_irq_setaffinity(struct spu *spu, int cpu);
168
169 /* system callbacks from the SPU */
170 struct spu_syscall_block {
171         u64 nr_ret;
172         u64 parm[6];
173 };
174 extern long spu_sys_callback(struct spu_syscall_block *s);
175
176 /* syscalls implemented in spufs */
177 struct file;
178 extern struct spufs_calls {
179         asmlinkage long (*create_thread)(const char __user *name,
180                                         unsigned int flags, mode_t mode);
181         asmlinkage long (*spu_run)(struct file *filp, __u32 __user *unpc,
182                                                 __u32 __user *ustatus);
183         struct module *owner;
184 } spufs_calls;
185
186 /* coredump calls implemented in spufs */
187 struct spu_coredump_calls {
188         asmlinkage int (*arch_notes_size)(void);
189         asmlinkage void (*arch_write_notes)(struct file *file);
190         struct module *owner;
191 };
192
193 /* return status from spu_run, same as in libspe */
194 #define SPE_EVENT_DMA_ALIGNMENT         0x0008  /*A DMA alignment error */
195 #define SPE_EVENT_SPE_ERROR             0x0010  /*An illegal instruction error*/
196 #define SPE_EVENT_SPE_DATA_SEGMENT      0x0020  /*A DMA segmentation error    */
197 #define SPE_EVENT_SPE_DATA_STORAGE      0x0040  /*A DMA storage error */
198 #define SPE_EVENT_INVALID_DMA           0x0800  /* Invalid MFC DMA */
199
200 /*
201  * Flags for sys_spu_create.
202  */
203 #define SPU_CREATE_EVENTS_ENABLED       0x0001
204 #define SPU_CREATE_GANG                 0x0002
205 #define SPU_CREATE_NOSCHED              0x0004
206 #define SPU_CREATE_ISOLATE              0x0008
207
208 #define SPU_CREATE_FLAG_ALL             0x000f /* mask of all valid flags */
209
210
211 #ifdef CONFIG_SPU_FS_MODULE
212 int register_spu_syscalls(struct spufs_calls *calls);
213 void unregister_spu_syscalls(struct spufs_calls *calls);
214 #else
215 static inline int register_spu_syscalls(struct spufs_calls *calls)
216 {
217         return 0;
218 }
219 static inline void unregister_spu_syscalls(struct spufs_calls *calls)
220 {
221 }
222 #endif /* MODULE */
223
224 int register_arch_coredump_calls(struct spu_coredump_calls *calls);
225 void unregister_arch_coredump_calls(struct spu_coredump_calls *calls);
226
227 int spu_add_sysdev_attr(struct sysdev_attribute *attr);
228 void spu_remove_sysdev_attr(struct sysdev_attribute *attr);
229
230 int spu_add_sysdev_attr_group(struct attribute_group *attrs);
231 void spu_remove_sysdev_attr_group(struct attribute_group *attrs);
232
233
234 /*
235  * Notifier blocks:
236  *
237  * oprofile can get notified when a context switch is performed
238  * on an spe. The notifer function that gets called is passed
239  * a pointer to the SPU structure as well as the object-id that
240  * identifies the binary running on that SPU now.
241  *
242  * For a context save, the object-id that is passed is zero,
243  * identifying that the kernel will run from that moment on.
244  *
245  * For a context restore, the object-id is the value written
246  * to object-id spufs file from user space and the notifer
247  * function can assume that spu->ctx is valid.
248  */
249 struct notifier_block;
250 int spu_switch_event_register(struct notifier_block * n);
251 int spu_switch_event_unregister(struct notifier_block * n);
252
253 /*
254  * This defines the Local Store, Problem Area and Privlege Area of an SPU.
255  */
256
257 union mfc_tag_size_class_cmd {
258         struct {
259                 u16 mfc_size;
260                 u16 mfc_tag;
261                 u8  pad;
262                 u8  mfc_rclassid;
263                 u16 mfc_cmd;
264         } u;
265         struct {
266                 u32 mfc_size_tag32;
267                 u32 mfc_class_cmd32;
268         } by32;
269         u64 all64;
270 };
271
272 struct mfc_cq_sr {
273         u64 mfc_cq_data0_RW;
274         u64 mfc_cq_data1_RW;
275         u64 mfc_cq_data2_RW;
276         u64 mfc_cq_data3_RW;
277 };
278
279 struct spu_problem {
280 #define MS_SYNC_PENDING         1L
281         u64 spc_mssync_RW;                                      /* 0x0000 */
282         u8  pad_0x0008_0x3000[0x3000 - 0x0008];
283
284         /* DMA Area */
285         u8  pad_0x3000_0x3004[0x4];                             /* 0x3000 */
286         u32 mfc_lsa_W;                                          /* 0x3004 */
287         u64 mfc_ea_W;                                           /* 0x3008 */
288         union mfc_tag_size_class_cmd mfc_union_W;                       /* 0x3010 */
289         u8  pad_0x3018_0x3104[0xec];                            /* 0x3018 */
290         u32 dma_qstatus_R;                                      /* 0x3104 */
291         u8  pad_0x3108_0x3204[0xfc];                            /* 0x3108 */
292         u32 dma_querytype_RW;                                   /* 0x3204 */
293         u8  pad_0x3208_0x321c[0x14];                            /* 0x3208 */
294         u32 dma_querymask_RW;                                   /* 0x321c */
295         u8  pad_0x3220_0x322c[0xc];                             /* 0x3220 */
296         u32 dma_tagstatus_R;                                    /* 0x322c */
297 #define DMA_TAGSTATUS_INTR_ANY  1u
298 #define DMA_TAGSTATUS_INTR_ALL  2u
299         u8  pad_0x3230_0x4000[0x4000 - 0x3230];                 /* 0x3230 */
300
301         /* SPU Control Area */
302         u8  pad_0x4000_0x4004[0x4];                             /* 0x4000 */
303         u32 pu_mb_R;                                            /* 0x4004 */
304         u8  pad_0x4008_0x400c[0x4];                             /* 0x4008 */
305         u32 spu_mb_W;                                           /* 0x400c */
306         u8  pad_0x4010_0x4014[0x4];                             /* 0x4010 */
307         u32 mb_stat_R;                                          /* 0x4014 */
308         u8  pad_0x4018_0x401c[0x4];                             /* 0x4018 */
309         u32 spu_runcntl_RW;                                     /* 0x401c */
310 #define SPU_RUNCNTL_STOP        0L
311 #define SPU_RUNCNTL_RUNNABLE    1L
312 #define SPU_RUNCNTL_ISOLATE     2L
313         u8  pad_0x4020_0x4024[0x4];                             /* 0x4020 */
314         u32 spu_status_R;                                       /* 0x4024 */
315 #define SPU_STOP_STATUS_SHIFT           16
316 #define SPU_STATUS_STOPPED              0x0
317 #define SPU_STATUS_RUNNING              0x1
318 #define SPU_STATUS_STOPPED_BY_STOP      0x2
319 #define SPU_STATUS_STOPPED_BY_HALT      0x4
320 #define SPU_STATUS_WAITING_FOR_CHANNEL  0x8
321 #define SPU_STATUS_SINGLE_STEP          0x10
322 #define SPU_STATUS_INVALID_INSTR        0x20
323 #define SPU_STATUS_INVALID_CH           0x40
324 #define SPU_STATUS_ISOLATED_STATE       0x80
325 #define SPU_STATUS_ISOLATED_LOAD_STATUS 0x200
326 #define SPU_STATUS_ISOLATED_EXIT_STATUS 0x400
327         u8  pad_0x4028_0x402c[0x4];                             /* 0x4028 */
328         u32 spu_spe_R;                                          /* 0x402c */
329         u8  pad_0x4030_0x4034[0x4];                             /* 0x4030 */
330         u32 spu_npc_RW;                                         /* 0x4034 */
331         u8  pad_0x4038_0x14000[0x14000 - 0x4038];               /* 0x4038 */
332
333         /* Signal Notification Area */
334         u8  pad_0x14000_0x1400c[0xc];                           /* 0x14000 */
335         u32 signal_notify1;                                     /* 0x1400c */
336         u8  pad_0x14010_0x1c00c[0x7ffc];                        /* 0x14010 */
337         u32 signal_notify2;                                     /* 0x1c00c */
338 } __attribute__ ((aligned(0x20000)));
339
340 /* SPU Privilege 2 State Area */
341 struct spu_priv2 {
342         /* MFC Registers */
343         u8  pad_0x0000_0x1100[0x1100 - 0x0000];                 /* 0x0000 */
344
345         /* SLB Management Registers */
346         u8  pad_0x1100_0x1108[0x8];                             /* 0x1100 */
347         u64 slb_index_W;                                        /* 0x1108 */
348 #define SLB_INDEX_MASK                          0x7L
349         u64 slb_esid_RW;                                        /* 0x1110 */
350         u64 slb_vsid_RW;                                        /* 0x1118 */
351 #define SLB_VSID_SUPERVISOR_STATE       (0x1ull << 11)
352 #define SLB_VSID_SUPERVISOR_STATE_MASK  (0x1ull << 11)
353 #define SLB_VSID_PROBLEM_STATE          (0x1ull << 10)
354 #define SLB_VSID_PROBLEM_STATE_MASK     (0x1ull << 10)
355 #define SLB_VSID_EXECUTE_SEGMENT        (0x1ull << 9)
356 #define SLB_VSID_NO_EXECUTE_SEGMENT     (0x1ull << 9)
357 #define SLB_VSID_EXECUTE_SEGMENT_MASK   (0x1ull << 9)
358 #define SLB_VSID_4K_PAGE                (0x0 << 8)
359 #define SLB_VSID_LARGE_PAGE             (0x1ull << 8)
360 #define SLB_VSID_PAGE_SIZE_MASK         (0x1ull << 8)
361 #define SLB_VSID_CLASS_MASK             (0x1ull << 7)
362 #define SLB_VSID_VIRTUAL_PAGE_SIZE_MASK (0x1ull << 6)
363         u64 slb_invalidate_entry_W;                             /* 0x1120 */
364         u64 slb_invalidate_all_W;                               /* 0x1128 */
365         u8  pad_0x1130_0x2000[0x2000 - 0x1130];                 /* 0x1130 */
366
367         /* Context Save / Restore Area */
368         struct mfc_cq_sr spuq[16];                              /* 0x2000 */
369         struct mfc_cq_sr puq[8];                                /* 0x2200 */
370         u8  pad_0x2300_0x3000[0x3000 - 0x2300];                 /* 0x2300 */
371
372         /* MFC Control */
373         u64 mfc_control_RW;                                     /* 0x3000 */
374 #define MFC_CNTL_RESUME_DMA_QUEUE               (0ull << 0)
375 #define MFC_CNTL_SUSPEND_DMA_QUEUE              (1ull << 0)
376 #define MFC_CNTL_SUSPEND_DMA_QUEUE_MASK         (1ull << 0)
377 #define MFC_CNTL_NORMAL_DMA_QUEUE_OPERATION     (0ull << 8)
378 #define MFC_CNTL_SUSPEND_IN_PROGRESS            (1ull << 8)
379 #define MFC_CNTL_SUSPEND_COMPLETE               (3ull << 8)
380 #define MFC_CNTL_SUSPEND_DMA_STATUS_MASK        (3ull << 8)
381 #define MFC_CNTL_DMA_QUEUES_EMPTY               (1ull << 14)
382 #define MFC_CNTL_DMA_QUEUES_EMPTY_MASK          (1ull << 14)
383 #define MFC_CNTL_PURGE_DMA_REQUEST              (1ull << 15)
384 #define MFC_CNTL_PURGE_DMA_IN_PROGRESS          (1ull << 24)
385 #define MFC_CNTL_PURGE_DMA_COMPLETE             (3ull << 24)
386 #define MFC_CNTL_PURGE_DMA_STATUS_MASK          (3ull << 24)
387 #define MFC_CNTL_RESTART_DMA_COMMAND            (1ull << 32)
388 #define MFC_CNTL_DMA_COMMAND_REISSUE_PENDING    (1ull << 32)
389 #define MFC_CNTL_DMA_COMMAND_REISSUE_STATUS_MASK (1ull << 32)
390 #define MFC_CNTL_MFC_PRIVILEGE_STATE            (2ull << 33)
391 #define MFC_CNTL_MFC_PROBLEM_STATE              (3ull << 33)
392 #define MFC_CNTL_MFC_KEY_PROTECTION_STATE_MASK  (3ull << 33)
393 #define MFC_CNTL_DECREMENTER_HALTED             (1ull << 35)
394 #define MFC_CNTL_DECREMENTER_RUNNING            (1ull << 40)
395 #define MFC_CNTL_DECREMENTER_STATUS_MASK        (1ull << 40)
396         u8  pad_0x3008_0x4000[0x4000 - 0x3008];                 /* 0x3008 */
397
398         /* Interrupt Mailbox */
399         u64 puint_mb_R;                                         /* 0x4000 */
400         u8  pad_0x4008_0x4040[0x4040 - 0x4008];                 /* 0x4008 */
401
402         /* SPU Control */
403         u64 spu_privcntl_RW;                                    /* 0x4040 */
404 #define SPU_PRIVCNTL_MODE_NORMAL                (0x0ull << 0)
405 #define SPU_PRIVCNTL_MODE_SINGLE_STEP           (0x1ull << 0)
406 #define SPU_PRIVCNTL_MODE_MASK                  (0x1ull << 0)
407 #define SPU_PRIVCNTL_NO_ATTENTION_EVENT         (0x0ull << 1)
408 #define SPU_PRIVCNTL_ATTENTION_EVENT            (0x1ull << 1)
409 #define SPU_PRIVCNTL_ATTENTION_EVENT_MASK       (0x1ull << 1)
410 #define SPU_PRIVCNT_LOAD_REQUEST_NORMAL         (0x0ull << 2)
411 #define SPU_PRIVCNT_LOAD_REQUEST_ENABLE_MASK    (0x1ull << 2)
412         u8  pad_0x4048_0x4058[0x10];                            /* 0x4048 */
413         u64 spu_lslr_RW;                                        /* 0x4058 */
414         u64 spu_chnlcntptr_RW;                                  /* 0x4060 */
415         u64 spu_chnlcnt_RW;                                     /* 0x4068 */
416         u64 spu_chnldata_RW;                                    /* 0x4070 */
417         u64 spu_cfg_RW;                                         /* 0x4078 */
418         u8  pad_0x4080_0x5000[0x5000 - 0x4080];                 /* 0x4080 */
419
420         /* PV2_ImplRegs: Implementation-specific privileged-state 2 regs */
421         u64 spu_pm_trace_tag_status_RW;                         /* 0x5000 */
422         u64 spu_tag_status_query_RW;                            /* 0x5008 */
423 #define TAG_STATUS_QUERY_CONDITION_BITS (0x3ull << 32)
424 #define TAG_STATUS_QUERY_MASK_BITS (0xffffffffull)
425         u64 spu_cmd_buf1_RW;                                    /* 0x5010 */
426 #define SPU_COMMAND_BUFFER_1_LSA_BITS (0x7ffffull << 32)
427 #define SPU_COMMAND_BUFFER_1_EAH_BITS (0xffffffffull)
428         u64 spu_cmd_buf2_RW;                                    /* 0x5018 */
429 #define SPU_COMMAND_BUFFER_2_EAL_BITS ((0xffffffffull) << 32)
430 #define SPU_COMMAND_BUFFER_2_TS_BITS (0xffffull << 16)
431 #define SPU_COMMAND_BUFFER_2_TAG_BITS (0x3full)
432         u64 spu_atomic_status_RW;                               /* 0x5020 */
433 } __attribute__ ((aligned(0x20000)));
434
435 /* SPU Privilege 1 State Area */
436 struct spu_priv1 {
437         /* Control and Configuration Area */
438         u64 mfc_sr1_RW;                                         /* 0x000 */
439 #define MFC_STATE1_LOCAL_STORAGE_DECODE_MASK    0x01ull
440 #define MFC_STATE1_BUS_TLBIE_MASK               0x02ull
441 #define MFC_STATE1_REAL_MODE_OFFSET_ENABLE_MASK 0x04ull
442 #define MFC_STATE1_PROBLEM_STATE_MASK           0x08ull
443 #define MFC_STATE1_RELOCATE_MASK                0x10ull
444 #define MFC_STATE1_MASTER_RUN_CONTROL_MASK      0x20ull
445         u64 mfc_lpid_RW;                                        /* 0x008 */
446         u64 spu_idr_RW;                                         /* 0x010 */
447         u64 mfc_vr_RO;                                          /* 0x018 */
448 #define MFC_VERSION_BITS                (0xffff << 16)
449 #define MFC_REVISION_BITS               (0xffff)
450 #define MFC_GET_VERSION_BITS(vr)        (((vr) & MFC_VERSION_BITS) >> 16)
451 #define MFC_GET_REVISION_BITS(vr)       ((vr) & MFC_REVISION_BITS)
452         u64 spu_vr_RO;                                          /* 0x020 */
453 #define SPU_VERSION_BITS                (0xffff << 16)
454 #define SPU_REVISION_BITS               (0xffff)
455 #define SPU_GET_VERSION_BITS(vr)        (vr & SPU_VERSION_BITS) >> 16
456 #define SPU_GET_REVISION_BITS(vr)       (vr & SPU_REVISION_BITS)
457         u8  pad_0x28_0x100[0x100 - 0x28];                       /* 0x28 */
458
459         /* Interrupt Area */
460         u64 int_mask_RW[3];                                     /* 0x100 */
461 #define CLASS0_ENABLE_DMA_ALIGNMENT_INTR                0x1L
462 #define CLASS0_ENABLE_INVALID_DMA_COMMAND_INTR          0x2L
463 #define CLASS0_ENABLE_SPU_ERROR_INTR                    0x4L
464 #define CLASS0_ENABLE_MFC_FIR_INTR                      0x8L
465 #define CLASS1_ENABLE_SEGMENT_FAULT_INTR                0x1L
466 #define CLASS1_ENABLE_STORAGE_FAULT_INTR                0x2L
467 #define CLASS1_ENABLE_LS_COMPARE_SUSPEND_ON_GET_INTR    0x4L
468 #define CLASS1_ENABLE_LS_COMPARE_SUSPEND_ON_PUT_INTR    0x8L
469 #define CLASS2_ENABLE_MAILBOX_INTR                      0x1L
470 #define CLASS2_ENABLE_SPU_STOP_INTR                     0x2L
471 #define CLASS2_ENABLE_SPU_HALT_INTR                     0x4L
472 #define CLASS2_ENABLE_SPU_DMA_TAG_GROUP_COMPLETE_INTR   0x8L
473         u8  pad_0x118_0x140[0x28];                              /* 0x118 */
474         u64 int_stat_RW[3];                                     /* 0x140 */
475         u8  pad_0x158_0x180[0x28];                              /* 0x158 */
476         u64 int_route_RW;                                       /* 0x180 */
477
478         /* Interrupt Routing */
479         u8  pad_0x188_0x200[0x200 - 0x188];                     /* 0x188 */
480
481         /* Atomic Unit Control Area */
482         u64 mfc_atomic_flush_RW;                                /* 0x200 */
483 #define mfc_atomic_flush_enable                 0x1L
484         u8  pad_0x208_0x280[0x78];                              /* 0x208 */
485         u64 resource_allocation_groupID_RW;                     /* 0x280 */
486         u64 resource_allocation_enable_RW;                      /* 0x288 */
487         u8  pad_0x290_0x3c8[0x3c8 - 0x290];                     /* 0x290 */
488
489         /* SPU_Cache_ImplRegs: Implementation-dependent cache registers */
490
491         u64 smf_sbi_signal_sel;                                 /* 0x3c8 */
492 #define smf_sbi_mask_lsb        56
493 #define smf_sbi_shift           (63 - smf_sbi_mask_lsb)
494 #define smf_sbi_mask            (0x301LL << smf_sbi_shift)
495 #define smf_sbi_bus0_bits       (0x001LL << smf_sbi_shift)
496 #define smf_sbi_bus2_bits       (0x100LL << smf_sbi_shift)
497 #define smf_sbi2_bus0_bits      (0x201LL << smf_sbi_shift)
498 #define smf_sbi2_bus2_bits      (0x300LL << smf_sbi_shift)
499         u64 smf_ato_signal_sel;                                 /* 0x3d0 */
500 #define smf_ato_mask_lsb        35
501 #define smf_ato_shift           (63 - smf_ato_mask_lsb)
502 #define smf_ato_mask            (0x3LL << smf_ato_shift)
503 #define smf_ato_bus0_bits       (0x2LL << smf_ato_shift)
504 #define smf_ato_bus2_bits       (0x1LL << smf_ato_shift)
505         u8  pad_0x3d8_0x400[0x400 - 0x3d8];                     /* 0x3d8 */
506
507         /* TLB Management Registers */
508         u64 mfc_sdr_RW;                                         /* 0x400 */
509         u8  pad_0x408_0x500[0xf8];                              /* 0x408 */
510         u64 tlb_index_hint_RO;                                  /* 0x500 */
511         u64 tlb_index_W;                                        /* 0x508 */
512         u64 tlb_vpn_RW;                                         /* 0x510 */
513         u64 tlb_rpn_RW;                                         /* 0x518 */
514         u8  pad_0x520_0x540[0x20];                              /* 0x520 */
515         u64 tlb_invalidate_entry_W;                             /* 0x540 */
516         u64 tlb_invalidate_all_W;                               /* 0x548 */
517         u8  pad_0x550_0x580[0x580 - 0x550];                     /* 0x550 */
518
519         /* SPU_MMU_ImplRegs: Implementation-dependent MMU registers */
520         u64 smm_hid;                                            /* 0x580 */
521 #define PAGE_SIZE_MASK          0xf000000000000000ull
522 #define PAGE_SIZE_16MB_64KB     0x2000000000000000ull
523         u8  pad_0x588_0x600[0x600 - 0x588];                     /* 0x588 */
524
525         /* MFC Status/Control Area */
526         u64 mfc_accr_RW;                                        /* 0x600 */
527 #define MFC_ACCR_EA_ACCESS_GET          (1 << 0)
528 #define MFC_ACCR_EA_ACCESS_PUT          (1 << 1)
529 #define MFC_ACCR_LS_ACCESS_GET          (1 << 3)
530 #define MFC_ACCR_LS_ACCESS_PUT          (1 << 4)
531         u8  pad_0x608_0x610[0x8];                               /* 0x608 */
532         u64 mfc_dsisr_RW;                                       /* 0x610 */
533 #define MFC_DSISR_PTE_NOT_FOUND         (1 << 30)
534 #define MFC_DSISR_ACCESS_DENIED         (1 << 27)
535 #define MFC_DSISR_ATOMIC                (1 << 26)
536 #define MFC_DSISR_ACCESS_PUT            (1 << 25)
537 #define MFC_DSISR_ADDR_MATCH            (1 << 22)
538 #define MFC_DSISR_LS                    (1 << 17)
539 #define MFC_DSISR_L                     (1 << 16)
540 #define MFC_DSISR_ADDRESS_OVERFLOW      (1 << 0)
541         u8  pad_0x618_0x620[0x8];                               /* 0x618 */
542         u64 mfc_dar_RW;                                         /* 0x620 */
543         u8  pad_0x628_0x700[0x700 - 0x628];                     /* 0x628 */
544
545         /* Replacement Management Table (RMT) Area */
546         u64 rmt_index_RW;                                       /* 0x700 */
547         u8  pad_0x708_0x710[0x8];                               /* 0x708 */
548         u64 rmt_data1_RW;                                       /* 0x710 */
549         u8  pad_0x718_0x800[0x800 - 0x718];                     /* 0x718 */
550
551         /* Control/Configuration Registers */
552         u64 mfc_dsir_R;                                         /* 0x800 */
553 #define MFC_DSIR_Q                      (1 << 31)
554 #define MFC_DSIR_SPU_QUEUE              MFC_DSIR_Q
555         u64 mfc_lsacr_RW;                                       /* 0x808 */
556 #define MFC_LSACR_COMPARE_MASK          ((~0ull) << 32)
557 #define MFC_LSACR_COMPARE_ADDR          ((~0ull) >> 32)
558         u64 mfc_lscrr_R;                                        /* 0x810 */
559 #define MFC_LSCRR_Q                     (1 << 31)
560 #define MFC_LSCRR_SPU_QUEUE             MFC_LSCRR_Q
561 #define MFC_LSCRR_QI_SHIFT              32
562 #define MFC_LSCRR_QI_MASK               ((~0ull) << MFC_LSCRR_QI_SHIFT)
563         u8  pad_0x818_0x820[0x8];                               /* 0x818 */
564         u64 mfc_tclass_id_RW;                                   /* 0x820 */
565 #define MFC_TCLASS_ID_ENABLE            (1L << 0L)
566 #define MFC_TCLASS_SLOT2_ENABLE         (1L << 5L)
567 #define MFC_TCLASS_SLOT1_ENABLE         (1L << 6L)
568 #define MFC_TCLASS_SLOT0_ENABLE         (1L << 7L)
569 #define MFC_TCLASS_QUOTA_2_SHIFT        8L
570 #define MFC_TCLASS_QUOTA_1_SHIFT        16L
571 #define MFC_TCLASS_QUOTA_0_SHIFT        24L
572 #define MFC_TCLASS_QUOTA_2_MASK         (0x1FL << MFC_TCLASS_QUOTA_2_SHIFT)
573 #define MFC_TCLASS_QUOTA_1_MASK         (0x1FL << MFC_TCLASS_QUOTA_1_SHIFT)
574 #define MFC_TCLASS_QUOTA_0_MASK         (0x1FL << MFC_TCLASS_QUOTA_0_SHIFT)
575         u8  pad_0x828_0x900[0x900 - 0x828];                     /* 0x828 */
576
577         /* Real Mode Support Registers */
578         u64 mfc_rm_boundary;                                    /* 0x900 */
579         u8  pad_0x908_0x938[0x30];                              /* 0x908 */
580         u64 smf_dma_signal_sel;                                 /* 0x938 */
581 #define mfc_dma1_mask_lsb       41
582 #define mfc_dma1_shift          (63 - mfc_dma1_mask_lsb)
583 #define mfc_dma1_mask           (0x3LL << mfc_dma1_shift)
584 #define mfc_dma1_bits           (0x1LL << mfc_dma1_shift)
585 #define mfc_dma2_mask_lsb       43
586 #define mfc_dma2_shift          (63 - mfc_dma2_mask_lsb)
587 #define mfc_dma2_mask           (0x3LL << mfc_dma2_shift)
588 #define mfc_dma2_bits           (0x1LL << mfc_dma2_shift)
589         u8  pad_0x940_0xa38[0xf8];                              /* 0x940 */
590         u64 smm_signal_sel;                                     /* 0xa38 */
591 #define smm_sig_mask_lsb        12
592 #define smm_sig_shift           (63 - smm_sig_mask_lsb)
593 #define smm_sig_mask            (0x3LL << smm_sig_shift)
594 #define smm_sig_bus0_bits       (0x2LL << smm_sig_shift)
595 #define smm_sig_bus2_bits       (0x1LL << smm_sig_shift)
596         u8  pad_0xa40_0xc00[0xc00 - 0xa40];                     /* 0xa40 */
597
598         /* DMA Command Error Area */
599         u64 mfc_cer_R;                                          /* 0xc00 */
600 #define MFC_CER_Q               (1 << 31)
601 #define MFC_CER_SPU_QUEUE       MFC_CER_Q
602         u8  pad_0xc08_0x1000[0x1000 - 0xc08];                   /* 0xc08 */
603
604         /* PV1_ImplRegs: Implementation-dependent privileged-state 1 regs */
605         /* DMA Command Error Area */
606         u64 spu_ecc_cntl_RW;                                    /* 0x1000 */
607 #define SPU_ECC_CNTL_E                  (1ull << 0ull)
608 #define SPU_ECC_CNTL_ENABLE             SPU_ECC_CNTL_E
609 #define SPU_ECC_CNTL_DISABLE            (~SPU_ECC_CNTL_E & 1L)
610 #define SPU_ECC_CNTL_S                  (1ull << 1ull)
611 #define SPU_ECC_STOP_AFTER_ERROR        SPU_ECC_CNTL_S
612 #define SPU_ECC_CONTINUE_AFTER_ERROR    (~SPU_ECC_CNTL_S & 2L)
613 #define SPU_ECC_CNTL_B                  (1ull << 2ull)
614 #define SPU_ECC_BACKGROUND_ENABLE       SPU_ECC_CNTL_B
615 #define SPU_ECC_BACKGROUND_DISABLE      (~SPU_ECC_CNTL_B & 4L)
616 #define SPU_ECC_CNTL_I_SHIFT            3ull
617 #define SPU_ECC_CNTL_I_MASK             (3ull << SPU_ECC_CNTL_I_SHIFT)
618 #define SPU_ECC_WRITE_ALWAYS            (~SPU_ECC_CNTL_I & 12L)
619 #define SPU_ECC_WRITE_CORRECTABLE       (1ull << SPU_ECC_CNTL_I_SHIFT)
620 #define SPU_ECC_WRITE_UNCORRECTABLE     (3ull << SPU_ECC_CNTL_I_SHIFT)
621 #define SPU_ECC_CNTL_D                  (1ull << 5ull)
622 #define SPU_ECC_DETECTION_ENABLE        SPU_ECC_CNTL_D
623 #define SPU_ECC_DETECTION_DISABLE       (~SPU_ECC_CNTL_D & 32L)
624         u64 spu_ecc_stat_RW;                                    /* 0x1008 */
625 #define SPU_ECC_CORRECTED_ERROR         (1ull << 0ul)
626 #define SPU_ECC_UNCORRECTED_ERROR       (1ull << 1ul)
627 #define SPU_ECC_SCRUB_COMPLETE          (1ull << 2ul)
628 #define SPU_ECC_SCRUB_IN_PROGRESS       (1ull << 3ul)
629 #define SPU_ECC_INSTRUCTION_ERROR       (1ull << 4ul)
630 #define SPU_ECC_DATA_ERROR              (1ull << 5ul)
631 #define SPU_ECC_DMA_ERROR               (1ull << 6ul)
632 #define SPU_ECC_STATUS_CNT_MASK         (256ull << 8)
633         u64 spu_ecc_addr_RW;                                    /* 0x1010 */
634         u64 spu_err_mask_RW;                                    /* 0x1018 */
635 #define SPU_ERR_ILLEGAL_INSTR           (1ull << 0ul)
636 #define SPU_ERR_ILLEGAL_CHANNEL         (1ull << 1ul)
637         u8  pad_0x1020_0x1028[0x1028 - 0x1020];                 /* 0x1020 */
638
639         /* SPU Debug-Trace Bus (DTB) Selection Registers */
640         u64 spu_trig0_sel;                                      /* 0x1028 */
641         u64 spu_trig1_sel;                                      /* 0x1030 */
642         u64 spu_trig2_sel;                                      /* 0x1038 */
643         u64 spu_trig3_sel;                                      /* 0x1040 */
644         u64 spu_trace_sel;                                      /* 0x1048 */
645 #define spu_trace_sel_mask              0x1f1fLL
646 #define spu_trace_sel_bus0_bits         0x1000LL
647 #define spu_trace_sel_bus2_bits         0x0010LL
648         u64 spu_event0_sel;                                     /* 0x1050 */
649         u64 spu_event1_sel;                                     /* 0x1058 */
650         u64 spu_event2_sel;                                     /* 0x1060 */
651         u64 spu_event3_sel;                                     /* 0x1068 */
652         u64 spu_trace_cntl;                                     /* 0x1070 */
653 } __attribute__ ((aligned(0x2000)));
654
655 #endif /* __KERNEL__ */
656 #endif