1 #ifndef _ASM_POWERPC_MPIC_H
2 #define _ASM_POWERPC_MPIC_H
10 #define MPIC_GREG_BASE 0x01000
12 #define MPIC_GREG_FEATURE_0 0x00000
13 #define MPIC_GREG_FEATURE_LAST_SRC_MASK 0x07ff0000
14 #define MPIC_GREG_FEATURE_LAST_SRC_SHIFT 16
15 #define MPIC_GREG_FEATURE_LAST_CPU_MASK 0x00001f00
16 #define MPIC_GREG_FEATURE_LAST_CPU_SHIFT 8
17 #define MPIC_GREG_FEATURE_VERSION_MASK 0xff
18 #define MPIC_GREG_FEATURE_1 0x00010
19 #define MPIC_GREG_GLOBAL_CONF_0 0x00020
20 #define MPIC_GREG_GCONF_RESET 0x80000000
21 #define MPIC_GREG_GCONF_8259_PTHROU_DIS 0x20000000
22 #define MPIC_GREG_GCONF_BASE_MASK 0x000fffff
23 #define MPIC_GREG_GLOBAL_CONF_1 0x00030
24 #define MPIC_GREG_VENDOR_0 0x00040
25 #define MPIC_GREG_VENDOR_1 0x00050
26 #define MPIC_GREG_VENDOR_2 0x00060
27 #define MPIC_GREG_VENDOR_3 0x00070
28 #define MPIC_GREG_VENDOR_ID 0x00080
29 #define MPIC_GREG_VENDOR_ID_STEPPING_MASK 0x00ff0000
30 #define MPIC_GREG_VENDOR_ID_STEPPING_SHIFT 16
31 #define MPIC_GREG_VENDOR_ID_DEVICE_ID_MASK 0x0000ff00
32 #define MPIC_GREG_VENDOR_ID_DEVICE_ID_SHIFT 8
33 #define MPIC_GREG_VENDOR_ID_VENDOR_ID_MASK 0x000000ff
34 #define MPIC_GREG_PROCESSOR_INIT 0x00090
35 #define MPIC_GREG_IPI_VECTOR_PRI_0 0x000a0
36 #define MPIC_GREG_IPI_VECTOR_PRI_1 0x000b0
37 #define MPIC_GREG_IPI_VECTOR_PRI_2 0x000c0
38 #define MPIC_GREG_IPI_VECTOR_PRI_3 0x000d0
39 #define MPIC_GREG_SPURIOUS 0x000e0
40 #define MPIC_GREG_TIMER_FREQ 0x000f0
46 #define MPIC_TIMER_BASE 0x01100
47 #define MPIC_TIMER_STRIDE 0x40
49 #define MPIC_TIMER_CURRENT_CNT 0x00000
50 #define MPIC_TIMER_BASE_CNT 0x00010
51 #define MPIC_TIMER_VECTOR_PRI 0x00020
52 #define MPIC_TIMER_DESTINATION 0x00030
55 * Per-Processor registers
58 #define MPIC_CPU_THISBASE 0x00000
59 #define MPIC_CPU_BASE 0x20000
60 #define MPIC_CPU_STRIDE 0x01000
62 #define MPIC_CPU_IPI_DISPATCH_0 0x00040
63 #define MPIC_CPU_IPI_DISPATCH_1 0x00050
64 #define MPIC_CPU_IPI_DISPATCH_2 0x00060
65 #define MPIC_CPU_IPI_DISPATCH_3 0x00070
66 #define MPIC_CPU_CURRENT_TASK_PRI 0x00080
67 #define MPIC_CPU_TASKPRI_MASK 0x0000000f
68 #define MPIC_CPU_WHOAMI 0x00090
69 #define MPIC_CPU_WHOAMI_MASK 0x0000001f
70 #define MPIC_CPU_INTACK 0x000a0
71 #define MPIC_CPU_EOI 0x000b0
74 * Per-source registers
77 #define MPIC_IRQ_BASE 0x10000
78 #define MPIC_IRQ_STRIDE 0x00020
79 #define MPIC_IRQ_VECTOR_PRI 0x00000
80 #define MPIC_VECPRI_MASK 0x80000000
81 #define MPIC_VECPRI_ACTIVITY 0x40000000 /* Read Only */
82 #define MPIC_VECPRI_PRIORITY_MASK 0x000f0000
83 #define MPIC_VECPRI_PRIORITY_SHIFT 16
84 #define MPIC_VECPRI_VECTOR_MASK 0x000007ff
85 #define MPIC_VECPRI_POLARITY_POSITIVE 0x00800000
86 #define MPIC_VECPRI_POLARITY_NEGATIVE 0x00000000
87 #define MPIC_VECPRI_POLARITY_MASK 0x00800000
88 #define MPIC_VECPRI_SENSE_LEVEL 0x00400000
89 #define MPIC_VECPRI_SENSE_EDGE 0x00000000
90 #define MPIC_VECPRI_SENSE_MASK 0x00400000
91 #define MPIC_IRQ_DESTINATION 0x00010
93 #define MPIC_MAX_IRQ_SOURCES 2048
94 #define MPIC_MAX_CPUS 32
95 #define MPIC_MAX_ISU 32
98 * Special vector numbers (internal use only)
100 #define MPIC_VEC_SPURRIOUS 255
101 #define MPIC_VEC_IPI_3 254
102 #define MPIC_VEC_IPI_2 253
103 #define MPIC_VEC_IPI_1 252
104 #define MPIC_VEC_IPI_0 251
107 #define MPIC_VEC_TIMER_3 250
108 #define MPIC_VEC_TIMER_2 249
109 #define MPIC_VEC_TIMER_1 248
110 #define MPIC_VEC_TIMER_0 247
112 /* Type definition of the cascade handler */
113 typedef int (*mpic_cascade_t)(struct pt_regs *regs, void *data);
115 #ifdef CONFIG_MPIC_BROKEN_U3
116 /* Fixup table entry */
117 struct mpic_irq_fixup
120 u8 __iomem *applebase;
124 #endif /* CONFIG_MPIC_BROKEN_U3 */
127 /* The instance data of a given MPIC */
130 /* The "linux" controller struct */
131 hw_irq_controller hc_irq;
133 hw_irq_controller hc_ipi;
138 /* How many irq sources in a given ISU */
139 unsigned int isu_size;
140 unsigned int isu_shift;
141 unsigned int isu_mask;
142 /* Offset of irq vector numbers */
143 unsigned int irq_offset;
144 unsigned int irq_count;
145 /* Offset of ipi vector numbers */
146 unsigned int ipi_offset;
147 /* Number of sources */
148 unsigned int num_sources;
150 unsigned int num_cpus;
151 /* cascade handler */
152 mpic_cascade_t cascade;
154 unsigned int cascade_vec;
156 unsigned char *senses;
157 unsigned int senses_count;
159 #ifdef CONFIG_MPIC_BROKEN_U3
160 /* The fixup table */
161 struct mpic_irq_fixup *fixups;
162 spinlock_t fixup_lock;
165 /* The various ioremap'ed bases */
166 volatile u32 __iomem *gregs;
167 volatile u32 __iomem *tmregs;
168 volatile u32 __iomem *cpuregs[MPIC_MAX_CPUS];
169 volatile u32 __iomem *isus[MPIC_MAX_ISU];
175 /* This is the primary controller, only that one has IPIs and
176 * has afinity control. A non-primary MPIC always uses CPU0
179 #define MPIC_PRIMARY 0x00000001
180 /* Set this for a big-endian MPIC */
181 #define MPIC_BIG_ENDIAN 0x00000002
183 #define MPIC_BROKEN_U3 0x00000004
184 /* Broken IPI registers (autodetected) */
185 #define MPIC_BROKEN_IPI 0x00000008
186 /* MPIC wants a reset */
187 #define MPIC_WANTS_RESET 0x00000010
189 /* Allocate the controller structure and setup the linux irq descs
190 * for the range if interrupts passed in. No HW initialization is
191 * actually performed.
193 * @phys_addr: physial base address of the MPIC
194 * @flags: flags, see constants above
195 * @isu_size: number of interrupts in an ISU. Use 0 to use a
196 * standard ISU-less setup (aka powermac)
197 * @irq_offset: first irq number to assign to this mpic
198 * @irq_count: number of irqs to use with this mpic IRQ sources. Pass 0
199 * to match the number of sources
200 * @ipi_offset: first irq number to assign to this mpic IPI sources,
201 * used only on primary mpic
202 * @senses: array of sense values
203 * @senses_num: number of entries in the array
205 * Note about the sense array. If none is passed, all interrupts are
206 * setup to be level negative unless MPIC_BROKEN_U3 is set in which
207 * case they are edge positive (and the array is ignored anyway).
208 * The values in the array start at the first source of the MPIC,
209 * that is senses[0] correspond to linux irq "irq_offset".
211 extern struct mpic *mpic_alloc(unsigned long phys_addr,
213 unsigned int isu_size,
214 unsigned int irq_offset,
215 unsigned int irq_count,
216 unsigned int ipi_offset,
217 unsigned char *senses,
218 unsigned int senses_num,
221 /* Assign ISUs, to call before mpic_init()
223 * @mpic: controller structure as returned by mpic_alloc()
224 * @isu_num: ISU number
225 * @phys_addr: physical address of the ISU
227 extern void mpic_assign_isu(struct mpic *mpic, unsigned int isu_num,
228 unsigned long phys_addr);
230 /* Initialize the controller. After this has been called, none of the above
231 * should be called again for this mpic
233 extern void mpic_init(struct mpic *mpic);
235 /* Setup a cascade. Currently, only one cascade is supported this
236 * way, though you can always do a normal request_irq() and add
237 * other cascades this way. You should call this _after_ having
240 * @irq_no: "linux" irq number of the cascade (that is offset'ed vector)
241 * @handler: cascade handler function
243 extern void mpic_setup_cascade(unsigned int irq_no, mpic_cascade_t hanlder,
247 * All of the following functions must only be used after the
248 * ISUs have been assigned and the controller fully initialized
253 /* Change/Read the priority of an interrupt. Default is 8 for irqs and
254 * 10 for IPIs. You can call this on both IPIs and IRQ numbers, but the
255 * IPI number is then the offset'ed (linux irq number mapped to the IPI)
257 extern void mpic_irq_set_priority(unsigned int irq, unsigned int pri);
258 extern unsigned int mpic_irq_get_priority(unsigned int irq);
260 /* Setup a non-boot CPU */
261 extern void mpic_setup_this_cpu(void);
263 /* Clean up for kexec (or cpu offline or ...) */
264 extern void mpic_teardown_this_cpu(int secondary);
266 /* Get the current cpu priority for this cpu (0..15) */
267 extern int mpic_cpu_get_priority(void);
269 /* Set the current cpu priority for this cpu */
270 extern void mpic_cpu_set_priority(int prio);
272 /* Request IPIs on primary mpic */
273 extern void mpic_request_ipis(void);
275 /* Send an IPI (non offseted number 0..3) */
276 extern void mpic_send_ipi(unsigned int ipi_no, unsigned int cpu_mask);
278 /* Send a message (IPI) to a given target (cpu number or MSG_*) */
279 void smp_mpic_message_pass(int target, int msg);
281 /* Fetch interrupt from a given mpic */
282 extern int mpic_get_one_irq(struct mpic *mpic, struct pt_regs *regs);
283 /* This one gets to the primary mpic */
284 extern int mpic_get_irq(struct pt_regs *regs);
286 /* global mpic for pSeries */
287 extern struct mpic *pSeries_mpic;
289 #endif /* _ASM_POWERPC_MPIC_H */