3e5b2deafe4493fe955bbbbd61971227d62f6bce
[linux-2.6.git] / include / asm-powerpc / cputable.h
1 #ifndef __ASM_POWERPC_CPUTABLE_H
2 #define __ASM_POWERPC_CPUTABLE_H
3
4 #include <asm/asm-compat.h>
5
6 #define PPC_FEATURE_32                  0x80000000
7 #define PPC_FEATURE_64                  0x40000000
8 #define PPC_FEATURE_601_INSTR           0x20000000
9 #define PPC_FEATURE_HAS_ALTIVEC         0x10000000
10 #define PPC_FEATURE_HAS_FPU             0x08000000
11 #define PPC_FEATURE_HAS_MMU             0x04000000
12 #define PPC_FEATURE_HAS_4xxMAC          0x02000000
13 #define PPC_FEATURE_UNIFIED_CACHE       0x01000000
14 #define PPC_FEATURE_HAS_SPE             0x00800000
15 #define PPC_FEATURE_HAS_EFP_SINGLE      0x00400000
16 #define PPC_FEATURE_HAS_EFP_DOUBLE      0x00200000
17 #define PPC_FEATURE_NO_TB               0x00100000
18 #define PPC_FEATURE_POWER4              0x00080000
19 #define PPC_FEATURE_POWER5              0x00040000
20 #define PPC_FEATURE_POWER5_PLUS         0x00020000
21 #define PPC_FEATURE_CELL                0x00010000
22 #define PPC_FEATURE_BOOKE               0x00008000
23 #define PPC_FEATURE_SMT                 0x00004000
24 #define PPC_FEATURE_ICACHE_SNOOP        0x00002000
25 #define PPC_FEATURE_ARCH_2_05           0x00001000
26 #define PPC_FEATURE_PA6T                0x00000800
27 #define PPC_FEATURE_HAS_DFP             0x00000400
28 #define PPC_FEATURE_POWER6_EXT          0x00000200
29 #define PPC_FEATURE_ARCH_2_06           0x00000100
30
31 #define PPC_FEATURE_TRUE_LE             0x00000002
32 #define PPC_FEATURE_PPC_LE              0x00000001
33
34 #ifdef __KERNEL__
35 #ifndef __ASSEMBLY__
36
37 /* This structure can grow, it's real size is used by head.S code
38  * via the mkdefs mechanism.
39  */
40 struct cpu_spec;
41
42 typedef void (*cpu_setup_t)(unsigned long offset, struct cpu_spec* spec);
43 typedef void (*cpu_restore_t)(void);
44
45 enum powerpc_oprofile_type {
46         PPC_OPROFILE_INVALID = 0,
47         PPC_OPROFILE_RS64 = 1,
48         PPC_OPROFILE_POWER4 = 2,
49         PPC_OPROFILE_G4 = 3,
50         PPC_OPROFILE_FSL_EMB = 4,
51         PPC_OPROFILE_CELL = 5,
52         PPC_OPROFILE_PA6T = 6,
53 };
54
55 enum powerpc_pmc_type {
56         PPC_PMC_DEFAULT = 0,
57         PPC_PMC_IBM = 1,
58         PPC_PMC_PA6T = 2,
59 };
60
61 struct pt_regs;
62
63 extern int machine_check_generic(struct pt_regs *regs);
64 extern int machine_check_4xx(struct pt_regs *regs);
65 extern int machine_check_440A(struct pt_regs *regs);
66 extern int machine_check_e500(struct pt_regs *regs);
67 extern int machine_check_e200(struct pt_regs *regs);
68
69 /* NOTE WELL: Update identify_cpu() if fields are added or removed! */
70 struct cpu_spec {
71         /* CPU is matched via (PVR & pvr_mask) == pvr_value */
72         unsigned int    pvr_mask;
73         unsigned int    pvr_value;
74
75         char            *cpu_name;
76         unsigned long   cpu_features;           /* Kernel features */
77         unsigned int    cpu_user_features;      /* Userland features */
78
79         /* cache line sizes */
80         unsigned int    icache_bsize;
81         unsigned int    dcache_bsize;
82
83         /* number of performance monitor counters */
84         unsigned int    num_pmcs;
85         enum powerpc_pmc_type pmc_type;
86
87         /* this is called to initialize various CPU bits like L1 cache,
88          * BHT, SPD, etc... from head.S before branching to identify_machine
89          */
90         cpu_setup_t     cpu_setup;
91         /* Used to restore cpu setup on secondary processors and at resume */
92         cpu_restore_t   cpu_restore;
93
94         /* Used by oprofile userspace to select the right counters */
95         char            *oprofile_cpu_type;
96
97         /* Processor specific oprofile operations */
98         enum powerpc_oprofile_type oprofile_type;
99
100         /* Bit locations inside the mmcra change */
101         unsigned long   oprofile_mmcra_sihv;
102         unsigned long   oprofile_mmcra_sipr;
103
104         /* Bits to clear during an oprofile exception */
105         unsigned long   oprofile_mmcra_clear;
106
107         /* Name of processor class, for the ELF AT_PLATFORM entry */
108         char            *platform;
109
110         /* Processor specific machine check handling. Return negative
111          * if the error is fatal, 1 if it was fully recovered and 0 to
112          * pass up (not CPU originated) */
113         int             (*machine_check)(struct pt_regs *regs);
114 };
115
116 extern struct cpu_spec          *cur_cpu_spec;
117
118 extern unsigned int __start___ftr_fixup, __stop___ftr_fixup;
119
120 extern struct cpu_spec *identify_cpu(unsigned long offset, unsigned int pvr);
121 extern void do_feature_fixups(unsigned long value, void *fixup_start,
122                               void *fixup_end);
123
124 #endif /* __ASSEMBLY__ */
125
126 /* CPU kernel features */
127
128 /* Retain the 32b definitions all use bottom half of word */
129 #define CPU_FTR_COHERENT_ICACHE         ASM_CONST(0x0000000000000001)
130 #define CPU_FTR_L2CR                    ASM_CONST(0x0000000000000002)
131 #define CPU_FTR_SPEC7450                ASM_CONST(0x0000000000000004)
132 #define CPU_FTR_ALTIVEC                 ASM_CONST(0x0000000000000008)
133 #define CPU_FTR_TAU                     ASM_CONST(0x0000000000000010)
134 #define CPU_FTR_CAN_DOZE                ASM_CONST(0x0000000000000020)
135 #define CPU_FTR_USE_TB                  ASM_CONST(0x0000000000000040)
136 #define CPU_FTR_L2CSR                   ASM_CONST(0x0000000000000080)
137 #define CPU_FTR_601                     ASM_CONST(0x0000000000000100)
138 #define CPU_FTR_HPTE_TABLE              ASM_CONST(0x0000000000000200)
139 #define CPU_FTR_CAN_NAP                 ASM_CONST(0x0000000000000400)
140 #define CPU_FTR_L3CR                    ASM_CONST(0x0000000000000800)
141 #define CPU_FTR_L3_DISABLE_NAP          ASM_CONST(0x0000000000001000)
142 #define CPU_FTR_NAP_DISABLE_L2_PR       ASM_CONST(0x0000000000002000)
143 #define CPU_FTR_DUAL_PLL_750FX          ASM_CONST(0x0000000000004000)
144 #define CPU_FTR_NO_DPM                  ASM_CONST(0x0000000000008000)
145 #define CPU_FTR_HAS_HIGH_BATS           ASM_CONST(0x0000000000010000)
146 #define CPU_FTR_NEED_COHERENT           ASM_CONST(0x0000000000020000)
147 #define CPU_FTR_NO_BTIC                 ASM_CONST(0x0000000000040000)
148 #define CPU_FTR_BIG_PHYS                ASM_CONST(0x0000000000080000)
149 #define CPU_FTR_NODSISRALIGN            ASM_CONST(0x0000000000100000)
150 #define CPU_FTR_PPC_LE                  ASM_CONST(0x0000000000200000)
151 #define CPU_FTR_REAL_LE                 ASM_CONST(0x0000000000400000)
152 #define CPU_FTR_FPU_UNAVAILABLE         ASM_CONST(0x0000000000800000)
153 #define CPU_FTR_UNIFIED_ID_CACHE        ASM_CONST(0x0000000001000000)
154 #define CPU_FTR_SPE                     ASM_CONST(0x0000000002000000)
155 #define CPU_FTR_NEED_PAIRED_STWCX       ASM_CONST(0x0000000004000000)
156
157 /*
158  * Add the 64-bit processor unique features in the top half of the word;
159  * on 32-bit, make the names available but defined to be 0.
160  */
161 #ifdef __powerpc64__
162 #define LONG_ASM_CONST(x)               ASM_CONST(x)
163 #else
164 #define LONG_ASM_CONST(x)               0
165 #endif
166
167 #define CPU_FTR_SLB                     LONG_ASM_CONST(0x0000000100000000)
168 #define CPU_FTR_16M_PAGE                LONG_ASM_CONST(0x0000000200000000)
169 #define CPU_FTR_TLBIEL                  LONG_ASM_CONST(0x0000000400000000)
170 #define CPU_FTR_NOEXECUTE               LONG_ASM_CONST(0x0000000800000000)
171 #define CPU_FTR_IABR                    LONG_ASM_CONST(0x0000002000000000)
172 #define CPU_FTR_MMCRA                   LONG_ASM_CONST(0x0000004000000000)
173 #define CPU_FTR_CTRL                    LONG_ASM_CONST(0x0000008000000000)
174 #define CPU_FTR_SMT                     LONG_ASM_CONST(0x0000010000000000)
175 #define CPU_FTR_LOCKLESS_TLBIE          LONG_ASM_CONST(0x0000040000000000)
176 #define CPU_FTR_CI_LARGE_PAGE           LONG_ASM_CONST(0x0000100000000000)
177 #define CPU_FTR_PAUSE_ZERO              LONG_ASM_CONST(0x0000200000000000)
178 #define CPU_FTR_PURR                    LONG_ASM_CONST(0x0000400000000000)
179 #define CPU_FTR_CELL_TB_BUG             LONG_ASM_CONST(0x0000800000000000)
180 #define CPU_FTR_SPURR                   LONG_ASM_CONST(0x0001000000000000)
181 #define CPU_FTR_DSCR                    LONG_ASM_CONST(0x0002000000000000)
182 #define CPU_FTR_1T_SEGMENT              LONG_ASM_CONST(0x0004000000000000)
183 #define CPU_FTR_NO_SLBIE_B              LONG_ASM_CONST(0x0008000000000000)
184
185 #ifndef __ASSEMBLY__
186
187 #define CPU_FTR_PPCAS_ARCH_V2   (CPU_FTR_SLB | \
188                                  CPU_FTR_TLBIEL | CPU_FTR_NOEXECUTE | \
189                                  CPU_FTR_NODSISRALIGN | CPU_FTR_16M_PAGE)
190
191 /* We only set the altivec features if the kernel was compiled with altivec
192  * support
193  */
194 #ifdef CONFIG_ALTIVEC
195 #define CPU_FTR_ALTIVEC_COMP    CPU_FTR_ALTIVEC
196 #define PPC_FEATURE_HAS_ALTIVEC_COMP PPC_FEATURE_HAS_ALTIVEC
197 #else
198 #define CPU_FTR_ALTIVEC_COMP    0
199 #define PPC_FEATURE_HAS_ALTIVEC_COMP    0
200 #endif
201
202 /* We only set the spe features if the kernel was compiled with spe
203  * support
204  */
205 #ifdef CONFIG_SPE
206 #define CPU_FTR_SPE_COMP        CPU_FTR_SPE
207 #define PPC_FEATURE_HAS_SPE_COMP PPC_FEATURE_HAS_SPE
208 #define PPC_FEATURE_HAS_EFP_SINGLE_COMP PPC_FEATURE_HAS_EFP_SINGLE
209 #define PPC_FEATURE_HAS_EFP_DOUBLE_COMP PPC_FEATURE_HAS_EFP_DOUBLE
210 #else
211 #define CPU_FTR_SPE_COMP        0
212 #define PPC_FEATURE_HAS_SPE_COMP    0
213 #define PPC_FEATURE_HAS_EFP_SINGLE_COMP 0
214 #define PPC_FEATURE_HAS_EFP_DOUBLE_COMP 0
215 #endif
216
217 /* We need to mark all pages as being coherent if we're SMP or we have a
218  * 74[45]x and an MPC107 host bridge. Also 83xx and PowerQUICC II
219  * require it for PCI "streaming/prefetch" to work properly.
220  */
221 #if defined(CONFIG_SMP) || defined(CONFIG_MPC10X_BRIDGE) \
222         || defined(CONFIG_PPC_83xx) || defined(CONFIG_8260)
223 #define CPU_FTR_COMMON                  CPU_FTR_NEED_COHERENT
224 #else
225 #define CPU_FTR_COMMON                  0
226 #endif
227
228 /* The powersave features NAP & DOZE seems to confuse BDI when
229    debugging. So if a BDI is used, disable theses
230  */
231 #ifndef CONFIG_BDI_SWITCH
232 #define CPU_FTR_MAYBE_CAN_DOZE  CPU_FTR_CAN_DOZE
233 #define CPU_FTR_MAYBE_CAN_NAP   CPU_FTR_CAN_NAP
234 #else
235 #define CPU_FTR_MAYBE_CAN_DOZE  0
236 #define CPU_FTR_MAYBE_CAN_NAP   0
237 #endif
238
239 #define CLASSIC_PPC (!defined(CONFIG_8xx) && !defined(CONFIG_4xx) && \
240                      !defined(CONFIG_POWER3) && !defined(CONFIG_POWER4) && \
241                      !defined(CONFIG_BOOKE))
242
243 #define CPU_FTRS_PPC601 (CPU_FTR_COMMON | CPU_FTR_601 | CPU_FTR_HPTE_TABLE | \
244         CPU_FTR_COHERENT_ICACHE | CPU_FTR_UNIFIED_ID_CACHE)
245 #define CPU_FTRS_603    (CPU_FTR_COMMON | \
246             CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | \
247             CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_PPC_LE)
248 #define CPU_FTRS_604    (CPU_FTR_COMMON | \
249             CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE | CPU_FTR_PPC_LE)
250 #define CPU_FTRS_740_NOTAU      (CPU_FTR_COMMON | \
251             CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR | \
252             CPU_FTR_HPTE_TABLE | CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_PPC_LE)
253 #define CPU_FTRS_740    (CPU_FTR_COMMON | \
254             CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR | \
255             CPU_FTR_TAU | CPU_FTR_HPTE_TABLE | CPU_FTR_MAYBE_CAN_NAP | \
256             CPU_FTR_PPC_LE)
257 #define CPU_FTRS_750    (CPU_FTR_COMMON | \
258             CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR | \
259             CPU_FTR_TAU | CPU_FTR_HPTE_TABLE | CPU_FTR_MAYBE_CAN_NAP | \
260             CPU_FTR_PPC_LE)
261 #define CPU_FTRS_750CL  (CPU_FTRS_750 | CPU_FTR_HAS_HIGH_BATS)
262 #define CPU_FTRS_750FX1 (CPU_FTRS_750 | CPU_FTR_DUAL_PLL_750FX | CPU_FTR_NO_DPM)
263 #define CPU_FTRS_750FX2 (CPU_FTRS_750 | CPU_FTR_NO_DPM)
264 #define CPU_FTRS_750FX  (CPU_FTRS_750 | CPU_FTR_DUAL_PLL_750FX | \
265                 CPU_FTR_HAS_HIGH_BATS)
266 #define CPU_FTRS_750GX  (CPU_FTRS_750FX)
267 #define CPU_FTRS_7400_NOTAU     (CPU_FTR_COMMON | \
268             CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR | \
269             CPU_FTR_ALTIVEC_COMP | CPU_FTR_HPTE_TABLE | \
270             CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_PPC_LE)
271 #define CPU_FTRS_7400   (CPU_FTR_COMMON | \
272             CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR | \
273             CPU_FTR_TAU | CPU_FTR_ALTIVEC_COMP | CPU_FTR_HPTE_TABLE | \
274             CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_PPC_LE)
275 #define CPU_FTRS_7450_20        (CPU_FTR_COMMON | \
276             CPU_FTR_USE_TB | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
277             CPU_FTR_L3CR | CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | \
278             CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE | CPU_FTR_NEED_PAIRED_STWCX)
279 #define CPU_FTRS_7450_21        (CPU_FTR_COMMON | \
280             CPU_FTR_USE_TB | \
281             CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
282             CPU_FTR_L3CR | CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | \
283             CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_L3_DISABLE_NAP | \
284             CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE | CPU_FTR_NEED_PAIRED_STWCX)
285 #define CPU_FTRS_7450_23        (CPU_FTR_COMMON | \
286             CPU_FTR_USE_TB | CPU_FTR_NEED_PAIRED_STWCX | \
287             CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
288             CPU_FTR_L3CR | CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | \
289             CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE)
290 #define CPU_FTRS_7455_1 (CPU_FTR_COMMON | \
291             CPU_FTR_USE_TB | CPU_FTR_NEED_PAIRED_STWCX | \
292             CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | CPU_FTR_L3CR | \
293             CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | CPU_FTR_HAS_HIGH_BATS | \
294             CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE)
295 #define CPU_FTRS_7455_20        (CPU_FTR_COMMON | \
296             CPU_FTR_USE_TB | CPU_FTR_NEED_PAIRED_STWCX | \
297             CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
298             CPU_FTR_L3CR | CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | \
299             CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_L3_DISABLE_NAP | \
300             CPU_FTR_NEED_COHERENT | CPU_FTR_HAS_HIGH_BATS | CPU_FTR_PPC_LE)
301 #define CPU_FTRS_7455   (CPU_FTR_COMMON | \
302             CPU_FTR_USE_TB | \
303             CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
304             CPU_FTR_L3CR | CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | \
305             CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_HAS_HIGH_BATS | \
306             CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE | CPU_FTR_NEED_PAIRED_STWCX)
307 #define CPU_FTRS_7447_10        (CPU_FTR_COMMON | \
308             CPU_FTR_USE_TB | \
309             CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
310             CPU_FTR_L3CR | CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | \
311             CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_HAS_HIGH_BATS | \
312             CPU_FTR_NEED_COHERENT | CPU_FTR_NO_BTIC | CPU_FTR_PPC_LE | \
313             CPU_FTR_NEED_PAIRED_STWCX)
314 #define CPU_FTRS_7447   (CPU_FTR_COMMON | \
315             CPU_FTR_USE_TB | \
316             CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
317             CPU_FTR_L3CR | CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | \
318             CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_HAS_HIGH_BATS | \
319             CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE | CPU_FTR_NEED_PAIRED_STWCX)
320 #define CPU_FTRS_7447A  (CPU_FTR_COMMON | \
321             CPU_FTR_USE_TB | \
322             CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
323             CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | \
324             CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_HAS_HIGH_BATS | \
325             CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE | CPU_FTR_NEED_PAIRED_STWCX)
326 #define CPU_FTRS_7448   (CPU_FTR_COMMON | \
327             CPU_FTR_USE_TB | \
328             CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
329             CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | \
330             CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_HAS_HIGH_BATS | \
331             CPU_FTR_PPC_LE | CPU_FTR_NEED_PAIRED_STWCX)
332 #define CPU_FTRS_82XX   (CPU_FTR_COMMON | \
333             CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB)
334 #define CPU_FTRS_G2_LE  (CPU_FTR_COMMON | CPU_FTR_MAYBE_CAN_DOZE | \
335             CPU_FTR_USE_TB | CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_HAS_HIGH_BATS)
336 #define CPU_FTRS_E300   (CPU_FTR_MAYBE_CAN_DOZE | \
337             CPU_FTR_USE_TB | CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_HAS_HIGH_BATS | \
338             CPU_FTR_COMMON)
339 #define CPU_FTRS_E300C2 (CPU_FTR_MAYBE_CAN_DOZE | \
340             CPU_FTR_USE_TB | CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_HAS_HIGH_BATS | \
341             CPU_FTR_COMMON | CPU_FTR_FPU_UNAVAILABLE)
342 #define CPU_FTRS_CLASSIC32      (CPU_FTR_COMMON | \
343             CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE)
344 #define CPU_FTRS_8XX    (CPU_FTR_USE_TB)
345 #define CPU_FTRS_40X    (CPU_FTR_USE_TB | CPU_FTR_NODSISRALIGN)
346 #define CPU_FTRS_44X    (CPU_FTR_USE_TB | CPU_FTR_NODSISRALIGN)
347 #define CPU_FTRS_E200   (CPU_FTR_USE_TB | CPU_FTR_SPE_COMP | \
348             CPU_FTR_NODSISRALIGN | CPU_FTR_COHERENT_ICACHE | \
349             CPU_FTR_UNIFIED_ID_CACHE)
350 #define CPU_FTRS_E500   (CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | \
351             CPU_FTR_SPE_COMP | CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_NODSISRALIGN)
352 #define CPU_FTRS_E500_2 (CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | \
353             CPU_FTR_SPE_COMP | CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_BIG_PHYS | \
354             CPU_FTR_NODSISRALIGN)
355 #define CPU_FTRS_E500MC (CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | \
356             CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_BIG_PHYS | CPU_FTR_NODSISRALIGN | \
357             CPU_FTR_L2CSR)
358 #define CPU_FTRS_GENERIC_32     (CPU_FTR_COMMON | CPU_FTR_NODSISRALIGN)
359
360 /* 64-bit CPUs */
361 #define CPU_FTRS_POWER3 (CPU_FTR_USE_TB | \
362             CPU_FTR_HPTE_TABLE | CPU_FTR_IABR | CPU_FTR_PPC_LE)
363 #define CPU_FTRS_RS64   (CPU_FTR_USE_TB | \
364             CPU_FTR_HPTE_TABLE | CPU_FTR_IABR | \
365             CPU_FTR_MMCRA | CPU_FTR_CTRL)
366 #define CPU_FTRS_POWER4 (CPU_FTR_USE_TB | \
367             CPU_FTR_HPTE_TABLE | CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | \
368             CPU_FTR_MMCRA)
369 #define CPU_FTRS_PPC970 (CPU_FTR_USE_TB | \
370             CPU_FTR_HPTE_TABLE | CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | \
371             CPU_FTR_ALTIVEC_COMP | CPU_FTR_CAN_NAP | CPU_FTR_MMCRA)
372 #define CPU_FTRS_POWER5 (CPU_FTR_USE_TB | \
373             CPU_FTR_HPTE_TABLE | CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | \
374             CPU_FTR_MMCRA | CPU_FTR_SMT | \
375             CPU_FTR_COHERENT_ICACHE | CPU_FTR_LOCKLESS_TLBIE | \
376             CPU_FTR_PURR)
377 #define CPU_FTRS_POWER6 (CPU_FTR_USE_TB | \
378             CPU_FTR_HPTE_TABLE | CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | \
379             CPU_FTR_MMCRA | CPU_FTR_SMT | \
380             CPU_FTR_COHERENT_ICACHE | CPU_FTR_LOCKLESS_TLBIE | \
381             CPU_FTR_PURR | CPU_FTR_SPURR | CPU_FTR_REAL_LE | \
382             CPU_FTR_DSCR)
383 #define CPU_FTRS_POWER7 (CPU_FTR_USE_TB | \
384             CPU_FTR_HPTE_TABLE | CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | \
385             CPU_FTR_MMCRA | CPU_FTR_SMT | \
386             CPU_FTR_COHERENT_ICACHE | CPU_FTR_LOCKLESS_TLBIE | \
387             CPU_FTR_PURR | CPU_FTR_SPURR | CPU_FTR_REAL_LE | \
388             CPU_FTR_DSCR)
389 #define CPU_FTRS_CELL   (CPU_FTR_USE_TB | \
390             CPU_FTR_HPTE_TABLE | CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | \
391             CPU_FTR_ALTIVEC_COMP | CPU_FTR_MMCRA | CPU_FTR_SMT | \
392             CPU_FTR_PAUSE_ZERO | CPU_FTR_CI_LARGE_PAGE | CPU_FTR_CELL_TB_BUG)
393 #define CPU_FTRS_PA6T (CPU_FTR_USE_TB | \
394             CPU_FTR_HPTE_TABLE | CPU_FTR_PPCAS_ARCH_V2 | \
395             CPU_FTR_ALTIVEC_COMP | CPU_FTR_CI_LARGE_PAGE | \
396             CPU_FTR_PURR | CPU_FTR_REAL_LE | CPU_FTR_NO_SLBIE_B)
397 #define CPU_FTRS_COMPATIBLE     (CPU_FTR_USE_TB | \
398             CPU_FTR_HPTE_TABLE | CPU_FTR_PPCAS_ARCH_V2)
399
400 #ifdef __powerpc64__
401 #define CPU_FTRS_POSSIBLE       \
402             (CPU_FTRS_POWER3 | CPU_FTRS_RS64 | CPU_FTRS_POWER4 |        \
403             CPU_FTRS_PPC970 | CPU_FTRS_POWER5 | CPU_FTRS_POWER6 |       \
404             CPU_FTRS_POWER7 | CPU_FTRS_CELL | CPU_FTRS_PA6T |           \
405             CPU_FTR_1T_SEGMENT)
406 #else
407 enum {
408         CPU_FTRS_POSSIBLE =
409 #if CLASSIC_PPC
410             CPU_FTRS_PPC601 | CPU_FTRS_603 | CPU_FTRS_604 | CPU_FTRS_740_NOTAU |
411             CPU_FTRS_740 | CPU_FTRS_750 | CPU_FTRS_750FX1 |
412             CPU_FTRS_750FX2 | CPU_FTRS_750FX | CPU_FTRS_750GX |
413             CPU_FTRS_7400_NOTAU | CPU_FTRS_7400 | CPU_FTRS_7450_20 |
414             CPU_FTRS_7450_21 | CPU_FTRS_7450_23 | CPU_FTRS_7455_1 |
415             CPU_FTRS_7455_20 | CPU_FTRS_7455 | CPU_FTRS_7447_10 |
416             CPU_FTRS_7447 | CPU_FTRS_7447A | CPU_FTRS_82XX |
417             CPU_FTRS_G2_LE | CPU_FTRS_E300 | CPU_FTRS_E300C2 |
418             CPU_FTRS_CLASSIC32 |
419 #else
420             CPU_FTRS_GENERIC_32 |
421 #endif
422 #ifdef CONFIG_8xx
423             CPU_FTRS_8XX |
424 #endif
425 #ifdef CONFIG_40x
426             CPU_FTRS_40X |
427 #endif
428 #ifdef CONFIG_44x
429             CPU_FTRS_44X |
430 #endif
431 #ifdef CONFIG_E200
432             CPU_FTRS_E200 |
433 #endif
434 #ifdef CONFIG_E500
435             CPU_FTRS_E500 | CPU_FTRS_E500_2 | CPU_FTRS_E500MC |
436 #endif
437             0,
438 };
439 #endif /* __powerpc64__ */
440
441 #ifdef __powerpc64__
442 #define CPU_FTRS_ALWAYS         \
443             (CPU_FTRS_POWER3 & CPU_FTRS_RS64 & CPU_FTRS_POWER4 &        \
444             CPU_FTRS_PPC970 & CPU_FTRS_POWER5 & CPU_FTRS_POWER6 &       \
445             CPU_FTRS_POWER7 & CPU_FTRS_CELL & CPU_FTRS_PA6T & CPU_FTRS_POSSIBLE)
446 #else
447 enum {
448         CPU_FTRS_ALWAYS =
449 #if CLASSIC_PPC
450             CPU_FTRS_PPC601 & CPU_FTRS_603 & CPU_FTRS_604 & CPU_FTRS_740_NOTAU &
451             CPU_FTRS_740 & CPU_FTRS_750 & CPU_FTRS_750FX1 &
452             CPU_FTRS_750FX2 & CPU_FTRS_750FX & CPU_FTRS_750GX &
453             CPU_FTRS_7400_NOTAU & CPU_FTRS_7400 & CPU_FTRS_7450_20 &
454             CPU_FTRS_7450_21 & CPU_FTRS_7450_23 & CPU_FTRS_7455_1 &
455             CPU_FTRS_7455_20 & CPU_FTRS_7455 & CPU_FTRS_7447_10 &
456             CPU_FTRS_7447 & CPU_FTRS_7447A & CPU_FTRS_82XX &
457             CPU_FTRS_G2_LE & CPU_FTRS_E300 & CPU_FTRS_E300C2 &
458             CPU_FTRS_CLASSIC32 &
459 #else
460             CPU_FTRS_GENERIC_32 &
461 #endif
462 #ifdef CONFIG_8xx
463             CPU_FTRS_8XX &
464 #endif
465 #ifdef CONFIG_40x
466             CPU_FTRS_40X &
467 #endif
468 #ifdef CONFIG_44x
469             CPU_FTRS_44X &
470 #endif
471 #ifdef CONFIG_E200
472             CPU_FTRS_E200 &
473 #endif
474 #ifdef CONFIG_E500
475             CPU_FTRS_E500 & CPU_FTRS_E500_2 & CPU_FTRS_E500MC &
476 #endif
477             CPU_FTRS_POSSIBLE,
478 };
479 #endif /* __powerpc64__ */
480
481 static inline int cpu_has_feature(unsigned long feature)
482 {
483         return (CPU_FTRS_ALWAYS & feature) ||
484                (CPU_FTRS_POSSIBLE
485                 & cur_cpu_spec->cpu_features
486                 & feature);
487 }
488
489 #endif /* !__ASSEMBLY__ */
490
491 #ifdef __ASSEMBLY__
492
493 #define BEGIN_FTR_SECTION_NESTED(label) label:
494 #define BEGIN_FTR_SECTION               BEGIN_FTR_SECTION_NESTED(97)
495 #define END_FTR_SECTION_NESTED(msk, val, label) \
496         MAKE_FTR_SECTION_ENTRY(msk, val, label, __ftr_fixup)
497 #define END_FTR_SECTION(msk, val)               \
498         END_FTR_SECTION_NESTED(msk, val, 97)
499
500 #define END_FTR_SECTION_IFSET(msk)      END_FTR_SECTION((msk), (msk))
501 #define END_FTR_SECTION_IFCLR(msk)      END_FTR_SECTION((msk), 0)
502 #endif /* __ASSEMBLY__ */
503
504 #endif /* __KERNEL__ */
505 #endif /* __ASM_POWERPC_CPUTABLE_H */