powerpc: Don't export asm/asm-compat.h to userspace
[linux-2.6.git] / include / asm-powerpc / cputable.h
1 #ifndef __ASM_POWERPC_CPUTABLE_H
2 #define __ASM_POWERPC_CPUTABLE_H
3
4 #define PPC_FEATURE_32                  0x80000000
5 #define PPC_FEATURE_64                  0x40000000
6 #define PPC_FEATURE_601_INSTR           0x20000000
7 #define PPC_FEATURE_HAS_ALTIVEC         0x10000000
8 #define PPC_FEATURE_HAS_FPU             0x08000000
9 #define PPC_FEATURE_HAS_MMU             0x04000000
10 #define PPC_FEATURE_HAS_4xxMAC          0x02000000
11 #define PPC_FEATURE_UNIFIED_CACHE       0x01000000
12 #define PPC_FEATURE_HAS_SPE             0x00800000
13 #define PPC_FEATURE_HAS_EFP_SINGLE      0x00400000
14 #define PPC_FEATURE_HAS_EFP_DOUBLE      0x00200000
15 #define PPC_FEATURE_NO_TB               0x00100000
16 #define PPC_FEATURE_POWER4              0x00080000
17 #define PPC_FEATURE_POWER5              0x00040000
18 #define PPC_FEATURE_POWER5_PLUS         0x00020000
19 #define PPC_FEATURE_CELL                0x00010000
20 #define PPC_FEATURE_BOOKE               0x00008000
21 #define PPC_FEATURE_SMT                 0x00004000
22 #define PPC_FEATURE_ICACHE_SNOOP        0x00002000
23 #define PPC_FEATURE_ARCH_2_05           0x00001000
24 #define PPC_FEATURE_PA6T                0x00000800
25 #define PPC_FEATURE_HAS_DFP             0x00000400
26 #define PPC_FEATURE_POWER6_EXT          0x00000200
27 #define PPC_FEATURE_ARCH_2_06           0x00000100
28
29 #define PPC_FEATURE_TRUE_LE             0x00000002
30 #define PPC_FEATURE_PPC_LE              0x00000001
31
32 #ifdef __KERNEL__
33
34 #include <asm/asm-compat.h>
35
36 #ifndef __ASSEMBLY__
37
38 /* This structure can grow, it's real size is used by head.S code
39  * via the mkdefs mechanism.
40  */
41 struct cpu_spec;
42
43 typedef void (*cpu_setup_t)(unsigned long offset, struct cpu_spec* spec);
44 typedef void (*cpu_restore_t)(void);
45
46 enum powerpc_oprofile_type {
47         PPC_OPROFILE_INVALID = 0,
48         PPC_OPROFILE_RS64 = 1,
49         PPC_OPROFILE_POWER4 = 2,
50         PPC_OPROFILE_G4 = 3,
51         PPC_OPROFILE_FSL_EMB = 4,
52         PPC_OPROFILE_CELL = 5,
53         PPC_OPROFILE_PA6T = 6,
54 };
55
56 enum powerpc_pmc_type {
57         PPC_PMC_DEFAULT = 0,
58         PPC_PMC_IBM = 1,
59         PPC_PMC_PA6T = 2,
60 };
61
62 struct pt_regs;
63
64 extern int machine_check_generic(struct pt_regs *regs);
65 extern int machine_check_4xx(struct pt_regs *regs);
66 extern int machine_check_440A(struct pt_regs *regs);
67 extern int machine_check_e500(struct pt_regs *regs);
68 extern int machine_check_e200(struct pt_regs *regs);
69
70 /* NOTE WELL: Update identify_cpu() if fields are added or removed! */
71 struct cpu_spec {
72         /* CPU is matched via (PVR & pvr_mask) == pvr_value */
73         unsigned int    pvr_mask;
74         unsigned int    pvr_value;
75
76         char            *cpu_name;
77         unsigned long   cpu_features;           /* Kernel features */
78         unsigned int    cpu_user_features;      /* Userland features */
79
80         /* cache line sizes */
81         unsigned int    icache_bsize;
82         unsigned int    dcache_bsize;
83
84         /* number of performance monitor counters */
85         unsigned int    num_pmcs;
86         enum powerpc_pmc_type pmc_type;
87
88         /* this is called to initialize various CPU bits like L1 cache,
89          * BHT, SPD, etc... from head.S before branching to identify_machine
90          */
91         cpu_setup_t     cpu_setup;
92         /* Used to restore cpu setup on secondary processors and at resume */
93         cpu_restore_t   cpu_restore;
94
95         /* Used by oprofile userspace to select the right counters */
96         char            *oprofile_cpu_type;
97
98         /* Processor specific oprofile operations */
99         enum powerpc_oprofile_type oprofile_type;
100
101         /* Bit locations inside the mmcra change */
102         unsigned long   oprofile_mmcra_sihv;
103         unsigned long   oprofile_mmcra_sipr;
104
105         /* Bits to clear during an oprofile exception */
106         unsigned long   oprofile_mmcra_clear;
107
108         /* Name of processor class, for the ELF AT_PLATFORM entry */
109         char            *platform;
110
111         /* Processor specific machine check handling. Return negative
112          * if the error is fatal, 1 if it was fully recovered and 0 to
113          * pass up (not CPU originated) */
114         int             (*machine_check)(struct pt_regs *regs);
115 };
116
117 extern struct cpu_spec          *cur_cpu_spec;
118
119 extern unsigned int __start___ftr_fixup, __stop___ftr_fixup;
120
121 extern struct cpu_spec *identify_cpu(unsigned long offset, unsigned int pvr);
122 extern void do_feature_fixups(unsigned long value, void *fixup_start,
123                               void *fixup_end);
124
125 #endif /* __ASSEMBLY__ */
126
127 /* CPU kernel features */
128
129 /* Retain the 32b definitions all use bottom half of word */
130 #define CPU_FTR_COHERENT_ICACHE         ASM_CONST(0x0000000000000001)
131 #define CPU_FTR_L2CR                    ASM_CONST(0x0000000000000002)
132 #define CPU_FTR_SPEC7450                ASM_CONST(0x0000000000000004)
133 #define CPU_FTR_ALTIVEC                 ASM_CONST(0x0000000000000008)
134 #define CPU_FTR_TAU                     ASM_CONST(0x0000000000000010)
135 #define CPU_FTR_CAN_DOZE                ASM_CONST(0x0000000000000020)
136 #define CPU_FTR_USE_TB                  ASM_CONST(0x0000000000000040)
137 #define CPU_FTR_L2CSR                   ASM_CONST(0x0000000000000080)
138 #define CPU_FTR_601                     ASM_CONST(0x0000000000000100)
139 #define CPU_FTR_HPTE_TABLE              ASM_CONST(0x0000000000000200)
140 #define CPU_FTR_CAN_NAP                 ASM_CONST(0x0000000000000400)
141 #define CPU_FTR_L3CR                    ASM_CONST(0x0000000000000800)
142 #define CPU_FTR_L3_DISABLE_NAP          ASM_CONST(0x0000000000001000)
143 #define CPU_FTR_NAP_DISABLE_L2_PR       ASM_CONST(0x0000000000002000)
144 #define CPU_FTR_DUAL_PLL_750FX          ASM_CONST(0x0000000000004000)
145 #define CPU_FTR_NO_DPM                  ASM_CONST(0x0000000000008000)
146 #define CPU_FTR_HAS_HIGH_BATS           ASM_CONST(0x0000000000010000)
147 #define CPU_FTR_NEED_COHERENT           ASM_CONST(0x0000000000020000)
148 #define CPU_FTR_NO_BTIC                 ASM_CONST(0x0000000000040000)
149 #define CPU_FTR_BIG_PHYS                ASM_CONST(0x0000000000080000)
150 #define CPU_FTR_NODSISRALIGN            ASM_CONST(0x0000000000100000)
151 #define CPU_FTR_PPC_LE                  ASM_CONST(0x0000000000200000)
152 #define CPU_FTR_REAL_LE                 ASM_CONST(0x0000000000400000)
153 #define CPU_FTR_FPU_UNAVAILABLE         ASM_CONST(0x0000000000800000)
154 #define CPU_FTR_UNIFIED_ID_CACHE        ASM_CONST(0x0000000001000000)
155 #define CPU_FTR_SPE                     ASM_CONST(0x0000000002000000)
156 #define CPU_FTR_NEED_PAIRED_STWCX       ASM_CONST(0x0000000004000000)
157
158 /*
159  * Add the 64-bit processor unique features in the top half of the word;
160  * on 32-bit, make the names available but defined to be 0.
161  */
162 #ifdef __powerpc64__
163 #define LONG_ASM_CONST(x)               ASM_CONST(x)
164 #else
165 #define LONG_ASM_CONST(x)               0
166 #endif
167
168 #define CPU_FTR_SLB                     LONG_ASM_CONST(0x0000000100000000)
169 #define CPU_FTR_16M_PAGE                LONG_ASM_CONST(0x0000000200000000)
170 #define CPU_FTR_TLBIEL                  LONG_ASM_CONST(0x0000000400000000)
171 #define CPU_FTR_NOEXECUTE               LONG_ASM_CONST(0x0000000800000000)
172 #define CPU_FTR_IABR                    LONG_ASM_CONST(0x0000002000000000)
173 #define CPU_FTR_MMCRA                   LONG_ASM_CONST(0x0000004000000000)
174 #define CPU_FTR_CTRL                    LONG_ASM_CONST(0x0000008000000000)
175 #define CPU_FTR_SMT                     LONG_ASM_CONST(0x0000010000000000)
176 #define CPU_FTR_LOCKLESS_TLBIE          LONG_ASM_CONST(0x0000040000000000)
177 #define CPU_FTR_CI_LARGE_PAGE           LONG_ASM_CONST(0x0000100000000000)
178 #define CPU_FTR_PAUSE_ZERO              LONG_ASM_CONST(0x0000200000000000)
179 #define CPU_FTR_PURR                    LONG_ASM_CONST(0x0000400000000000)
180 #define CPU_FTR_CELL_TB_BUG             LONG_ASM_CONST(0x0000800000000000)
181 #define CPU_FTR_SPURR                   LONG_ASM_CONST(0x0001000000000000)
182 #define CPU_FTR_DSCR                    LONG_ASM_CONST(0x0002000000000000)
183 #define CPU_FTR_1T_SEGMENT              LONG_ASM_CONST(0x0004000000000000)
184 #define CPU_FTR_NO_SLBIE_B              LONG_ASM_CONST(0x0008000000000000)
185
186 #ifndef __ASSEMBLY__
187
188 #define CPU_FTR_PPCAS_ARCH_V2   (CPU_FTR_SLB | \
189                                  CPU_FTR_TLBIEL | CPU_FTR_NOEXECUTE | \
190                                  CPU_FTR_NODSISRALIGN | CPU_FTR_16M_PAGE)
191
192 /* We only set the altivec features if the kernel was compiled with altivec
193  * support
194  */
195 #ifdef CONFIG_ALTIVEC
196 #define CPU_FTR_ALTIVEC_COMP    CPU_FTR_ALTIVEC
197 #define PPC_FEATURE_HAS_ALTIVEC_COMP PPC_FEATURE_HAS_ALTIVEC
198 #else
199 #define CPU_FTR_ALTIVEC_COMP    0
200 #define PPC_FEATURE_HAS_ALTIVEC_COMP    0
201 #endif
202
203 /* We only set the spe features if the kernel was compiled with spe
204  * support
205  */
206 #ifdef CONFIG_SPE
207 #define CPU_FTR_SPE_COMP        CPU_FTR_SPE
208 #define PPC_FEATURE_HAS_SPE_COMP PPC_FEATURE_HAS_SPE
209 #define PPC_FEATURE_HAS_EFP_SINGLE_COMP PPC_FEATURE_HAS_EFP_SINGLE
210 #define PPC_FEATURE_HAS_EFP_DOUBLE_COMP PPC_FEATURE_HAS_EFP_DOUBLE
211 #else
212 #define CPU_FTR_SPE_COMP        0
213 #define PPC_FEATURE_HAS_SPE_COMP    0
214 #define PPC_FEATURE_HAS_EFP_SINGLE_COMP 0
215 #define PPC_FEATURE_HAS_EFP_DOUBLE_COMP 0
216 #endif
217
218 /* We need to mark all pages as being coherent if we're SMP or we have a
219  * 74[45]x and an MPC107 host bridge. Also 83xx and PowerQUICC II
220  * require it for PCI "streaming/prefetch" to work properly.
221  */
222 #if defined(CONFIG_SMP) || defined(CONFIG_MPC10X_BRIDGE) \
223         || defined(CONFIG_PPC_83xx) || defined(CONFIG_8260)
224 #define CPU_FTR_COMMON                  CPU_FTR_NEED_COHERENT
225 #else
226 #define CPU_FTR_COMMON                  0
227 #endif
228
229 /* The powersave features NAP & DOZE seems to confuse BDI when
230    debugging. So if a BDI is used, disable theses
231  */
232 #ifndef CONFIG_BDI_SWITCH
233 #define CPU_FTR_MAYBE_CAN_DOZE  CPU_FTR_CAN_DOZE
234 #define CPU_FTR_MAYBE_CAN_NAP   CPU_FTR_CAN_NAP
235 #else
236 #define CPU_FTR_MAYBE_CAN_DOZE  0
237 #define CPU_FTR_MAYBE_CAN_NAP   0
238 #endif
239
240 #define CLASSIC_PPC (!defined(CONFIG_8xx) && !defined(CONFIG_4xx) && \
241                      !defined(CONFIG_POWER3) && !defined(CONFIG_POWER4) && \
242                      !defined(CONFIG_BOOKE))
243
244 #define CPU_FTRS_PPC601 (CPU_FTR_COMMON | CPU_FTR_601 | CPU_FTR_HPTE_TABLE | \
245         CPU_FTR_COHERENT_ICACHE | CPU_FTR_UNIFIED_ID_CACHE)
246 #define CPU_FTRS_603    (CPU_FTR_COMMON | \
247             CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | \
248             CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_PPC_LE)
249 #define CPU_FTRS_604    (CPU_FTR_COMMON | \
250             CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE | CPU_FTR_PPC_LE)
251 #define CPU_FTRS_740_NOTAU      (CPU_FTR_COMMON | \
252             CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR | \
253             CPU_FTR_HPTE_TABLE | CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_PPC_LE)
254 #define CPU_FTRS_740    (CPU_FTR_COMMON | \
255             CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR | \
256             CPU_FTR_TAU | CPU_FTR_HPTE_TABLE | CPU_FTR_MAYBE_CAN_NAP | \
257             CPU_FTR_PPC_LE)
258 #define CPU_FTRS_750    (CPU_FTR_COMMON | \
259             CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR | \
260             CPU_FTR_TAU | CPU_FTR_HPTE_TABLE | CPU_FTR_MAYBE_CAN_NAP | \
261             CPU_FTR_PPC_LE)
262 #define CPU_FTRS_750CL  (CPU_FTRS_750 | CPU_FTR_HAS_HIGH_BATS)
263 #define CPU_FTRS_750FX1 (CPU_FTRS_750 | CPU_FTR_DUAL_PLL_750FX | CPU_FTR_NO_DPM)
264 #define CPU_FTRS_750FX2 (CPU_FTRS_750 | CPU_FTR_NO_DPM)
265 #define CPU_FTRS_750FX  (CPU_FTRS_750 | CPU_FTR_DUAL_PLL_750FX | \
266                 CPU_FTR_HAS_HIGH_BATS)
267 #define CPU_FTRS_750GX  (CPU_FTRS_750FX)
268 #define CPU_FTRS_7400_NOTAU     (CPU_FTR_COMMON | \
269             CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR | \
270             CPU_FTR_ALTIVEC_COMP | CPU_FTR_HPTE_TABLE | \
271             CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_PPC_LE)
272 #define CPU_FTRS_7400   (CPU_FTR_COMMON | \
273             CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR | \
274             CPU_FTR_TAU | CPU_FTR_ALTIVEC_COMP | CPU_FTR_HPTE_TABLE | \
275             CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_PPC_LE)
276 #define CPU_FTRS_7450_20        (CPU_FTR_COMMON | \
277             CPU_FTR_USE_TB | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
278             CPU_FTR_L3CR | CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | \
279             CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE | CPU_FTR_NEED_PAIRED_STWCX)
280 #define CPU_FTRS_7450_21        (CPU_FTR_COMMON | \
281             CPU_FTR_USE_TB | \
282             CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
283             CPU_FTR_L3CR | CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | \
284             CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_L3_DISABLE_NAP | \
285             CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE | CPU_FTR_NEED_PAIRED_STWCX)
286 #define CPU_FTRS_7450_23        (CPU_FTR_COMMON | \
287             CPU_FTR_USE_TB | CPU_FTR_NEED_PAIRED_STWCX | \
288             CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
289             CPU_FTR_L3CR | CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | \
290             CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE)
291 #define CPU_FTRS_7455_1 (CPU_FTR_COMMON | \
292             CPU_FTR_USE_TB | CPU_FTR_NEED_PAIRED_STWCX | \
293             CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | CPU_FTR_L3CR | \
294             CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | CPU_FTR_HAS_HIGH_BATS | \
295             CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE)
296 #define CPU_FTRS_7455_20        (CPU_FTR_COMMON | \
297             CPU_FTR_USE_TB | CPU_FTR_NEED_PAIRED_STWCX | \
298             CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
299             CPU_FTR_L3CR | CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | \
300             CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_L3_DISABLE_NAP | \
301             CPU_FTR_NEED_COHERENT | CPU_FTR_HAS_HIGH_BATS | CPU_FTR_PPC_LE)
302 #define CPU_FTRS_7455   (CPU_FTR_COMMON | \
303             CPU_FTR_USE_TB | \
304             CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
305             CPU_FTR_L3CR | CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | \
306             CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_HAS_HIGH_BATS | \
307             CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE | CPU_FTR_NEED_PAIRED_STWCX)
308 #define CPU_FTRS_7447_10        (CPU_FTR_COMMON | \
309             CPU_FTR_USE_TB | \
310             CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
311             CPU_FTR_L3CR | CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | \
312             CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_HAS_HIGH_BATS | \
313             CPU_FTR_NEED_COHERENT | CPU_FTR_NO_BTIC | CPU_FTR_PPC_LE | \
314             CPU_FTR_NEED_PAIRED_STWCX)
315 #define CPU_FTRS_7447   (CPU_FTR_COMMON | \
316             CPU_FTR_USE_TB | \
317             CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
318             CPU_FTR_L3CR | CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | \
319             CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_HAS_HIGH_BATS | \
320             CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE | CPU_FTR_NEED_PAIRED_STWCX)
321 #define CPU_FTRS_7447A  (CPU_FTR_COMMON | \
322             CPU_FTR_USE_TB | \
323             CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
324             CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | \
325             CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_HAS_HIGH_BATS | \
326             CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE | CPU_FTR_NEED_PAIRED_STWCX)
327 #define CPU_FTRS_7448   (CPU_FTR_COMMON | \
328             CPU_FTR_USE_TB | \
329             CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
330             CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | \
331             CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_HAS_HIGH_BATS | \
332             CPU_FTR_PPC_LE | CPU_FTR_NEED_PAIRED_STWCX)
333 #define CPU_FTRS_82XX   (CPU_FTR_COMMON | \
334             CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB)
335 #define CPU_FTRS_G2_LE  (CPU_FTR_COMMON | CPU_FTR_MAYBE_CAN_DOZE | \
336             CPU_FTR_USE_TB | CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_HAS_HIGH_BATS)
337 #define CPU_FTRS_E300   (CPU_FTR_MAYBE_CAN_DOZE | \
338             CPU_FTR_USE_TB | CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_HAS_HIGH_BATS | \
339             CPU_FTR_COMMON)
340 #define CPU_FTRS_E300C2 (CPU_FTR_MAYBE_CAN_DOZE | \
341             CPU_FTR_USE_TB | CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_HAS_HIGH_BATS | \
342             CPU_FTR_COMMON | CPU_FTR_FPU_UNAVAILABLE)
343 #define CPU_FTRS_CLASSIC32      (CPU_FTR_COMMON | \
344             CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE)
345 #define CPU_FTRS_8XX    (CPU_FTR_USE_TB)
346 #define CPU_FTRS_40X    (CPU_FTR_USE_TB | CPU_FTR_NODSISRALIGN)
347 #define CPU_FTRS_44X    (CPU_FTR_USE_TB | CPU_FTR_NODSISRALIGN)
348 #define CPU_FTRS_E200   (CPU_FTR_USE_TB | CPU_FTR_SPE_COMP | \
349             CPU_FTR_NODSISRALIGN | CPU_FTR_COHERENT_ICACHE | \
350             CPU_FTR_UNIFIED_ID_CACHE)
351 #define CPU_FTRS_E500   (CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | \
352             CPU_FTR_SPE_COMP | CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_NODSISRALIGN)
353 #define CPU_FTRS_E500_2 (CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | \
354             CPU_FTR_SPE_COMP | CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_BIG_PHYS | \
355             CPU_FTR_NODSISRALIGN)
356 #define CPU_FTRS_E500MC (CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | \
357             CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_BIG_PHYS | CPU_FTR_NODSISRALIGN | \
358             CPU_FTR_L2CSR)
359 #define CPU_FTRS_GENERIC_32     (CPU_FTR_COMMON | CPU_FTR_NODSISRALIGN)
360
361 /* 64-bit CPUs */
362 #define CPU_FTRS_POWER3 (CPU_FTR_USE_TB | \
363             CPU_FTR_HPTE_TABLE | CPU_FTR_IABR | CPU_FTR_PPC_LE)
364 #define CPU_FTRS_RS64   (CPU_FTR_USE_TB | \
365             CPU_FTR_HPTE_TABLE | CPU_FTR_IABR | \
366             CPU_FTR_MMCRA | CPU_FTR_CTRL)
367 #define CPU_FTRS_POWER4 (CPU_FTR_USE_TB | \
368             CPU_FTR_HPTE_TABLE | CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | \
369             CPU_FTR_MMCRA)
370 #define CPU_FTRS_PPC970 (CPU_FTR_USE_TB | \
371             CPU_FTR_HPTE_TABLE | CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | \
372             CPU_FTR_ALTIVEC_COMP | CPU_FTR_CAN_NAP | CPU_FTR_MMCRA)
373 #define CPU_FTRS_POWER5 (CPU_FTR_USE_TB | \
374             CPU_FTR_HPTE_TABLE | CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | \
375             CPU_FTR_MMCRA | CPU_FTR_SMT | \
376             CPU_FTR_COHERENT_ICACHE | CPU_FTR_LOCKLESS_TLBIE | \
377             CPU_FTR_PURR)
378 #define CPU_FTRS_POWER6 (CPU_FTR_USE_TB | \
379             CPU_FTR_HPTE_TABLE | CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | \
380             CPU_FTR_MMCRA | CPU_FTR_SMT | \
381             CPU_FTR_COHERENT_ICACHE | CPU_FTR_LOCKLESS_TLBIE | \
382             CPU_FTR_PURR | CPU_FTR_SPURR | CPU_FTR_REAL_LE | \
383             CPU_FTR_DSCR)
384 #define CPU_FTRS_POWER7 (CPU_FTR_USE_TB | \
385             CPU_FTR_HPTE_TABLE | CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | \
386             CPU_FTR_MMCRA | CPU_FTR_SMT | \
387             CPU_FTR_COHERENT_ICACHE | CPU_FTR_LOCKLESS_TLBIE | \
388             CPU_FTR_PURR | CPU_FTR_SPURR | CPU_FTR_REAL_LE | \
389             CPU_FTR_DSCR)
390 #define CPU_FTRS_CELL   (CPU_FTR_USE_TB | \
391             CPU_FTR_HPTE_TABLE | CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | \
392             CPU_FTR_ALTIVEC_COMP | CPU_FTR_MMCRA | CPU_FTR_SMT | \
393             CPU_FTR_PAUSE_ZERO | CPU_FTR_CI_LARGE_PAGE | CPU_FTR_CELL_TB_BUG)
394 #define CPU_FTRS_PA6T (CPU_FTR_USE_TB | \
395             CPU_FTR_HPTE_TABLE | CPU_FTR_PPCAS_ARCH_V2 | \
396             CPU_FTR_ALTIVEC_COMP | CPU_FTR_CI_LARGE_PAGE | \
397             CPU_FTR_PURR | CPU_FTR_REAL_LE | CPU_FTR_NO_SLBIE_B)
398 #define CPU_FTRS_COMPATIBLE     (CPU_FTR_USE_TB | \
399             CPU_FTR_HPTE_TABLE | CPU_FTR_PPCAS_ARCH_V2)
400
401 #ifdef __powerpc64__
402 #define CPU_FTRS_POSSIBLE       \
403             (CPU_FTRS_POWER3 | CPU_FTRS_RS64 | CPU_FTRS_POWER4 |        \
404             CPU_FTRS_PPC970 | CPU_FTRS_POWER5 | CPU_FTRS_POWER6 |       \
405             CPU_FTRS_POWER7 | CPU_FTRS_CELL | CPU_FTRS_PA6T |           \
406             CPU_FTR_1T_SEGMENT)
407 #else
408 enum {
409         CPU_FTRS_POSSIBLE =
410 #if CLASSIC_PPC
411             CPU_FTRS_PPC601 | CPU_FTRS_603 | CPU_FTRS_604 | CPU_FTRS_740_NOTAU |
412             CPU_FTRS_740 | CPU_FTRS_750 | CPU_FTRS_750FX1 |
413             CPU_FTRS_750FX2 | CPU_FTRS_750FX | CPU_FTRS_750GX |
414             CPU_FTRS_7400_NOTAU | CPU_FTRS_7400 | CPU_FTRS_7450_20 |
415             CPU_FTRS_7450_21 | CPU_FTRS_7450_23 | CPU_FTRS_7455_1 |
416             CPU_FTRS_7455_20 | CPU_FTRS_7455 | CPU_FTRS_7447_10 |
417             CPU_FTRS_7447 | CPU_FTRS_7447A | CPU_FTRS_82XX |
418             CPU_FTRS_G2_LE | CPU_FTRS_E300 | CPU_FTRS_E300C2 |
419             CPU_FTRS_CLASSIC32 |
420 #else
421             CPU_FTRS_GENERIC_32 |
422 #endif
423 #ifdef CONFIG_8xx
424             CPU_FTRS_8XX |
425 #endif
426 #ifdef CONFIG_40x
427             CPU_FTRS_40X |
428 #endif
429 #ifdef CONFIG_44x
430             CPU_FTRS_44X |
431 #endif
432 #ifdef CONFIG_E200
433             CPU_FTRS_E200 |
434 #endif
435 #ifdef CONFIG_E500
436             CPU_FTRS_E500 | CPU_FTRS_E500_2 | CPU_FTRS_E500MC |
437 #endif
438             0,
439 };
440 #endif /* __powerpc64__ */
441
442 #ifdef __powerpc64__
443 #define CPU_FTRS_ALWAYS         \
444             (CPU_FTRS_POWER3 & CPU_FTRS_RS64 & CPU_FTRS_POWER4 &        \
445             CPU_FTRS_PPC970 & CPU_FTRS_POWER5 & CPU_FTRS_POWER6 &       \
446             CPU_FTRS_POWER7 & CPU_FTRS_CELL & CPU_FTRS_PA6T & CPU_FTRS_POSSIBLE)
447 #else
448 enum {
449         CPU_FTRS_ALWAYS =
450 #if CLASSIC_PPC
451             CPU_FTRS_PPC601 & CPU_FTRS_603 & CPU_FTRS_604 & CPU_FTRS_740_NOTAU &
452             CPU_FTRS_740 & CPU_FTRS_750 & CPU_FTRS_750FX1 &
453             CPU_FTRS_750FX2 & CPU_FTRS_750FX & CPU_FTRS_750GX &
454             CPU_FTRS_7400_NOTAU & CPU_FTRS_7400 & CPU_FTRS_7450_20 &
455             CPU_FTRS_7450_21 & CPU_FTRS_7450_23 & CPU_FTRS_7455_1 &
456             CPU_FTRS_7455_20 & CPU_FTRS_7455 & CPU_FTRS_7447_10 &
457             CPU_FTRS_7447 & CPU_FTRS_7447A & CPU_FTRS_82XX &
458             CPU_FTRS_G2_LE & CPU_FTRS_E300 & CPU_FTRS_E300C2 &
459             CPU_FTRS_CLASSIC32 &
460 #else
461             CPU_FTRS_GENERIC_32 &
462 #endif
463 #ifdef CONFIG_8xx
464             CPU_FTRS_8XX &
465 #endif
466 #ifdef CONFIG_40x
467             CPU_FTRS_40X &
468 #endif
469 #ifdef CONFIG_44x
470             CPU_FTRS_44X &
471 #endif
472 #ifdef CONFIG_E200
473             CPU_FTRS_E200 &
474 #endif
475 #ifdef CONFIG_E500
476             CPU_FTRS_E500 & CPU_FTRS_E500_2 & CPU_FTRS_E500MC &
477 #endif
478             CPU_FTRS_POSSIBLE,
479 };
480 #endif /* __powerpc64__ */
481
482 static inline int cpu_has_feature(unsigned long feature)
483 {
484         return (CPU_FTRS_ALWAYS & feature) ||
485                (CPU_FTRS_POSSIBLE
486                 & cur_cpu_spec->cpu_features
487                 & feature);
488 }
489
490 #endif /* !__ASSEMBLY__ */
491
492 #ifdef __ASSEMBLY__
493
494 #define BEGIN_FTR_SECTION_NESTED(label) label:
495 #define BEGIN_FTR_SECTION               BEGIN_FTR_SECTION_NESTED(97)
496 #define END_FTR_SECTION_NESTED(msk, val, label) \
497         MAKE_FTR_SECTION_ENTRY(msk, val, label, __ftr_fixup)
498 #define END_FTR_SECTION(msk, val)               \
499         END_FTR_SECTION_NESTED(msk, val, 97)
500
501 #define END_FTR_SECTION_IFSET(msk)      END_FTR_SECTION((msk), (msk))
502 #define END_FTR_SECTION_IFCLR(msk)      END_FTR_SECTION((msk), 0)
503 #endif /* __ASSEMBLY__ */
504
505 #endif /* __KERNEL__ */
506 #endif /* __ASM_POWERPC_CPUTABLE_H */