[MIPS] TRACE_IRQFLAGS_SUPPORT support.
[linux-2.6.git] / include / asm-mips / mipsregs.h
1 /*
2  * This file is subject to the terms and conditions of the GNU General Public
3  * License.  See the file "COPYING" in the main directory of this archive
4  * for more details.
5  *
6  * Copyright (C) 1994, 1995, 1996, 1997, 2000, 2001 by Ralf Baechle
7  * Copyright (C) 2000 Silicon Graphics, Inc.
8  * Modified for further R[236]000 support by Paul M. Antoine, 1996.
9  * Kevin D. Kissell, kevink@mips.com and Carsten Langgaard, carstenl@mips.com
10  * Copyright (C) 2000 MIPS Technologies, Inc.  All rights reserved.
11  * Copyright (C) 2003, 2004  Maciej W. Rozycki
12  */
13 #ifndef _ASM_MIPSREGS_H
14 #define _ASM_MIPSREGS_H
15
16 #include <linux/linkage.h>
17 #include <asm/hazards.h>
18
19 /*
20  * The following macros are especially useful for __asm__
21  * inline assembler.
22  */
23 #ifndef __STR
24 #define __STR(x) #x
25 #endif
26 #ifndef STR
27 #define STR(x) __STR(x)
28 #endif
29
30 /*
31  *  Configure language
32  */
33 #ifdef __ASSEMBLY__
34 #define _ULCAST_
35 #else
36 #define _ULCAST_ (unsigned long)
37 #endif
38
39 /*
40  * Coprocessor 0 register names
41  */
42 #define CP0_INDEX $0
43 #define CP0_RANDOM $1
44 #define CP0_ENTRYLO0 $2
45 #define CP0_ENTRYLO1 $3
46 #define CP0_CONF $3
47 #define CP0_CONTEXT $4
48 #define CP0_PAGEMASK $5
49 #define CP0_WIRED $6
50 #define CP0_INFO $7
51 #define CP0_BADVADDR $8
52 #define CP0_COUNT $9
53 #define CP0_ENTRYHI $10
54 #define CP0_COMPARE $11
55 #define CP0_STATUS $12
56 #define CP0_CAUSE $13
57 #define CP0_EPC $14
58 #define CP0_PRID $15
59 #define CP0_CONFIG $16
60 #define CP0_LLADDR $17
61 #define CP0_WATCHLO $18
62 #define CP0_WATCHHI $19
63 #define CP0_XCONTEXT $20
64 #define CP0_FRAMEMASK $21
65 #define CP0_DIAGNOSTIC $22
66 #define CP0_DEBUG $23
67 #define CP0_DEPC $24
68 #define CP0_PERFORMANCE $25
69 #define CP0_ECC $26
70 #define CP0_CACHEERR $27
71 #define CP0_TAGLO $28
72 #define CP0_TAGHI $29
73 #define CP0_ERROREPC $30
74 #define CP0_DESAVE $31
75
76 /*
77  * R4640/R4650 cp0 register names.  These registers are listed
78  * here only for completeness; without MMU these CPUs are not useable
79  * by Linux.  A future ELKS port might take make Linux run on them
80  * though ...
81  */
82 #define CP0_IBASE $0
83 #define CP0_IBOUND $1
84 #define CP0_DBASE $2
85 #define CP0_DBOUND $3
86 #define CP0_CALG $17
87 #define CP0_IWATCH $18
88 #define CP0_DWATCH $19
89
90 /*
91  * Coprocessor 0 Set 1 register names
92  */
93 #define CP0_S1_DERRADDR0  $26
94 #define CP0_S1_DERRADDR1  $27
95 #define CP0_S1_INTCONTROL $20
96
97 /*
98  * Coprocessor 0 Set 2 register names
99  */
100 #define CP0_S2_SRSCTL     $12   /* MIPSR2 */
101
102 /*
103  * Coprocessor 0 Set 3 register names
104  */
105 #define CP0_S3_SRSMAP     $12   /* MIPSR2 */
106
107 /*
108  *  TX39 Series
109  */
110 #define CP0_TX39_CACHE  $7
111
112 /*
113  * Coprocessor 1 (FPU) register names
114  */
115 #define CP1_REVISION   $0
116 #define CP1_STATUS     $31
117
118 /*
119  * FPU Status Register Values
120  */
121 /*
122  * Status Register Values
123  */
124
125 #define FPU_CSR_FLUSH   0x01000000      /* flush denormalised results to 0 */
126 #define FPU_CSR_COND    0x00800000      /* $fcc0 */
127 #define FPU_CSR_COND0   0x00800000      /* $fcc0 */
128 #define FPU_CSR_COND1   0x02000000      /* $fcc1 */
129 #define FPU_CSR_COND2   0x04000000      /* $fcc2 */
130 #define FPU_CSR_COND3   0x08000000      /* $fcc3 */
131 #define FPU_CSR_COND4   0x10000000      /* $fcc4 */
132 #define FPU_CSR_COND5   0x20000000      /* $fcc5 */
133 #define FPU_CSR_COND6   0x40000000      /* $fcc6 */
134 #define FPU_CSR_COND7   0x80000000      /* $fcc7 */
135
136 /*
137  * X the exception cause indicator
138  * E the exception enable
139  * S the sticky/flag bit
140 */
141 #define FPU_CSR_ALL_X   0x0003f000
142 #define FPU_CSR_UNI_X   0x00020000
143 #define FPU_CSR_INV_X   0x00010000
144 #define FPU_CSR_DIV_X   0x00008000
145 #define FPU_CSR_OVF_X   0x00004000
146 #define FPU_CSR_UDF_X   0x00002000
147 #define FPU_CSR_INE_X   0x00001000
148
149 #define FPU_CSR_ALL_E   0x00000f80
150 #define FPU_CSR_INV_E   0x00000800
151 #define FPU_CSR_DIV_E   0x00000400
152 #define FPU_CSR_OVF_E   0x00000200
153 #define FPU_CSR_UDF_E   0x00000100
154 #define FPU_CSR_INE_E   0x00000080
155
156 #define FPU_CSR_ALL_S   0x0000007c
157 #define FPU_CSR_INV_S   0x00000040
158 #define FPU_CSR_DIV_S   0x00000020
159 #define FPU_CSR_OVF_S   0x00000010
160 #define FPU_CSR_UDF_S   0x00000008
161 #define FPU_CSR_INE_S   0x00000004
162
163 /* rounding mode */
164 #define FPU_CSR_RN      0x0     /* nearest */
165 #define FPU_CSR_RZ      0x1     /* towards zero */
166 #define FPU_CSR_RU      0x2     /* towards +Infinity */
167 #define FPU_CSR_RD      0x3     /* towards -Infinity */
168
169
170 /*
171  * Values for PageMask register
172  */
173 #ifdef CONFIG_CPU_VR41XX
174
175 /* Why doesn't stupidity hurt ... */
176
177 #define PM_1K           0x00000000
178 #define PM_4K           0x00001800
179 #define PM_16K          0x00007800
180 #define PM_64K          0x0001f800
181 #define PM_256K         0x0007f800
182
183 #else
184
185 #define PM_4K           0x00000000
186 #define PM_16K          0x00006000
187 #define PM_64K          0x0001e000
188 #define PM_256K         0x0007e000
189 #define PM_1M           0x001fe000
190 #define PM_4M           0x007fe000
191 #define PM_16M          0x01ffe000
192 #define PM_64M          0x07ffe000
193 #define PM_256M         0x1fffe000
194
195 #endif
196
197 /*
198  * Default page size for a given kernel configuration
199  */
200 #ifdef CONFIG_PAGE_SIZE_4KB
201 #define PM_DEFAULT_MASK PM_4K
202 #elif defined(CONFIG_PAGE_SIZE_16KB)
203 #define PM_DEFAULT_MASK PM_16K
204 #elif defined(CONFIG_PAGE_SIZE_64KB)
205 #define PM_DEFAULT_MASK PM_64K
206 #else
207 #error Bad page size configuration!
208 #endif
209
210
211 /*
212  * Values used for computation of new tlb entries
213  */
214 #define PL_4K           12
215 #define PL_16K          14
216 #define PL_64K          16
217 #define PL_256K         18
218 #define PL_1M           20
219 #define PL_4M           22
220 #define PL_16M          24
221 #define PL_64M          26
222 #define PL_256M         28
223
224 /*
225  * R4x00 interrupt enable / cause bits
226  */
227 #define IE_SW0          (_ULCAST_(1) <<  8)
228 #define IE_SW1          (_ULCAST_(1) <<  9)
229 #define IE_IRQ0         (_ULCAST_(1) << 10)
230 #define IE_IRQ1         (_ULCAST_(1) << 11)
231 #define IE_IRQ2         (_ULCAST_(1) << 12)
232 #define IE_IRQ3         (_ULCAST_(1) << 13)
233 #define IE_IRQ4         (_ULCAST_(1) << 14)
234 #define IE_IRQ5         (_ULCAST_(1) << 15)
235
236 /*
237  * R4x00 interrupt cause bits
238  */
239 #define C_SW0           (_ULCAST_(1) <<  8)
240 #define C_SW1           (_ULCAST_(1) <<  9)
241 #define C_IRQ0          (_ULCAST_(1) << 10)
242 #define C_IRQ1          (_ULCAST_(1) << 11)
243 #define C_IRQ2          (_ULCAST_(1) << 12)
244 #define C_IRQ3          (_ULCAST_(1) << 13)
245 #define C_IRQ4          (_ULCAST_(1) << 14)
246 #define C_IRQ5          (_ULCAST_(1) << 15)
247
248 /*
249  * Bitfields in the R4xx0 cp0 status register
250  */
251 #define ST0_IE                  0x00000001
252 #define ST0_EXL                 0x00000002
253 #define ST0_ERL                 0x00000004
254 #define ST0_KSU                 0x00000018
255 #  define KSU_USER              0x00000010
256 #  define KSU_SUPERVISOR        0x00000008
257 #  define KSU_KERNEL            0x00000000
258 #define ST0_UX                  0x00000020
259 #define ST0_SX                  0x00000040
260 #define ST0_KX                  0x00000080
261 #define ST0_DE                  0x00010000
262 #define ST0_CE                  0x00020000
263
264 /*
265  * Setting c0_status.co enables Hit_Writeback and Hit_Writeback_Invalidate
266  * cacheops in userspace.  This bit exists only on RM7000 and RM9000
267  * processors.
268  */
269 #define ST0_CO                  0x08000000
270
271 /*
272  * Bitfields in the R[23]000 cp0 status register.
273  */
274 #define ST0_IEC                 0x00000001
275 #define ST0_KUC                 0x00000002
276 #define ST0_IEP                 0x00000004
277 #define ST0_KUP                 0x00000008
278 #define ST0_IEO                 0x00000010
279 #define ST0_KUO                 0x00000020
280 /* bits 6 & 7 are reserved on R[23]000 */
281 #define ST0_ISC                 0x00010000
282 #define ST0_SWC                 0x00020000
283 #define ST0_CM                  0x00080000
284
285 /*
286  * Bits specific to the R4640/R4650
287  */
288 #define ST0_UM                  (_ULCAST_(1) <<  4)
289 #define ST0_IL                  (_ULCAST_(1) << 23)
290 #define ST0_DL                  (_ULCAST_(1) << 24)
291
292 /*
293  * Enable the MIPS MDMX and DSP ASEs
294  */
295 #define ST0_MX                  0x01000000
296
297 /*
298  * Bitfields in the TX39 family CP0 Configuration Register 3
299  */
300 #define TX39_CONF_ICS_SHIFT     19
301 #define TX39_CONF_ICS_MASK      0x00380000
302 #define TX39_CONF_ICS_1KB       0x00000000
303 #define TX39_CONF_ICS_2KB       0x00080000
304 #define TX39_CONF_ICS_4KB       0x00100000
305 #define TX39_CONF_ICS_8KB       0x00180000
306 #define TX39_CONF_ICS_16KB      0x00200000
307
308 #define TX39_CONF_DCS_SHIFT     16
309 #define TX39_CONF_DCS_MASK      0x00070000
310 #define TX39_CONF_DCS_1KB       0x00000000
311 #define TX39_CONF_DCS_2KB       0x00010000
312 #define TX39_CONF_DCS_4KB       0x00020000
313 #define TX39_CONF_DCS_8KB       0x00030000
314 #define TX39_CONF_DCS_16KB      0x00040000
315
316 #define TX39_CONF_CWFON         0x00004000
317 #define TX39_CONF_WBON          0x00002000
318 #define TX39_CONF_RF_SHIFT      10
319 #define TX39_CONF_RF_MASK       0x00000c00
320 #define TX39_CONF_DOZE          0x00000200
321 #define TX39_CONF_HALT          0x00000100
322 #define TX39_CONF_LOCK          0x00000080
323 #define TX39_CONF_ICE           0x00000020
324 #define TX39_CONF_DCE           0x00000010
325 #define TX39_CONF_IRSIZE_SHIFT  2
326 #define TX39_CONF_IRSIZE_MASK   0x0000000c
327 #define TX39_CONF_DRSIZE_SHIFT  0
328 #define TX39_CONF_DRSIZE_MASK   0x00000003
329
330 /*
331  * Status register bits available in all MIPS CPUs.
332  */
333 #define ST0_IM                  0x0000ff00
334 #define  STATUSB_IP0            8
335 #define  STATUSF_IP0            (_ULCAST_(1) <<  8)
336 #define  STATUSB_IP1            9
337 #define  STATUSF_IP1            (_ULCAST_(1) <<  9)
338 #define  STATUSB_IP2            10
339 #define  STATUSF_IP2            (_ULCAST_(1) << 10)
340 #define  STATUSB_IP3            11
341 #define  STATUSF_IP3            (_ULCAST_(1) << 11)
342 #define  STATUSB_IP4            12
343 #define  STATUSF_IP4            (_ULCAST_(1) << 12)
344 #define  STATUSB_IP5            13
345 #define  STATUSF_IP5            (_ULCAST_(1) << 13)
346 #define  STATUSB_IP6            14
347 #define  STATUSF_IP6            (_ULCAST_(1) << 14)
348 #define  STATUSB_IP7            15
349 #define  STATUSF_IP7            (_ULCAST_(1) << 15)
350 #define  STATUSB_IP8            0
351 #define  STATUSF_IP8            (_ULCAST_(1) <<  0)
352 #define  STATUSB_IP9            1
353 #define  STATUSF_IP9            (_ULCAST_(1) <<  1)
354 #define  STATUSB_IP10           2
355 #define  STATUSF_IP10           (_ULCAST_(1) <<  2)
356 #define  STATUSB_IP11           3
357 #define  STATUSF_IP11           (_ULCAST_(1) <<  3)
358 #define  STATUSB_IP12           4
359 #define  STATUSF_IP12           (_ULCAST_(1) <<  4)
360 #define  STATUSB_IP13           5
361 #define  STATUSF_IP13           (_ULCAST_(1) <<  5)
362 #define  STATUSB_IP14           6
363 #define  STATUSF_IP14           (_ULCAST_(1) <<  6)
364 #define  STATUSB_IP15           7
365 #define  STATUSF_IP15           (_ULCAST_(1) <<  7)
366 #define ST0_CH                  0x00040000
367 #define ST0_SR                  0x00100000
368 #define ST0_TS                  0x00200000
369 #define ST0_BEV                 0x00400000
370 #define ST0_RE                  0x02000000
371 #define ST0_FR                  0x04000000
372 #define ST0_CU                  0xf0000000
373 #define ST0_CU0                 0x10000000
374 #define ST0_CU1                 0x20000000
375 #define ST0_CU2                 0x40000000
376 #define ST0_CU3                 0x80000000
377 #define ST0_XX                  0x80000000      /* MIPS IV naming */
378
379 /*
380  * Bitfields and bit numbers in the coprocessor 0 cause register.
381  *
382  * Refer to your MIPS R4xx0 manual, chapter 5 for explanation.
383  */
384 #define  CAUSEB_EXCCODE         2
385 #define  CAUSEF_EXCCODE         (_ULCAST_(31)  <<  2)
386 #define  CAUSEB_IP              8
387 #define  CAUSEF_IP              (_ULCAST_(255) <<  8)
388 #define  CAUSEB_IP0             8
389 #define  CAUSEF_IP0             (_ULCAST_(1)   <<  8)
390 #define  CAUSEB_IP1             9
391 #define  CAUSEF_IP1             (_ULCAST_(1)   <<  9)
392 #define  CAUSEB_IP2             10
393 #define  CAUSEF_IP2             (_ULCAST_(1)   << 10)
394 #define  CAUSEB_IP3             11
395 #define  CAUSEF_IP3             (_ULCAST_(1)   << 11)
396 #define  CAUSEB_IP4             12
397 #define  CAUSEF_IP4             (_ULCAST_(1)   << 12)
398 #define  CAUSEB_IP5             13
399 #define  CAUSEF_IP5             (_ULCAST_(1)   << 13)
400 #define  CAUSEB_IP6             14
401 #define  CAUSEF_IP6             (_ULCAST_(1)   << 14)
402 #define  CAUSEB_IP7             15
403 #define  CAUSEF_IP7             (_ULCAST_(1)   << 15)
404 #define  CAUSEB_IV              23
405 #define  CAUSEF_IV              (_ULCAST_(1)   << 23)
406 #define  CAUSEB_CE              28
407 #define  CAUSEF_CE              (_ULCAST_(3)   << 28)
408 #define  CAUSEB_BD              31
409 #define  CAUSEF_BD              (_ULCAST_(1)   << 31)
410
411 /*
412  * Bits in the coprocessor 0 config register.
413  */
414 /* Generic bits.  */
415 #define CONF_CM_CACHABLE_NO_WA          0
416 #define CONF_CM_CACHABLE_WA             1
417 #define CONF_CM_UNCACHED                2
418 #define CONF_CM_CACHABLE_NONCOHERENT    3
419 #define CONF_CM_CACHABLE_CE             4
420 #define CONF_CM_CACHABLE_COW            5
421 #define CONF_CM_CACHABLE_CUW            6
422 #define CONF_CM_CACHABLE_ACCELERATED    7
423 #define CONF_CM_CMASK                   7
424 #define CONF_BE                 (_ULCAST_(1) << 15)
425
426 /* Bits common to various processors.  */
427 #define CONF_CU                 (_ULCAST_(1) <<  3)
428 #define CONF_DB                 (_ULCAST_(1) <<  4)
429 #define CONF_IB                 (_ULCAST_(1) <<  5)
430 #define CONF_DC                 (_ULCAST_(7) <<  6)
431 #define CONF_IC                 (_ULCAST_(7) <<  9)
432 #define CONF_EB                 (_ULCAST_(1) << 13)
433 #define CONF_EM                 (_ULCAST_(1) << 14)
434 #define CONF_SM                 (_ULCAST_(1) << 16)
435 #define CONF_SC                 (_ULCAST_(1) << 17)
436 #define CONF_EW                 (_ULCAST_(3) << 18)
437 #define CONF_EP                 (_ULCAST_(15)<< 24)
438 #define CONF_EC                 (_ULCAST_(7) << 28)
439 #define CONF_CM                 (_ULCAST_(1) << 31)
440
441 /* Bits specific to the R4xx0.  */
442 #define R4K_CONF_SW             (_ULCAST_(1) << 20)
443 #define R4K_CONF_SS             (_ULCAST_(1) << 21)
444 #define R4K_CONF_SB             (_ULCAST_(3) << 22)
445
446 /* Bits specific to the R5000.  */
447 #define R5K_CONF_SE             (_ULCAST_(1) << 12)
448 #define R5K_CONF_SS             (_ULCAST_(3) << 20)
449
450 /* Bits specific to the RM7000.  */
451 #define RM7K_CONF_SE            (_ULCAST_(1) <<  3)
452 #define RM7K_CONF_TE            (_ULCAST_(1) << 12)
453 #define RM7K_CONF_CLK           (_ULCAST_(1) << 16)
454 #define RM7K_CONF_TC            (_ULCAST_(1) << 17)
455 #define RM7K_CONF_SI            (_ULCAST_(3) << 20)
456 #define RM7K_CONF_SC            (_ULCAST_(1) << 31)
457
458 /* Bits specific to the R10000.  */
459 #define R10K_CONF_DN            (_ULCAST_(3) <<  3)
460 #define R10K_CONF_CT            (_ULCAST_(1) <<  5)
461 #define R10K_CONF_PE            (_ULCAST_(1) <<  6)
462 #define R10K_CONF_PM            (_ULCAST_(3) <<  7)
463 #define R10K_CONF_EC            (_ULCAST_(15)<<  9)
464 #define R10K_CONF_SB            (_ULCAST_(1) << 13)
465 #define R10K_CONF_SK            (_ULCAST_(1) << 14)
466 #define R10K_CONF_SS            (_ULCAST_(7) << 16)
467 #define R10K_CONF_SC            (_ULCAST_(7) << 19)
468 #define R10K_CONF_DC            (_ULCAST_(7) << 26)
469 #define R10K_CONF_IC            (_ULCAST_(7) << 29)
470
471 /* Bits specific to the VR41xx.  */
472 #define VR41_CONF_CS            (_ULCAST_(1) << 12)
473 #define VR41_CONF_BP            (_ULCAST_(1) << 16)
474 #define VR41_CONF_M16           (_ULCAST_(1) << 20)
475 #define VR41_CONF_AD            (_ULCAST_(1) << 23)
476
477 /* Bits specific to the R30xx.  */
478 #define R30XX_CONF_FDM          (_ULCAST_(1) << 19)
479 #define R30XX_CONF_REV          (_ULCAST_(1) << 22)
480 #define R30XX_CONF_AC           (_ULCAST_(1) << 23)
481 #define R30XX_CONF_RF           (_ULCAST_(1) << 24)
482 #define R30XX_CONF_HALT         (_ULCAST_(1) << 25)
483 #define R30XX_CONF_FPINT        (_ULCAST_(7) << 26)
484 #define R30XX_CONF_DBR          (_ULCAST_(1) << 29)
485 #define R30XX_CONF_SB           (_ULCAST_(1) << 30)
486 #define R30XX_CONF_LOCK         (_ULCAST_(1) << 31)
487
488 /* Bits specific to the TX49.  */
489 #define TX49_CONF_DC            (_ULCAST_(1) << 16)
490 #define TX49_CONF_IC            (_ULCAST_(1) << 17)  /* conflict with CONF_SC */
491 #define TX49_CONF_HALT          (_ULCAST_(1) << 18)
492 #define TX49_CONF_CWFON         (_ULCAST_(1) << 27)
493
494 /* Bits specific to the MIPS32/64 PRA.  */
495 #define MIPS_CONF_MT            (_ULCAST_(7) <<  7)
496 #define MIPS_CONF_AR            (_ULCAST_(7) << 10)
497 #define MIPS_CONF_AT            (_ULCAST_(3) << 13)
498 #define MIPS_CONF_M             (_ULCAST_(1) << 31)
499
500 /*
501  * Bits in the MIPS32/64 PRA coprocessor 0 config registers 1 and above.
502  */
503 #define MIPS_CONF1_FP           (_ULCAST_(1) <<  0)
504 #define MIPS_CONF1_EP           (_ULCAST_(1) <<  1)
505 #define MIPS_CONF1_CA           (_ULCAST_(1) <<  2)
506 #define MIPS_CONF1_WR           (_ULCAST_(1) <<  3)
507 #define MIPS_CONF1_PC           (_ULCAST_(1) <<  4)
508 #define MIPS_CONF1_MD           (_ULCAST_(1) <<  5)
509 #define MIPS_CONF1_C2           (_ULCAST_(1) <<  6)
510 #define MIPS_CONF1_DA           (_ULCAST_(7) <<  7)
511 #define MIPS_CONF1_DL           (_ULCAST_(7) << 10)
512 #define MIPS_CONF1_DS           (_ULCAST_(7) << 13)
513 #define MIPS_CONF1_IA           (_ULCAST_(7) << 16)
514 #define MIPS_CONF1_IL           (_ULCAST_(7) << 19)
515 #define MIPS_CONF1_IS           (_ULCAST_(7) << 22)
516 #define MIPS_CONF1_TLBS         (_ULCAST_(63)<< 25)
517
518 #define MIPS_CONF2_SA           (_ULCAST_(15)<<  0)
519 #define MIPS_CONF2_SL           (_ULCAST_(15)<<  4)
520 #define MIPS_CONF2_SS           (_ULCAST_(15)<<  8)
521 #define MIPS_CONF2_SU           (_ULCAST_(15)<< 12)
522 #define MIPS_CONF2_TA           (_ULCAST_(15)<< 16)
523 #define MIPS_CONF2_TL           (_ULCAST_(15)<< 20)
524 #define MIPS_CONF2_TS           (_ULCAST_(15)<< 24)
525 #define MIPS_CONF2_TU           (_ULCAST_(7) << 28)
526
527 #define MIPS_CONF3_TL           (_ULCAST_(1) <<  0)
528 #define MIPS_CONF3_SM           (_ULCAST_(1) <<  1)
529 #define MIPS_CONF3_MT           (_ULCAST_(1) <<  2)
530 #define MIPS_CONF3_SP           (_ULCAST_(1) <<  4)
531 #define MIPS_CONF3_VINT         (_ULCAST_(1) <<  5)
532 #define MIPS_CONF3_VEIC         (_ULCAST_(1) <<  6)
533 #define MIPS_CONF3_LPA          (_ULCAST_(1) <<  7)
534 #define MIPS_CONF3_DSP          (_ULCAST_(1) << 10)
535
536 /*
537  * Bits in the MIPS32/64 coprocessor 1 (FPU) revision register.
538  */
539 #define MIPS_FPIR_S             (_ULCAST_(1) << 16)
540 #define MIPS_FPIR_D             (_ULCAST_(1) << 17)
541 #define MIPS_FPIR_PS            (_ULCAST_(1) << 18)
542 #define MIPS_FPIR_3D            (_ULCAST_(1) << 19)
543 #define MIPS_FPIR_W             (_ULCAST_(1) << 20)
544 #define MIPS_FPIR_L             (_ULCAST_(1) << 21)
545 #define MIPS_FPIR_F64           (_ULCAST_(1) << 22)
546
547 /*
548  * R10000 performance counter definitions.
549  *
550  * FIXME: The R10000 performance counter opens a nice way to implement CPU
551  *        time accounting with a precission of one cycle.  I don't have
552  *        R10000 silicon but just a manual, so ...
553  */
554
555 /*
556  * Events counted by counter #0
557  */
558 #define CE0_CYCLES                      0
559 #define CE0_INSN_ISSUED                 1
560 #define CE0_LPSC_ISSUED                 2
561 #define CE0_S_ISSUED                    3
562 #define CE0_SC_ISSUED                   4
563 #define CE0_SC_FAILED                   5
564 #define CE0_BRANCH_DECODED              6
565 #define CE0_QW_WB_SECONDARY             7
566 #define CE0_CORRECTED_ECC_ERRORS        8
567 #define CE0_ICACHE_MISSES               9
568 #define CE0_SCACHE_I_MISSES             10
569 #define CE0_SCACHE_I_WAY_MISSPREDICTED  11
570 #define CE0_EXT_INTERVENTIONS_REQ       12
571 #define CE0_EXT_INVALIDATE_REQ          13
572 #define CE0_VIRTUAL_COHERENCY_COND      14
573 #define CE0_INSN_GRADUATED              15
574
575 /*
576  * Events counted by counter #1
577  */
578 #define CE1_CYCLES                      0
579 #define CE1_INSN_GRADUATED              1
580 #define CE1_LPSC_GRADUATED              2
581 #define CE1_S_GRADUATED                 3
582 #define CE1_SC_GRADUATED                4
583 #define CE1_FP_INSN_GRADUATED           5
584 #define CE1_QW_WB_PRIMARY               6
585 #define CE1_TLB_REFILL                  7
586 #define CE1_BRANCH_MISSPREDICTED        8
587 #define CE1_DCACHE_MISS                 9
588 #define CE1_SCACHE_D_MISSES             10
589 #define CE1_SCACHE_D_WAY_MISSPREDICTED  11
590 #define CE1_EXT_INTERVENTION_HITS       12
591 #define CE1_EXT_INVALIDATE_REQ          13
592 #define CE1_SP_HINT_TO_CEXCL_SC_BLOCKS  14
593 #define CE1_SP_HINT_TO_SHARED_SC_BLOCKS 15
594
595 /*
596  * These flags define in which privilege mode the counters count events
597  */
598 #define CEB_USER        8       /* Count events in user mode, EXL = ERL = 0 */
599 #define CEB_SUPERVISOR  4       /* Count events in supvervisor mode EXL = ERL = 0 */
600 #define CEB_KERNEL      2       /* Count events in kernel mode EXL = ERL = 0 */
601 #define CEB_EXL         1       /* Count events with EXL = 1, ERL = 0 */
602
603 #ifndef __ASSEMBLY__
604
605 /*
606  * Functions to access the R10000 performance counters.  These are basically
607  * mfc0 and mtc0 instructions from and to coprocessor register with a 5-bit
608  * performance counter number encoded into bits 1 ... 5 of the instruction.
609  * Only performance counters 0 to 1 actually exist, so for a non-R10000 aware
610  * disassembler these will look like an access to sel 0 or 1.
611  */
612 #define read_r10k_perf_cntr(counter)                            \
613 ({                                                              \
614         unsigned int __res;                                     \
615         __asm__ __volatile__(                                   \
616         "mfpc\t%0, %1"                                          \
617         : "=r" (__res)                                          \
618         : "i" (counter));                                       \
619                                                                 \
620         __res;                                                  \
621 })
622
623 #define write_r10k_perf_cntr(counter,val)                       \
624 do {                                                            \
625         __asm__ __volatile__(                                   \
626         "mtpc\t%0, %1"                                          \
627         :                                                       \
628         : "r" (val), "i" (counter));                            \
629 } while (0)
630
631 #define read_r10k_perf_event(counter)                           \
632 ({                                                              \
633         unsigned int __res;                                     \
634         __asm__ __volatile__(                                   \
635         "mfps\t%0, %1"                                          \
636         : "=r" (__res)                                          \
637         : "i" (counter));                                       \
638                                                                 \
639         __res;                                                  \
640 })
641
642 #define write_r10k_perf_cntl(counter,val)                       \
643 do {                                                            \
644         __asm__ __volatile__(                                   \
645         "mtps\t%0, %1"                                          \
646         :                                                       \
647         : "r" (val), "i" (counter));                            \
648 } while (0)
649
650
651 /*
652  * Macros to access the system control coprocessor
653  */
654
655 #define __read_32bit_c0_register(source, sel)                           \
656 ({ int __res;                                                           \
657         if (sel == 0)                                                   \
658                 __asm__ __volatile__(                                   \
659                         "mfc0\t%0, " #source "\n\t"                     \
660                         : "=r" (__res));                                \
661         else                                                            \
662                 __asm__ __volatile__(                                   \
663                         ".set\tmips32\n\t"                              \
664                         "mfc0\t%0, " #source ", " #sel "\n\t"           \
665                         ".set\tmips0\n\t"                               \
666                         : "=r" (__res));                                \
667         __res;                                                          \
668 })
669
670 #define __read_64bit_c0_register(source, sel)                           \
671 ({ unsigned long long __res;                                            \
672         if (sizeof(unsigned long) == 4)                                 \
673                 __res = __read_64bit_c0_split(source, sel);             \
674         else if (sel == 0)                                              \
675                 __asm__ __volatile__(                                   \
676                         ".set\tmips3\n\t"                               \
677                         "dmfc0\t%0, " #source "\n\t"                    \
678                         ".set\tmips0"                                   \
679                         : "=r" (__res));                                \
680         else                                                            \
681                 __asm__ __volatile__(                                   \
682                         ".set\tmips64\n\t"                              \
683                         "dmfc0\t%0, " #source ", " #sel "\n\t"          \
684                         ".set\tmips0"                                   \
685                         : "=r" (__res));                                \
686         __res;                                                          \
687 })
688
689 #define __write_32bit_c0_register(register, sel, value)                 \
690 do {                                                                    \
691         if (sel == 0)                                                   \
692                 __asm__ __volatile__(                                   \
693                         "mtc0\t%z0, " #register "\n\t"                  \
694                         : : "Jr" ((unsigned int)(value)));              \
695         else                                                            \
696                 __asm__ __volatile__(                                   \
697                         ".set\tmips32\n\t"                              \
698                         "mtc0\t%z0, " #register ", " #sel "\n\t"        \
699                         ".set\tmips0"                                   \
700                         : : "Jr" ((unsigned int)(value)));              \
701 } while (0)
702
703 #define __write_64bit_c0_register(register, sel, value)                 \
704 do {                                                                    \
705         if (sizeof(unsigned long) == 4)                                 \
706                 __write_64bit_c0_split(register, sel, value);           \
707         else if (sel == 0)                                              \
708                 __asm__ __volatile__(                                   \
709                         ".set\tmips3\n\t"                               \
710                         "dmtc0\t%z0, " #register "\n\t"                 \
711                         ".set\tmips0"                                   \
712                         : : "Jr" (value));                              \
713         else                                                            \
714                 __asm__ __volatile__(                                   \
715                         ".set\tmips64\n\t"                              \
716                         "dmtc0\t%z0, " #register ", " #sel "\n\t"       \
717                         ".set\tmips0"                                   \
718                         : : "Jr" (value));                              \
719 } while (0)
720
721 #define __read_ulong_c0_register(reg, sel)                              \
722         ((sizeof(unsigned long) == 4) ?                                 \
723         (unsigned long) __read_32bit_c0_register(reg, sel) :            \
724         (unsigned long) __read_64bit_c0_register(reg, sel))
725
726 #define __write_ulong_c0_register(reg, sel, val)                        \
727 do {                                                                    \
728         if (sizeof(unsigned long) == 4)                                 \
729                 __write_32bit_c0_register(reg, sel, val);               \
730         else                                                            \
731                 __write_64bit_c0_register(reg, sel, val);               \
732 } while (0)
733
734 /*
735  * On RM7000/RM9000 these are uses to access cop0 set 1 registers
736  */
737 #define __read_32bit_c0_ctrl_register(source)                           \
738 ({ int __res;                                                           \
739         __asm__ __volatile__(                                           \
740                 "cfc0\t%0, " #source "\n\t"                             \
741                 : "=r" (__res));                                        \
742         __res;                                                          \
743 })
744
745 #define __write_32bit_c0_ctrl_register(register, value)                 \
746 do {                                                                    \
747         __asm__ __volatile__(                                           \
748                 "ctc0\t%z0, " #register "\n\t"                          \
749                 : : "Jr" ((unsigned int)(value)));                      \
750 } while (0)
751
752 /*
753  * These versions are only needed for systems with more than 38 bits of
754  * physical address space running the 32-bit kernel.  That's none atm :-)
755  */
756 #define __read_64bit_c0_split(source, sel)                              \
757 ({                                                                      \
758         unsigned long long val;                                         \
759         unsigned long flags;                                            \
760                                                                         \
761         local_irq_save(flags);                                          \
762         if (sel == 0)                                                   \
763                 __asm__ __volatile__(                                   \
764                         ".set\tmips64\n\t"                              \
765                         "dmfc0\t%M0, " #source "\n\t"                   \
766                         "dsll\t%L0, %M0, 32\n\t"                        \
767                         "dsrl\t%M0, %M0, 32\n\t"                        \
768                         "dsrl\t%L0, %L0, 32\n\t"                        \
769                         ".set\tmips0"                                   \
770                         : "=r" (val));                                  \
771         else                                                            \
772                 __asm__ __volatile__(                                   \
773                         ".set\tmips64\n\t"                              \
774                         "dmfc0\t%M0, " #source ", " #sel "\n\t"         \
775                         "dsll\t%L0, %M0, 32\n\t"                        \
776                         "dsrl\t%M0, %M0, 32\n\t"                        \
777                         "dsrl\t%L0, %L0, 32\n\t"                        \
778                         ".set\tmips0"                                   \
779                         : "=r" (val));                                  \
780         local_irq_restore(flags);                                       \
781                                                                         \
782         val;                                                            \
783 })
784
785 #define __write_64bit_c0_split(source, sel, val)                        \
786 do {                                                                    \
787         unsigned long flags;                                            \
788                                                                         \
789         local_irq_save(flags);                                          \
790         if (sel == 0)                                                   \
791                 __asm__ __volatile__(                                   \
792                         ".set\tmips64\n\t"                              \
793                         "dsll\t%L0, %L0, 32\n\t"                        \
794                         "dsrl\t%L0, %L0, 32\n\t"                        \
795                         "dsll\t%M0, %M0, 32\n\t"                        \
796                         "or\t%L0, %L0, %M0\n\t"                         \
797                         "dmtc0\t%L0, " #source "\n\t"                   \
798                         ".set\tmips0"                                   \
799                         : : "r" (val));                                 \
800         else                                                            \
801                 __asm__ __volatile__(                                   \
802                         ".set\tmips64\n\t"                              \
803                         "dsll\t%L0, %L0, 32\n\t"                        \
804                         "dsrl\t%L0, %L0, 32\n\t"                        \
805                         "dsll\t%M0, %M0, 32\n\t"                        \
806                         "or\t%L0, %L0, %M0\n\t"                         \
807                         "dmtc0\t%L0, " #source ", " #sel "\n\t"         \
808                         ".set\tmips0"                                   \
809                         : : "r" (val));                                 \
810         local_irq_restore(flags);                                       \
811 } while (0)
812
813 #define read_c0_index()         __read_32bit_c0_register($0, 0)
814 #define write_c0_index(val)     __write_32bit_c0_register($0, 0, val)
815
816 #define read_c0_entrylo0()      __read_ulong_c0_register($2, 0)
817 #define write_c0_entrylo0(val)  __write_ulong_c0_register($2, 0, val)
818
819 #define read_c0_entrylo1()      __read_ulong_c0_register($3, 0)
820 #define write_c0_entrylo1(val)  __write_ulong_c0_register($3, 0, val)
821
822 #define read_c0_conf()          __read_32bit_c0_register($3, 0)
823 #define write_c0_conf(val)      __write_32bit_c0_register($3, 0, val)
824
825 #define read_c0_context()       __read_ulong_c0_register($4, 0)
826 #define write_c0_context(val)   __write_ulong_c0_register($4, 0, val)
827
828 #define read_c0_pagemask()      __read_32bit_c0_register($5, 0)
829 #define write_c0_pagemask(val)  __write_32bit_c0_register($5, 0, val)
830
831 #define read_c0_wired()         __read_32bit_c0_register($6, 0)
832 #define write_c0_wired(val)     __write_32bit_c0_register($6, 0, val)
833
834 #define read_c0_info()          __read_32bit_c0_register($7, 0)
835
836 #define read_c0_cache()         __read_32bit_c0_register($7, 0) /* TX39xx */
837 #define write_c0_cache(val)     __write_32bit_c0_register($7, 0, val)
838
839 #define read_c0_badvaddr()      __read_ulong_c0_register($8, 0)
840 #define write_c0_badvaddr(val)  __write_ulong_c0_register($8, 0, val)
841
842 #define read_c0_count()         __read_32bit_c0_register($9, 0)
843 #define write_c0_count(val)     __write_32bit_c0_register($9, 0, val)
844
845 #define read_c0_count2()        __read_32bit_c0_register($9, 6) /* pnx8550 */
846 #define write_c0_count2(val)    __write_32bit_c0_register($9, 6, val)
847
848 #define read_c0_count3()        __read_32bit_c0_register($9, 7) /* pnx8550 */
849 #define write_c0_count3(val)    __write_32bit_c0_register($9, 7, val)
850
851 #define read_c0_entryhi()       __read_ulong_c0_register($10, 0)
852 #define write_c0_entryhi(val)   __write_ulong_c0_register($10, 0, val)
853
854 #define read_c0_compare()       __read_32bit_c0_register($11, 0)
855 #define write_c0_compare(val)   __write_32bit_c0_register($11, 0, val)
856
857 #define read_c0_compare2()      __read_32bit_c0_register($11, 6) /* pnx8550 */
858 #define write_c0_compare2(val)  __write_32bit_c0_register($11, 6, val)
859
860 #define read_c0_compare3()      __read_32bit_c0_register($11, 7) /* pnx8550 */
861 #define write_c0_compare3(val)  __write_32bit_c0_register($11, 7, val)
862
863 #define read_c0_status()        __read_32bit_c0_register($12, 0)
864 #ifdef CONFIG_MIPS_MT_SMTC
865 #define write_c0_status(val)                                            \
866 do {                                                                    \
867         __write_32bit_c0_register($12, 0, val);                         \
868         __ehb();                                                        \
869 } while (0)
870 #else
871 /*
872  * Legacy non-SMTC code, which may be hazardous
873  * but which might not support EHB
874  */
875 #define write_c0_status(val)    __write_32bit_c0_register($12, 0, val)
876 #endif /* CONFIG_MIPS_MT_SMTC */
877
878 #define read_c0_cause()         __read_32bit_c0_register($13, 0)
879 #define write_c0_cause(val)     __write_32bit_c0_register($13, 0, val)
880
881 #define read_c0_epc()           __read_ulong_c0_register($14, 0)
882 #define write_c0_epc(val)       __write_ulong_c0_register($14, 0, val)
883
884 #define read_c0_prid()          __read_32bit_c0_register($15, 0)
885
886 #define read_c0_config()        __read_32bit_c0_register($16, 0)
887 #define read_c0_config1()       __read_32bit_c0_register($16, 1)
888 #define read_c0_config2()       __read_32bit_c0_register($16, 2)
889 #define read_c0_config3()       __read_32bit_c0_register($16, 3)
890 #define read_c0_config4()       __read_32bit_c0_register($16, 4)
891 #define read_c0_config5()       __read_32bit_c0_register($16, 5)
892 #define read_c0_config6()       __read_32bit_c0_register($16, 6)
893 #define read_c0_config7()       __read_32bit_c0_register($16, 7)
894 #define write_c0_config(val)    __write_32bit_c0_register($16, 0, val)
895 #define write_c0_config1(val)   __write_32bit_c0_register($16, 1, val)
896 #define write_c0_config2(val)   __write_32bit_c0_register($16, 2, val)
897 #define write_c0_config3(val)   __write_32bit_c0_register($16, 3, val)
898 #define write_c0_config4(val)   __write_32bit_c0_register($16, 4, val)
899 #define write_c0_config5(val)   __write_32bit_c0_register($16, 5, val)
900 #define write_c0_config6(val)   __write_32bit_c0_register($16, 6, val)
901 #define write_c0_config7(val)   __write_32bit_c0_register($16, 7, val)
902
903 /*
904  * The WatchLo register.  There may be upto 8 of them.
905  */
906 #define read_c0_watchlo0()      __read_ulong_c0_register($18, 0)
907 #define read_c0_watchlo1()      __read_ulong_c0_register($18, 1)
908 #define read_c0_watchlo2()      __read_ulong_c0_register($18, 2)
909 #define read_c0_watchlo3()      __read_ulong_c0_register($18, 3)
910 #define read_c0_watchlo4()      __read_ulong_c0_register($18, 4)
911 #define read_c0_watchlo5()      __read_ulong_c0_register($18, 5)
912 #define read_c0_watchlo6()      __read_ulong_c0_register($18, 6)
913 #define read_c0_watchlo7()      __read_ulong_c0_register($18, 7)
914 #define write_c0_watchlo0(val)  __write_ulong_c0_register($18, 0, val)
915 #define write_c0_watchlo1(val)  __write_ulong_c0_register($18, 1, val)
916 #define write_c0_watchlo2(val)  __write_ulong_c0_register($18, 2, val)
917 #define write_c0_watchlo3(val)  __write_ulong_c0_register($18, 3, val)
918 #define write_c0_watchlo4(val)  __write_ulong_c0_register($18, 4, val)
919 #define write_c0_watchlo5(val)  __write_ulong_c0_register($18, 5, val)
920 #define write_c0_watchlo6(val)  __write_ulong_c0_register($18, 6, val)
921 #define write_c0_watchlo7(val)  __write_ulong_c0_register($18, 7, val)
922
923 /*
924  * The WatchHi register.  There may be upto 8 of them.
925  */
926 #define read_c0_watchhi0()      __read_32bit_c0_register($19, 0)
927 #define read_c0_watchhi1()      __read_32bit_c0_register($19, 1)
928 #define read_c0_watchhi2()      __read_32bit_c0_register($19, 2)
929 #define read_c0_watchhi3()      __read_32bit_c0_register($19, 3)
930 #define read_c0_watchhi4()      __read_32bit_c0_register($19, 4)
931 #define read_c0_watchhi5()      __read_32bit_c0_register($19, 5)
932 #define read_c0_watchhi6()      __read_32bit_c0_register($19, 6)
933 #define read_c0_watchhi7()      __read_32bit_c0_register($19, 7)
934
935 #define write_c0_watchhi0(val)  __write_32bit_c0_register($19, 0, val)
936 #define write_c0_watchhi1(val)  __write_32bit_c0_register($19, 1, val)
937 #define write_c0_watchhi2(val)  __write_32bit_c0_register($19, 2, val)
938 #define write_c0_watchhi3(val)  __write_32bit_c0_register($19, 3, val)
939 #define write_c0_watchhi4(val)  __write_32bit_c0_register($19, 4, val)
940 #define write_c0_watchhi5(val)  __write_32bit_c0_register($19, 5, val)
941 #define write_c0_watchhi6(val)  __write_32bit_c0_register($19, 6, val)
942 #define write_c0_watchhi7(val)  __write_32bit_c0_register($19, 7, val)
943
944 #define read_c0_xcontext()      __read_ulong_c0_register($20, 0)
945 #define write_c0_xcontext(val)  __write_ulong_c0_register($20, 0, val)
946
947 #define read_c0_intcontrol()    __read_32bit_c0_ctrl_register($20)
948 #define write_c0_intcontrol(val) __write_32bit_c0_ctrl_register($20, val)
949
950 #define read_c0_framemask()     __read_32bit_c0_register($21, 0)
951 #define write_c0_framemask(val) __write_32bit_c0_register($21, 0, val)
952
953 /* RM9000 PerfControl performance counter control register */
954 #define read_c0_perfcontrol()   __read_32bit_c0_register($22, 0)
955 #define write_c0_perfcontrol(val) __write_32bit_c0_register($22, 0, val)
956
957 #define read_c0_diag()          __read_32bit_c0_register($22, 0)
958 #define write_c0_diag(val)      __write_32bit_c0_register($22, 0, val)
959
960 #define read_c0_diag1()         __read_32bit_c0_register($22, 1)
961 #define write_c0_diag1(val)     __write_32bit_c0_register($22, 1, val)
962
963 #define read_c0_diag2()         __read_32bit_c0_register($22, 2)
964 #define write_c0_diag2(val)     __write_32bit_c0_register($22, 2, val)
965
966 #define read_c0_diag3()         __read_32bit_c0_register($22, 3)
967 #define write_c0_diag3(val)     __write_32bit_c0_register($22, 3, val)
968
969 #define read_c0_diag4()         __read_32bit_c0_register($22, 4)
970 #define write_c0_diag4(val)     __write_32bit_c0_register($22, 4, val)
971
972 #define read_c0_diag5()         __read_32bit_c0_register($22, 5)
973 #define write_c0_diag5(val)     __write_32bit_c0_register($22, 5, val)
974
975 #define read_c0_debug()         __read_32bit_c0_register($23, 0)
976 #define write_c0_debug(val)     __write_32bit_c0_register($23, 0, val)
977
978 #define read_c0_depc()          __read_ulong_c0_register($24, 0)
979 #define write_c0_depc(val)      __write_ulong_c0_register($24, 0, val)
980
981 /*
982  * MIPS32 / MIPS64 performance counters
983  */
984 #define read_c0_perfctrl0()     __read_32bit_c0_register($25, 0)
985 #define write_c0_perfctrl0(val) __write_32bit_c0_register($25, 0, val)
986 #define read_c0_perfcntr0()     __read_32bit_c0_register($25, 1)
987 #define write_c0_perfcntr0(val) __write_32bit_c0_register($25, 1, val)
988 #define read_c0_perfctrl1()     __read_32bit_c0_register($25, 2)
989 #define write_c0_perfctrl1(val) __write_32bit_c0_register($25, 2, val)
990 #define read_c0_perfcntr1()     __read_32bit_c0_register($25, 3)
991 #define write_c0_perfcntr1(val) __write_32bit_c0_register($25, 3, val)
992 #define read_c0_perfctrl2()     __read_32bit_c0_register($25, 4)
993 #define write_c0_perfctrl2(val) __write_32bit_c0_register($25, 4, val)
994 #define read_c0_perfcntr2()     __read_32bit_c0_register($25, 5)
995 #define write_c0_perfcntr2(val) __write_32bit_c0_register($25, 5, val)
996 #define read_c0_perfctrl3()     __read_32bit_c0_register($25, 6)
997 #define write_c0_perfctrl3(val) __write_32bit_c0_register($25, 6, val)
998 #define read_c0_perfcntr3()     __read_32bit_c0_register($25, 7)
999 #define write_c0_perfcntr3(val) __write_32bit_c0_register($25, 7, val)
1000
1001 /* RM9000 PerfCount performance counter register */
1002 #define read_c0_perfcount()     __read_64bit_c0_register($25, 0)
1003 #define write_c0_perfcount(val) __write_64bit_c0_register($25, 0, val)
1004
1005 #define read_c0_ecc()           __read_32bit_c0_register($26, 0)
1006 #define write_c0_ecc(val)       __write_32bit_c0_register($26, 0, val)
1007
1008 #define read_c0_derraddr0()     __read_ulong_c0_register($26, 1)
1009 #define write_c0_derraddr0(val) __write_ulong_c0_register($26, 1, val)
1010
1011 #define read_c0_cacheerr()      __read_32bit_c0_register($27, 0)
1012
1013 #define read_c0_derraddr1()     __read_ulong_c0_register($27, 1)
1014 #define write_c0_derraddr1(val) __write_ulong_c0_register($27, 1, val)
1015
1016 #define read_c0_taglo()         __read_32bit_c0_register($28, 0)
1017 #define write_c0_taglo(val)     __write_32bit_c0_register($28, 0, val)
1018
1019 #define read_c0_dtaglo()        __read_32bit_c0_register($28, 2)
1020 #define write_c0_dtaglo(val)    __write_32bit_c0_register($28, 2, val)
1021
1022 #define read_c0_taghi()         __read_32bit_c0_register($29, 0)
1023 #define write_c0_taghi(val)     __write_32bit_c0_register($29, 0, val)
1024
1025 #define read_c0_errorepc()      __read_ulong_c0_register($30, 0)
1026 #define write_c0_errorepc(val)  __write_ulong_c0_register($30, 0, val)
1027
1028 /* MIPSR2 */
1029 #define read_c0_hwrena()        __read_32bit_c0_register($7,0)
1030 #define write_c0_hwrena(val)    __write_32bit_c0_register($7, 0, val)
1031
1032 #define read_c0_intctl()        __read_32bit_c0_register($12, 1)
1033 #define write_c0_intctl(val)    __write_32bit_c0_register($12, 1, val)
1034
1035 #define read_c0_srsctl()        __read_32bit_c0_register($12, 2)
1036 #define write_c0_srsctl(val)    __write_32bit_c0_register($12, 2, val)
1037
1038 #define read_c0_srsmap()        __read_32bit_c0_register($12, 3)
1039 #define write_c0_srsmap(val)    __write_32bit_c0_register($12, 3, val)
1040
1041 #define read_c0_ebase()         __read_32bit_c0_register($15,1)
1042 #define write_c0_ebase(val)     __write_32bit_c0_register($15, 1, val)
1043
1044 /*
1045  * Macros to access the floating point coprocessor control registers
1046  */
1047 #define read_32bit_cp1_register(source)                         \
1048 ({ int __res;                                                   \
1049         __asm__ __volatile__(                                   \
1050         ".set\tpush\n\t"                                        \
1051         ".set\treorder\n\t"                                     \
1052         "cfc1\t%0,"STR(source)"\n\t"                            \
1053         ".set\tpop"                                             \
1054         : "=r" (__res));                                        \
1055         __res;})
1056
1057 #define rddsp(mask)                                                     \
1058 ({                                                                      \
1059         unsigned int __res;                                             \
1060                                                                         \
1061         __asm__ __volatile__(                                           \
1062         "       .set    push                            \n"             \
1063         "       .set    noat                            \n"             \
1064         "       # rddsp $1, %x1                         \n"             \
1065         "       .word   0x7c000cb8 | (%x1 << 16)        \n"             \
1066         "       move    %0, $1                          \n"             \
1067         "       .set    pop                             \n"             \
1068         : "=r" (__res)                                                  \
1069         : "i" (mask));                                                  \
1070         __res;                                                          \
1071 })
1072
1073 #define wrdsp(val, mask)                                                \
1074 do {                                                                    \
1075         __asm__ __volatile__(                                           \
1076         "       .set    push                                    \n"     \
1077         "       .set    noat                                    \n"     \
1078         "       move    $1, %0                                  \n"     \
1079         "       # wrdsp $1, %x1                                 \n"     \
1080         "       .word   0x7c2004f8 | (%x1 << 11)                \n"     \
1081         "       .set    pop                                     \n"     \
1082         :                                                               \
1083         : "r" (val), "i" (mask));                                       \
1084 } while (0)
1085
1086 #if 0   /* Need DSP ASE capable assembler ... */
1087 #define mflo0() ({ long mflo0; __asm__("mflo %0, $ac0" : "=r" (mflo0)); mflo0;})
1088 #define mflo1() ({ long mflo1; __asm__("mflo %0, $ac1" : "=r" (mflo1)); mflo1;})
1089 #define mflo2() ({ long mflo2; __asm__("mflo %0, $ac2" : "=r" (mflo2)); mflo2;})
1090 #define mflo3() ({ long mflo3; __asm__("mflo %0, $ac3" : "=r" (mflo3)); mflo3;})
1091
1092 #define mfhi0() ({ long mfhi0; __asm__("mfhi %0, $ac0" : "=r" (mfhi0)); mfhi0;})
1093 #define mfhi1() ({ long mfhi1; __asm__("mfhi %0, $ac1" : "=r" (mfhi1)); mfhi1;})
1094 #define mfhi2() ({ long mfhi2; __asm__("mfhi %0, $ac2" : "=r" (mfhi2)); mfhi2;})
1095 #define mfhi3() ({ long mfhi3; __asm__("mfhi %0, $ac3" : "=r" (mfhi3)); mfhi3;})
1096
1097 #define mtlo0(x) __asm__("mtlo %0, $ac0" ::"r" (x))
1098 #define mtlo1(x) __asm__("mtlo %0, $ac1" ::"r" (x))
1099 #define mtlo2(x) __asm__("mtlo %0, $ac2" ::"r" (x))
1100 #define mtlo3(x) __asm__("mtlo %0, $ac3" ::"r" (x))
1101
1102 #define mthi0(x) __asm__("mthi %0, $ac0" ::"r" (x))
1103 #define mthi1(x) __asm__("mthi %0, $ac1" ::"r" (x))
1104 #define mthi2(x) __asm__("mthi %0, $ac2" ::"r" (x))
1105 #define mthi3(x) __asm__("mthi %0, $ac3" ::"r" (x))
1106
1107 #else
1108
1109 #define mfhi0()                                                         \
1110 ({                                                                      \
1111         unsigned long __treg;                                           \
1112                                                                         \
1113         __asm__ __volatile__(                                           \
1114         "       .set    push                    \n"                     \
1115         "       .set    noat                    \n"                     \
1116         "       # mfhi  %0, $ac0                \n"                     \
1117         "       .word   0x00000810              \n"                     \
1118         "       move    %0, $1                  \n"                     \
1119         "       .set    pop                     \n"                     \
1120         : "=r" (__treg));                                               \
1121         __treg;                                                         \
1122 })
1123
1124 #define mfhi1()                                                         \
1125 ({                                                                      \
1126         unsigned long __treg;                                           \
1127                                                                         \
1128         __asm__ __volatile__(                                           \
1129         "       .set    push                    \n"                     \
1130         "       .set    noat                    \n"                     \
1131         "       # mfhi  %0, $ac1                \n"                     \
1132         "       .word   0x00200810              \n"                     \
1133         "       move    %0, $1                  \n"                     \
1134         "       .set    pop                     \n"                     \
1135         : "=r" (__treg));                                               \
1136         __treg;                                                         \
1137 })
1138
1139 #define mfhi2()                                                         \
1140 ({                                                                      \
1141         unsigned long __treg;                                           \
1142                                                                         \
1143         __asm__ __volatile__(                                           \
1144         "       .set    push                    \n"                     \
1145         "       .set    noat                    \n"                     \
1146         "       # mfhi  %0, $ac2                \n"                     \
1147         "       .word   0x00400810              \n"                     \
1148         "       move    %0, $1                  \n"                     \
1149         "       .set    pop                     \n"                     \
1150         : "=r" (__treg));                                               \
1151         __treg;                                                         \
1152 })
1153
1154 #define mfhi3()                                                         \
1155 ({                                                                      \
1156         unsigned long __treg;                                           \
1157                                                                         \
1158         __asm__ __volatile__(                                           \
1159         "       .set    push                    \n"                     \
1160         "       .set    noat                    \n"                     \
1161         "       # mfhi  %0, $ac3                \n"                     \
1162         "       .word   0x00600810              \n"                     \
1163         "       move    %0, $1                  \n"                     \
1164         "       .set    pop                     \n"                     \
1165         : "=r" (__treg));                                               \
1166         __treg;                                                         \
1167 })
1168
1169 #define mflo0()                                                         \
1170 ({                                                                      \
1171         unsigned long __treg;                                           \
1172                                                                         \
1173         __asm__ __volatile__(                                           \
1174         "       .set    push                    \n"                     \
1175         "       .set    noat                    \n"                     \
1176         "       # mflo  %0, $ac0                \n"                     \
1177         "       .word   0x00000812              \n"                     \
1178         "       move    %0, $1                  \n"                     \
1179         "       .set    pop                     \n"                     \
1180         : "=r" (__treg));                                               \
1181         __treg;                                                         \
1182 })
1183
1184 #define mflo1()                                                         \
1185 ({                                                                      \
1186         unsigned long __treg;                                           \
1187                                                                         \
1188         __asm__ __volatile__(                                           \
1189         "       .set    push                    \n"                     \
1190         "       .set    noat                    \n"                     \
1191         "       # mflo  %0, $ac1                \n"                     \
1192         "       .word   0x00200812              \n"                     \
1193         "       move    %0, $1                  \n"                     \
1194         "       .set    pop                     \n"                     \
1195         : "=r" (__treg));                                               \
1196         __treg;                                                         \
1197 })
1198
1199 #define mflo2()                                                         \
1200 ({                                                                      \
1201         unsigned long __treg;                                           \
1202                                                                         \
1203         __asm__ __volatile__(                                           \
1204         "       .set    push                    \n"                     \
1205         "       .set    noat                    \n"                     \
1206         "       # mflo  %0, $ac2                \n"                     \
1207         "       .word   0x00400812              \n"                     \
1208         "       move    %0, $1                  \n"                     \
1209         "       .set    pop                     \n"                     \
1210         : "=r" (__treg));                                               \
1211         __treg;                                                         \
1212 })
1213
1214 #define mflo3()                                                         \
1215 ({                                                                      \
1216         unsigned long __treg;                                           \
1217                                                                         \
1218         __asm__ __volatile__(                                           \
1219         "       .set    push                    \n"                     \
1220         "       .set    noat                    \n"                     \
1221         "       # mflo  %0, $ac3                \n"                     \
1222         "       .word   0x00600812              \n"                     \
1223         "       move    %0, $1                  \n"                     \
1224         "       .set    pop                     \n"                     \
1225         : "=r" (__treg));                                               \
1226         __treg;                                                         \
1227 })
1228
1229 #define mthi0(x)                                                        \
1230 do {                                                                    \
1231         __asm__ __volatile__(                                           \
1232         "       .set    push                                    \n"     \
1233         "       .set    noat                                    \n"     \
1234         "       move    $1, %0                                  \n"     \
1235         "       # mthi  $1, $ac0                                \n"     \
1236         "       .word   0x00200011                              \n"     \
1237         "       .set    pop                                     \n"     \
1238         :                                                               \
1239         : "r" (x));                                                     \
1240 } while (0)
1241
1242 #define mthi1(x)                                                        \
1243 do {                                                                    \
1244         __asm__ __volatile__(                                           \
1245         "       .set    push                                    \n"     \
1246         "       .set    noat                                    \n"     \
1247         "       move    $1, %0                                  \n"     \
1248         "       # mthi  $1, $ac1                                \n"     \
1249         "       .word   0x00200811                              \n"     \
1250         "       .set    pop                                     \n"     \
1251         :                                                               \
1252         : "r" (x));                                                     \
1253 } while (0)
1254
1255 #define mthi2(x)                                                        \
1256 do {                                                                    \
1257         __asm__ __volatile__(                                           \
1258         "       .set    push                                    \n"     \
1259         "       .set    noat                                    \n"     \
1260         "       move    $1, %0                                  \n"     \
1261         "       # mthi  $1, $ac2                                \n"     \
1262         "       .word   0x00201011                              \n"     \
1263         "       .set    pop                                     \n"     \
1264         :                                                               \
1265         : "r" (x));                                                     \
1266 } while (0)
1267
1268 #define mthi3(x)                                                        \
1269 do {                                                                    \
1270         __asm__ __volatile__(                                           \
1271         "       .set    push                                    \n"     \
1272         "       .set    noat                                    \n"     \
1273         "       move    $1, %0                                  \n"     \
1274         "       # mthi  $1, $ac3                                \n"     \
1275         "       .word   0x00201811                              \n"     \
1276         "       .set    pop                                     \n"     \
1277         :                                                               \
1278         : "r" (x));                                                     \
1279 } while (0)
1280
1281 #define mtlo0(x)                                                        \
1282 do {                                                                    \
1283         __asm__ __volatile__(                                           \
1284         "       .set    push                                    \n"     \
1285         "       .set    noat                                    \n"     \
1286         "       move    $1, %0                                  \n"     \
1287         "       # mtlo  $1, $ac0                                \n"     \
1288         "       .word   0x00200013                              \n"     \
1289         "       .set    pop                                     \n"     \
1290         :                                                               \
1291         : "r" (x));                                                     \
1292 } while (0)
1293
1294 #define mtlo1(x)                                                        \
1295 do {                                                                    \
1296         __asm__ __volatile__(                                           \
1297         "       .set    push                                    \n"     \
1298         "       .set    noat                                    \n"     \
1299         "       move    $1, %0                                  \n"     \
1300         "       # mtlo  $1, $ac1                                \n"     \
1301         "       .word   0x00200813                              \n"     \
1302         "       .set    pop                                     \n"     \
1303         :                                                               \
1304         : "r" (x));                                                     \
1305 } while (0)
1306
1307 #define mtlo2(x)                                                        \
1308 do {                                                                    \
1309         __asm__ __volatile__(                                           \
1310         "       .set    push                                    \n"     \
1311         "       .set    noat                                    \n"     \
1312         "       move    $1, %0                                  \n"     \
1313         "       # mtlo  $1, $ac2                                \n"     \
1314         "       .word   0x00201013                              \n"     \
1315         "       .set    pop                                     \n"     \
1316         :                                                               \
1317         : "r" (x));                                                     \
1318 } while (0)
1319
1320 #define mtlo3(x)                                                        \
1321 do {                                                                    \
1322         __asm__ __volatile__(                                           \
1323         "       .set    push                                    \n"     \
1324         "       .set    noat                                    \n"     \
1325         "       move    $1, %0                                  \n"     \
1326         "       # mtlo  $1, $ac3                                \n"     \
1327         "       .word   0x00201813                              \n"     \
1328         "       .set    pop                                     \n"     \
1329         :                                                               \
1330         : "r" (x));                                                     \
1331 } while (0)
1332
1333 #endif
1334
1335 /*
1336  * TLB operations.
1337  *
1338  * It is responsibility of the caller to take care of any TLB hazards.
1339  */
1340 static inline void tlb_probe(void)
1341 {
1342         __asm__ __volatile__(
1343                 ".set noreorder\n\t"
1344                 "tlbp\n\t"
1345                 ".set reorder");
1346 }
1347
1348 static inline void tlb_read(void)
1349 {
1350         __asm__ __volatile__(
1351                 ".set noreorder\n\t"
1352                 "tlbr\n\t"
1353                 ".set reorder");
1354 }
1355
1356 static inline void tlb_write_indexed(void)
1357 {
1358         __asm__ __volatile__(
1359                 ".set noreorder\n\t"
1360                 "tlbwi\n\t"
1361                 ".set reorder");
1362 }
1363
1364 static inline void tlb_write_random(void)
1365 {
1366         __asm__ __volatile__(
1367                 ".set noreorder\n\t"
1368                 "tlbwr\n\t"
1369                 ".set reorder");
1370 }
1371
1372 /*
1373  * Manipulate bits in a c0 register.
1374  */
1375 #ifndef CONFIG_MIPS_MT_SMTC
1376 /*
1377  * SMTC Linux requires shutting-down microthread scheduling
1378  * during CP0 register read-modify-write sequences.
1379  */
1380 #define __BUILD_SET_C0(name)                                    \
1381 static inline unsigned int                                      \
1382 set_c0_##name(unsigned int set)                                 \
1383 {                                                               \
1384         unsigned int res;                                       \
1385                                                                 \
1386         res = read_c0_##name();                                 \
1387         res |= set;                                             \
1388         write_c0_##name(res);                                   \
1389                                                                 \
1390         return res;                                             \
1391 }                                                               \
1392                                                                 \
1393 static inline unsigned int                                      \
1394 clear_c0_##name(unsigned int clear)                             \
1395 {                                                               \
1396         unsigned int res;                                       \
1397                                                                 \
1398         res = read_c0_##name();                                 \
1399         res &= ~clear;                                          \
1400         write_c0_##name(res);                                   \
1401                                                                 \
1402         return res;                                             \
1403 }                                                               \
1404                                                                 \
1405 static inline unsigned int                                      \
1406 change_c0_##name(unsigned int change, unsigned int new)         \
1407 {                                                               \
1408         unsigned int res;                                       \
1409                                                                 \
1410         res = read_c0_##name();                                 \
1411         res &= ~change;                                         \
1412         res |= (new & change);                                  \
1413         write_c0_##name(res);                                   \
1414                                                                 \
1415         return res;                                             \
1416 }
1417
1418 #else /* SMTC versions that manage MT scheduling */
1419
1420 #include <linux/irqflags.h>
1421
1422 /*
1423  * This is a duplicate of dmt() in mipsmtregs.h to avoid problems with
1424  * header file recursion.
1425  */
1426 static inline unsigned int __dmt(void)
1427 {
1428         int res;
1429
1430         __asm__ __volatile__(
1431         "       .set    push                                            \n"
1432         "       .set    mips32r2                                        \n"
1433         "       .set    noat                                            \n"
1434         "       .word   0x41610BC1                      # dmt $1        \n"
1435         "       ehb                                                     \n"
1436         "       move    %0, $1                                          \n"
1437         "       .set    pop                                             \n"
1438         : "=r" (res));
1439
1440         instruction_hazard();
1441
1442         return res;
1443 }
1444
1445 #define __VPECONTROL_TE_SHIFT   15
1446 #define __VPECONTROL_TE         (1UL << __VPECONTROL_TE_SHIFT)
1447
1448 #define __EMT_ENABLE            __VPECONTROL_TE
1449
1450 static inline void __emt(unsigned int previous)
1451 {
1452         if ((previous & __EMT_ENABLE))
1453                 __asm__ __volatile__(
1454                 "       .set    mips32r2                                \n"
1455                 "       .word   0x41600be1              # emt           \n"
1456                 "       ehb                                             \n"
1457                 "       .set    mips0                                   \n");
1458 }
1459
1460 static inline void __ehb(void)
1461 {
1462         __asm__ __volatile__(
1463         "       .set    mips32r2                                        \n"
1464         "       ehb                                                     \n"             "       .set    mips0                                           \n");
1465 }
1466
1467 /*
1468  * Note that local_irq_save/restore affect TC-specific IXMT state,
1469  * not Status.IE as in non-SMTC kernel.
1470  */
1471
1472 #define __BUILD_SET_C0(name)                                    \
1473 static inline unsigned int                                      \
1474 set_c0_##name(unsigned int set)                                 \
1475 {                                                               \
1476         unsigned int res;                                       \
1477         unsigned int omt;                                       \
1478         unsigned int flags;                                     \
1479                                                                 \
1480         local_irq_save(flags);                                  \
1481         omt = __dmt();                                          \
1482         res = read_c0_##name();                                 \
1483         res |= set;                                             \
1484         write_c0_##name(res);                                   \
1485         __emt(omt);                                             \
1486         local_irq_restore(flags);                               \
1487                                                                 \
1488         return res;                                             \
1489 }                                                               \
1490                                                                 \
1491 static inline unsigned int                                      \
1492 clear_c0_##name(unsigned int clear)                             \
1493 {                                                               \
1494         unsigned int res;                                       \
1495         unsigned int omt;                                       \
1496         unsigned int flags;                                     \
1497                                                                 \
1498         local_irq_save(flags);                                  \
1499         omt = __dmt();                                          \
1500         res = read_c0_##name();                                 \
1501         res &= ~clear;                                          \
1502         write_c0_##name(res);                                   \
1503         __emt(omt);                                             \
1504         local_irq_restore(flags);                               \
1505                                                                 \
1506         return res;                                             \
1507 }                                                               \
1508                                                                 \
1509 static inline unsigned int                                      \
1510 change_c0_##name(unsigned int change, unsigned int new)         \
1511 {                                                               \
1512         unsigned int res;                                       \
1513         unsigned int omt;                                       \
1514         unsigned int flags;                                     \
1515                                                                 \
1516         local_irq_save(flags);                                  \
1517                                                                 \
1518         omt = __dmt();                                          \
1519         res = read_c0_##name();                                 \
1520         res &= ~change;                                         \
1521         res |= (new & change);                                  \
1522         write_c0_##name(res);                                   \
1523         __emt(omt);                                             \
1524         local_irq_restore(flags);                               \
1525                                                                 \
1526         return res;                                             \
1527 }
1528 #endif
1529
1530 __BUILD_SET_C0(status)
1531 __BUILD_SET_C0(cause)
1532 __BUILD_SET_C0(config)
1533 __BUILD_SET_C0(intcontrol)
1534 __BUILD_SET_C0(intctl)
1535 __BUILD_SET_C0(srsmap)
1536
1537 #endif /* !__ASSEMBLY__ */
1538
1539 #endif /* _ASM_MIPSREGS_H */