2807f8d766d4c576c593d42834a3f56e2b999c4d
[linux-2.6.git] / include / asm-ia64 / processor.h
1 #ifndef _ASM_IA64_PROCESSOR_H
2 #define _ASM_IA64_PROCESSOR_H
3
4 /*
5  * Copyright (C) 1998-2004 Hewlett-Packard Co
6  *      David Mosberger-Tang <davidm@hpl.hp.com>
7  *      Stephane Eranian <eranian@hpl.hp.com>
8  * Copyright (C) 1999 Asit Mallick <asit.k.mallick@intel.com>
9  * Copyright (C) 1999 Don Dugger <don.dugger@intel.com>
10  *
11  * 11/24/98     S.Eranian       added ia64_set_iva()
12  * 12/03/99     D. Mosberger    implement thread_saved_pc() via kernel unwind API
13  * 06/16/00     A. Mallick      added csd/ssd/tssd for ia32 support
14  */
15
16 #include <linux/config.h>
17
18 #include <asm/intrinsics.h>
19 #include <asm/kregs.h>
20 #include <asm/ptrace.h>
21 #include <asm/ustack.h>
22
23 /* Our arch specific arch_init_sched_domain is in arch/ia64/kernel/domain.c */
24 #define ARCH_HAS_SCHED_DOMAIN
25
26 #define IA64_NUM_DBG_REGS       8
27 /*
28  * Limits for PMC and PMD are set to less than maximum architected values
29  * but should be sufficient for a while
30  */
31 #define IA64_NUM_PMC_REGS       32
32 #define IA64_NUM_PMD_REGS       32
33
34 #define DEFAULT_MAP_BASE        __IA64_UL_CONST(0x2000000000000000)
35 #define DEFAULT_TASK_SIZE       __IA64_UL_CONST(0xa000000000000000)
36
37 /*
38  * TASK_SIZE really is a mis-named.  It really is the maximum user
39  * space address (plus one).  On IA-64, there are five regions of 2TB
40  * each (assuming 8KB page size), for a total of 8TB of user virtual
41  * address space.
42  */
43 #define TASK_SIZE               (current->thread.task_size)
44
45 /*
46  * This decides where the kernel will search for a free chunk of vm
47  * space during mmap's.
48  */
49 #define TASK_UNMAPPED_BASE      (current->thread.map_base)
50
51 #define IA64_THREAD_FPH_VALID   (__IA64_UL(1) << 0)     /* floating-point high state valid? */
52 #define IA64_THREAD_DBG_VALID   (__IA64_UL(1) << 1)     /* debug registers valid? */
53 #define IA64_THREAD_PM_VALID    (__IA64_UL(1) << 2)     /* performance registers valid? */
54 #define IA64_THREAD_UAC_NOPRINT (__IA64_UL(1) << 3)     /* don't log unaligned accesses */
55 #define IA64_THREAD_UAC_SIGBUS  (__IA64_UL(1) << 4)     /* generate SIGBUS on unaligned acc. */
56                                                         /* bit 5 is currently unused */
57 #define IA64_THREAD_FPEMU_NOPRINT (__IA64_UL(1) << 6)   /* don't log any fpswa faults */
58 #define IA64_THREAD_FPEMU_SIGFPE  (__IA64_UL(1) << 7)   /* send a SIGFPE for fpswa faults */
59
60 #define IA64_THREAD_UAC_SHIFT   3
61 #define IA64_THREAD_UAC_MASK    (IA64_THREAD_UAC_NOPRINT | IA64_THREAD_UAC_SIGBUS)
62 #define IA64_THREAD_FPEMU_SHIFT 6
63 #define IA64_THREAD_FPEMU_MASK  (IA64_THREAD_FPEMU_NOPRINT | IA64_THREAD_FPEMU_SIGFPE)
64
65
66 /*
67  * This shift should be large enough to be able to represent 1000000000/itc_freq with good
68  * accuracy while being small enough to fit 10*1000000000<<IA64_NSEC_PER_CYC_SHIFT in 64 bits
69  * (this will give enough slack to represent 10 seconds worth of time as a scaled number).
70  */
71 #define IA64_NSEC_PER_CYC_SHIFT 30
72
73 #ifndef __ASSEMBLY__
74
75 #include <linux/cache.h>
76 #include <linux/compiler.h>
77 #include <linux/threads.h>
78 #include <linux/types.h>
79
80 #include <asm/fpu.h>
81 #include <asm/page.h>
82 #include <asm/percpu.h>
83 #include <asm/rse.h>
84 #include <asm/unwind.h>
85 #include <asm/atomic.h>
86 #ifdef CONFIG_NUMA
87 #include <asm/nodedata.h>
88 #endif
89
90 /* like above but expressed as bitfields for more efficient access: */
91 struct ia64_psr {
92         __u64 reserved0 : 1;
93         __u64 be : 1;
94         __u64 up : 1;
95         __u64 ac : 1;
96         __u64 mfl : 1;
97         __u64 mfh : 1;
98         __u64 reserved1 : 7;
99         __u64 ic : 1;
100         __u64 i : 1;
101         __u64 pk : 1;
102         __u64 reserved2 : 1;
103         __u64 dt : 1;
104         __u64 dfl : 1;
105         __u64 dfh : 1;
106         __u64 sp : 1;
107         __u64 pp : 1;
108         __u64 di : 1;
109         __u64 si : 1;
110         __u64 db : 1;
111         __u64 lp : 1;
112         __u64 tb : 1;
113         __u64 rt : 1;
114         __u64 reserved3 : 4;
115         __u64 cpl : 2;
116         __u64 is : 1;
117         __u64 mc : 1;
118         __u64 it : 1;
119         __u64 id : 1;
120         __u64 da : 1;
121         __u64 dd : 1;
122         __u64 ss : 1;
123         __u64 ri : 2;
124         __u64 ed : 1;
125         __u64 bn : 1;
126         __u64 reserved4 : 19;
127 };
128
129 /*
130  * CPU type, hardware bug flags, and per-CPU state.  Frequently used
131  * state comes earlier:
132  */
133 struct cpuinfo_ia64 {
134         __u32 softirq_pending;
135         __u64 itm_delta;        /* # of clock cycles between clock ticks */
136         __u64 itm_next;         /* interval timer mask value to use for next clock tick */
137         __u64 nsec_per_cyc;     /* (1000000000<<IA64_NSEC_PER_CYC_SHIFT)/itc_freq */
138         __u64 unimpl_va_mask;   /* mask of unimplemented virtual address bits (from PAL) */
139         __u64 unimpl_pa_mask;   /* mask of unimplemented physical address bits (from PAL) */
140         __u64 *pgd_quick;
141         __u64 *pmd_quick;
142         __u64 pgtable_cache_sz;
143         __u64 itc_freq;         /* frequency of ITC counter */
144         __u64 proc_freq;        /* frequency of processor */
145         __u64 cyc_per_usec;     /* itc_freq/1000000 */
146         __u64 ptce_base;
147         __u32 ptce_count[2];
148         __u32 ptce_stride[2];
149         struct task_struct *ksoftirqd;  /* kernel softirq daemon for this CPU */
150
151 #ifdef CONFIG_SMP
152         __u64 loops_per_jiffy;
153         int cpu;
154 #endif
155
156         /* CPUID-derived information: */
157         __u64 ppn;
158         __u64 features;
159         __u8 number;
160         __u8 revision;
161         __u8 model;
162         __u8 family;
163         __u8 archrev;
164         char vendor[16];
165
166 #ifdef CONFIG_NUMA
167         struct ia64_node_data *node_data;
168 #endif
169 };
170
171 DECLARE_PER_CPU(struct cpuinfo_ia64, cpu_info);
172
173 /*
174  * The "local" data variable.  It refers to the per-CPU data of the currently executing
175  * CPU, much like "current" points to the per-task data of the currently executing task.
176  * Do not use the address of local_cpu_data, since it will be different from
177  * cpu_data(smp_processor_id())!
178  */
179 #define local_cpu_data          (&__ia64_per_cpu_var(cpu_info))
180 #define cpu_data(cpu)           (&per_cpu(cpu_info, cpu))
181
182 extern void identify_cpu (struct cpuinfo_ia64 *);
183 extern void print_cpu_info (struct cpuinfo_ia64 *);
184
185 typedef struct {
186         unsigned long seg;
187 } mm_segment_t;
188
189 #define SET_UNALIGN_CTL(task,value)                                                             \
190 ({                                                                                              \
191         (task)->thread.flags = (((task)->thread.flags & ~IA64_THREAD_UAC_MASK)                  \
192                                 | (((value) << IA64_THREAD_UAC_SHIFT) & IA64_THREAD_UAC_MASK)); \
193         0;                                                                                      \
194 })
195 #define GET_UNALIGN_CTL(task,addr)                                                              \
196 ({                                                                                              \
197         put_user(((task)->thread.flags & IA64_THREAD_UAC_MASK) >> IA64_THREAD_UAC_SHIFT,        \
198                  (int __user *) (addr));                                                        \
199 })
200
201 #define SET_FPEMU_CTL(task,value)                                                               \
202 ({                                                                                              \
203         (task)->thread.flags = (((task)->thread.flags & ~IA64_THREAD_FPEMU_MASK)                \
204                           | (((value) << IA64_THREAD_FPEMU_SHIFT) & IA64_THREAD_FPEMU_MASK));   \
205         0;                                                                                      \
206 })
207 #define GET_FPEMU_CTL(task,addr)                                                                \
208 ({                                                                                              \
209         put_user(((task)->thread.flags & IA64_THREAD_FPEMU_MASK) >> IA64_THREAD_FPEMU_SHIFT,    \
210                  (int __user *) (addr));                                                        \
211 })
212
213 #ifdef CONFIG_IA32_SUPPORT
214 struct desc_struct {
215         unsigned int a, b;
216 };
217
218 #define desc_empty(desc)                (!((desc)->a + (desc)->b))
219 #define desc_equal(desc1, desc2)        (((desc1)->a == (desc2)->a) && ((desc1)->b == (desc2)->b))
220
221 #define GDT_ENTRY_TLS_ENTRIES   3
222 #define GDT_ENTRY_TLS_MIN       6
223 #define GDT_ENTRY_TLS_MAX       (GDT_ENTRY_TLS_MIN + GDT_ENTRY_TLS_ENTRIES - 1)
224
225 #define TLS_SIZE (GDT_ENTRY_TLS_ENTRIES * 8)
226
227 struct partial_page_list;
228 #endif
229
230 struct thread_struct {
231         __u32 flags;                    /* various thread flags (see IA64_THREAD_*) */
232         /* writing on_ustack is performance-critical, so it's worth spending 8 bits on it... */
233         __u8 on_ustack;                 /* executing on user-stacks? */
234         __u8 pad[3];
235         __u64 ksp;                      /* kernel stack pointer */
236         __u64 map_base;                 /* base address for get_unmapped_area() */
237         __u64 task_size;                /* limit for task size */
238         __u64 rbs_bot;                  /* the base address for the RBS */
239         int last_fph_cpu;               /* CPU that may hold the contents of f32-f127 */
240
241 #ifdef CONFIG_IA32_SUPPORT
242         __u64 eflag;                    /* IA32 EFLAGS reg */
243         __u64 fsr;                      /* IA32 floating pt status reg */
244         __u64 fcr;                      /* IA32 floating pt control reg */
245         __u64 fir;                      /* IA32 fp except. instr. reg */
246         __u64 fdr;                      /* IA32 fp except. data reg */
247         __u64 old_k1;                   /* old value of ar.k1 */
248         __u64 old_iob;                  /* old IOBase value */
249         struct partial_page_list *ppl;  /* partial page list for 4K page size issue */
250         /* cached TLS descriptors. */
251         struct desc_struct tls_array[GDT_ENTRY_TLS_ENTRIES];
252
253 # define INIT_THREAD_IA32       .eflag =        0,                      \
254                                 .fsr =          0,                      \
255                                 .fcr =          0x17800000037fULL,      \
256                                 .fir =          0,                      \
257                                 .fdr =          0,                      \
258                                 .old_k1 =       0,                      \
259                                 .old_iob =      0,                      \
260                                 .ppl =          NULL,
261 #else
262 # define INIT_THREAD_IA32
263 #endif /* CONFIG_IA32_SUPPORT */
264 #ifdef CONFIG_PERFMON
265         __u64 pmcs[IA64_NUM_PMC_REGS];
266         __u64 pmds[IA64_NUM_PMD_REGS];
267         void *pfm_context;                   /* pointer to detailed PMU context */
268         unsigned long pfm_needs_checking;    /* when >0, pending perfmon work on kernel exit */
269 # define INIT_THREAD_PM         .pmcs =                 {0UL, },  \
270                                 .pmds =                 {0UL, },  \
271                                 .pfm_context =          NULL,     \
272                                 .pfm_needs_checking =   0UL,
273 #else
274 # define INIT_THREAD_PM
275 #endif
276         __u64 dbr[IA64_NUM_DBG_REGS];
277         __u64 ibr[IA64_NUM_DBG_REGS];
278         struct ia64_fpreg fph[96];      /* saved/loaded on demand */
279 };
280
281 #define INIT_THREAD {                                           \
282         .flags =        0,                                      \
283         .on_ustack =    0,                                      \
284         .ksp =          0,                                      \
285         .map_base =     DEFAULT_MAP_BASE,                       \
286         .rbs_bot =      STACK_TOP - DEFAULT_USER_STACK_SIZE,    \
287         .task_size =    DEFAULT_TASK_SIZE,                      \
288         .last_fph_cpu =  -1,                                    \
289         INIT_THREAD_IA32                                        \
290         INIT_THREAD_PM                                          \
291         .dbr =          {0, },                                  \
292         .ibr =          {0, },                                  \
293         .fph =          {{{{0}}}, }                             \
294 }
295
296 #define start_thread(regs,new_ip,new_sp) do {                                                   \
297         set_fs(USER_DS);                                                                        \
298         regs->cr_ipsr = ((regs->cr_ipsr | (IA64_PSR_BITS_TO_SET | IA64_PSR_CPL))                \
299                          & ~(IA64_PSR_BITS_TO_CLEAR | IA64_PSR_RI | IA64_PSR_IS));              \
300         regs->cr_iip = new_ip;                                                                  \
301         regs->ar_rsc = 0xf;             /* eager mode, privilege level 3 */                     \
302         regs->ar_rnat = 0;                                                                      \
303         regs->ar_bspstore = current->thread.rbs_bot;                                            \
304         regs->ar_fpsr = FPSR_DEFAULT;                                                           \
305         regs->loadrs = 0;                                                                       \
306         regs->r8 = current->mm->dumpable;       /* set "don't zap registers" flag */            \
307         regs->r12 = new_sp - 16;        /* allocate 16 byte scratch area */                     \
308         if (unlikely(!current->mm->dumpable)) {                                                 \
309                 /*                                                                              \
310                  * Zap scratch regs to avoid leaking bits between processes with different      \
311                  * uid/privileges.                                                              \
312                  */                                                                             \
313                 regs->ar_pfs = 0; regs->b0 = 0; regs->pr = 0;                                   \
314                 regs->r1 = 0; regs->r9  = 0; regs->r11 = 0; regs->r13 = 0; regs->r15 = 0;       \
315         }                                                                                       \
316 } while (0)
317
318 /* Forward declarations, a strange C thing... */
319 struct mm_struct;
320 struct task_struct;
321
322 /*
323  * Free all resources held by a thread. This is called after the
324  * parent of DEAD_TASK has collected the exit status of the task via
325  * wait().
326  */
327 #define release_thread(dead_task)
328
329 /* Prepare to copy thread state - unlazy all lazy status */
330 #define prepare_to_copy(tsk)    do { } while (0)
331
332 /*
333  * This is the mechanism for creating a new kernel thread.
334  *
335  * NOTE 1: Only a kernel-only process (ie the swapper or direct
336  * descendants who haven't done an "execve()") should use this: it
337  * will work within a system call from a "real" process, but the
338  * process memory space will not be free'd until both the parent and
339  * the child have exited.
340  *
341  * NOTE 2: This MUST NOT be an inlined function.  Otherwise, we get
342  * into trouble in init/main.c when the child thread returns to
343  * do_basic_setup() and the timing is such that free_initmem() has
344  * been called already.
345  */
346 extern pid_t kernel_thread (int (*fn)(void *), void *arg, unsigned long flags);
347
348 /* Get wait channel for task P.  */
349 extern unsigned long get_wchan (struct task_struct *p);
350
351 /* Return instruction pointer of blocked task TSK.  */
352 #define KSTK_EIP(tsk)                                   \
353   ({                                                    \
354         struct pt_regs *_regs = ia64_task_regs(tsk);    \
355         _regs->cr_iip + ia64_psr(_regs)->ri;            \
356   })
357
358 /* Return stack pointer of blocked task TSK.  */
359 #define KSTK_ESP(tsk)  ((tsk)->thread.ksp)
360
361 extern void ia64_getreg_unknown_kr (void);
362 extern void ia64_setreg_unknown_kr (void);
363
364 #define ia64_get_kr(regnum)                                     \
365 ({                                                              \
366         unsigned long r = 0;                                    \
367                                                                 \
368         switch (regnum) {                                       \
369             case 0: r = ia64_getreg(_IA64_REG_AR_KR0); break;   \
370             case 1: r = ia64_getreg(_IA64_REG_AR_KR1); break;   \
371             case 2: r = ia64_getreg(_IA64_REG_AR_KR2); break;   \
372             case 3: r = ia64_getreg(_IA64_REG_AR_KR3); break;   \
373             case 4: r = ia64_getreg(_IA64_REG_AR_KR4); break;   \
374             case 5: r = ia64_getreg(_IA64_REG_AR_KR5); break;   \
375             case 6: r = ia64_getreg(_IA64_REG_AR_KR6); break;   \
376             case 7: r = ia64_getreg(_IA64_REG_AR_KR7); break;   \
377             default: ia64_getreg_unknown_kr(); break;           \
378         }                                                       \
379         r;                                                      \
380 })
381
382 #define ia64_set_kr(regnum, r)                                  \
383 ({                                                              \
384         switch (regnum) {                                       \
385             case 0: ia64_setreg(_IA64_REG_AR_KR0, r); break;    \
386             case 1: ia64_setreg(_IA64_REG_AR_KR1, r); break;    \
387             case 2: ia64_setreg(_IA64_REG_AR_KR2, r); break;    \
388             case 3: ia64_setreg(_IA64_REG_AR_KR3, r); break;    \
389             case 4: ia64_setreg(_IA64_REG_AR_KR4, r); break;    \
390             case 5: ia64_setreg(_IA64_REG_AR_KR5, r); break;    \
391             case 6: ia64_setreg(_IA64_REG_AR_KR6, r); break;    \
392             case 7: ia64_setreg(_IA64_REG_AR_KR7, r); break;    \
393             default: ia64_setreg_unknown_kr(); break;           \
394         }                                                       \
395 })
396
397 /*
398  * The following three macros can't be inline functions because we don't have struct
399  * task_struct at this point.
400  */
401
402 /* Return TRUE if task T owns the fph partition of the CPU we're running on. */
403 #define ia64_is_local_fpu_owner(t)                                                              \
404 ({                                                                                              \
405         struct task_struct *__ia64_islfo_task = (t);                                            \
406         (__ia64_islfo_task->thread.last_fph_cpu == smp_processor_id()                           \
407          && __ia64_islfo_task == (struct task_struct *) ia64_get_kr(IA64_KR_FPU_OWNER));        \
408 })
409
410 /* Mark task T as owning the fph partition of the CPU we're running on. */
411 #define ia64_set_local_fpu_owner(t) do {                                                \
412         struct task_struct *__ia64_slfo_task = (t);                                     \
413         __ia64_slfo_task->thread.last_fph_cpu = smp_processor_id();                     \
414         ia64_set_kr(IA64_KR_FPU_OWNER, (unsigned long) __ia64_slfo_task);               \
415 } while (0)
416
417 /* Mark the fph partition of task T as being invalid on all CPUs.  */
418 #define ia64_drop_fpu(t)        ((t)->thread.last_fph_cpu = -1)
419
420 extern void __ia64_init_fpu (void);
421 extern void __ia64_save_fpu (struct ia64_fpreg *fph);
422 extern void __ia64_load_fpu (struct ia64_fpreg *fph);
423 extern void ia64_save_debug_regs (unsigned long *save_area);
424 extern void ia64_load_debug_regs (unsigned long *save_area);
425
426 #ifdef CONFIG_IA32_SUPPORT
427 extern void ia32_save_state (struct task_struct *task);
428 extern void ia32_load_state (struct task_struct *task);
429 #endif
430
431 #define ia64_fph_enable()       do { ia64_rsm(IA64_PSR_DFH); ia64_srlz_d(); } while (0)
432 #define ia64_fph_disable()      do { ia64_ssm(IA64_PSR_DFH); ia64_srlz_d(); } while (0)
433
434 /* load fp 0.0 into fph */
435 static inline void
436 ia64_init_fpu (void) {
437         ia64_fph_enable();
438         __ia64_init_fpu();
439         ia64_fph_disable();
440 }
441
442 /* save f32-f127 at FPH */
443 static inline void
444 ia64_save_fpu (struct ia64_fpreg *fph) {
445         ia64_fph_enable();
446         __ia64_save_fpu(fph);
447         ia64_fph_disable();
448 }
449
450 /* load f32-f127 from FPH */
451 static inline void
452 ia64_load_fpu (struct ia64_fpreg *fph) {
453         ia64_fph_enable();
454         __ia64_load_fpu(fph);
455         ia64_fph_disable();
456 }
457
458 static inline __u64
459 ia64_clear_ic (void)
460 {
461         __u64 psr;
462         psr = ia64_getreg(_IA64_REG_PSR);
463         ia64_stop();
464         ia64_rsm(IA64_PSR_I | IA64_PSR_IC);
465         ia64_srlz_i();
466         return psr;
467 }
468
469 /*
470  * Restore the psr.
471  */
472 static inline void
473 ia64_set_psr (__u64 psr)
474 {
475         ia64_stop();
476         ia64_setreg(_IA64_REG_PSR_L, psr);
477         ia64_srlz_d();
478 }
479
480 /*
481  * Insert a translation into an instruction and/or data translation
482  * register.
483  */
484 static inline void
485 ia64_itr (__u64 target_mask, __u64 tr_num,
486           __u64 vmaddr, __u64 pte,
487           __u64 log_page_size)
488 {
489         ia64_setreg(_IA64_REG_CR_ITIR, (log_page_size << 2));
490         ia64_setreg(_IA64_REG_CR_IFA, vmaddr);
491         ia64_stop();
492         if (target_mask & 0x1)
493                 ia64_itri(tr_num, pte);
494         if (target_mask & 0x2)
495                 ia64_itrd(tr_num, pte);
496 }
497
498 /*
499  * Insert a translation into the instruction and/or data translation
500  * cache.
501  */
502 static inline void
503 ia64_itc (__u64 target_mask, __u64 vmaddr, __u64 pte,
504           __u64 log_page_size)
505 {
506         ia64_setreg(_IA64_REG_CR_ITIR, (log_page_size << 2));
507         ia64_setreg(_IA64_REG_CR_IFA, vmaddr);
508         ia64_stop();
509         /* as per EAS2.6, itc must be the last instruction in an instruction group */
510         if (target_mask & 0x1)
511                 ia64_itci(pte);
512         if (target_mask & 0x2)
513                 ia64_itcd(pte);
514 }
515
516 /*
517  * Purge a range of addresses from instruction and/or data translation
518  * register(s).
519  */
520 static inline void
521 ia64_ptr (__u64 target_mask, __u64 vmaddr, __u64 log_size)
522 {
523         if (target_mask & 0x1)
524                 ia64_ptri(vmaddr, (log_size << 2));
525         if (target_mask & 0x2)
526                 ia64_ptrd(vmaddr, (log_size << 2));
527 }
528
529 /* Set the interrupt vector address.  The address must be suitably aligned (32KB).  */
530 static inline void
531 ia64_set_iva (void *ivt_addr)
532 {
533         ia64_setreg(_IA64_REG_CR_IVA, (__u64) ivt_addr);
534         ia64_srlz_i();
535 }
536
537 /* Set the page table address and control bits.  */
538 static inline void
539 ia64_set_pta (__u64 pta)
540 {
541         /* Note: srlz.i implies srlz.d */
542         ia64_setreg(_IA64_REG_CR_PTA, pta);
543         ia64_srlz_i();
544 }
545
546 static inline void
547 ia64_eoi (void)
548 {
549         ia64_setreg(_IA64_REG_CR_EOI, 0);
550         ia64_srlz_d();
551 }
552
553 #define cpu_relax()     ia64_hint(ia64_hint_pause)
554
555 static inline void
556 ia64_set_lrr0 (unsigned long val)
557 {
558         ia64_setreg(_IA64_REG_CR_LRR0, val);
559         ia64_srlz_d();
560 }
561
562 static inline void
563 ia64_set_lrr1 (unsigned long val)
564 {
565         ia64_setreg(_IA64_REG_CR_LRR1, val);
566         ia64_srlz_d();
567 }
568
569
570 /*
571  * Given the address to which a spill occurred, return the unat bit
572  * number that corresponds to this address.
573  */
574 static inline __u64
575 ia64_unat_pos (void *spill_addr)
576 {
577         return ((__u64) spill_addr >> 3) & 0x3f;
578 }
579
580 /*
581  * Set the NaT bit of an integer register which was spilled at address
582  * SPILL_ADDR.  UNAT is the mask to be updated.
583  */
584 static inline void
585 ia64_set_unat (__u64 *unat, void *spill_addr, unsigned long nat)
586 {
587         __u64 bit = ia64_unat_pos(spill_addr);
588         __u64 mask = 1UL << bit;
589
590         *unat = (*unat & ~mask) | (nat << bit);
591 }
592
593 /*
594  * Return saved PC of a blocked thread.
595  * Note that the only way T can block is through a call to schedule() -> switch_to().
596  */
597 static inline unsigned long
598 thread_saved_pc (struct task_struct *t)
599 {
600         struct unw_frame_info info;
601         unsigned long ip;
602
603         unw_init_from_blocked_task(&info, t);
604         if (unw_unwind(&info) < 0)
605                 return 0;
606         unw_get_ip(&info, &ip);
607         return ip;
608 }
609
610 /*
611  * Get the current instruction/program counter value.
612  */
613 #define current_text_addr() \
614         ({ void *_pc; _pc = (void *)ia64_getreg(_IA64_REG_IP); _pc; })
615
616 static inline __u64
617 ia64_get_ivr (void)
618 {
619         __u64 r;
620         ia64_srlz_d();
621         r = ia64_getreg(_IA64_REG_CR_IVR);
622         ia64_srlz_d();
623         return r;
624 }
625
626 static inline void
627 ia64_set_dbr (__u64 regnum, __u64 value)
628 {
629         __ia64_set_dbr(regnum, value);
630 #ifdef CONFIG_ITANIUM
631         ia64_srlz_d();
632 #endif
633 }
634
635 static inline __u64
636 ia64_get_dbr (__u64 regnum)
637 {
638         __u64 retval;
639
640         retval = __ia64_get_dbr(regnum);
641 #ifdef CONFIG_ITANIUM
642         ia64_srlz_d();
643 #endif
644         return retval;
645 }
646
647 static inline __u64
648 ia64_rotr (__u64 w, __u64 n)
649 {
650         return (w >> n) | (w << (64 - n));
651 }
652
653 #define ia64_rotl(w,n)  ia64_rotr((w), (64) - (n))
654
655 /*
656  * Take a mapped kernel address and return the equivalent address
657  * in the region 7 identity mapped virtual area.
658  */
659 static inline void *
660 ia64_imva (void *addr)
661 {
662         void *result;
663         result = (void *) ia64_tpa(addr);
664         return __va(result);
665 }
666
667 #define ARCH_HAS_PREFETCH
668 #define ARCH_HAS_PREFETCHW
669 #define ARCH_HAS_SPINLOCK_PREFETCH
670 #define PREFETCH_STRIDE                 L1_CACHE_BYTES
671
672 static inline void
673 prefetch (const void *x)
674 {
675          ia64_lfetch(ia64_lfhint_none, x);
676 }
677
678 static inline void
679 prefetchw (const void *x)
680 {
681         ia64_lfetch_excl(ia64_lfhint_none, x);
682 }
683
684 #define spin_lock_prefetch(x)   prefetchw(x)
685
686 extern unsigned long boot_option_idle_override;
687
688 #endif /* !__ASSEMBLY__ */
689
690 #endif /* _ASM_IA64_PROCESSOR_H */