Merge branch 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/ieee1394...
[linux-2.6.git] / include / asm-ia64 / pal.h
1 #ifndef _ASM_IA64_PAL_H
2 #define _ASM_IA64_PAL_H
3
4 /*
5  * Processor Abstraction Layer definitions.
6  *
7  * This is based on Intel IA-64 Architecture Software Developer's Manual rev 1.0
8  * chapter 11 IA-64 Processor Abstraction Layer
9  *
10  * Copyright (C) 1998-2001 Hewlett-Packard Co
11  *      David Mosberger-Tang <davidm@hpl.hp.com>
12  *      Stephane Eranian <eranian@hpl.hp.com>
13  * Copyright (C) 1999 VA Linux Systems
14  * Copyright (C) 1999 Walt Drummond <drummond@valinux.com>
15  * Copyright (C) 1999 Srinivasa Prasad Thirumalachar <sprasad@sprasad.engr.sgi.com>
16  *
17  * 99/10/01     davidm  Make sure we pass zero for reserved parameters.
18  * 00/03/07     davidm  Updated pal_cache_flush() to be in sync with PAL v2.6.
19  * 00/03/23     cfleck  Modified processor min-state save area to match updated PAL & SAL info
20  * 00/05/24     eranian Updated to latest PAL spec, fix structures bugs, added
21  * 00/05/25     eranian Support for stack calls, and static physical calls
22  * 00/06/18     eranian Support for stacked physical calls
23  * 06/10/26     rja     Support for Intel Itanium Architecture Software Developer's
24  *                      Manual Rev 2.2 (Jan 2006)
25  */
26
27 /*
28  * Note that some of these calls use a static-register only calling
29  * convention which has nothing to do with the regular calling
30  * convention.
31  */
32 #define PAL_CACHE_FLUSH         1       /* flush i/d cache */
33 #define PAL_CACHE_INFO          2       /* get detailed i/d cache info */
34 #define PAL_CACHE_INIT          3       /* initialize i/d cache */
35 #define PAL_CACHE_SUMMARY       4       /* get summary of cache hierarchy */
36 #define PAL_MEM_ATTRIB          5       /* list supported memory attributes */
37 #define PAL_PTCE_INFO           6       /* purge TLB info */
38 #define PAL_VM_INFO             7       /* return supported virtual memory features */
39 #define PAL_VM_SUMMARY          8       /* return summary on supported vm features */
40 #define PAL_BUS_GET_FEATURES    9       /* return processor bus interface features settings */
41 #define PAL_BUS_SET_FEATURES    10      /* set processor bus features */
42 #define PAL_DEBUG_INFO          11      /* get number of debug registers */
43 #define PAL_FIXED_ADDR          12      /* get fixed component of processors's directed address */
44 #define PAL_FREQ_BASE           13      /* base frequency of the platform */
45 #define PAL_FREQ_RATIOS         14      /* ratio of processor, bus and ITC frequency */
46 #define PAL_PERF_MON_INFO       15      /* return performance monitor info */
47 #define PAL_PLATFORM_ADDR       16      /* set processor interrupt block and IO port space addr */
48 #define PAL_PROC_GET_FEATURES   17      /* get configurable processor features & settings */
49 #define PAL_PROC_SET_FEATURES   18      /* enable/disable configurable processor features */
50 #define PAL_RSE_INFO            19      /* return rse information */
51 #define PAL_VERSION             20      /* return version of PAL code */
52 #define PAL_MC_CLEAR_LOG        21      /* clear all processor log info */
53 #define PAL_MC_DRAIN            22      /* drain operations which could result in an MCA */
54 #define PAL_MC_EXPECTED         23      /* set/reset expected MCA indicator */
55 #define PAL_MC_DYNAMIC_STATE    24      /* get processor dynamic state */
56 #define PAL_MC_ERROR_INFO       25      /* get processor MCA info and static state */
57 #define PAL_MC_RESUME           26      /* Return to interrupted process */
58 #define PAL_MC_REGISTER_MEM     27      /* Register memory for PAL to use during MCAs and inits */
59 #define PAL_HALT                28      /* enter the low power HALT state */
60 #define PAL_HALT_LIGHT          29      /* enter the low power light halt state*/
61 #define PAL_COPY_INFO           30      /* returns info needed to relocate PAL */
62 #define PAL_CACHE_LINE_INIT     31      /* init tags & data of cache line */
63 #define PAL_PMI_ENTRYPOINT      32      /* register PMI memory entry points with the processor */
64 #define PAL_ENTER_IA_32_ENV     33      /* enter IA-32 system environment */
65 #define PAL_VM_PAGE_SIZE        34      /* return vm TC and page walker page sizes */
66
67 #define PAL_MEM_FOR_TEST        37      /* get amount of memory needed for late processor test */
68 #define PAL_CACHE_PROT_INFO     38      /* get i/d cache protection info */
69 #define PAL_REGISTER_INFO       39      /* return AR and CR register information*/
70 #define PAL_SHUTDOWN            40      /* enter processor shutdown state */
71 #define PAL_PREFETCH_VISIBILITY 41      /* Make Processor Prefetches Visible */
72 #define PAL_LOGICAL_TO_PHYSICAL 42      /* returns information on logical to physical processor mapping */
73 #define PAL_CACHE_SHARED_INFO   43      /* returns information on caches shared by logical processor */
74 #define PAL_GET_HW_POLICY       48      /* Get current hardware resource sharing policy */
75 #define PAL_SET_HW_POLICY       49      /* Set current hardware resource sharing policy */
76
77 #define PAL_COPY_PAL            256     /* relocate PAL procedures and PAL PMI */
78 #define PAL_HALT_INFO           257     /* return the low power capabilities of processor */
79 #define PAL_TEST_PROC           258     /* perform late processor self-test */
80 #define PAL_CACHE_READ          259     /* read tag & data of cacheline for diagnostic testing */
81 #define PAL_CACHE_WRITE         260     /* write tag & data of cacheline for diagnostic testing */
82 #define PAL_VM_TR_READ          261     /* read contents of translation register */
83 #define PAL_GET_PSTATE          262     /* get the current P-state */
84 #define PAL_SET_PSTATE          263     /* set the P-state */
85 #define PAL_BRAND_INFO          274     /* Processor branding information */
86
87 #define PAL_GET_PSTATE_TYPE_LASTSET     0
88 #define PAL_GET_PSTATE_TYPE_AVGANDRESET 1
89 #define PAL_GET_PSTATE_TYPE_AVGNORESET  2
90 #define PAL_GET_PSTATE_TYPE_INSTANT     3
91
92 #ifndef __ASSEMBLY__
93
94 #include <linux/types.h>
95 #include <asm/fpu.h>
96
97 /*
98  * Data types needed to pass information into PAL procedures and
99  * interpret information returned by them.
100  */
101
102 /* Return status from the PAL procedure */
103 typedef s64                             pal_status_t;
104
105 #define PAL_STATUS_SUCCESS              0       /* No error */
106 #define PAL_STATUS_UNIMPLEMENTED        (-1)    /* Unimplemented procedure */
107 #define PAL_STATUS_EINVAL               (-2)    /* Invalid argument */
108 #define PAL_STATUS_ERROR                (-3)    /* Error */
109 #define PAL_STATUS_CACHE_INIT_FAIL      (-4)    /* Could not initialize the
110                                                  * specified level and type of
111                                                  * cache without sideeffects
112                                                  * and "restrict" was 1
113                                                  */
114 #define PAL_STATUS_REQUIRES_MEMORY      (-9)    /* Call requires PAL memory buffer */
115
116 /* Processor cache level in the hierarchy */
117 typedef u64                             pal_cache_level_t;
118 #define PAL_CACHE_LEVEL_L0              0       /* L0 */
119 #define PAL_CACHE_LEVEL_L1              1       /* L1 */
120 #define PAL_CACHE_LEVEL_L2              2       /* L2 */
121
122
123 /* Processor cache type at a particular level in the hierarchy */
124
125 typedef u64                             pal_cache_type_t;
126 #define PAL_CACHE_TYPE_INSTRUCTION      1       /* Instruction cache */
127 #define PAL_CACHE_TYPE_DATA             2       /* Data or unified cache */
128 #define PAL_CACHE_TYPE_INSTRUCTION_DATA 3       /* Both Data & Instruction */
129
130
131 #define PAL_CACHE_FLUSH_INVALIDATE      1       /* Invalidate clean lines */
132 #define PAL_CACHE_FLUSH_CHK_INTRS       2       /* check for interrupts/mc while flushing */
133
134 /* Processor cache line size in bytes  */
135 typedef int                             pal_cache_line_size_t;
136
137 /* Processor cache line state */
138 typedef u64                             pal_cache_line_state_t;
139 #define PAL_CACHE_LINE_STATE_INVALID    0       /* Invalid */
140 #define PAL_CACHE_LINE_STATE_SHARED     1       /* Shared */
141 #define PAL_CACHE_LINE_STATE_EXCLUSIVE  2       /* Exclusive */
142 #define PAL_CACHE_LINE_STATE_MODIFIED   3       /* Modified */
143
144 typedef struct pal_freq_ratio {
145         u32 den, num;           /* numerator & denominator */
146 } itc_ratio, proc_ratio;
147
148 typedef union  pal_cache_config_info_1_s {
149         struct {
150                 u64             u               : 1,    /* 0 Unified cache ? */
151                                 at              : 2,    /* 2-1 Cache mem attr*/
152                                 reserved        : 5,    /* 7-3 Reserved */
153                                 associativity   : 8,    /* 16-8 Associativity*/
154                                 line_size       : 8,    /* 23-17 Line size */
155                                 stride          : 8,    /* 31-24 Stride */
156                                 store_latency   : 8,    /*39-32 Store latency*/
157                                 load_latency    : 8,    /* 47-40 Load latency*/
158                                 store_hints     : 8,    /* 55-48 Store hints*/
159                                 load_hints      : 8;    /* 63-56 Load hints */
160         } pcci1_bits;
161         u64                     pcci1_data;
162 } pal_cache_config_info_1_t;
163
164 typedef union  pal_cache_config_info_2_s {
165         struct {
166                 u32             cache_size;             /*cache size in bytes*/
167
168
169                 u32             alias_boundary  : 8,    /* 39-32 aliased addr
170                                                          * separation for max
171                                                          * performance.
172                                                          */
173                                 tag_ls_bit      : 8,    /* 47-40 LSb of addr*/
174                                 tag_ms_bit      : 8,    /* 55-48 MSb of addr*/
175                                 reserved        : 8;    /* 63-56 Reserved */
176         } pcci2_bits;
177         u64                     pcci2_data;
178 } pal_cache_config_info_2_t;
179
180
181 typedef struct pal_cache_config_info_s {
182         pal_status_t                    pcci_status;
183         pal_cache_config_info_1_t       pcci_info_1;
184         pal_cache_config_info_2_t       pcci_info_2;
185         u64                             pcci_reserved;
186 } pal_cache_config_info_t;
187
188 #define pcci_ld_hints           pcci_info_1.pcci1_bits.load_hints
189 #define pcci_st_hints           pcci_info_1.pcci1_bits.store_hints
190 #define pcci_ld_latency         pcci_info_1.pcci1_bits.load_latency
191 #define pcci_st_latency         pcci_info_1.pcci1_bits.store_latency
192 #define pcci_stride             pcci_info_1.pcci1_bits.stride
193 #define pcci_line_size          pcci_info_1.pcci1_bits.line_size
194 #define pcci_assoc              pcci_info_1.pcci1_bits.associativity
195 #define pcci_cache_attr         pcci_info_1.pcci1_bits.at
196 #define pcci_unified            pcci_info_1.pcci1_bits.u
197 #define pcci_tag_msb            pcci_info_2.pcci2_bits.tag_ms_bit
198 #define pcci_tag_lsb            pcci_info_2.pcci2_bits.tag_ls_bit
199 #define pcci_alias_boundary     pcci_info_2.pcci2_bits.alias_boundary
200 #define pcci_cache_size         pcci_info_2.pcci2_bits.cache_size
201
202
203
204 /* Possible values for cache attributes */
205
206 #define PAL_CACHE_ATTR_WT               0       /* Write through cache */
207 #define PAL_CACHE_ATTR_WB               1       /* Write back cache */
208 #define PAL_CACHE_ATTR_WT_OR_WB         2       /* Either write thru or write
209                                                  * back depending on TLB
210                                                  * memory attributes
211                                                  */
212
213
214 /* Possible values for cache hints */
215
216 #define PAL_CACHE_HINT_TEMP_1           0       /* Temporal level 1 */
217 #define PAL_CACHE_HINT_NTEMP_1          1       /* Non-temporal level 1 */
218 #define PAL_CACHE_HINT_NTEMP_ALL        3       /* Non-temporal all levels */
219
220 /* Processor cache protection  information */
221 typedef union pal_cache_protection_element_u {
222         u32                     pcpi_data;
223         struct {
224                 u32             data_bits       : 8, /* # data bits covered by
225                                                       * each unit of protection
226                                                       */
227
228                                 tagprot_lsb     : 6, /* Least -do- */
229                                 tagprot_msb     : 6, /* Most Sig. tag address
230                                                       * bit that this
231                                                       * protection covers.
232                                                       */
233                                 prot_bits       : 6, /* # of protection bits */
234                                 method          : 4, /* Protection method */
235                                 t_d             : 2; /* Indicates which part
236                                                       * of the cache this
237                                                       * protection encoding
238                                                       * applies.
239                                                       */
240         } pcp_info;
241 } pal_cache_protection_element_t;
242
243 #define pcpi_cache_prot_part    pcp_info.t_d
244 #define pcpi_prot_method        pcp_info.method
245 #define pcpi_prot_bits          pcp_info.prot_bits
246 #define pcpi_tagprot_msb        pcp_info.tagprot_msb
247 #define pcpi_tagprot_lsb        pcp_info.tagprot_lsb
248 #define pcpi_data_bits          pcp_info.data_bits
249
250 /* Processor cache part encodings */
251 #define PAL_CACHE_PROT_PART_DATA        0       /* Data protection  */
252 #define PAL_CACHE_PROT_PART_TAG         1       /* Tag  protection */
253 #define PAL_CACHE_PROT_PART_TAG_DATA    2       /* Tag+data protection (tag is
254                                                  * more significant )
255                                                  */
256 #define PAL_CACHE_PROT_PART_DATA_TAG    3       /* Data+tag protection (data is
257                                                  * more significant )
258                                                  */
259 #define PAL_CACHE_PROT_PART_MAX         6
260
261
262 typedef struct pal_cache_protection_info_s {
263         pal_status_t                    pcpi_status;
264         pal_cache_protection_element_t  pcp_info[PAL_CACHE_PROT_PART_MAX];
265 } pal_cache_protection_info_t;
266
267
268 /* Processor cache protection method encodings */
269 #define PAL_CACHE_PROT_METHOD_NONE              0       /* No protection */
270 #define PAL_CACHE_PROT_METHOD_ODD_PARITY        1       /* Odd parity */
271 #define PAL_CACHE_PROT_METHOD_EVEN_PARITY       2       /* Even parity */
272 #define PAL_CACHE_PROT_METHOD_ECC               3       /* ECC protection */
273
274
275 /* Processor cache line identification in the hierarchy */
276 typedef union pal_cache_line_id_u {
277         u64                     pclid_data;
278         struct {
279                 u64             cache_type      : 8,    /* 7-0 cache type */
280                                 level           : 8,    /* 15-8 level of the
281                                                          * cache in the
282                                                          * hierarchy.
283                                                          */
284                                 way             : 8,    /* 23-16 way in the set
285                                                          */
286                                 part            : 8,    /* 31-24 part of the
287                                                          * cache
288                                                          */
289                                 reserved        : 32;   /* 63-32 is reserved*/
290         } pclid_info_read;
291         struct {
292                 u64             cache_type      : 8,    /* 7-0 cache type */
293                                 level           : 8,    /* 15-8 level of the
294                                                          * cache in the
295                                                          * hierarchy.
296                                                          */
297                                 way             : 8,    /* 23-16 way in the set
298                                                          */
299                                 part            : 8,    /* 31-24 part of the
300                                                          * cache
301                                                          */
302                                 mesi            : 8,    /* 39-32 cache line
303                                                          * state
304                                                          */
305                                 start           : 8,    /* 47-40 lsb of data to
306                                                          * invert
307                                                          */
308                                 length          : 8,    /* 55-48 #bits to
309                                                          * invert
310                                                          */
311                                 trigger         : 8;    /* 63-56 Trigger error
312                                                          * by doing a load
313                                                          * after the write
314                                                          */
315
316         } pclid_info_write;
317 } pal_cache_line_id_u_t;
318
319 #define pclid_read_part         pclid_info_read.part
320 #define pclid_read_way          pclid_info_read.way
321 #define pclid_read_level        pclid_info_read.level
322 #define pclid_read_cache_type   pclid_info_read.cache_type
323
324 #define pclid_write_trigger     pclid_info_write.trigger
325 #define pclid_write_length      pclid_info_write.length
326 #define pclid_write_start       pclid_info_write.start
327 #define pclid_write_mesi        pclid_info_write.mesi
328 #define pclid_write_part        pclid_info_write.part
329 #define pclid_write_way         pclid_info_write.way
330 #define pclid_write_level       pclid_info_write.level
331 #define pclid_write_cache_type  pclid_info_write.cache_type
332
333 /* Processor cache line part encodings */
334 #define PAL_CACHE_LINE_ID_PART_DATA             0       /* Data */
335 #define PAL_CACHE_LINE_ID_PART_TAG              1       /* Tag */
336 #define PAL_CACHE_LINE_ID_PART_DATA_PROT        2       /* Data protection */
337 #define PAL_CACHE_LINE_ID_PART_TAG_PROT         3       /* Tag protection */
338 #define PAL_CACHE_LINE_ID_PART_DATA_TAG_PROT    4       /* Data+tag
339                                                          * protection
340                                                          */
341 typedef struct pal_cache_line_info_s {
342         pal_status_t            pcli_status;            /* Return status of the read cache line
343                                                          * info call.
344                                                          */
345         u64                     pcli_data;              /* 64-bit data, tag, protection bits .. */
346         u64                     pcli_data_len;          /* data length in bits */
347         pal_cache_line_state_t  pcli_cache_line_state;  /* mesi state */
348
349 } pal_cache_line_info_t;
350
351
352 /* Machine Check related crap */
353
354 /* Pending event status bits  */
355 typedef u64                                     pal_mc_pending_events_t;
356
357 #define PAL_MC_PENDING_MCA                      (1 << 0)
358 #define PAL_MC_PENDING_INIT                     (1 << 1)
359
360 /* Error information type */
361 typedef u64                                     pal_mc_info_index_t;
362
363 #define PAL_MC_INFO_PROCESSOR                   0       /* Processor */
364 #define PAL_MC_INFO_CACHE_CHECK                 1       /* Cache check */
365 #define PAL_MC_INFO_TLB_CHECK                   2       /* Tlb check */
366 #define PAL_MC_INFO_BUS_CHECK                   3       /* Bus check */
367 #define PAL_MC_INFO_REQ_ADDR                    4       /* Requestor address */
368 #define PAL_MC_INFO_RESP_ADDR                   5       /* Responder address */
369 #define PAL_MC_INFO_TARGET_ADDR                 6       /* Target address */
370 #define PAL_MC_INFO_IMPL_DEP                    7       /* Implementation
371                                                          * dependent
372                                                          */
373
374 #define PAL_TLB_CHECK_OP_PURGE                  8
375
376 typedef struct pal_process_state_info_s {
377         u64             reserved1       : 2,
378                         rz              : 1,    /* PAL_CHECK processor
379                                                  * rendezvous
380                                                  * successful.
381                                                  */
382
383                         ra              : 1,    /* PAL_CHECK attempted
384                                                  * a rendezvous.
385                                                  */
386                         me              : 1,    /* Distinct multiple
387                                                  * errors occurred
388                                                  */
389
390                         mn              : 1,    /* Min. state save
391                                                  * area has been
392                                                  * registered with PAL
393                                                  */
394
395                         sy              : 1,    /* Storage integrity
396                                                  * synched
397                                                  */
398
399
400                         co              : 1,    /* Continuable */
401                         ci              : 1,    /* MC isolated */
402                         us              : 1,    /* Uncontained storage
403                                                  * damage.
404                                                  */
405
406
407                         hd              : 1,    /* Non-essential hw
408                                                  * lost (no loss of
409                                                  * functionality)
410                                                  * causing the
411                                                  * processor to run in
412                                                  * degraded mode.
413                                                  */
414
415                         tl              : 1,    /* 1 => MC occurred
416                                                  * after an instr was
417                                                  * executed but before
418                                                  * the trap that
419                                                  * resulted from instr
420                                                  * execution was
421                                                  * generated.
422                                                  * (Trap Lost )
423                                                  */
424                         mi              : 1,    /* More information available
425                                                  * call PAL_MC_ERROR_INFO
426                                                  */
427                         pi              : 1,    /* Precise instruction pointer */
428                         pm              : 1,    /* Precise min-state save area */
429
430                         dy              : 1,    /* Processor dynamic
431                                                  * state valid
432                                                  */
433
434
435                         in              : 1,    /* 0 = MC, 1 = INIT */
436                         rs              : 1,    /* RSE valid */
437                         cm              : 1,    /* MC corrected */
438                         ex              : 1,    /* MC is expected */
439                         cr              : 1,    /* Control regs valid*/
440                         pc              : 1,    /* Perf cntrs valid */
441                         dr              : 1,    /* Debug regs valid */
442                         tr              : 1,    /* Translation regs
443                                                  * valid
444                                                  */
445                         rr              : 1,    /* Region regs valid */
446                         ar              : 1,    /* App regs valid */
447                         br              : 1,    /* Branch regs valid */
448                         pr              : 1,    /* Predicate registers
449                                                  * valid
450                                                  */
451
452                         fp              : 1,    /* fp registers valid*/
453                         b1              : 1,    /* Preserved bank one
454                                                  * general registers
455                                                  * are valid
456                                                  */
457                         b0              : 1,    /* Preserved bank zero
458                                                  * general registers
459                                                  * are valid
460                                                  */
461                         gr              : 1,    /* General registers
462                                                  * are valid
463                                                  * (excl. banked regs)
464                                                  */
465                         dsize           : 16,   /* size of dynamic
466                                                  * state returned
467                                                  * by the processor
468                                                  */
469
470                         se              : 1,    /* Shared error.  MCA in a
471                                                    shared structure */
472                         reserved2       : 10,
473                         cc              : 1,    /* Cache check */
474                         tc              : 1,    /* TLB check */
475                         bc              : 1,    /* Bus check */
476                         rc              : 1,    /* Register file check */
477                         uc              : 1;    /* Uarch check */
478
479 } pal_processor_state_info_t;
480
481 typedef struct pal_cache_check_info_s {
482         u64             op              : 4,    /* Type of cache
483                                                  * operation that
484                                                  * caused the machine
485                                                  * check.
486                                                  */
487                         level           : 2,    /* Cache level */
488                         reserved1       : 2,
489                         dl              : 1,    /* Failure in data part
490                                                  * of cache line
491                                                  */
492                         tl              : 1,    /* Failure in tag part
493                                                  * of cache line
494                                                  */
495                         dc              : 1,    /* Failure in dcache */
496                         ic              : 1,    /* Failure in icache */
497                         mesi            : 3,    /* Cache line state */
498                         mv              : 1,    /* mesi valid */
499                         way             : 5,    /* Way in which the
500                                                  * error occurred
501                                                  */
502                         wiv             : 1,    /* Way field valid */
503                         reserved2       : 1,
504                         dp              : 1,    /* Data poisoned on MBE */
505                         reserved3       : 8,
506
507                         index           : 20,   /* Cache line index */
508                         reserved4       : 2,
509
510                         is              : 1,    /* instruction set (1 == ia32) */
511                         iv              : 1,    /* instruction set field valid */
512                         pl              : 2,    /* privilege level */
513                         pv              : 1,    /* privilege level field valid */
514                         mcc             : 1,    /* Machine check corrected */
515                         tv              : 1,    /* Target address
516                                                  * structure is valid
517                                                  */
518                         rq              : 1,    /* Requester identifier
519                                                  * structure is valid
520                                                  */
521                         rp              : 1,    /* Responder identifier
522                                                  * structure is valid
523                                                  */
524                         pi              : 1;    /* Precise instruction pointer
525                                                  * structure is valid
526                                                  */
527 } pal_cache_check_info_t;
528
529 typedef struct pal_tlb_check_info_s {
530
531         u64             tr_slot         : 8,    /* Slot# of TR where
532                                                  * error occurred
533                                                  */
534                         trv             : 1,    /* tr_slot field is valid */
535                         reserved1       : 1,
536                         level           : 2,    /* TLB level where failure occurred */
537                         reserved2       : 4,
538                         dtr             : 1,    /* Fail in data TR */
539                         itr             : 1,    /* Fail in inst TR */
540                         dtc             : 1,    /* Fail in data TC */
541                         itc             : 1,    /* Fail in inst. TC */
542                         op              : 4,    /* Cache operation */
543                         reserved3       : 30,
544
545                         is              : 1,    /* instruction set (1 == ia32) */
546                         iv              : 1,    /* instruction set field valid */
547                         pl              : 2,    /* privilege level */
548                         pv              : 1,    /* privilege level field valid */
549                         mcc             : 1,    /* Machine check corrected */
550                         tv              : 1,    /* Target address
551                                                  * structure is valid
552                                                  */
553                         rq              : 1,    /* Requester identifier
554                                                  * structure is valid
555                                                  */
556                         rp              : 1,    /* Responder identifier
557                                                  * structure is valid
558                                                  */
559                         pi              : 1;    /* Precise instruction pointer
560                                                  * structure is valid
561                                                  */
562 } pal_tlb_check_info_t;
563
564 typedef struct pal_bus_check_info_s {
565         u64             size            : 5,    /* Xaction size */
566                         ib              : 1,    /* Internal bus error */
567                         eb              : 1,    /* External bus error */
568                         cc              : 1,    /* Error occurred
569                                                  * during cache-cache
570                                                  * transfer.
571                                                  */
572                         type            : 8,    /* Bus xaction type*/
573                         sev             : 5,    /* Bus error severity*/
574                         hier            : 2,    /* Bus hierarchy level */
575                         dp              : 1,    /* Data poisoned on MBE */
576                         bsi             : 8,    /* Bus error status
577                                                  * info
578                                                  */
579                         reserved2       : 22,
580
581                         is              : 1,    /* instruction set (1 == ia32) */
582                         iv              : 1,    /* instruction set field valid */
583                         pl              : 2,    /* privilege level */
584                         pv              : 1,    /* privilege level field valid */
585                         mcc             : 1,    /* Machine check corrected */
586                         tv              : 1,    /* Target address
587                                                  * structure is valid
588                                                  */
589                         rq              : 1,    /* Requester identifier
590                                                  * structure is valid
591                                                  */
592                         rp              : 1,    /* Responder identifier
593                                                  * structure is valid
594                                                  */
595                         pi              : 1;    /* Precise instruction pointer
596                                                  * structure is valid
597                                                  */
598 } pal_bus_check_info_t;
599
600 typedef struct pal_reg_file_check_info_s {
601         u64             id              : 4,    /* Register file identifier */
602                         op              : 4,    /* Type of register
603                                                  * operation that
604                                                  * caused the machine
605                                                  * check.
606                                                  */
607                         reg_num         : 7,    /* Register number */
608                         rnv             : 1,    /* reg_num valid */
609                         reserved2       : 38,
610
611                         is              : 1,    /* instruction set (1 == ia32) */
612                         iv              : 1,    /* instruction set field valid */
613                         pl              : 2,    /* privilege level */
614                         pv              : 1,    /* privilege level field valid */
615                         mcc             : 1,    /* Machine check corrected */
616                         reserved3       : 3,
617                         pi              : 1;    /* Precise instruction pointer
618                                                  * structure is valid
619                                                  */
620 } pal_reg_file_check_info_t;
621
622 typedef struct pal_uarch_check_info_s {
623         u64             sid             : 5,    /* Structure identification */
624                         level           : 3,    /* Level of failure */
625                         array_id        : 4,    /* Array identification */
626                         op              : 4,    /* Type of
627                                                  * operation that
628                                                  * caused the machine
629                                                  * check.
630                                                  */
631                         way             : 6,    /* Way of structure */
632                         wv              : 1,    /* way valid */
633                         xv              : 1,    /* index valid */
634                         reserved1       : 8,
635                         index           : 8,    /* Index or set of the uarch
636                                                  * structure that failed.
637                                                  */
638                         reserved2       : 24,
639
640                         is              : 1,    /* instruction set (1 == ia32) */
641                         iv              : 1,    /* instruction set field valid */
642                         pl              : 2,    /* privilege level */
643                         pv              : 1,    /* privilege level field valid */
644                         mcc             : 1,    /* Machine check corrected */
645                         tv              : 1,    /* Target address
646                                                  * structure is valid
647                                                  */
648                         rq              : 1,    /* Requester identifier
649                                                  * structure is valid
650                                                  */
651                         rp              : 1,    /* Responder identifier
652                                                  * structure is valid
653                                                  */
654                         pi              : 1;    /* Precise instruction pointer
655                                                  * structure is valid
656                                                  */
657 } pal_uarch_check_info_t;
658
659 typedef union pal_mc_error_info_u {
660         u64                             pmei_data;
661         pal_processor_state_info_t      pme_processor;
662         pal_cache_check_info_t          pme_cache;
663         pal_tlb_check_info_t            pme_tlb;
664         pal_bus_check_info_t            pme_bus;
665         pal_reg_file_check_info_t       pme_reg_file;
666         pal_uarch_check_info_t          pme_uarch;
667 } pal_mc_error_info_t;
668
669 #define pmci_proc_unknown_check                 pme_processor.uc
670 #define pmci_proc_bus_check                     pme_processor.bc
671 #define pmci_proc_tlb_check                     pme_processor.tc
672 #define pmci_proc_cache_check                   pme_processor.cc
673 #define pmci_proc_dynamic_state_size            pme_processor.dsize
674 #define pmci_proc_gpr_valid                     pme_processor.gr
675 #define pmci_proc_preserved_bank0_gpr_valid     pme_processor.b0
676 #define pmci_proc_preserved_bank1_gpr_valid     pme_processor.b1
677 #define pmci_proc_fp_valid                      pme_processor.fp
678 #define pmci_proc_predicate_regs_valid          pme_processor.pr
679 #define pmci_proc_branch_regs_valid             pme_processor.br
680 #define pmci_proc_app_regs_valid                pme_processor.ar
681 #define pmci_proc_region_regs_valid             pme_processor.rr
682 #define pmci_proc_translation_regs_valid        pme_processor.tr
683 #define pmci_proc_debug_regs_valid              pme_processor.dr
684 #define pmci_proc_perf_counters_valid           pme_processor.pc
685 #define pmci_proc_control_regs_valid            pme_processor.cr
686 #define pmci_proc_machine_check_expected        pme_processor.ex
687 #define pmci_proc_machine_check_corrected       pme_processor.cm
688 #define pmci_proc_rse_valid                     pme_processor.rs
689 #define pmci_proc_machine_check_or_init         pme_processor.in
690 #define pmci_proc_dynamic_state_valid           pme_processor.dy
691 #define pmci_proc_operation                     pme_processor.op
692 #define pmci_proc_trap_lost                     pme_processor.tl
693 #define pmci_proc_hardware_damage               pme_processor.hd
694 #define pmci_proc_uncontained_storage_damage    pme_processor.us
695 #define pmci_proc_machine_check_isolated        pme_processor.ci
696 #define pmci_proc_continuable                   pme_processor.co
697 #define pmci_proc_storage_intergrity_synced     pme_processor.sy
698 #define pmci_proc_min_state_save_area_regd      pme_processor.mn
699 #define pmci_proc_distinct_multiple_errors      pme_processor.me
700 #define pmci_proc_pal_attempted_rendezvous      pme_processor.ra
701 #define pmci_proc_pal_rendezvous_complete       pme_processor.rz
702
703
704 #define pmci_cache_level                        pme_cache.level
705 #define pmci_cache_line_state                   pme_cache.mesi
706 #define pmci_cache_line_state_valid             pme_cache.mv
707 #define pmci_cache_line_index                   pme_cache.index
708 #define pmci_cache_instr_cache_fail             pme_cache.ic
709 #define pmci_cache_data_cache_fail              pme_cache.dc
710 #define pmci_cache_line_tag_fail                pme_cache.tl
711 #define pmci_cache_line_data_fail               pme_cache.dl
712 #define pmci_cache_operation                    pme_cache.op
713 #define pmci_cache_way_valid                    pme_cache.wv
714 #define pmci_cache_target_address_valid         pme_cache.tv
715 #define pmci_cache_way                          pme_cache.way
716 #define pmci_cache_mc                           pme_cache.mc
717
718 #define pmci_tlb_instr_translation_cache_fail   pme_tlb.itc
719 #define pmci_tlb_data_translation_cache_fail    pme_tlb.dtc
720 #define pmci_tlb_instr_translation_reg_fail     pme_tlb.itr
721 #define pmci_tlb_data_translation_reg_fail      pme_tlb.dtr
722 #define pmci_tlb_translation_reg_slot           pme_tlb.tr_slot
723 #define pmci_tlb_mc                             pme_tlb.mc
724
725 #define pmci_bus_status_info                    pme_bus.bsi
726 #define pmci_bus_req_address_valid              pme_bus.rq
727 #define pmci_bus_resp_address_valid             pme_bus.rp
728 #define pmci_bus_target_address_valid           pme_bus.tv
729 #define pmci_bus_error_severity                 pme_bus.sev
730 #define pmci_bus_transaction_type               pme_bus.type
731 #define pmci_bus_cache_cache_transfer           pme_bus.cc
732 #define pmci_bus_transaction_size               pme_bus.size
733 #define pmci_bus_internal_error                 pme_bus.ib
734 #define pmci_bus_external_error                 pme_bus.eb
735 #define pmci_bus_mc                             pme_bus.mc
736
737 /*
738  * NOTE: this min_state_save area struct only includes the 1KB
739  * architectural state save area.  The other 3 KB is scratch space
740  * for PAL.
741  */
742
743 typedef struct pal_min_state_area_s {
744         u64     pmsa_nat_bits;          /* nat bits for saved GRs  */
745         u64     pmsa_gr[15];            /* GR1  - GR15             */
746         u64     pmsa_bank0_gr[16];      /* GR16 - GR31             */
747         u64     pmsa_bank1_gr[16];      /* GR16 - GR31             */
748         u64     pmsa_pr;                /* predicate registers     */
749         u64     pmsa_br0;               /* branch register 0       */
750         u64     pmsa_rsc;               /* ar.rsc                  */
751         u64     pmsa_iip;               /* cr.iip                  */
752         u64     pmsa_ipsr;              /* cr.ipsr                 */
753         u64     pmsa_ifs;               /* cr.ifs                  */
754         u64     pmsa_xip;               /* previous iip            */
755         u64     pmsa_xpsr;              /* previous psr            */
756         u64     pmsa_xfs;               /* previous ifs            */
757         u64     pmsa_br1;               /* branch register 1       */
758         u64     pmsa_reserved[70];      /* pal_min_state_area should total to 1KB */
759 } pal_min_state_area_t;
760
761
762 struct ia64_pal_retval {
763         /*
764          * A zero status value indicates call completed without error.
765          * A negative status value indicates reason of call failure.
766          * A positive status value indicates success but an
767          * informational value should be printed (e.g., "reboot for
768          * change to take effect").
769          */
770         s64 status;
771         u64 v0;
772         u64 v1;
773         u64 v2;
774 };
775
776 /*
777  * Note: Currently unused PAL arguments are generally labeled
778  * "reserved" so the value specified in the PAL documentation
779  * (generally 0) MUST be passed.  Reserved parameters are not optional
780  * parameters.
781  */
782 extern struct ia64_pal_retval ia64_pal_call_static (u64, u64, u64, u64);
783 extern struct ia64_pal_retval ia64_pal_call_stacked (u64, u64, u64, u64);
784 extern struct ia64_pal_retval ia64_pal_call_phys_static (u64, u64, u64, u64);
785 extern struct ia64_pal_retval ia64_pal_call_phys_stacked (u64, u64, u64, u64);
786 extern void ia64_save_scratch_fpregs (struct ia64_fpreg *);
787 extern void ia64_load_scratch_fpregs (struct ia64_fpreg *);
788
789 #define PAL_CALL(iprv,a0,a1,a2,a3) do {                 \
790         struct ia64_fpreg fr[6];                        \
791         ia64_save_scratch_fpregs(fr);                   \
792         iprv = ia64_pal_call_static(a0, a1, a2, a3);    \
793         ia64_load_scratch_fpregs(fr);                   \
794 } while (0)
795
796 #define PAL_CALL_STK(iprv,a0,a1,a2,a3) do {             \
797         struct ia64_fpreg fr[6];                        \
798         ia64_save_scratch_fpregs(fr);                   \
799         iprv = ia64_pal_call_stacked(a0, a1, a2, a3);   \
800         ia64_load_scratch_fpregs(fr);                   \
801 } while (0)
802
803 #define PAL_CALL_PHYS(iprv,a0,a1,a2,a3) do {                    \
804         struct ia64_fpreg fr[6];                                \
805         ia64_save_scratch_fpregs(fr);                           \
806         iprv = ia64_pal_call_phys_static(a0, a1, a2, a3);       \
807         ia64_load_scratch_fpregs(fr);                           \
808 } while (0)
809
810 #define PAL_CALL_PHYS_STK(iprv,a0,a1,a2,a3) do {                \
811         struct ia64_fpreg fr[6];                                \
812         ia64_save_scratch_fpregs(fr);                           \
813         iprv = ia64_pal_call_phys_stacked(a0, a1, a2, a3);      \
814         ia64_load_scratch_fpregs(fr);                           \
815 } while (0)
816
817 typedef int (*ia64_pal_handler) (u64, ...);
818 extern ia64_pal_handler ia64_pal;
819 extern void ia64_pal_handler_init (void *);
820
821 extern ia64_pal_handler ia64_pal;
822
823 extern pal_cache_config_info_t          l0d_cache_config_info;
824 extern pal_cache_config_info_t          l0i_cache_config_info;
825 extern pal_cache_config_info_t          l1_cache_config_info;
826 extern pal_cache_config_info_t          l2_cache_config_info;
827
828 extern pal_cache_protection_info_t      l0d_cache_protection_info;
829 extern pal_cache_protection_info_t      l0i_cache_protection_info;
830 extern pal_cache_protection_info_t      l1_cache_protection_info;
831 extern pal_cache_protection_info_t      l2_cache_protection_info;
832
833 extern pal_cache_config_info_t          pal_cache_config_info_get(pal_cache_level_t,
834                                                                   pal_cache_type_t);
835
836 extern pal_cache_protection_info_t      pal_cache_protection_info_get(pal_cache_level_t,
837                                                                       pal_cache_type_t);
838
839
840 extern void                             pal_error(int);
841
842
843 /* Useful wrappers for the current list of pal procedures */
844
845 typedef union pal_bus_features_u {
846         u64     pal_bus_features_val;
847         struct {
848                 u64     pbf_reserved1                           :       29;
849                 u64     pbf_req_bus_parking                     :       1;
850                 u64     pbf_bus_lock_mask                       :       1;
851                 u64     pbf_enable_half_xfer_rate               :       1;
852                 u64     pbf_reserved2                           :       20;
853                 u64     pbf_enable_shared_line_replace          :       1;
854                 u64     pbf_enable_exclusive_line_replace       :       1;
855                 u64     pbf_disable_xaction_queueing            :       1;
856                 u64     pbf_disable_resp_err_check              :       1;
857                 u64     pbf_disable_berr_check                  :       1;
858                 u64     pbf_disable_bus_req_internal_err_signal :       1;
859                 u64     pbf_disable_bus_req_berr_signal         :       1;
860                 u64     pbf_disable_bus_init_event_check        :       1;
861                 u64     pbf_disable_bus_init_event_signal       :       1;
862                 u64     pbf_disable_bus_addr_err_check          :       1;
863                 u64     pbf_disable_bus_addr_err_signal         :       1;
864                 u64     pbf_disable_bus_data_err_check          :       1;
865         } pal_bus_features_s;
866 } pal_bus_features_u_t;
867
868 extern void pal_bus_features_print (u64);
869
870 /* Provide information about configurable processor bus features */
871 static inline s64
872 ia64_pal_bus_get_features (pal_bus_features_u_t *features_avail,
873                            pal_bus_features_u_t *features_status,
874                            pal_bus_features_u_t *features_control)
875 {
876         struct ia64_pal_retval iprv;
877         PAL_CALL_PHYS(iprv, PAL_BUS_GET_FEATURES, 0, 0, 0);
878         if (features_avail)
879                 features_avail->pal_bus_features_val = iprv.v0;
880         if (features_status)
881                 features_status->pal_bus_features_val = iprv.v1;
882         if (features_control)
883                 features_control->pal_bus_features_val = iprv.v2;
884         return iprv.status;
885 }
886
887 /* Enables/disables specific processor bus features */
888 static inline s64
889 ia64_pal_bus_set_features (pal_bus_features_u_t feature_select)
890 {
891         struct ia64_pal_retval iprv;
892         PAL_CALL_PHYS(iprv, PAL_BUS_SET_FEATURES, feature_select.pal_bus_features_val, 0, 0);
893         return iprv.status;
894 }
895
896 /* Get detailed cache information */
897 static inline s64
898 ia64_pal_cache_config_info (u64 cache_level, u64 cache_type, pal_cache_config_info_t *conf)
899 {
900         struct ia64_pal_retval iprv;
901
902         PAL_CALL(iprv, PAL_CACHE_INFO, cache_level, cache_type, 0);
903
904         if (iprv.status == 0) {
905                 conf->pcci_status                 = iprv.status;
906                 conf->pcci_info_1.pcci1_data      = iprv.v0;
907                 conf->pcci_info_2.pcci2_data      = iprv.v1;
908                 conf->pcci_reserved               = iprv.v2;
909         }
910         return iprv.status;
911
912 }
913
914 /* Get detailed cche protection information */
915 static inline s64
916 ia64_pal_cache_prot_info (u64 cache_level, u64 cache_type, pal_cache_protection_info_t *prot)
917 {
918         struct ia64_pal_retval iprv;
919
920         PAL_CALL(iprv, PAL_CACHE_PROT_INFO, cache_level, cache_type, 0);
921
922         if (iprv.status == 0) {
923                 prot->pcpi_status           = iprv.status;
924                 prot->pcp_info[0].pcpi_data = iprv.v0 & 0xffffffff;
925                 prot->pcp_info[1].pcpi_data = iprv.v0 >> 32;
926                 prot->pcp_info[2].pcpi_data = iprv.v1 & 0xffffffff;
927                 prot->pcp_info[3].pcpi_data = iprv.v1 >> 32;
928                 prot->pcp_info[4].pcpi_data = iprv.v2 & 0xffffffff;
929                 prot->pcp_info[5].pcpi_data = iprv.v2 >> 32;
930         }
931         return iprv.status;
932 }
933
934 /*
935  * Flush the processor instruction or data caches.  *PROGRESS must be
936  * initialized to zero before calling this for the first time..
937  */
938 static inline s64
939 ia64_pal_cache_flush (u64 cache_type, u64 invalidate, u64 *progress, u64 *vector)
940 {
941         struct ia64_pal_retval iprv;
942         PAL_CALL(iprv, PAL_CACHE_FLUSH, cache_type, invalidate, *progress);
943         if (vector)
944                 *vector = iprv.v0;
945         *progress = iprv.v1;
946         return iprv.status;
947 }
948
949
950 /* Initialize the processor controlled caches */
951 static inline s64
952 ia64_pal_cache_init (u64 level, u64 cache_type, u64 rest)
953 {
954         struct ia64_pal_retval iprv;
955         PAL_CALL(iprv, PAL_CACHE_INIT, level, cache_type, rest);
956         return iprv.status;
957 }
958
959 /* Initialize the tags and data of a data or unified cache line of
960  * processor controlled cache to known values without the availability
961  * of backing memory.
962  */
963 static inline s64
964 ia64_pal_cache_line_init (u64 physical_addr, u64 data_value)
965 {
966         struct ia64_pal_retval iprv;
967         PAL_CALL(iprv, PAL_CACHE_LINE_INIT, physical_addr, data_value, 0);
968         return iprv.status;
969 }
970
971
972 /* Read the data and tag of a processor controlled cache line for diags */
973 static inline s64
974 ia64_pal_cache_read (pal_cache_line_id_u_t line_id, u64 physical_addr)
975 {
976         struct ia64_pal_retval iprv;
977         PAL_CALL_PHYS_STK(iprv, PAL_CACHE_READ, line_id.pclid_data,
978                                 physical_addr, 0);
979         return iprv.status;
980 }
981
982 /* Return summary information about the hierarchy of caches controlled by the processor */
983 static inline s64
984 ia64_pal_cache_summary (u64 *cache_levels, u64 *unique_caches)
985 {
986         struct ia64_pal_retval iprv;
987         PAL_CALL(iprv, PAL_CACHE_SUMMARY, 0, 0, 0);
988         if (cache_levels)
989                 *cache_levels = iprv.v0;
990         if (unique_caches)
991                 *unique_caches = iprv.v1;
992         return iprv.status;
993 }
994
995 /* Write the data and tag of a processor-controlled cache line for diags */
996 static inline s64
997 ia64_pal_cache_write (pal_cache_line_id_u_t line_id, u64 physical_addr, u64 data)
998 {
999         struct ia64_pal_retval iprv;
1000         PAL_CALL_PHYS_STK(iprv, PAL_CACHE_WRITE, line_id.pclid_data,
1001                                 physical_addr, data);
1002         return iprv.status;
1003 }
1004
1005
1006 /* Return the parameters needed to copy relocatable PAL procedures from ROM to memory */
1007 static inline s64
1008 ia64_pal_copy_info (u64 copy_type, u64 num_procs, u64 num_iopics,
1009                     u64 *buffer_size, u64 *buffer_align)
1010 {
1011         struct ia64_pal_retval iprv;
1012         PAL_CALL(iprv, PAL_COPY_INFO, copy_type, num_procs, num_iopics);
1013         if (buffer_size)
1014                 *buffer_size = iprv.v0;
1015         if (buffer_align)
1016                 *buffer_align = iprv.v1;
1017         return iprv.status;
1018 }
1019
1020 /* Copy relocatable PAL procedures from ROM to memory */
1021 static inline s64
1022 ia64_pal_copy_pal (u64 target_addr, u64 alloc_size, u64 processor, u64 *pal_proc_offset)
1023 {
1024         struct ia64_pal_retval iprv;
1025         PAL_CALL(iprv, PAL_COPY_PAL, target_addr, alloc_size, processor);
1026         if (pal_proc_offset)
1027                 *pal_proc_offset = iprv.v0;
1028         return iprv.status;
1029 }
1030
1031 /* Return the number of instruction and data debug register pairs */
1032 static inline s64
1033 ia64_pal_debug_info (u64 *inst_regs,  u64 *data_regs)
1034 {
1035         struct ia64_pal_retval iprv;
1036         PAL_CALL(iprv, PAL_DEBUG_INFO, 0, 0, 0);
1037         if (inst_regs)
1038                 *inst_regs = iprv.v0;
1039         if (data_regs)
1040                 *data_regs = iprv.v1;
1041
1042         return iprv.status;
1043 }
1044
1045 #ifdef TBD
1046 /* Switch from IA64-system environment to IA-32 system environment */
1047 static inline s64
1048 ia64_pal_enter_ia32_env (ia32_env1, ia32_env2, ia32_env3)
1049 {
1050         struct ia64_pal_retval iprv;
1051         PAL_CALL(iprv, PAL_ENTER_IA_32_ENV, ia32_env1, ia32_env2, ia32_env3);
1052         return iprv.status;
1053 }
1054 #endif
1055
1056 /* Get unique geographical address of this processor on its bus */
1057 static inline s64
1058 ia64_pal_fixed_addr (u64 *global_unique_addr)
1059 {
1060         struct ia64_pal_retval iprv;
1061         PAL_CALL(iprv, PAL_FIXED_ADDR, 0, 0, 0);
1062         if (global_unique_addr)
1063                 *global_unique_addr = iprv.v0;
1064         return iprv.status;
1065 }
1066
1067 /* Get base frequency of the platform if generated by the processor */
1068 static inline s64
1069 ia64_pal_freq_base (u64 *platform_base_freq)
1070 {
1071         struct ia64_pal_retval iprv;
1072         PAL_CALL(iprv, PAL_FREQ_BASE, 0, 0, 0);
1073         if (platform_base_freq)
1074                 *platform_base_freq = iprv.v0;
1075         return iprv.status;
1076 }
1077
1078 /*
1079  * Get the ratios for processor frequency, bus frequency and interval timer to
1080  * to base frequency of the platform
1081  */
1082 static inline s64
1083 ia64_pal_freq_ratios (struct pal_freq_ratio *proc_ratio, struct pal_freq_ratio *bus_ratio,
1084                       struct pal_freq_ratio *itc_ratio)
1085 {
1086         struct ia64_pal_retval iprv;
1087         PAL_CALL(iprv, PAL_FREQ_RATIOS, 0, 0, 0);
1088         if (proc_ratio)
1089                 *(u64 *)proc_ratio = iprv.v0;
1090         if (bus_ratio)
1091                 *(u64 *)bus_ratio = iprv.v1;
1092         if (itc_ratio)
1093                 *(u64 *)itc_ratio = iprv.v2;
1094         return iprv.status;
1095 }
1096
1097 /*
1098  * Get the current hardware resource sharing policy of the processor
1099  */
1100 static inline s64
1101 ia64_pal_get_hw_policy (u64 proc_num, u64 *cur_policy, u64 *num_impacted,
1102                         u64 *la)
1103 {
1104         struct ia64_pal_retval iprv;
1105         PAL_CALL(iprv, PAL_GET_HW_POLICY, proc_num, 0, 0);
1106         if (cur_policy)
1107                 *cur_policy = iprv.v0;
1108         if (num_impacted)
1109                 *num_impacted = iprv.v1;
1110         if (la)
1111                 *la = iprv.v2;
1112         return iprv.status;
1113 }
1114
1115 /* Make the processor enter HALT or one of the implementation dependent low
1116  * power states where prefetching and execution are suspended and cache and
1117  * TLB coherency is not maintained.
1118  */
1119 static inline s64
1120 ia64_pal_halt (u64 halt_state)
1121 {
1122         struct ia64_pal_retval iprv;
1123         PAL_CALL(iprv, PAL_HALT, halt_state, 0, 0);
1124         return iprv.status;
1125 }
1126
1127 typedef union pal_power_mgmt_info_u {
1128         u64                     ppmi_data;
1129         struct {
1130                u64              exit_latency            : 16,
1131                                 entry_latency           : 16,
1132                                 power_consumption       : 28,
1133                                 im                      : 1,
1134                                 co                      : 1,
1135                                 reserved                : 2;
1136         } pal_power_mgmt_info_s;
1137 } pal_power_mgmt_info_u_t;
1138
1139 /* Return information about processor's optional power management capabilities. */
1140 static inline s64
1141 ia64_pal_halt_info (pal_power_mgmt_info_u_t *power_buf)
1142 {
1143         struct ia64_pal_retval iprv;
1144         PAL_CALL_STK(iprv, PAL_HALT_INFO, (unsigned long) power_buf, 0, 0);
1145         return iprv.status;
1146 }
1147
1148 /* Get the current P-state information */
1149 static inline s64
1150 ia64_pal_get_pstate (u64 *pstate_index, unsigned long type)
1151 {
1152         struct ia64_pal_retval iprv;
1153         PAL_CALL_STK(iprv, PAL_GET_PSTATE, type, 0, 0);
1154         *pstate_index = iprv.v0;
1155         return iprv.status;
1156 }
1157
1158 /* Set the P-state */
1159 static inline s64
1160 ia64_pal_set_pstate (u64 pstate_index)
1161 {
1162         struct ia64_pal_retval iprv;
1163         PAL_CALL_STK(iprv, PAL_SET_PSTATE, pstate_index, 0, 0);
1164         return iprv.status;
1165 }
1166
1167 /* Processor branding information*/
1168 static inline s64
1169 ia64_pal_get_brand_info (char *brand_info)
1170 {
1171         struct ia64_pal_retval iprv;
1172         PAL_CALL_STK(iprv, PAL_BRAND_INFO, 0, (u64)brand_info, 0);
1173         return iprv.status;
1174 }
1175
1176 /* Cause the processor to enter LIGHT HALT state, where prefetching and execution are
1177  * suspended, but cache and TLB coherency is maintained.
1178  */
1179 static inline s64
1180 ia64_pal_halt_light (void)
1181 {
1182         struct ia64_pal_retval iprv;
1183         PAL_CALL(iprv, PAL_HALT_LIGHT, 0, 0, 0);
1184         return iprv.status;
1185 }
1186
1187 /* Clear all the processor error logging   registers and reset the indicator that allows
1188  * the error logging registers to be written. This procedure also checks the pending
1189  * machine check bit and pending INIT bit and reports their states.
1190  */
1191 static inline s64
1192 ia64_pal_mc_clear_log (u64 *pending_vector)
1193 {
1194         struct ia64_pal_retval iprv;
1195         PAL_CALL(iprv, PAL_MC_CLEAR_LOG, 0, 0, 0);
1196         if (pending_vector)
1197                 *pending_vector = iprv.v0;
1198         return iprv.status;
1199 }
1200
1201 /* Ensure that all outstanding transactions in a processor are completed or that any
1202  * MCA due to thes outstanding transaction is taken.
1203  */
1204 static inline s64
1205 ia64_pal_mc_drain (void)
1206 {
1207         struct ia64_pal_retval iprv;
1208         PAL_CALL(iprv, PAL_MC_DRAIN, 0, 0, 0);
1209         return iprv.status;
1210 }
1211
1212 /* Return the machine check dynamic processor state */
1213 static inline s64
1214 ia64_pal_mc_dynamic_state (u64 offset, u64 *size, u64 *pds)
1215 {
1216         struct ia64_pal_retval iprv;
1217         PAL_CALL(iprv, PAL_MC_DYNAMIC_STATE, offset, 0, 0);
1218         if (size)
1219                 *size = iprv.v0;
1220         if (pds)
1221                 *pds = iprv.v1;
1222         return iprv.status;
1223 }
1224
1225 /* Return processor machine check information */
1226 static inline s64
1227 ia64_pal_mc_error_info (u64 info_index, u64 type_index, u64 *size, u64 *error_info)
1228 {
1229         struct ia64_pal_retval iprv;
1230         PAL_CALL(iprv, PAL_MC_ERROR_INFO, info_index, type_index, 0);
1231         if (size)
1232                 *size = iprv.v0;
1233         if (error_info)
1234                 *error_info = iprv.v1;
1235         return iprv.status;
1236 }
1237
1238 /* Inform PALE_CHECK whether a machine check is expected so that PALE_CHECK willnot
1239  * attempt to correct any expected machine checks.
1240  */
1241 static inline s64
1242 ia64_pal_mc_expected (u64 expected, u64 *previous)
1243 {
1244         struct ia64_pal_retval iprv;
1245         PAL_CALL(iprv, PAL_MC_EXPECTED, expected, 0, 0);
1246         if (previous)
1247                 *previous = iprv.v0;
1248         return iprv.status;
1249 }
1250
1251 /* Register a platform dependent location with PAL to which it can save
1252  * minimal processor state in the event of a machine check or initialization
1253  * event.
1254  */
1255 static inline s64
1256 ia64_pal_mc_register_mem (u64 physical_addr)
1257 {
1258         struct ia64_pal_retval iprv;
1259         PAL_CALL(iprv, PAL_MC_REGISTER_MEM, physical_addr, 0, 0);
1260         return iprv.status;
1261 }
1262
1263 /* Restore minimal architectural processor state, set CMC interrupt if necessary
1264  * and resume execution
1265  */
1266 static inline s64
1267 ia64_pal_mc_resume (u64 set_cmci, u64 save_ptr)
1268 {
1269         struct ia64_pal_retval iprv;
1270         PAL_CALL(iprv, PAL_MC_RESUME, set_cmci, save_ptr, 0);
1271         return iprv.status;
1272 }
1273
1274 /* Return the memory attributes implemented by the processor */
1275 static inline s64
1276 ia64_pal_mem_attrib (u64 *mem_attrib)
1277 {
1278         struct ia64_pal_retval iprv;
1279         PAL_CALL(iprv, PAL_MEM_ATTRIB, 0, 0, 0);
1280         if (mem_attrib)
1281                 *mem_attrib = iprv.v0 & 0xff;
1282         return iprv.status;
1283 }
1284
1285 /* Return the amount of memory needed for second phase of processor
1286  * self-test and the required alignment of memory.
1287  */
1288 static inline s64
1289 ia64_pal_mem_for_test (u64 *bytes_needed, u64 *alignment)
1290 {
1291         struct ia64_pal_retval iprv;
1292         PAL_CALL(iprv, PAL_MEM_FOR_TEST, 0, 0, 0);
1293         if (bytes_needed)
1294                 *bytes_needed = iprv.v0;
1295         if (alignment)
1296                 *alignment = iprv.v1;
1297         return iprv.status;
1298 }
1299
1300 typedef union pal_perf_mon_info_u {
1301         u64                       ppmi_data;
1302         struct {
1303                u64              generic         : 8,
1304                                 width           : 8,
1305                                 cycles          : 8,
1306                                 retired         : 8,
1307                                 reserved        : 32;
1308         } pal_perf_mon_info_s;
1309 } pal_perf_mon_info_u_t;
1310
1311 /* Return the performance monitor information about what can be counted
1312  * and how to configure the monitors to count the desired events.
1313  */
1314 static inline s64
1315 ia64_pal_perf_mon_info (u64 *pm_buffer, pal_perf_mon_info_u_t *pm_info)
1316 {
1317         struct ia64_pal_retval iprv;
1318         PAL_CALL(iprv, PAL_PERF_MON_INFO, (unsigned long) pm_buffer, 0, 0);
1319         if (pm_info)
1320                 pm_info->ppmi_data = iprv.v0;
1321         return iprv.status;
1322 }
1323
1324 /* Specifies the physical address of the processor interrupt block
1325  * and I/O port space.
1326  */
1327 static inline s64
1328 ia64_pal_platform_addr (u64 type, u64 physical_addr)
1329 {
1330         struct ia64_pal_retval iprv;
1331         PAL_CALL(iprv, PAL_PLATFORM_ADDR, type, physical_addr, 0);
1332         return iprv.status;
1333 }
1334
1335 /* Set the SAL PMI entrypoint in memory */
1336 static inline s64
1337 ia64_pal_pmi_entrypoint (u64 sal_pmi_entry_addr)
1338 {
1339         struct ia64_pal_retval iprv;
1340         PAL_CALL(iprv, PAL_PMI_ENTRYPOINT, sal_pmi_entry_addr, 0, 0);
1341         return iprv.status;
1342 }
1343
1344 struct pal_features_s;
1345 /* Provide information about configurable processor features */
1346 static inline s64
1347 ia64_pal_proc_get_features (u64 *features_avail,
1348                             u64 *features_status,
1349                             u64 *features_control)
1350 {
1351         struct ia64_pal_retval iprv;
1352         PAL_CALL_PHYS(iprv, PAL_PROC_GET_FEATURES, 0, 0, 0);
1353         if (iprv.status == 0) {
1354                 *features_avail   = iprv.v0;
1355                 *features_status  = iprv.v1;
1356                 *features_control = iprv.v2;
1357         }
1358         return iprv.status;
1359 }
1360
1361 /* Enable/disable processor dependent features */
1362 static inline s64
1363 ia64_pal_proc_set_features (u64 feature_select)
1364 {
1365         struct ia64_pal_retval iprv;
1366         PAL_CALL_PHYS(iprv, PAL_PROC_SET_FEATURES, feature_select, 0, 0);
1367         return iprv.status;
1368 }
1369
1370 /*
1371  * Put everything in a struct so we avoid the global offset table whenever
1372  * possible.
1373  */
1374 typedef struct ia64_ptce_info_s {
1375         u64             base;
1376         u32             count[2];
1377         u32             stride[2];
1378 } ia64_ptce_info_t;
1379
1380 /* Return the information required for the architected loop used to purge
1381  * (initialize) the entire TC
1382  */
1383 static inline s64
1384 ia64_get_ptce (ia64_ptce_info_t *ptce)
1385 {
1386         struct ia64_pal_retval iprv;
1387
1388         if (!ptce)
1389                 return -1;
1390
1391         PAL_CALL(iprv, PAL_PTCE_INFO, 0, 0, 0);
1392         if (iprv.status == 0) {
1393                 ptce->base = iprv.v0;
1394                 ptce->count[0] = iprv.v1 >> 32;
1395                 ptce->count[1] = iprv.v1 & 0xffffffff;
1396                 ptce->stride[0] = iprv.v2 >> 32;
1397                 ptce->stride[1] = iprv.v2 & 0xffffffff;
1398         }
1399         return iprv.status;
1400 }
1401
1402 /* Return info about implemented application and control registers. */
1403 static inline s64
1404 ia64_pal_register_info (u64 info_request, u64 *reg_info_1, u64 *reg_info_2)
1405 {
1406         struct ia64_pal_retval iprv;
1407         PAL_CALL(iprv, PAL_REGISTER_INFO, info_request, 0, 0);
1408         if (reg_info_1)
1409                 *reg_info_1 = iprv.v0;
1410         if (reg_info_2)
1411                 *reg_info_2 = iprv.v1;
1412         return iprv.status;
1413 }
1414
1415 typedef union pal_hints_u {
1416         u64                     ph_data;
1417         struct {
1418                u64              si              : 1,
1419                                 li              : 1,
1420                                 reserved        : 62;
1421         } pal_hints_s;
1422 } pal_hints_u_t;
1423
1424 /* Return information about the register stack and RSE for this processor
1425  * implementation.
1426  */
1427 static inline s64
1428 ia64_pal_rse_info (u64 *num_phys_stacked, pal_hints_u_t *hints)
1429 {
1430         struct ia64_pal_retval iprv;
1431         PAL_CALL(iprv, PAL_RSE_INFO, 0, 0, 0);
1432         if (num_phys_stacked)
1433                 *num_phys_stacked = iprv.v0;
1434         if (hints)
1435                 hints->ph_data = iprv.v1;
1436         return iprv.status;
1437 }
1438
1439 /*
1440  * Set the current hardware resource sharing policy of the processor
1441  */
1442 static inline s64
1443 ia64_pal_set_hw_policy (u64 policy)
1444 {
1445         struct ia64_pal_retval iprv;
1446         PAL_CALL(iprv, PAL_SET_HW_POLICY, policy, 0, 0);
1447         return iprv.status;
1448 }
1449
1450 /* Cause the processor to enter SHUTDOWN state, where prefetching and execution are
1451  * suspended, but cause cache and TLB coherency to be maintained.
1452  * This is usually called in IA-32 mode.
1453  */
1454 static inline s64
1455 ia64_pal_shutdown (void)
1456 {
1457         struct ia64_pal_retval iprv;
1458         PAL_CALL(iprv, PAL_SHUTDOWN, 0, 0, 0);
1459         return iprv.status;
1460 }
1461
1462 /* Perform the second phase of processor self-test. */
1463 static inline s64
1464 ia64_pal_test_proc (u64 test_addr, u64 test_size, u64 attributes, u64 *self_test_state)
1465 {
1466         struct ia64_pal_retval iprv;
1467         PAL_CALL(iprv, PAL_TEST_PROC, test_addr, test_size, attributes);
1468         if (self_test_state)
1469                 *self_test_state = iprv.v0;
1470         return iprv.status;
1471 }
1472
1473 typedef union  pal_version_u {
1474         u64     pal_version_val;
1475         struct {
1476                 u64     pv_pal_b_rev            :       8;
1477                 u64     pv_pal_b_model          :       8;
1478                 u64     pv_reserved1            :       8;
1479                 u64     pv_pal_vendor           :       8;
1480                 u64     pv_pal_a_rev            :       8;
1481                 u64     pv_pal_a_model          :       8;
1482                 u64     pv_reserved2            :       16;
1483         } pal_version_s;
1484 } pal_version_u_t;
1485
1486
1487 /*
1488  * Return PAL version information.  While the documentation states that
1489  * PAL_VERSION can be called in either physical or virtual mode, some
1490  * implementations only allow physical calls.  We don't call it very often,
1491  * so the overhead isn't worth eliminating.
1492  */
1493 static inline s64
1494 ia64_pal_version (pal_version_u_t *pal_min_version, pal_version_u_t *pal_cur_version)
1495 {
1496         struct ia64_pal_retval iprv;
1497         PAL_CALL_PHYS(iprv, PAL_VERSION, 0, 0, 0);
1498         if (pal_min_version)
1499                 pal_min_version->pal_version_val = iprv.v0;
1500
1501         if (pal_cur_version)
1502                 pal_cur_version->pal_version_val = iprv.v1;
1503
1504         return iprv.status;
1505 }
1506
1507 typedef union pal_tc_info_u {
1508         u64                     pti_val;
1509         struct {
1510                u64              num_sets        :       8,
1511                                 associativity   :       8,
1512                                 num_entries     :       16,
1513                                 pf              :       1,
1514                                 unified         :       1,
1515                                 reduce_tr       :       1,
1516                                 reserved        :       29;
1517         } pal_tc_info_s;
1518 } pal_tc_info_u_t;
1519
1520 #define tc_reduce_tr            pal_tc_info_s.reduce_tr
1521 #define tc_unified              pal_tc_info_s.unified
1522 #define tc_pf                   pal_tc_info_s.pf
1523 #define tc_num_entries          pal_tc_info_s.num_entries
1524 #define tc_associativity        pal_tc_info_s.associativity
1525 #define tc_num_sets             pal_tc_info_s.num_sets
1526
1527
1528 /* Return information about the virtual memory characteristics of the processor
1529  * implementation.
1530  */
1531 static inline s64
1532 ia64_pal_vm_info (u64 tc_level, u64 tc_type,  pal_tc_info_u_t *tc_info, u64 *tc_pages)
1533 {
1534         struct ia64_pal_retval iprv;
1535         PAL_CALL(iprv, PAL_VM_INFO, tc_level, tc_type, 0);
1536         if (tc_info)
1537                 tc_info->pti_val = iprv.v0;
1538         if (tc_pages)
1539                 *tc_pages = iprv.v1;
1540         return iprv.status;
1541 }
1542
1543 /* Get page size information about the virtual memory characteristics of the processor
1544  * implementation.
1545  */
1546 static inline s64
1547 ia64_pal_vm_page_size (u64 *tr_pages, u64 *vw_pages)
1548 {
1549         struct ia64_pal_retval iprv;
1550         PAL_CALL(iprv, PAL_VM_PAGE_SIZE, 0, 0, 0);
1551         if (tr_pages)
1552                 *tr_pages = iprv.v0;
1553         if (vw_pages)
1554                 *vw_pages = iprv.v1;
1555         return iprv.status;
1556 }
1557
1558 typedef union pal_vm_info_1_u {
1559         u64                     pvi1_val;
1560         struct {
1561                 u64             vw              : 1,
1562                                 phys_add_size   : 7,
1563                                 key_size        : 8,
1564                                 max_pkr         : 8,
1565                                 hash_tag_id     : 8,
1566                                 max_dtr_entry   : 8,
1567                                 max_itr_entry   : 8,
1568                                 max_unique_tcs  : 8,
1569                                 num_tc_levels   : 8;
1570         } pal_vm_info_1_s;
1571 } pal_vm_info_1_u_t;
1572
1573 #define PAL_MAX_PURGES          0xFFFF          /* all ones is means unlimited */
1574
1575 typedef union pal_vm_info_2_u {
1576         u64                     pvi2_val;
1577         struct {
1578                 u64             impl_va_msb     : 8,
1579                                 rid_size        : 8,
1580                                 max_purges      : 16,
1581                                 reserved        : 32;
1582         } pal_vm_info_2_s;
1583 } pal_vm_info_2_u_t;
1584
1585 /* Get summary information about the virtual memory characteristics of the processor
1586  * implementation.
1587  */
1588 static inline s64
1589 ia64_pal_vm_summary (pal_vm_info_1_u_t *vm_info_1, pal_vm_info_2_u_t *vm_info_2)
1590 {
1591         struct ia64_pal_retval iprv;
1592         PAL_CALL(iprv, PAL_VM_SUMMARY, 0, 0, 0);
1593         if (vm_info_1)
1594                 vm_info_1->pvi1_val = iprv.v0;
1595         if (vm_info_2)
1596                 vm_info_2->pvi2_val = iprv.v1;
1597         return iprv.status;
1598 }
1599
1600 typedef union pal_itr_valid_u {
1601         u64                     piv_val;
1602         struct {
1603                u64              access_rights_valid     : 1,
1604                                 priv_level_valid        : 1,
1605                                 dirty_bit_valid         : 1,
1606                                 mem_attr_valid          : 1,
1607                                 reserved                : 60;
1608         } pal_tr_valid_s;
1609 } pal_tr_valid_u_t;
1610
1611 /* Read a translation register */
1612 static inline s64
1613 ia64_pal_tr_read (u64 reg_num, u64 tr_type, u64 *tr_buffer, pal_tr_valid_u_t *tr_valid)
1614 {
1615         struct ia64_pal_retval iprv;
1616         PAL_CALL_PHYS_STK(iprv, PAL_VM_TR_READ, reg_num, tr_type,(u64)ia64_tpa(tr_buffer));
1617         if (tr_valid)
1618                 tr_valid->piv_val = iprv.v0;
1619         return iprv.status;
1620 }
1621
1622 /*
1623  * PAL_PREFETCH_VISIBILITY transaction types
1624  */
1625 #define PAL_VISIBILITY_VIRTUAL          0
1626 #define PAL_VISIBILITY_PHYSICAL         1
1627
1628 /*
1629  * PAL_PREFETCH_VISIBILITY return codes
1630  */
1631 #define PAL_VISIBILITY_OK               1
1632 #define PAL_VISIBILITY_OK_REMOTE_NEEDED 0
1633 #define PAL_VISIBILITY_INVAL_ARG        -2
1634 #define PAL_VISIBILITY_ERROR            -3
1635
1636 static inline s64
1637 ia64_pal_prefetch_visibility (s64 trans_type)
1638 {
1639         struct ia64_pal_retval iprv;
1640         PAL_CALL(iprv, PAL_PREFETCH_VISIBILITY, trans_type, 0, 0);
1641         return iprv.status;
1642 }
1643
1644 /* data structure for getting information on logical to physical mappings */
1645 typedef union pal_log_overview_u {
1646         struct {
1647                 u64     num_log         :16,    /* Total number of logical
1648                                                  * processors on this die
1649                                                  */
1650                         tpc             :8,     /* Threads per core */
1651                         reserved3       :8,     /* Reserved */
1652                         cpp             :8,     /* Cores per processor */
1653                         reserved2       :8,     /* Reserved */
1654                         ppid            :8,     /* Physical processor ID */
1655                         reserved1       :8;     /* Reserved */
1656         } overview_bits;
1657         u64 overview_data;
1658 } pal_log_overview_t;
1659
1660 typedef union pal_proc_n_log_info1_u{
1661         struct {
1662                 u64     tid             :16,    /* Thread id */
1663                         reserved2       :16,    /* Reserved */
1664                         cid             :16,    /* Core id */
1665                         reserved1       :16;    /* Reserved */
1666         } ppli1_bits;
1667         u64     ppli1_data;
1668 } pal_proc_n_log_info1_t;
1669
1670 typedef union pal_proc_n_log_info2_u {
1671         struct {
1672                 u64     la              :16,    /* Logical address */
1673                         reserved        :48;    /* Reserved */
1674         } ppli2_bits;
1675         u64     ppli2_data;
1676 } pal_proc_n_log_info2_t;
1677
1678 typedef struct pal_logical_to_physical_s
1679 {
1680         pal_log_overview_t overview;
1681         pal_proc_n_log_info1_t ppli1;
1682         pal_proc_n_log_info2_t ppli2;
1683 } pal_logical_to_physical_t;
1684
1685 #define overview_num_log        overview.overview_bits.num_log
1686 #define overview_tpc            overview.overview_bits.tpc
1687 #define overview_cpp            overview.overview_bits.cpp
1688 #define overview_ppid           overview.overview_bits.ppid
1689 #define log1_tid                ppli1.ppli1_bits.tid
1690 #define log1_cid                ppli1.ppli1_bits.cid
1691 #define log2_la                 ppli2.ppli2_bits.la
1692
1693 /* Get information on logical to physical processor mappings. */
1694 static inline s64
1695 ia64_pal_logical_to_phys(u64 proc_number, pal_logical_to_physical_t *mapping)
1696 {
1697         struct ia64_pal_retval iprv;
1698
1699         PAL_CALL(iprv, PAL_LOGICAL_TO_PHYSICAL, proc_number, 0, 0);
1700
1701         if (iprv.status == PAL_STATUS_SUCCESS)
1702         {
1703                 mapping->overview.overview_data = iprv.v0;
1704                 mapping->ppli1.ppli1_data = iprv.v1;
1705                 mapping->ppli2.ppli2_data = iprv.v2;
1706         }
1707
1708         return iprv.status;
1709 }
1710
1711 typedef struct pal_cache_shared_info_s
1712 {
1713         u64 num_shared;
1714         pal_proc_n_log_info1_t ppli1;
1715         pal_proc_n_log_info2_t ppli2;
1716 } pal_cache_shared_info_t;
1717
1718 /* Get information on logical to physical processor mappings. */
1719 static inline s64
1720 ia64_pal_cache_shared_info(u64 level,
1721                 u64 type,
1722                 u64 proc_number,
1723                 pal_cache_shared_info_t *info)
1724 {
1725         struct ia64_pal_retval iprv;
1726
1727         PAL_CALL(iprv, PAL_CACHE_SHARED_INFO, level, type, proc_number);
1728
1729         if (iprv.status == PAL_STATUS_SUCCESS) {
1730                 info->num_shared = iprv.v0;
1731                 info->ppli1.ppli1_data = iprv.v1;
1732                 info->ppli2.ppli2_data = iprv.v2;
1733         }
1734
1735         return iprv.status;
1736 }
1737 #endif /* __ASSEMBLY__ */
1738
1739 #endif /* _ASM_IA64_PAL_H */