drivers/usb/host/ehci-sched.c

   1 /*
   2  * Copyright (c) 2001-2004 by David Brownell
   3  * Copyright (c) 2003 Michal Sojka, for high-speed iso transfers
   4  *
   5  * This program is free software; you can redistribute it and/or modify it
   6  * under the terms of the GNU General Public License as published by the
   7  * Free Software Foundation; either version 2 of the License, or (at your
   8  * option) any later version.
   9  *
  10  * This program is distributed in the hope that it will be useful, but
  11  * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  12  * or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
  13  * for more details.
  14  *
  15  * You should have received a copy of the GNU General Public License
  16  * along with this program; if not, write to the Free Software Foundation,
  17  * Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  18  */
  19
  20 /* this file is part of ehci-hcd.c */
  21
  22 /*-------------------------------------------------------------------------*/
  23
  24 /*
  25  * EHCI scheduled transaction support:  interrupt, iso, split iso
  26  * These are called "periodic" transactions in the EHCI spec.
  27  *
  28  * Note that for interrupt transfers, the QH/QTD manipulation is shared
  29  * with the "asynchronous" transaction support (control/bulk transfers).
  30  * The only real difference is in how interrupt transfers are scheduled.
  31  *
  32  * For ISO, we make an "iso_stream" head to serve the same role as a QH.
  33  * It keeps track of every ITD (or SITD) that's linked, and holds enough
  34  * pre-calculated schedule data to make appending to the queue be quick.
  35  */
  36
  37 static int ehci_get_frame (struct usb_hcd *hcd);
  38
  39 /*-------------------------------------------------------------------------*/
  40
  41 /*
  42  * periodic_next_shadow - return "next" pointer on shadow list
  43  * @periodic: host pointer to qh/itd/sitd
  44  * @tag: hardware tag for type of this record
  45  */
  46 static union ehci_shadow *
  47 periodic_next_shadow(struct ehci_hcd *ehci, union ehci_shadow *periodic,
  48                 __hc32 tag)
  49 {
  50         switch (hc32_to_cpu(ehci, tag)) {
  51         case Q_TYPE_QH:
  52                 return &periodic->qh->qh_next;
  53         case Q_TYPE_FSTN:
  54                 return &periodic->fstn->fstn_next;
  55         case Q_TYPE_ITD:
  56                 return &periodic->itd->itd_next;
  57         // case Q_TYPE_SITD:
  58         default:
  59                 return &periodic->sitd->sitd_next;
  60         }
  61 }
  62
  63 /* caller must hold ehci->lock */
  64 static void periodic_unlink (struct ehci_hcd *ehci, unsigned frame, void *ptr)
  65 {
  66         union ehci_shadow       *prev_p = &ehci->pshadow[frame];
  67         __hc32                  *hw_p = &ehci->periodic[frame];
  68         union ehci_shadow       here = *prev_p;
  69
  70         /* find predecessor of "ptr"; hw and shadow lists are in sync */
  71         while (here.ptr && here.ptr != ptr) {
  72                 prev_p = periodic_next_shadow(ehci, prev_p,
  73                                 Q_NEXT_TYPE(ehci, *hw_p));
  74                 hw_p = here.hw_next;
  75                 here = *prev_p;
  76         }
  77         /* an interrupt entry (at list end) could have been shared */
  78         if (!here.ptr)
  79                 return;
  80
  81         /* update shadow and hardware lists ... the old "next" pointers
  82          * from ptr may still be in use, the caller updates them.
  83          */
  84         *prev_p = *periodic_next_shadow(ehci, &here,
  85                         Q_NEXT_TYPE(ehci, *hw_p));
  86         *hw_p = *here.hw_next;
  87 }
  88
  89 /* how many of the uframe's 125 usecs are allocated? */
  90 static unsigned short
  91 periodic_usecs (struct ehci_hcd *ehci, unsigned frame, unsigned uframe)
  92 {
  93         __hc32                  *hw_p = &ehci->periodic [frame];
  94         union ehci_shadow       *q = &ehci->pshadow [frame];
  95         unsigned                usecs = 0;
  96
  97         while (q->ptr) {
  98                 switch (hc32_to_cpu(ehci, Q_NEXT_TYPE(ehci, *hw_p))) {
  99                 case Q_TYPE_QH:
 100                         /* is it in the S-mask? */
 101                         if (q->qh->hw_info2 & cpu_to_hc32(ehci, 1 << uframe))
 102                                 usecs += q->qh->usecs;
 103                         /* ... or C-mask? */
 104                         if (q->qh->hw_info2 & cpu_to_hc32(ehci,
 105                                         1 << (8 + uframe)))
 106                                 usecs += q->qh->c_usecs;
 107                         hw_p = &q->qh->hw_next;
 108                         q = &q->qh->qh_next;
 109                         break;
 110                 // case Q_TYPE_FSTN:
 111                 default:
 112                         /* for "save place" FSTNs, count the relevant INTR
 113                          * bandwidth from the previous frame
 114                          */
 115                         if (q->fstn->hw_prev != EHCI_LIST_END(ehci)) {
 116                                 ehci_dbg (ehci, "ignoring FSTN cost ...\n");
 117                         }
 118                         hw_p = &q->fstn->hw_next;
 119                         q = &q->fstn->fstn_next;
 120                         break;
 121                 case Q_TYPE_ITD:
 122                         if (q->itd->hw_transaction[uframe])
 123                                 usecs += q->itd->stream->usecs;
 124                         hw_p = &q->itd->hw_next;
 125                         q = &q->itd->itd_next;
 126                         break;
 127                 case Q_TYPE_SITD:
 128                         /* is it in the S-mask?  (count SPLIT, DATA) */
 129                         if (q->sitd->hw_uframe & cpu_to_hc32(ehci,
 130                                         1 << uframe)) {
 131                                 if (q->sitd->hw_fullspeed_ep &
 132                                                 cpu_to_hc32(ehci, 1<<31))
 133                                         usecs += q->sitd->stream->usecs;
 134                                 else    /* worst case for OUT start-split */
 135                                         usecs += HS_USECS_ISO (188);
 136                         }
 137
 138                         /* ... C-mask?  (count CSPLIT, DATA) */
 139                         if (q->sitd->hw_uframe &
 140                                         cpu_to_hc32(ehci, 1 << (8 + uframe))) {
 141                                 /* worst case for IN complete-split */
 142                                 usecs += q->sitd->stream->c_usecs;
 143                         }
 144
 145                         hw_p = &q->sitd->hw_next;
 146                         q = &q->sitd->sitd_next;
 147                         break;
 148                 }
 149         }
 150 #ifdef  DEBUG
 151         if (usecs > 100)
 152                 ehci_err (ehci, "uframe %d sched overrun: %d usecs\n",
 153                         frame * 8 + uframe, usecs);
 154 #endif
 155         return usecs;
 156 }
 157
 158 /*-------------------------------------------------------------------------*/
 159
 160 static int same_tt (struct usb_device *dev1, struct usb_device *dev2)
 161 {
 162         if (!dev1->tt || !dev2->tt)
 163                 return 0;
 164         if (dev1->tt != dev2->tt)
 165                 return 0;
 166         if (dev1->tt->multi)
 167                 return dev1->ttport == dev2->ttport;
 168         else
 169                 return 1;
 170 }
 171
 172 #ifdef CONFIG_USB_EHCI_TT_NEWSCHED
 173
 174 /* Which uframe does the low/fullspeed transfer start in?
 175  *
 176  * The parameter is the mask of ssplits in "H-frame" terms
 177  * and this returns the transfer start uframe in "B-frame" terms,
 178  * which allows both to match, e.g. a ssplit in "H-frame" uframe 0
 179  * will cause a transfer in "B-frame" uframe 0.  "B-frames" lag
 180  * "H-frames" by 1 uframe.  See the EHCI spec sec 4.5 and figure 4.7.
 181  */
 182 static inline unsigned char tt_start_uframe(struct ehci_hcd *ehci, __hc32 mask)
 183 {
 184         unsigned char smask = QH_SMASK & hc32_to_cpu(ehci, mask);
 185         if (!smask) {
 186                 ehci_err(ehci, "invalid empty smask!\n");
 187                 /* uframe 7 can't have bw so this will indicate failure */
 188                 return 7;
 189         }
 190         return ffs(smask) - 1;
 191 }
 192
 193 static const unsigned char
 194 max_tt_usecs[] = { 125, 125, 125, 125, 125, 125, 30, 0 };
 195
 196 /* carryover low/fullspeed bandwidth that crosses uframe boundries */
 197 static inline void carryover_tt_bandwidth(unsigned short tt_usecs[8])
 198 {
 199         int i;
 200         for (i=0; i<7; i++) {
 201                 if (max_tt_usecs[i] < tt_usecs[i]) {
 202                         tt_usecs[i+1] += tt_usecs[i] - max_tt_usecs[i];
 203                         tt_usecs[i] = max_tt_usecs[i];
 204                 }
 205         }
 206 }
 207
 208 /* How many of the tt's periodic downstream 1000 usecs are allocated?
 209  *
 210  * While this measures the bandwidth in terms of usecs/uframe,
 211  * the low/fullspeed bus has no notion of uframes, so any particular
 212  * low/fullspeed transfer can "carry over" from one uframe to the next,
 213  * since the TT just performs downstream transfers in sequence.
 214  *
 215  * For example two separate 100 usec transfers can start in the same uframe,
 216  * and the second one would "carry over" 75 usecs into the next uframe.
 217  */
 218 static void
 219 periodic_tt_usecs (
 220         struct ehci_hcd *ehci,
 221         struct usb_device *dev,
 222         unsigned frame,
 223         unsigned short tt_usecs[8]
 224 )
 225 {
 226         __hc32                  *hw_p = &ehci->periodic [frame];
 227         union ehci_shadow       *q = &ehci->pshadow [frame];
 228         unsigned char           uf;
 229
 230         memset(tt_usecs, 0, 16);
 231
 232         while (q->ptr) {
 233                 switch (hc32_to_cpu(ehci, Q_NEXT_TYPE(ehci, *hw_p))) {
 234                 case Q_TYPE_ITD:
 235                         hw_p = &q->itd->hw_next;
 236                         q = &q->itd->itd_next;
 237                         continue;
 238                 case Q_TYPE_QH:
 239                         if (same_tt(dev, q->qh->dev)) {
 240                                 uf = tt_start_uframe(ehci, q->qh->hw_info2);
 241                                 tt_usecs[uf] += q->qh->tt_usecs;
 242                         }
 243                         hw_p = &q->qh->hw_next;
 244                         q = &q->qh->qh_next;
 245                         continue;
 246                 case Q_TYPE_SITD:
 247                         if (same_tt(dev, q->sitd->urb->dev)) {
 248                                 uf = tt_start_uframe(ehci, q->sitd->hw_uframe);
 249                                 tt_usecs[uf] += q->sitd->stream->tt_usecs;
 250                         }
 251                         hw_p = &q->sitd->hw_next;
 252                         q = &q->sitd->sitd_next;
 253                         continue;
 254                 // case Q_TYPE_FSTN:
 255                 default:
 256                         ehci_dbg(ehci, "ignoring periodic frame %d FSTN\n",
 257                                         frame);
 258                         hw_p = &q->fstn->hw_next;
 259                         q = &q->fstn->fstn_next;
 260                 }
 261         }
 262
 263         carryover_tt_bandwidth(tt_usecs);
 264
 265         if (max_tt_usecs[7] < tt_usecs[7])
 266                 ehci_err(ehci, "frame %d tt sched overrun: %d usecs\n",
 267                         frame, tt_usecs[7] - max_tt_usecs[7]);
 268 }
 269
 270 /*
 271  * Return true if the device's tt's downstream bus is available for a
 272  * periodic transfer of the specified length (usecs), starting at the
 273  * specified frame/uframe.  Note that (as summarized in section 11.19
 274  * of the usb 2.0 spec) TTs can buffer multiple transactions for each
 275  * uframe.
 276  *
 277  * The uframe parameter is when the fullspeed/lowspeed transfer
 278  * should be executed in "B-frame" terms, which is the same as the
 279  * highspeed ssplit's uframe (which is in "H-frame" terms).  For example
 280  * a ssplit in "H-frame" 0 causes a transfer in "B-frame" 0.
 281  * See the EHCI spec sec 4.5 and fig 4.7.
 282  *
 283  * This checks if the full/lowspeed bus, at the specified starting uframe,
 284  * has the specified bandwidth available, according to rules listed
 285  * in USB 2.0 spec section 11.18.1 fig 11-60.
 286  *
 287  * This does not check if the transfer would exceed the max ssplit
 288  * limit of 16, specified in USB 2.0 spec section 11.18.4 requirement #4,
 289  * since proper scheduling limits ssplits to less than 16 per uframe.
 290  */
 291 static int tt_available (
 292         struct ehci_hcd         *ehci,
 293         unsigned                period,
 294         struct usb_device       *dev,
 295         unsigned                frame,
 296         unsigned                uframe,
 297         u16                     usecs
 298 )
 299 {
 300         if ((period == 0) || (uframe >= 7))     /* error */
 301                 return 0;
 302
 303         for (; frame < ehci->periodic_size; frame += period) {
 304                 unsigned short tt_usecs[8];
 305
 306                 periodic_tt_usecs (ehci, dev, frame, tt_usecs);
 307
 308                 ehci_vdbg(ehci, "tt frame %d check %d usecs start uframe %d in"
 309                         " schedule %d/%d/%d/%d/%d/%d/%d/%d\n",
 310                         frame, usecs, uframe,
 311                         tt_usecs[0], tt_usecs[1], tt_usecs[2], tt_usecs[3],
 312                         tt_usecs[4], tt_usecs[5], tt_usecs[6], tt_usecs[7]);
 313
 314                 if (max_tt_usecs[uframe] <= tt_usecs[uframe]) {
 315                         ehci_vdbg(ehci, "frame %d uframe %d fully scheduled\n",
 316                                 frame, uframe);
 317                         return 0;
 318                 }
 319
 320                 /* special case for isoc transfers larger than 125us:
 321                  * the first and each subsequent fully used uframe
 322                  * must be empty, so as to not illegally delay
 323                  * already scheduled transactions
 324                  */
 325                 if (125 < usecs) {
 326                         int ufs = (usecs / 125);
 327                         int i;
 328                         for (i = uframe; i < (uframe + ufs) && i < 8; i++)
 329                                 if (0 < tt_usecs[i]) {
 330                                         ehci_vdbg(ehci,
 331                                                 "multi-uframe xfer can't fit "
 332                                                 "in frame %d uframe %d\n",
 333                                                 frame, i);
 334                                         return 0;
 335                                 }
 336                 }
 337
 338                 tt_usecs[uframe] += usecs;
 339
 340                 carryover_tt_bandwidth(tt_usecs);
 341
 342                 /* fail if the carryover pushed bw past the last uframe's limit */
 343                 if (max_tt_usecs[7] < tt_usecs[7]) {
 344                         ehci_vdbg(ehci,
 345                                 "tt unavailable usecs %d frame %d uframe %d\n",
 346                                 usecs, frame, uframe);
 347                         return 0;
 348                 }
 349         }
 350
 351         return 1;
 352 }
 353
 354 #else
 355
 356 /* return true iff the device's transaction translator is available
 357  * for a periodic transfer starting at the specified frame, using
 358  * all the uframes in the mask.
 359  */
 360 static int tt_no_collision (
 361         struct ehci_hcd         *ehci,
 362         unsigned                period,
 363         struct usb_device       *dev,
 364         unsigned                frame,
 365         u32                     uf_mask
 366 )
 367 {
 368         if (period == 0)        /* error */
 369                 return 0;
 370
 371         /* note bandwidth wastage:  split never follows csplit
 372          * (different dev or endpoint) until the next uframe.
 373          * calling convention doesn't make that distinction.
 374          */
 375         for (; frame < ehci->periodic_size; frame += period) {
 376                 union ehci_shadow       here;
 377                 __hc32                  type;
 378
 379                 here = ehci->pshadow [frame];
 380                 type = Q_NEXT_TYPE(ehci, ehci->periodic [frame]);
 381                 while (here.ptr) {
 382                         switch (hc32_to_cpu(ehci, type)) {
 383                         case Q_TYPE_ITD:
 384                                 type = Q_NEXT_TYPE(ehci, here.itd->hw_next);
 385                                 here = here.itd->itd_next;
 386                                 continue;
 387                         case Q_TYPE_QH:
 388                                 if (same_tt (dev, here.qh->dev)) {
 389                                         u32             mask;
 390
 391                                         mask = hc32_to_cpu(ehci,
 392                                                         here.qh->hw_info2);
 393                                         /* "knows" no gap is needed */
 394                                         mask |= mask >> 8;
 395                                         if (mask & uf_mask)
 396                                                 break;
 397                                 }
 398                                 type = Q_NEXT_TYPE(ehci, here.qh->hw_next);
 399                                 here = here.qh->qh_next;
 400                                 continue;
 401                         case Q_TYPE_SITD:
 402                                 if (same_tt (dev, here.sitd->urb->dev)) {
 403                                         u16             mask;
 404
 405                                         mask = hc32_to_cpu(ehci, here.sitd
 406                                                                 ->hw_uframe);
 407                                         /* FIXME assumes no gap for IN! */
 408                                         mask |= mask >> 8;
 409                                         if (mask & uf_mask)
 410                                                 break;
 411                                 }
 412                                 type = Q_NEXT_TYPE(ehci, here.sitd->hw_next);
 413                                 here = here.sitd->sitd_next;
 414                                 continue;
 415                         // case Q_TYPE_FSTN:
 416                         default:
 417                                 ehci_dbg (ehci,
 418                                         "periodic frame %d bogus type %d\n",
 419                                         frame, type);
 420                         }
 421
 422                         /* collision or error */
 423                         return 0;
 424                 }
 425         }
 426
 427         /* no collision */
 428         return 1;
 429 }
 430
 431 #endif /* CONFIG_USB_EHCI_TT_NEWSCHED */
 432
 433 /*-------------------------------------------------------------------------*/
 434
 435 static int enable_periodic (struct ehci_hcd *ehci)
 436 {
 437         u32     cmd;
 438         int     status;
 439
 440         if (ehci->periodic_sched++)
 441                 return 0;
 442
 443         /* did clearing PSE did take effect yet?
 444          * takes effect only at frame boundaries...
 445          */
 446         status = handshake_on_error_set_halt(ehci, &ehci->regs->status,
 447                                              STS_PSS, 0, 9 * 125);
 448         if (status)
 449                 return status;
 450
 451         cmd = ehci_readl(ehci, &ehci->regs->command) | CMD_PSE;
 452         ehci_writel(ehci, cmd, &ehci->regs->command);
 453         /* posted write ... PSS happens later */
 454         ehci_to_hcd(ehci)->state = HC_STATE_RUNNING;
 455
 456         /* make sure ehci_work scans these */
 457         ehci->next_uframe = ehci_readl(ehci, &ehci->regs->frame_index)
 458                 % (ehci->periodic_size << 3);
 459         return 0;
 460 }
 461
 462 static int disable_periodic (struct ehci_hcd *ehci)
 463 {
 464         u32     cmd;
 465         int     status;
 466
 467         if (--ehci->periodic_sched)
 468                 return 0;
 469
 470         /* did setting PSE not take effect yet?
 471          * takes effect only at frame boundaries...
 472          */
 473         status = handshake_on_error_set_halt(ehci, &ehci->regs->status,
 474                                              STS_PSS, STS_PSS, 9 * 125);
 475         if (status)
 476                 return status;
 477
 478         cmd = ehci_readl(ehci, &ehci->regs->command) & ~CMD_PSE;
 479         ehci_writel(ehci, cmd, &ehci->regs->command);
 480         /* posted write ... */
 481
 482         ehci->next_uframe = -1;
 483         return 0;
 484 }
 485
 486 /*-------------------------------------------------------------------------*/
 487
 488 /* periodic schedule slots have iso tds (normal or split) first, then a
 489  * sparse tree for active interrupt transfers.
 490  *
 491  * this just links in a qh; caller guarantees uframe masks are set right.
 492  * no FSTN support (yet; ehci 0.96+)
 493  */
 494 static int qh_link_periodic (struct ehci_hcd *ehci, struct ehci_qh *qh)
 495 {
 496         unsigned        i;
 497         unsigned        period = qh->period;
 498
 499         dev_dbg (&qh->dev->dev,
 500                 "link qh%d-%04x/%p start %d [%d/%d us]\n",
 501                 period, hc32_to_cpup(ehci, &qh->hw_info2) & (QH_CMASK | QH_SMASK),
 502                 qh, qh->start, qh->usecs, qh->c_usecs);
 503
 504         /* high bandwidth, or otherwise every microframe */
 505         if (period == 0)
 506                 period = 1;
 507
 508         for (i = qh->start; i < ehci->periodic_size; i += period) {
 509                 union ehci_shadow       *prev = &ehci->pshadow[i];
 510                 __hc32                  *hw_p = &ehci->periodic[i];
 511                 union ehci_shadow       here = *prev;
 512                 __hc32                  type = 0;
 513
 514                 /* skip the iso nodes at list head */
 515                 while (here.ptr) {
 516                         type = Q_NEXT_TYPE(ehci, *hw_p);
 517                         if (type == cpu_to_hc32(ehci, Q_TYPE_QH))
 518                                 break;
 519                         prev = periodic_next_shadow(ehci, prev, type);
 520                         hw_p = &here.qh->hw_next;
 521                         here = *prev;
 522                 }
 523
 524                 /* sorting each branch by period (slow-->fast)
 525                  * enables sharing interior tree nodes
 526                  */
 527                 while (here.ptr && qh != here.qh) {
 528                         if (qh->period > here.qh->period)
 529                                 break;
 530                         prev = &here.qh->qh_next;
 531                         hw_p = &here.qh->hw_next;
 532                         here = *prev;
 533                 }
 534                 /* link in this qh, unless some earlier pass did that */
 535                 if (qh != here.qh) {
 536                         qh->qh_next = here;
 537                         if (here.qh)
 538                                 qh->hw_next = *hw_p;
 539                         wmb ();
 540                         prev->qh = qh;
 541                         *hw_p = QH_NEXT (ehci, qh->qh_dma);
 542                 }
 543         }
 544         qh->qh_state = QH_STATE_LINKED;
 545         qh_get (qh);
 546
 547         /* update per-qh bandwidth for usbfs */
 548         ehci_to_hcd(ehci)->self.bandwidth_allocated += qh->period
 549                 ? ((qh->usecs + qh->c_usecs) / qh->period)
 550                 : (qh->usecs * 8);
 551
 552         /* maybe enable periodic schedule processing */
 553         return enable_periodic(ehci);
 554 }
 555
 556 static int qh_unlink_periodic(struct ehci_hcd *ehci, struct ehci_qh *qh)
 557 {
 558         unsigned        i;
 559         unsigned        period;
 560
 561         // FIXME:
 562         // IF this isn't high speed
 563         //   and this qh is active in the current uframe
 564         //   (and overlay token SplitXstate is false?)
 565         // THEN
 566         //   qh->hw_info1 |= cpu_to_hc32(1 << 7 /* "ignore" */);
 567
 568         /* high bandwidth, or otherwise part of every microframe */
 569         if ((period = qh->period) == 0)
 570                 period = 1;
 571
 572         for (i = qh->start; i < ehci->periodic_size; i += period)
 573                 periodic_unlink (ehci, i, qh);
 574
 575         /* update per-qh bandwidth for usbfs */
 576         ehci_to_hcd(ehci)->self.bandwidth_allocated -= qh->period
 577                 ? ((qh->usecs + qh->c_usecs) / qh->period)
 578                 : (qh->usecs * 8);
 579
 580         dev_dbg (&qh->dev->dev,
 581                 "unlink qh%d-%04x/%p start %d [%d/%d us]\n",
 582                 qh->period,
 583                 hc32_to_cpup(ehci, &qh->hw_info2) & (QH_CMASK | QH_SMASK),
 584                 qh, qh->start, qh->usecs, qh->c_usecs);
 585
 586         /* qh->qh_next still "live" to HC */
 587         qh->qh_state = QH_STATE_UNLINK;
 588         qh->qh_next.ptr = NULL;
 589         qh_put (qh);
 590
 591         /* maybe turn off periodic schedule */
 592         return disable_periodic(ehci);
 593 }
 594
 595 static void intr_deschedule (struct ehci_hcd *ehci, struct ehci_qh *qh)
 596 {
 597         unsigned        wait;
 598
 599         qh_unlink_periodic (ehci, qh);
 600
 601         /* simple/paranoid:  always delay, expecting the HC needs to read
 602          * qh->hw_next or finish a writeback after SPLIT/CSPLIT ... and
 603          * expect khubd to clean up after any CSPLITs we won't issue.
 604          * active high speed queues may need bigger delays...
 605          */
 606         if (list_empty (&qh->qtd_list)
 607                         || (cpu_to_hc32(ehci, QH_CMASK)
 608                                         & qh->hw_info2) != 0)
 609                 wait = 2;
 610         else
 611                 wait = 55;      /* worst case: 3 * 1024 */
 612
 613         udelay (wait);
 614         qh->qh_state = QH_STATE_IDLE;
 615         qh->hw_next = EHCI_LIST_END(ehci);
 616         wmb ();
 617 }
 618
 619 /*-------------------------------------------------------------------------*/
 620
 621 static int check_period (
 622         struct ehci_hcd *ehci,
 623         unsigned        frame,
 624         unsigned        uframe,
 625         unsigned        period,
 626         unsigned        usecs
 627 ) {
 628         int             claimed;
 629
 630         /* complete split running into next frame?
 631          * given FSTN support, we could sometimes check...
 632          */
 633         if (uframe >= 8)
 634                 return 0;
 635
 636         /*
 637          * 80% periodic == 100 usec/uframe available
 638          * convert "usecs we need" to "max already claimed"
 639          */
 640         usecs = 100 - usecs;
 641
 642         /* we "know" 2 and 4 uframe intervals were rejected; so
 643          * for period 0, check _every_ microframe in the schedule.
 644          */
 645         if (unlikely (period == 0)) {
 646                 do {
 647                         for (uframe = 0; uframe < 7; uframe++) {
 648                                 claimed = periodic_usecs (ehci, frame, uframe);
 649                                 if (claimed > usecs)
 650                                         return 0;
 651                         }
 652                 } while ((frame += 1) < ehci->periodic_size);
 653
 654         /* just check the specified uframe, at that period */
 655         } else {
 656                 do {
 657                         claimed = periodic_usecs (ehci, frame, uframe);
 658                         if (claimed > usecs)
 659                                 return 0;
 660                 } while ((frame += period) < ehci->periodic_size);
 661         }
 662
 663         // success!
 664         return 1;
 665 }
 666
 667 static int check_intr_schedule (
 668         struct ehci_hcd         *ehci,
 669         unsigned                frame,
 670         unsigned                uframe,
 671         const struct ehci_qh    *qh,
 672         __hc32                  *c_maskp
 673 )
 674 {
 675         int             retval = -ENOSPC;
 676         u8              mask = 0;
 677
 678         if (qh->c_usecs && uframe >= 6)         /* FSTN territory? */
 679                 goto done;
 680
 681         if (!check_period (ehci, frame, uframe, qh->period, qh->usecs))
 682                 goto done;
 683         if (!qh->c_usecs) {
 684                 retval = 0;
 685                 *c_maskp = 0;
 686                 goto done;
 687         }
 688
 689 #ifdef CONFIG_USB_EHCI_TT_NEWSCHED
 690         if (tt_available (ehci, qh->period, qh->dev, frame, uframe,
 691                                 qh->tt_usecs)) {
 692                 unsigned i;
 693
 694                 /* TODO : this may need FSTN for SSPLIT in uframe 5. */
 695                 for (i=uframe+1; i<8 && i<uframe+4; i++)
 696                         if (!check_period (ehci, frame, i,
 697                                                 qh->period, qh->c_usecs))
 698                                 goto done;
 699                         else
 700                                 mask |= 1 << i;
 701
 702                 retval = 0;
 703
 704                 *c_maskp = cpu_to_hc32(ehci, mask << 8);
 705         }
 706 #else
 707         /* Make sure this tt's buffer is also available for CSPLITs.
 708          * We pessimize a bit; probably the typical full speed case
 709          * doesn't need the second CSPLIT.
 710          *
 711          * NOTE:  both SPLIT and CSPLIT could be checked in just
 712          * one smart pass...
 713          */
 714         mask = 0x03 << (uframe + qh->gap_uf);
 715         *c_maskp = cpu_to_hc32(ehci, mask << 8);
 716
 717         mask |= 1 << uframe;
 718         if (tt_no_collision (ehci, qh->period, qh->dev, frame, mask)) {
 719                 if (!check_period (ehci, frame, uframe + qh->gap_uf + 1,
 720                                         qh->period, qh->c_usecs))
 721                         goto done;
 722                 if (!check_period (ehci, frame, uframe + qh->gap_uf,
 723                                         qh->period, qh->c_usecs))
 724                         goto done;
 725                 retval = 0;
 726         }
 727 #endif
 728 done:
 729         return retval;
 730 }
 731
 732 /* "first fit" scheduling policy used the first time through,
 733  * or when the previous schedule slot can't be re-used.
 734  */
 735 static int qh_schedule(struct ehci_hcd *ehci, struct ehci_qh *qh)
 736 {
 737         int             status;
 738         unsigned        uframe;
 739         __hc32          c_mask;
 740         unsigned        frame;          /* 0..(qh->period - 1), or NO_FRAME */
 741
 742         qh_refresh(ehci, qh);
 743         qh->hw_next = EHCI_LIST_END(ehci);
 744         frame = qh->start;
 745
 746         /* reuse the previous schedule slots, if we can */
 747         if (frame < qh->period) {
 748                 uframe = ffs(hc32_to_cpup(ehci, &qh->hw_info2) & QH_SMASK);
 749                 status = check_intr_schedule (ehci, frame, --uframe,
 750                                 qh, &c_mask);
 751         } else {
 752                 uframe = 0;
 753                 c_mask = 0;
 754                 status = -ENOSPC;
 755         }
 756
 757         /* else scan the schedule to find a group of slots such that all
 758          * uframes have enough periodic bandwidth available.
 759          */
 760         if (status) {
 761                 /* "normal" case, uframing flexible except with splits */
 762                 if (qh->period) {
 763                         int             i;
 764
 765                         for (i = qh->period; status && i > 0; --i) {
 766                                 frame = ++ehci->random_frame % qh->period;
 767                                 for (uframe = 0; uframe < 8; uframe++) {
 768                                         status = check_intr_schedule (ehci,
 769                                                         frame, uframe, qh,
 770                                                         &c_mask);
 771                                         if (status == 0)
 772                                                 break;
 773                                 }
 774                         }
 775
 776                 /* qh->period == 0 means every uframe */
 777                 } else {
 778                         frame = 0;
 779                         status = check_intr_schedule (ehci, 0, 0, qh, &c_mask);
 780                 }
 781                 if (status)
 782                         goto done;
 783                 qh->start = frame;
 784
 785                 /* reset S-frame and (maybe) C-frame masks */
 786                 qh->hw_info2 &= cpu_to_hc32(ehci, ~(QH_CMASK | QH_SMASK));
 787                 qh->hw_info2 |= qh->period
 788                         ? cpu_to_hc32(ehci, 1 << uframe)
 789                         : cpu_to_hc32(ehci, QH_SMASK);
 790                 qh->hw_info2 |= c_mask;
 791         } else
 792                 ehci_dbg (ehci, "reused qh %p schedule\n", qh);
 793
 794         /* stuff into the periodic schedule */
 795         status = qh_link_periodic (ehci, qh);
 796 done:
 797         return status;
 798 }
 799
 800 static int intr_submit (
 801         struct ehci_hcd         *ehci,
 802         struct urb              *urb,
 803         struct list_head        *qtd_list,
 804         gfp_t                   mem_flags
 805 ) {
 806         unsigned                epnum;
 807         unsigned long           flags;
 808         struct ehci_qh          *qh;
 809         int                     status;
 810         struct list_head        empty;
 811
 812         /* get endpoint and transfer/schedule data */
 813         epnum = urb->ep->desc.bEndpointAddress;
 814
 815         spin_lock_irqsave (&ehci->lock, flags);
 816
 817         if (unlikely(!test_bit(HCD_FLAG_HW_ACCESSIBLE,
 818                         &ehci_to_hcd(ehci)->flags))) {
 819                 status = -ESHUTDOWN;
 820                 goto done_not_linked;
 821         }
 822         status = usb_hcd_link_urb_to_ep(ehci_to_hcd(ehci), urb);
 823         if (unlikely(status))
 824                 goto done_not_linked;
 825
 826         /* get qh and force any scheduling errors */
 827         INIT_LIST_HEAD (&empty);
 828         qh = qh_append_tds(ehci, urb, &empty, epnum, &urb->ep->hcpriv);
 829         if (qh == NULL) {
 830                 status = -ENOMEM;
 831                 goto done;
 832         }
 833         if (qh->qh_state == QH_STATE_IDLE) {
 834                 if ((status = qh_schedule (ehci, qh)) != 0)
 835                         goto done;
 836         }
 837
 838         /* then queue the urb's tds to the qh */
 839         qh = qh_append_tds(ehci, urb, qtd_list, epnum, &urb->ep->hcpriv);
 840         BUG_ON (qh == NULL);
 841
 842         /* ... update usbfs periodic stats */
 843         ehci_to_hcd(ehci)->self.bandwidth_int_reqs++;
 844
 845 done:
 846         if (unlikely(status))
 847                 usb_hcd_unlink_urb_from_ep(ehci_to_hcd(ehci), urb);
 848 done_not_linked:
 849         spin_unlock_irqrestore (&ehci->lock, flags);
 850         if (status)
 851                 qtd_list_free (ehci, urb, qtd_list);
 852
 853         return status;
 854 }
 855
 856 /*-------------------------------------------------------------------------*/
 857
 858 /* ehci_iso_stream ops work with both ITD and SITD */
 859
 860 static struct ehci_iso_stream *
 861 iso_stream_alloc (gfp_t mem_flags)
 862 {
 863         struct ehci_iso_stream *stream;
 864
 865         stream = kzalloc(sizeof *stream, mem_flags);
 866         if (likely (stream != NULL)) {
 867                 INIT_LIST_HEAD(&stream->td_list);
 868                 INIT_LIST_HEAD(&stream->free_list);
 869                 stream->next_uframe = -1;
 870                 stream->refcount = 1;
 871         }
 872         return stream;
 873 }
 874
 875 static void
 876 iso_stream_init (
 877         struct ehci_hcd         *ehci,
 878         struct ehci_iso_stream  *stream,
 879         struct usb_device       *dev,
 880         int                     pipe,
 881         unsigned                interval
 882 )
 883 {
 884         static const u8 smask_out [] = { 0x01, 0x03, 0x07, 0x0f, 0x1f, 0x3f };
 885
 886         u32                     buf1;
 887         unsigned                epnum, maxp;
 888         int                     is_input;
 889         long                    bandwidth;
 890
 891         /*
 892          * this might be a "high bandwidth" highspeed endpoint,
 893          * as encoded in the ep descriptor's wMaxPacket field
 894          */
 895         epnum = usb_pipeendpoint (pipe);
 896         is_input = usb_pipein (pipe) ? USB_DIR_IN : 0;
 897         maxp = usb_maxpacket(dev, pipe, !is_input);
 898         if (is_input) {
 899                 buf1 = (1 << 11);
 900         } else {
 901                 buf1 = 0;
 902         }
 903
 904         /* knows about ITD vs SITD */
 905         if (dev->speed == USB_SPEED_HIGH) {
 906                 unsigned multi = hb_mult(maxp);
 907
 908                 stream->highspeed = 1;
 909
 910                 maxp = max_packet(maxp);
 911                 buf1 |= maxp;
 912                 maxp *= multi;
 913
 914                 stream->buf0 = cpu_to_hc32(ehci, (epnum << 8) | dev->devnum);
 915                 stream->buf1 = cpu_to_hc32(ehci, buf1);
 916                 stream->buf2 = cpu_to_hc32(ehci, multi);
 917
 918                 /* usbfs wants to report the average usecs per frame tied up
 919                  * when transfers on this endpoint are scheduled ...
 920                  */
 921                 stream->usecs = HS_USECS_ISO (maxp);
 922                 bandwidth = stream->usecs * 8;
 923                 bandwidth /= interval;
 924
 925         } else {
 926                 u32             addr;
 927                 int             think_time;
 928                 int             hs_transfers;
 929
 930                 addr = dev->ttport << 24;
 931                 if (!ehci_is_TDI(ehci)
 932                                 || (dev->tt->hub !=
 933                                         ehci_to_hcd(ehci)->self.root_hub))
 934                         addr |= dev->tt->hub->devnum << 16;
 935                 addr |= epnum << 8;
 936                 addr |= dev->devnum;
 937                 stream->usecs = HS_USECS_ISO (maxp);
 938                 think_time = dev->tt ? dev->tt->think_time : 0;
 939                 stream->tt_usecs = NS_TO_US (think_time + usb_calc_bus_time (
 940                                 dev->speed, is_input, 1, maxp));
 941                 hs_transfers = max (1u, (maxp + 187) / 188);
 942                 if (is_input) {
 943                         u32     tmp;
 944
 945                         addr |= 1 << 31;
 946                         stream->c_usecs = stream->usecs;
 947                         stream->usecs = HS_USECS_ISO (1);
 948                         stream->raw_mask = 1;
 949
 950                         /* c-mask as specified in USB 2.0 11.18.4 3.c */
 951                         tmp = (1 << (hs_transfers + 2)) - 1;
 952                         stream->raw_mask |= tmp << (8 + 2);
 953                 } else
 954                         stream->raw_mask = smask_out [hs_transfers - 1];
 955                 bandwidth = stream->usecs + stream->c_usecs;
 956                 bandwidth /= interval << 3;
 957
 958                 /* stream->splits gets created from raw_mask later */
 959                 stream->address = cpu_to_hc32(ehci, addr);
 960         }
 961         stream->bandwidth = bandwidth;
 962
 963         stream->udev = dev;
 964
 965         stream->bEndpointAddress = is_input | epnum;
 966         stream->interval = interval;
 967         stream->maxp = maxp;
 968 }
 969
 970 static void
 971 iso_stream_put(struct ehci_hcd *ehci, struct ehci_iso_stream *stream)
 972 {
 973         stream->refcount--;
 974
 975         /* free whenever just a dev->ep reference remains.
 976          * not like a QH -- no persistent state (toggle, halt)
 977          */
 978         if (stream->refcount == 1) {
 979                 int             is_in;
 980
 981                 // BUG_ON (!list_empty(&stream->td_list));
 982
 983                 while (!list_empty (&stream->free_list)) {
 984                         struct list_head        *entry;
 985
 986                         entry = stream->free_list.next;
 987                         list_del (entry);
 988
 989                         /* knows about ITD vs SITD */
 990                         if (stream->highspeed) {
 991                                 struct ehci_itd         *itd;
 992
 993                                 itd = list_entry (entry, struct ehci_itd,
 994                                                 itd_list);
 995                                 dma_pool_free (ehci->itd_pool, itd,
 996                                                 itd->itd_dma);
 997                         } else {
 998                                 struct ehci_sitd        *sitd;
 999
1000                                 sitd = list_entry (entry, struct ehci_sitd,
1001                                                 sitd_list);
1002                                 dma_pool_free (ehci->sitd_pool, sitd,
1003                                                 sitd->sitd_dma);
1004                         }
1005                 }
1006
1007                 is_in = (stream->bEndpointAddress & USB_DIR_IN) ? 0x10 : 0;
1008                 stream->bEndpointAddress &= 0x0f;
1009                 if (stream->ep)
1010                         stream->ep->hcpriv = NULL;
1011
1012                 if (stream->rescheduled) {
1013                         ehci_info (ehci, "ep%d%s-iso rescheduled "
1014                                 "%lu times in %lu seconds\n",
1015                                 stream->bEndpointAddress, is_in ? "in" : "out",
1016                                 stream->rescheduled,
1017                                 ((jiffies - stream->start)/HZ)
1018                                 );
1019                 }
1020
1021                 kfree(stream);
1022         }
1023 }
1024
1025 static inline struct ehci_iso_stream *
1026 iso_stream_get (struct ehci_iso_stream *stream)
1027 {
1028         if (likely (stream != NULL))
1029                 stream->refcount++;
1030         return stream;
1031 }
1032
1033 static struct ehci_iso_stream *
1034 iso_stream_find (struct ehci_hcd *ehci, struct urb *urb)
1035 {
1036         unsigned                epnum;
1037         struct ehci_iso_stream  *stream;
1038         struct usb_host_endpoint *ep;
1039         unsigned long           flags;
1040
1041         epnum = usb_pipeendpoint (urb->pipe);
1042         if (usb_pipein(urb->pipe))
1043                 ep = urb->dev->ep_in[epnum];
1044         else
1045                 ep = urb->dev->ep_out[epnum];
1046
1047         spin_lock_irqsave (&ehci->lock, flags);
1048         stream = ep->hcpriv;
1049
1050         if (unlikely (stream == NULL)) {
1051                 stream = iso_stream_alloc(GFP_ATOMIC);
1052                 if (likely (stream != NULL)) {
1053                         /* dev->ep owns the initial refcount */
1054                         ep->hcpriv = stream;
1055                         stream->ep = ep;
1056                         iso_stream_init(ehci, stream, urb->dev, urb->pipe,
1057                                         urb->interval);
1058                 }
1059
1060         /* if dev->ep [epnum] is a QH, info1.maxpacket is nonzero */
1061         } else if (unlikely (stream->hw_info1 != 0)) {
1062                 ehci_dbg (ehci, "dev %s ep%d%s, not iso??\n",
1063                         urb->dev->devpath, epnum,
1064                         usb_pipein(urb->pipe) ? "in" : "out");
1065                 stream = NULL;
1066         }
1067
1068         /* caller guarantees an eventual matching iso_stream_put */
1069         stream = iso_stream_get (stream);
1070
1071         spin_unlock_irqrestore (&ehci->lock, flags);
1072         return stream;
1073 }
1074
1075 /*-------------------------------------------------------------------------*/
1076
1077 /* ehci_iso_sched ops can be ITD-only or SITD-only */
1078
1079 static struct ehci_iso_sched *
1080 iso_sched_alloc (unsigned packets, gfp_t mem_flags)
1081 {
1082         struct ehci_iso_sched   *iso_sched;
1083         int                     size = sizeof *iso_sched;
1084
1085         size += packets * sizeof (struct ehci_iso_packet);
1086         iso_sched = kzalloc(size, mem_flags);
1087         if (likely (iso_sched != NULL)) {
1088                 INIT_LIST_HEAD (&iso_sched->td_list);
1089         }
1090         return iso_sched;
1091 }
1092
1093 static inline void
1094 itd_sched_init(
1095         struct ehci_hcd         *ehci,
1096         struct ehci_iso_sched   *iso_sched,
1097         struct ehci_iso_stream  *stream,
1098         struct urb              *urb
1099 )
1100 {
1101         unsigned        i;
1102         dma_addr_t      dma = urb->transfer_dma;
1103
1104         /* how many uframes are needed for these transfers */
1105         iso_sched->span = urb->number_of_packets * stream->interval;
1106
1107         /* figure out per-uframe itd fields that we'll need later
1108          * when we fit new itds into the schedule.
1109          */
1110         for (i = 0; i < urb->number_of_packets; i++) {
1111                 struct ehci_iso_packet  *uframe = &iso_sched->packet [i];
1112                 unsigned                length;
1113                 dma_addr_t              buf;
1114                 u32                     trans;
1115
1116                 length = urb->iso_frame_desc [i].length;
1117                 buf = dma + urb->iso_frame_desc [i].offset;
1118
1119                 trans = EHCI_ISOC_ACTIVE;
1120                 trans |= buf & 0x0fff;
1121                 if (unlikely (((i + 1) == urb->number_of_packets))
1122                                 && !(urb->transfer_flags & URB_NO_INTERRUPT))
1123                         trans |= EHCI_ITD_IOC;
1124                 trans |= length << 16;
1125                 uframe->transaction = cpu_to_hc32(ehci, trans);
1126
1127                 /* might need to cross a buffer page within a uframe */
1128                 uframe->bufp = (buf & ~(u64)0x0fff);
1129                 buf += length;
1130                 if (unlikely ((uframe->bufp != (buf & ~(u64)0x0fff))))
1131                         uframe->cross = 1;
1132         }
1133 }
1134
1135 static void
1136 iso_sched_free (
1137         struct ehci_iso_stream  *stream,
1138         struct ehci_iso_sched   *iso_sched
1139 )
1140 {
1141         if (!iso_sched)
1142                 return;
1143         // caller must hold ehci->lock!
1144         list_splice (&iso_sched->td_list, &stream->free_list);
1145         kfree (iso_sched);
1146 }
1147
1148 static int
1149 itd_urb_transaction (
1150         struct ehci_iso_stream  *stream,
1151         struct ehci_hcd         *ehci,
1152         struct urb              *urb,
1153         gfp_t                   mem_flags
1154 )
1155 {
1156         struct ehci_itd         *itd;
1157         dma_addr_t              itd_dma;
1158         int                     i;
1159         unsigned                num_itds;
1160         struct ehci_iso_sched   *sched;
1161         unsigned long           flags;
1162
1163         sched = iso_sched_alloc (urb->number_of_packets, mem_flags);
1164         if (unlikely (sched == NULL))
1165                 return -ENOMEM;
1166
1167         itd_sched_init(ehci, sched, stream, urb);
1168
1169         if (urb->interval < 8)
1170                 num_itds = 1 + (sched->span + 7) / 8;
1171         else
1172                 num_itds = urb->number_of_packets;
1173
1174         /* allocate/init ITDs */
1175         spin_lock_irqsave (&ehci->lock, flags);
1176         for (i = 0; i < num_itds; i++) {
1177
1178                 /* free_list.next might be cache-hot ... but maybe
1179                  * the HC caches it too. avoid that issue for now.
1180                  */
1181
1182                 /* prefer previously-allocated itds */
1183                 if (likely (!list_empty(&stream->free_list))) {
1184                         itd = list_entry (stream->free_list.prev,
1185                                         struct ehci_itd, itd_list);
1186                         list_del (&itd->itd_list);
1187                         itd_dma = itd->itd_dma;
1188                 } else {
1189                         spin_unlock_irqrestore (&ehci->lock, flags);
1190                         itd = dma_pool_alloc (ehci->itd_pool, mem_flags,
1191                                         &itd_dma);
1192                         spin_lock_irqsave (&ehci->lock, flags);
1193                         if (!itd) {
1194                                 iso_sched_free(stream, sched);
1195                                 spin_unlock_irqrestore(&ehci->lock, flags);
1196                                 return -ENOMEM;
1197                         }
1198                 }
1199
1200                 memset (itd, 0, sizeof *itd);
1201                 itd->itd_dma = itd_dma;
1202                 list_add (&itd->itd_list, &sched->td_list);
1203         }
1204         spin_unlock_irqrestore (&ehci->lock, flags);
1205
1206         /* temporarily store schedule info in hcpriv */
1207         urb->hcpriv = sched;
1208         urb->error_count = 0;
1209         return 0;
1210 }
1211
1212 /*-------------------------------------------------------------------------*/
1213
1214 static inline int
1215 itd_slot_ok (
1216         struct ehci_hcd         *ehci,
1217         u32                     mod,
1218         u32                     uframe,
1219         u8                      usecs,
1220         u32                     period
1221 )
1222 {
1223         uframe %= period;
1224         do {
1225                 /* can't commit more than 80% periodic == 100 usec */
1226                 if (periodic_usecs (ehci, uframe >> 3, uframe & 0x7)
1227                                 > (100 - usecs))
1228                         return 0;
1229
1230                 /* we know urb->interval is 2^N uframes */
1231                 uframe += period;
1232         } while (uframe < mod);
1233         return 1;
1234 }
1235
1236 static inline int
1237 sitd_slot_ok (
1238         struct ehci_hcd         *ehci,
1239         u32                     mod,
1240         struct ehci_iso_stream  *stream,
1241         u32                     uframe,
1242         struct ehci_iso_sched   *sched,
1243         u32                     period_uframes
1244 )
1245 {
1246         u32                     mask, tmp;
1247         u32                     frame, uf;
1248
1249         mask = stream->raw_mask << (uframe & 7);
1250
1251         /* for IN, don't wrap CSPLIT into the next frame */
1252         if (mask & ~0xffff)
1253                 return 0;
1254
1255         /* this multi-pass logic is simple, but performance may
1256          * suffer when the schedule data isn't cached.
1257          */
1258
1259         /* check bandwidth */
1260         uframe %= period_uframes;
1261         do {
1262                 u32             max_used;
1263
1264                 frame = uframe >> 3;
1265                 uf = uframe & 7;
1266
1267 #ifdef CONFIG_USB_EHCI_TT_NEWSCHED
1268                 /* The tt's fullspeed bus bandwidth must be available.
1269                  * tt_available scheduling guarantees 10+% for control/bulk.
1270                  */
1271                 if (!tt_available (ehci, period_uframes << 3,
1272                                 stream->udev, frame, uf, stream->tt_usecs))
1273                         return 0;
1274 #else
1275                 /* tt must be idle for start(s), any gap, and csplit.
1276                  * assume scheduling slop leaves 10+% for control/bulk.
1277                  */
1278                 if (!tt_no_collision (ehci, period_uframes << 3,
1279                                 stream->udev, frame, mask))
1280                         return 0;
1281 #endif
1282
1283                 /* check starts (OUT uses more than one) */
1284                 max_used = 100 - stream->usecs;
1285                 for (tmp = stream->raw_mask & 0xff; tmp; tmp >>= 1, uf++) {
1286                         if (periodic_usecs (ehci, frame, uf) > max_used)
1287                                 return 0;
1288                 }
1289
1290                 /* for IN, check CSPLIT */
1291                 if (stream->c_usecs) {
1292                         uf = uframe & 7;
1293                         max_used = 100 - stream->c_usecs;
1294                         do {
1295                                 tmp = 1 << uf;
1296                                 tmp <<= 8;
1297                                 if ((stream->raw_mask & tmp) == 0)
1298                                         continue;
1299                                 if (periodic_usecs (ehci, frame, uf)
1300                                                 > max_used)
1301                                         return 0;
1302                         } while (++uf < 8);
1303                 }
1304
1305                 /* we know urb->interval is 2^N uframes */
1306                 uframe += period_uframes;
1307         } while (uframe < mod);
1308
1309         stream->splits = cpu_to_hc32(ehci, stream->raw_mask << (uframe & 7));
1310         return 1;
1311 }
1312
1313 /*
1314  * This scheduler plans almost as far into the future as it has actual
1315  * periodic schedule slots.  (Affected by TUNE_FLS, which defaults to
1316  * "as small as possible" to be cache-friendlier.)  That limits the size
1317  * transfers you can stream reliably; avoid more than 64 msec per urb.
1318  * Also avoid queue depths of less than ehci's worst irq latency (affected
1319  * by the per-urb URB_NO_INTERRUPT hint, the log2_irq_thresh module parameter,
1320  * and other factors); or more than about 230 msec total (for portability,
1321  * given EHCI_TUNE_FLS and the slop).  Or, write a smarter scheduler!
1322  */
1323
1324 #define SCHEDULE_SLOP   10      /* frames */
1325
1326 static int
1327 iso_stream_schedule (
1328         struct ehci_hcd         *ehci,
1329         struct urb              *urb,
1330         struct ehci_iso_stream  *stream
1331 )
1332 {
1333         u32                     now, start, max, period;
1334         int                     status;
1335         unsigned                mod = ehci->periodic_size << 3;
1336         struct ehci_iso_sched   *sched = urb->hcpriv;
1337
1338         if (sched->span > (mod - 8 * SCHEDULE_SLOP)) {
1339                 ehci_dbg (ehci, "iso request %p too long\n", urb);
1340                 status = -EFBIG;
1341                 goto fail;
1342         }
1343
1344         if ((stream->depth + sched->span) > mod) {
1345                 ehci_dbg (ehci, "request %p would overflow (%d+%d>%d)\n",
1346                         urb, stream->depth, sched->span, mod);
1347                 status = -EFBIG;
1348                 goto fail;
1349         }
1350
1351         now = ehci_readl(ehci, &ehci->regs->frame_index) % mod;
1352
1353         /* when's the last uframe this urb could start? */
1354         max = now + mod;
1355
1356         /* Typical case: reuse current schedule, stream is still active.
1357          * Hopefully there are no gaps from the host falling behind
1358          * (irq delays etc), but if there are we'll take the next
1359          * slot in the schedule, implicitly assuming URB_ISO_ASAP.
1360          */
1361         if (likely (!list_empty (&stream->td_list))) {
1362                 start = stream->next_uframe;
1363                 if (start < now)
1364                         start += mod;
1365
1366                 /* Fell behind (by up to twice the slop amount)? */
1367                 if (start >= max - 2 * 8 * SCHEDULE_SLOP)
1368                         start += stream->interval * DIV_ROUND_UP(
1369                                         max - start, stream->interval) - mod;
1370
1371                 /* Tried to schedule too far into the future? */
1372                 if (unlikely((start + sched->span) >= max)) {
1373                         status = -EFBIG;
1374                         goto fail;
1375                 }
1376                 goto ready;
1377         }
1378
1379         /* need to schedule; when's the next (u)frame we could start?
1380          * this is bigger than ehci->i_thresh allows; scheduling itself
1381          * isn't free, the slop should handle reasonably slow cpus.  it
1382          * can also help high bandwidth if the dma and irq loads don't
1383          * jump until after the queue is primed.
1384          */
1385         start = SCHEDULE_SLOP * 8 + (now & ~0x07);
1386         start %= mod;
1387         stream->next_uframe = start;
1388
1389         /* NOTE:  assumes URB_ISO_ASAP, to limit complexity/bugs */
1390
1391         period = urb->interval;
1392         if (!stream->highspeed)
1393                 period <<= 3;
1394
1395         /* find a uframe slot with enough bandwidth */
1396         for (; start < (stream->next_uframe + period); start++) {
1397                 int             enough_space;
1398
1399                 /* check schedule: enough space? */
1400                 if (stream->highspeed)
1401                         enough_space = itd_slot_ok (ehci, mod, start,
1402                                         stream->usecs, period);
1403                 else {
1404                         if ((start % 8) >= 6)
1405                                 continue;
1406                         enough_space = sitd_slot_ok (ehci, mod, stream,
1407                                         start, sched, period);
1408                 }
1409
1410                 /* schedule it here if there's enough bandwidth */
1411                 if (enough_space) {
1412                         stream->next_uframe = start % mod;
1413                         goto ready;
1414                 }
1415         }
1416
1417         /* no room in the schedule */
1418         ehci_dbg (ehci, "iso %ssched full %p (now %d max %d)\n",
1419                 list_empty (&stream->td_list) ? "" : "re",
1420                 urb, now, max);
1421         status = -ENOSPC;
1422
1423 fail:
1424         iso_sched_free (stream, sched);
1425         urb->hcpriv = NULL;
1426         return status;
1427
1428 ready:
1429         /* report high speed start in uframes; full speed, in frames */
1430         urb->start_frame = stream->next_uframe;
1431         if (!stream->highspeed)
1432                 urb->start_frame >>= 3;
1433         return 0;
1434 }
1435
1436 /*-------------------------------------------------------------------------*/
1437
1438 static inline void
1439 itd_init(struct ehci_hcd *ehci, struct ehci_iso_stream *stream,
1440                 struct ehci_itd *itd)
1441 {
1442         int i;
1443
1444         /* it's been recently zeroed */
1445         itd->hw_next = EHCI_LIST_END(ehci);
1446         itd->hw_bufp [0] = stream->buf0;
1447         itd->hw_bufp [1] = stream->buf1;
1448         itd->hw_bufp [2] = stream->buf2;
1449
1450         for (i = 0; i < 8; i++)
1451                 itd->index[i] = -1;
1452
1453         /* All other fields are filled when scheduling */
1454 }
1455
1456 static inline void
1457 itd_patch(
1458         struct ehci_hcd         *ehci,
1459         struct ehci_itd         *itd,
1460         struct ehci_iso_sched   *iso_sched,
1461         unsigned                index,
1462         u16                     uframe
1463 )
1464 {
1465         struct ehci_iso_packet  *uf = &iso_sched->packet [index];
1466         unsigned                pg = itd->pg;
1467
1468         // BUG_ON (pg == 6 && uf->cross);
1469
1470         uframe &= 0x07;
1471         itd->index [uframe] = index;
1472
1473         itd->hw_transaction[uframe] = uf->transaction;
1474         itd->hw_transaction[uframe] |= cpu_to_hc32(ehci, pg << 12);
1475         itd->hw_bufp[pg] |= cpu_to_hc32(ehci, uf->bufp & ~(u32)0);
1476         itd->hw_bufp_hi[pg] |= cpu_to_hc32(ehci, (u32)(uf->bufp >> 32));
1477
1478         /* iso_frame_desc[].offset must be strictly increasing */
1479         if (unlikely (uf->cross)) {
1480                 u64     bufp = uf->bufp + 4096;
1481
1482                 itd->pg = ++pg;
1483                 itd->hw_bufp[pg] |= cpu_to_hc32(ehci, bufp & ~(u32)0);
1484                 itd->hw_bufp_hi[pg] |= cpu_to_hc32(ehci, (u32)(bufp >> 32));
1485         }
1486 }
1487
1488 static inline void
1489 itd_link (struct ehci_hcd *ehci, unsigned frame, struct ehci_itd *itd)
1490 {
1491         /* always prepend ITD/SITD ... only QH tree is order-sensitive */
1492         itd->itd_next = ehci->pshadow [frame];
1493         itd->hw_next = ehci->periodic [frame];
1494         ehci->pshadow [frame].itd = itd;
1495         itd->frame = frame;
1496         wmb ();
1497         ehci->periodic[frame] = cpu_to_hc32(ehci, itd->itd_dma | Q_TYPE_ITD);
1498 }
1499
1500 /* fit urb's itds into the selected schedule slot; activate as needed */
1501 static int
1502 itd_link_urb (
1503         struct ehci_hcd         *ehci,
1504         struct urb              *urb,
1505         unsigned                mod,
1506         struct ehci_iso_stream  *stream
1507 )
1508 {
1509         int                     packet;
1510         unsigned                next_uframe, uframe, frame;
1511         struct ehci_iso_sched   *iso_sched = urb->hcpriv;
1512         struct ehci_itd         *itd;
1513
1514         next_uframe = stream->next_uframe % mod;
1515
1516         if (unlikely (list_empty(&stream->td_list))) {
1517                 ehci_to_hcd(ehci)->self.bandwidth_allocated
1518                                 += stream->bandwidth;
1519                 ehci_vdbg (ehci,
1520                         "schedule devp %s ep%d%s-iso period %d start %d.%d\n",
1521                         urb->dev->devpath, stream->bEndpointAddress & 0x0f,
1522                         (stream->bEndpointAddress & USB_DIR_IN) ? "in" : "out",
1523                         urb->interval,
1524                         next_uframe >> 3, next_uframe & 0x7);
1525                 stream->start = jiffies;
1526         }
1527         ehci_to_hcd(ehci)->self.bandwidth_isoc_reqs++;
1528
1529         /* fill iTDs uframe by uframe */
1530         for (packet = 0, itd = NULL; packet < urb->number_of_packets; ) {
1531                 if (itd == NULL) {
1532                         /* ASSERT:  we have all necessary itds */
1533                         // BUG_ON (list_empty (&iso_sched->td_list));
1534
1535                         /* ASSERT:  no itds for this endpoint in this uframe */
1536
1537                         itd = list_entry (iso_sched->td_list.next,
1538                                         struct ehci_itd, itd_list);
1539                         list_move_tail (&itd->itd_list, &stream->td_list);
1540                         itd->stream = iso_stream_get (stream);
1541                         itd->urb = urb;
1542                         itd_init (ehci, stream, itd);
1543                 }
1544
1545                 uframe = next_uframe & 0x07;
1546                 frame = next_uframe >> 3;
1547
1548                 itd_patch(ehci, itd, iso_sched, packet, uframe);
1549
1550                 next_uframe += stream->interval;
1551                 stream->depth += stream->interval;
1552                 next_uframe %= mod;
1553                 packet++;
1554
1555                 /* link completed itds into the schedule */
1556                 if (((next_uframe >> 3) != frame)
1557                                 || packet == urb->number_of_packets) {
1558                         itd_link (ehci, frame % ehci->periodic_size, itd);
1559                         itd = NULL;
1560                 }
1561         }
1562         stream->next_uframe = next_uframe;
1563
1564         /* don't need that schedule data any more */
1565         iso_sched_free (stream, iso_sched);
1566         urb->hcpriv = NULL;
1567
1568         timer_action (ehci, TIMER_IO_WATCHDOG);
1569         return enable_periodic(ehci);
1570 }
1571
1572 #define ISO_ERRS (EHCI_ISOC_BUF_ERR | EHCI_ISOC_BABBLE | EHCI_ISOC_XACTERR)
1573
1574 /* Process and recycle a completed ITD.  Return true iff its urb completed,
1575  * and hence its completion callback probably added things to the hardware
1576  * schedule.
1577  *
1578  * Note that we carefully avoid recycling this descriptor until after any
1579  * completion callback runs, so that it won't be reused quickly.  That is,
1580  * assuming (a) no more than two urbs per frame on this endpoint, and also
1581  * (b) only this endpoint's completions submit URBs.  It seems some silicon
1582  * corrupts things if you reuse completed descriptors very quickly...
1583  */
1584 static unsigned
1585 itd_complete (
1586         struct ehci_hcd *ehci,
1587         struct ehci_itd *itd
1588 ) {
1589         struct urb                              *urb = itd->urb;
1590         struct usb_iso_packet_descriptor        *desc;
1591         u32                                     t;
1592         unsigned                                uframe;
1593         int                                     urb_index = -1;
1594         struct ehci_iso_stream                  *stream = itd->stream;
1595         struct usb_device                       *dev;
1596         unsigned                                retval = false;
1597
1598         /* for each uframe with a packet */
1599         for (uframe = 0; uframe < 8; uframe++) {
1600                 if (likely (itd->index[uframe] == -1))
1601                         continue;
1602                 urb_index = itd->index[uframe];
1603                 desc = &urb->iso_frame_desc [urb_index];
1604
1605                 t = hc32_to_cpup(ehci, &itd->hw_transaction [uframe]);
1606                 itd->hw_transaction [uframe] = 0;
1607                 stream->depth -= stream->interval;
1608
1609                 /* report transfer status */
1610                 if (unlikely (t & ISO_ERRS)) {
1611                         urb->error_count++;
1612                         if (t & EHCI_ISOC_BUF_ERR)
1613                                 desc->status = usb_pipein (urb->pipe)
1614                                         ? -ENOSR  /* hc couldn't read */
1615                                         : -ECOMM; /* hc couldn't write */
1616                         else if (t & EHCI_ISOC_BABBLE)
1617                                 desc->status = -EOVERFLOW;
1618                         else /* (t & EHCI_ISOC_XACTERR) */
1619                                 desc->status = -EPROTO;
1620
1621                         /* HC need not update length with this error */
1622                         if (!(t & EHCI_ISOC_BABBLE))
1623                                 desc->actual_length = EHCI_ITD_LENGTH (t);
1624                 } else if (likely ((t & EHCI_ISOC_ACTIVE) == 0)) {
1625                         desc->status = 0;
1626                         desc->actual_length = EHCI_ITD_LENGTH (t);
1627                 } else {
1628                         /* URB was too late */
1629                         desc->status = -EXDEV;
1630                 }
1631         }
1632
1633         /* handle completion now? */
1634         if (likely ((urb_index + 1) != urb->number_of_packets))
1635                 goto done;
1636
1637         /* ASSERT: it's really the last itd for this urb
1638         list_for_each_entry (itd, &stream->td_list, itd_list)
1639                 BUG_ON (itd->urb == urb);
1640          */
1641
1642         /* give urb back to the driver; completion often (re)submits */
1643         dev = urb->dev;
1644         ehci_urb_done(ehci, urb, 0);
1645         retval = true;
1646         urb = NULL;
1647         (void) disable_periodic(ehci);
1648         ehci_to_hcd(ehci)->self.bandwidth_isoc_reqs--;
1649
1650         if (unlikely(list_is_singular(&stream->td_list))) {
1651                 ehci_to_hcd(ehci)->self.bandwidth_allocated
1652                                 -= stream->bandwidth;
1653                 ehci_vdbg (ehci,
1654                         "deschedule devp %s ep%d%s-iso\n",
1655                         dev->devpath, stream->bEndpointAddress & 0x0f,
1656                         (stream->bEndpointAddress & USB_DIR_IN) ? "in" : "out");
1657         }
1658         iso_stream_put (ehci, stream);
1659
1660 done:
1661         itd->urb = NULL;
1662         if (ehci->clock_frame != itd->frame || itd->index[7] != -1) {
1663                 /* OK to recycle this ITD now. */
1664                 itd->stream = NULL;
1665                 list_move(&itd->itd_list, &stream->free_list);
1666                 iso_stream_put(ehci, stream);
1667         } else {
1668                 /* HW might remember this ITD, so we can't recycle it yet.
1669                  * Move it to a safe place until a new frame starts.
1670                  */
1671                 list_move(&itd->itd_list, &ehci->cached_itd_list);
1672                 if (stream->refcount == 2) {
1673                         /* If iso_stream_put() were called here, stream
1674                          * would be freed.  Instead, just prevent reuse.
1675                          */
1676                         stream->ep->hcpriv = NULL;
1677                         stream->ep = NULL;
1678                 }
1679         }
1680         return retval;
1681 }
1682
1683 /*-------------------------------------------------------------------------*/
1684
1685 static int itd_submit (struct ehci_hcd *ehci, struct urb *urb,
1686         gfp_t mem_flags)
1687 {
1688         int                     status = -EINVAL;
1689         unsigned long           flags;
1690         struct ehci_iso_stream  *stream;
1691
1692         /* Get iso_stream head */
1693         stream = iso_stream_find (ehci, urb);
1694         if (unlikely (stream == NULL)) {
1695                 ehci_dbg (ehci, "can't get iso stream\n");
1696                 return -ENOMEM;
1697         }
1698         if (unlikely (urb->interval != stream->interval)) {
1699                 ehci_dbg (ehci, "can't change iso interval %d --> %d\n",
1700                         stream->interval, urb->interval);
1701                 goto done;
1702         }
1703
1704 #ifdef EHCI_URB_TRACE
1705         ehci_dbg (ehci,
1706                 "%s %s urb %p ep%d%s len %d, %d pkts %d uframes [%p]\n",
1707                 __func__, urb->dev->devpath, urb,
1708                 usb_pipeendpoint (urb->pipe),
1709                 usb_pipein (urb->pipe) ? "in" : "out",
1710                 urb->transfer_buffer_length,
1711                 urb->number_of_packets, urb->interval,
1712                 stream);
1713 #endif
1714
1715         /* allocate ITDs w/o locking anything */
1716         status = itd_urb_transaction (stream, ehci, urb, mem_flags);
1717         if (unlikely (status < 0)) {
1718                 ehci_dbg (ehci, "can't init itds\n");
1719                 goto done;
1720         }
1721
1722         /* schedule ... need to lock */
1723         spin_lock_irqsave (&ehci->lock, flags);
1724         if (unlikely(!test_bit(HCD_FLAG_HW_ACCESSIBLE,
1725                                &ehci_to_hcd(ehci)->flags))) {
1726                 status = -ESHUTDOWN;
1727                 goto done_not_linked;
1728         }
1729         status = usb_hcd_link_urb_to_ep(ehci_to_hcd(ehci), urb);
1730         if (unlikely(status))
1731                 goto done_not_linked;
1732         status = iso_stream_schedule(ehci, urb, stream);
1733         if (likely (status == 0))
1734                 itd_link_urb (ehci, urb, ehci->periodic_size << 3, stream);
1735         else
1736                 usb_hcd_unlink_urb_from_ep(ehci_to_hcd(ehci), urb);
1737 done_not_linked:
1738         spin_unlock_irqrestore (&ehci->lock, flags);
1739
1740 done:
1741         if (unlikely (status < 0))
1742                 iso_stream_put (ehci, stream);
1743         return status;
1744 }
1745
1746 /*-------------------------------------------------------------------------*/
1747
1748 /*
1749  * "Split ISO TDs" ... used for USB 1.1 devices going through the
1750  * TTs in USB 2.0 hubs.  These need microframe scheduling.
1751  */
1752
1753 static inline void
1754 sitd_sched_init(
1755         struct ehci_hcd         *ehci,
1756         struct ehci_iso_sched   *iso_sched,
1757         struct ehci_iso_stream  *stream,
1758         struct urb              *urb
1759 )
1760 {
1761         unsigned        i;
1762         dma_addr_t      dma = urb->transfer_dma;
1763
1764         /* how many frames are needed for these transfers */
1765         iso_sched->span = urb->number_of_packets * stream->interval;
1766
1767         /* figure out per-frame sitd fields that we'll need later
1768          * when we fit new sitds into the schedule.
1769          */
1770         for (i = 0; i < urb->number_of_packets; i++) {
1771                 struct ehci_iso_packet  *packet = &iso_sched->packet [i];
1772                 unsigned                length;
1773                 dma_addr_t              buf;
1774                 u32                     trans;
1775
1776                 length = urb->iso_frame_desc [i].length & 0x03ff;
1777                 buf = dma + urb->iso_frame_desc [i].offset;
1778
1779                 trans = SITD_STS_ACTIVE;
1780                 if (((i + 1) == urb->number_of_packets)
1781                                 && !(urb->transfer_flags & URB_NO_INTERRUPT))
1782                         trans |= SITD_IOC;
1783                 trans |= length << 16;
1784                 packet->transaction = cpu_to_hc32(ehci, trans);
1785
1786                 /* might need to cross a buffer page within a td */
1787                 packet->bufp = buf;
1788                 packet->buf1 = (buf + length) & ~0x0fff;
1789                 if (packet->buf1 != (buf & ~(u64)0x0fff))
1790                         packet->cross = 1;
1791
1792                 /* OUT uses multiple start-splits */
1793                 if (stream->bEndpointAddress & USB_DIR_IN)
1794                         continue;
1795                 length = (length + 187) / 188;
1796                 if (length > 1) /* BEGIN vs ALL */
1797                         length |= 1 << 3;
1798                 packet->buf1 |= length;
1799         }
1800 }
1801
1802 static int
1803 sitd_urb_transaction (
1804         struct ehci_iso_stream  *stream,
1805         struct ehci_hcd         *ehci,
1806         struct urb              *urb,
1807         gfp_t                   mem_flags
1808 )
1809 {
1810         struct ehci_sitd        *sitd;
1811         dma_addr_t              sitd_dma;
1812         int                     i;
1813         struct ehci_iso_sched   *iso_sched;
1814         unsigned long           flags;
1815
1816         iso_sched = iso_sched_alloc (urb->number_of_packets, mem_flags);
1817         if (iso_sched == NULL)
1818                 return -ENOMEM;
1819
1820         sitd_sched_init(ehci, iso_sched, stream, urb);
1821
1822         /* allocate/init sITDs */
1823         spin_lock_irqsave (&ehci->lock, flags);
1824         for (i = 0; i < urb->number_of_packets; i++) {
1825
1826                 /* NOTE:  for now, we don't try to handle wraparound cases
1827                  * for IN (using sitd->hw_backpointer, like a FSTN), which
1828                  * means we never need two sitds for full speed packets.
1829                  */
1830
1831                 /* free_list.next might be cache-hot ... but maybe
1832                  * the HC caches it too. avoid that issue for now.
1833                  */
1834
1835                 /* prefer previously-allocated sitds */
1836                 if (!list_empty(&stream->free_list)) {
1837                         sitd = list_entry (stream->free_list.prev,
1838                                          struct ehci_sitd, sitd_list);
1839                         list_del (&sitd->sitd_list);
1840                         sitd_dma = sitd->sitd_dma;
1841                 } else {
1842                         spin_unlock_irqrestore (&ehci->lock, flags);
1843                         sitd = dma_pool_alloc (ehci->sitd_pool, mem_flags,
1844                                         &sitd_dma);
1845                         spin_lock_irqsave (&ehci->lock, flags);
1846                         if (!sitd) {
1847                                 iso_sched_free(stream, iso_sched);
1848                                 spin_unlock_irqrestore(&ehci->lock, flags);
1849                                 return -ENOMEM;
1850                         }
1851                 }
1852
1853                 memset (sitd, 0, sizeof *sitd);
1854                 sitd->sitd_dma = sitd_dma;
1855                 list_add (&sitd->sitd_list, &iso_sched->td_list);
1856         }
1857
1858         /* temporarily store schedule info in hcpriv */
1859         urb->hcpriv = iso_sched;
1860         urb->error_count = 0;
1861
1862         spin_unlock_irqrestore (&ehci->lock, flags);
1863         return 0;
1864 }
1865
1866 /*-------------------------------------------------------------------------*/
1867
1868 static inline void
1869 sitd_patch(
1870         struct ehci_hcd         *ehci,
1871         struct ehci_iso_stream  *stream,
1872         struct ehci_sitd        *sitd,
1873         struct ehci_iso_sched   *iso_sched,
1874         unsigned                index
1875 )
1876 {
1877         struct ehci_iso_packet  *uf = &iso_sched->packet [index];
1878         u64                     bufp = uf->bufp;
1879
1880         sitd->hw_next = EHCI_LIST_END(ehci);
1881         sitd->hw_fullspeed_ep = stream->address;
1882         sitd->hw_uframe = stream->splits;
1883         sitd->hw_results = uf->transaction;
1884         sitd->hw_backpointer = EHCI_LIST_END(ehci);
1885
1886         bufp = uf->bufp;
1887         sitd->hw_buf[0] = cpu_to_hc32(ehci, bufp);
1888         sitd->hw_buf_hi[0] = cpu_to_hc32(ehci, bufp >> 32);
1889
1890         sitd->hw_buf[1] = cpu_to_hc32(ehci, uf->buf1);
1891         if (uf->cross)
1892                 bufp += 4096;
1893         sitd->hw_buf_hi[1] = cpu_to_hc32(ehci, bufp >> 32);
1894         sitd->index = index;
1895 }
1896
1897 static inline void
1898 sitd_link (struct ehci_hcd *ehci, unsigned frame, struct ehci_sitd *sitd)
1899 {
1900         /* note: sitd ordering could matter (CSPLIT then SSPLIT) */
1901         sitd->sitd_next = ehci->pshadow [frame];
1902         sitd->hw_next = ehci->periodic [frame];
1903         ehci->pshadow [frame].sitd = sitd;
1904         sitd->frame = frame;
1905         wmb ();
1906         ehci->periodic[frame] = cpu_to_hc32(ehci, sitd->sitd_dma | Q_TYPE_SITD);
1907 }
1908
1909 /* fit urb's sitds into the selected schedule slot; activate as needed */
1910 static int
1911 sitd_link_urb (
1912         struct ehci_hcd         *ehci,
1913         struct urb              *urb,
1914         unsigned                mod,
1915         struct ehci_iso_stream  *stream
1916 )
1917 {
1918         int                     packet;
1919         unsigned                next_uframe;
1920         struct ehci_iso_sched   *sched = urb->hcpriv;
1921         struct ehci_sitd        *sitd;
1922
1923         next_uframe = stream->next_uframe;
1924
1925         if (list_empty(&stream->td_list)) {
1926                 /* usbfs ignores TT bandwidth */
1927                 ehci_to_hcd(ehci)->self.bandwidth_allocated
1928                                 += stream->bandwidth;
1929                 ehci_vdbg (ehci,
1930                         "sched devp %s ep%d%s-iso [%d] %dms/%04x\n",
1931                         urb->dev->devpath, stream->bEndpointAddress & 0x0f,
1932                         (stream->bEndpointAddress & USB_DIR_IN) ? "in" : "out",
1933                         (next_uframe >> 3) % ehci->periodic_size,
1934                         stream->interval, hc32_to_cpu(ehci, stream->splits));
1935                 stream->start = jiffies;
1936         }
1937         ehci_to_hcd(ehci)->self.bandwidth_isoc_reqs++;
1938
1939         /* fill sITDs frame by frame */
1940         for (packet = 0, sitd = NULL;
1941                         packet < urb->number_of_packets;
1942                         packet++) {
1943
1944                 /* ASSERT:  we have all necessary sitds */
1945                 BUG_ON (list_empty (&sched->td_list));
1946
1947                 /* ASSERT:  no itds for this endpoint in this frame */
1948
1949                 sitd = list_entry (sched->td_list.next,
1950                                 struct ehci_sitd, sitd_list);
1951                 list_move_tail (&sitd->sitd_list, &stream->td_list);
1952                 sitd->stream = iso_stream_get (stream);
1953                 sitd->urb = urb;
1954
1955                 sitd_patch(ehci, stream, sitd, sched, packet);
1956                 sitd_link (ehci, (next_uframe >> 3) % ehci->periodic_size,
1957                                 sitd);
1958
1959                 next_uframe += stream->interval << 3;
1960                 stream->depth += stream->interval << 3;
1961         }
1962         stream->next_uframe = next_uframe % mod;
1963
1964         /* don't need that schedule data any more */
1965         iso_sched_free (stream, sched);
1966         urb->hcpriv = NULL;
1967
1968         timer_action (ehci, TIMER_IO_WATCHDOG);
1969         return enable_periodic(ehci);
1970 }
1971
1972 /*-------------------------------------------------------------------------*/
1973
1974 #define SITD_ERRS (SITD_STS_ERR | SITD_STS_DBE | SITD_STS_BABBLE \
1975                                 | SITD_STS_XACT | SITD_STS_MMF)
1976
1977 /* Process and recycle a completed SITD.  Return true iff its urb completed,
1978  * and hence its completion callback probably added things to the hardware
1979  * schedule.
1980  *
1981  * Note that we carefully avoid recycling this descriptor until after any
1982  * completion callback runs, so that it won't be reused quickly.  That is,
1983  * assuming (a) no more than two urbs per frame on this endpoint, and also
1984  * (b) only this endpoint's completions submit URBs.  It seems some silicon
1985  * corrupts things if you reuse completed descriptors very quickly...
1986  */
1987 static unsigned
1988 sitd_complete (
1989         struct ehci_hcd         *ehci,
1990         struct ehci_sitd        *sitd
1991 ) {
1992         struct urb                              *urb = sitd->urb;
1993         struct usb_iso_packet_descriptor        *desc;
1994         u32                                     t;
1995         int                                     urb_index = -1;
1996         struct ehci_iso_stream                  *stream = sitd->stream;
1997         struct usb_device                       *dev;
1998         unsigned                                retval = false;
1999
2000         urb_index = sitd->index;
2001         desc = &urb->iso_frame_desc [urb_index];
2002         t = hc32_to_cpup(ehci, &sitd->hw_results);
2003
2004         /* report transfer status */
2005         if (t & SITD_ERRS) {
2006                 urb->error_count++;
2007                 if (t & SITD_STS_DBE)
2008                         desc->status = usb_pipein (urb->pipe)
2009                                 ? -ENOSR  /* hc couldn't read */
2010                                 : -ECOMM; /* hc couldn't write */
2011                 else if (t & SITD_STS_BABBLE)
2012                         desc->status = -EOVERFLOW;
2013                 else /* XACT, MMF, etc */
2014                         desc->status = -EPROTO;
2015         } else {
2016                 desc->status = 0;
2017                 desc->actual_length = desc->length - SITD_LENGTH (t);
2018         }
2019         stream->depth -= stream->interval << 3;
2020
2021         /* handle completion now? */
2022         if ((urb_index + 1) != urb->number_of_packets)
2023                 goto done;
2024
2025         /* ASSERT: it's really the last sitd for this urb
2026         list_for_each_entry (sitd, &stream->td_list, sitd_list)
2027                 BUG_ON (sitd->urb == urb);
2028          */
2029
2030         /* give urb back to the driver; completion often (re)submits */
2031         dev = urb->dev;
2032         ehci_urb_done(ehci, urb, 0);
2033         retval = true;
2034         urb = NULL;
2035         (void) disable_periodic(ehci);
2036         ehci_to_hcd(ehci)->self.bandwidth_isoc_reqs--;
2037
2038         if (list_is_singular(&stream->td_list)) {
2039                 ehci_to_hcd(ehci)->self.bandwidth_allocated
2040                                 -= stream->bandwidth;
2041                 ehci_vdbg (ehci,
2042                         "deschedule devp %s ep%d%s-iso\n",
2043                         dev->devpath, stream->bEndpointAddress & 0x0f,
2044                         (stream->bEndpointAddress & USB_DIR_IN) ? "in" : "out");
2045         }
2046         iso_stream_put (ehci, stream);
2047         /* OK to recycle this SITD now that its completion callback ran. */
2048 done:
2049         sitd->urb = NULL;
2050         sitd->stream = NULL;
2051         list_move(&sitd->sitd_list, &stream->free_list);
2052         iso_stream_put(ehci, stream);
2053
2054         return retval;
2055 }
2056
2057
2058 static int sitd_submit (struct ehci_hcd *ehci, struct urb *urb,
2059         gfp_t mem_flags)
2060 {
2061         int                     status = -EINVAL;
2062         unsigned long           flags;
2063         struct ehci_iso_stream  *stream;
2064
2065         /* Get iso_stream head */
2066         stream = iso_stream_find (ehci, urb);
2067         if (stream == NULL) {
2068                 ehci_dbg (ehci, "can't get iso stream\n");
2069                 return -ENOMEM;
2070         }
2071         if (urb->interval != stream->interval) {
2072                 ehci_dbg (ehci, "can't change iso interval %d --> %d\n",
2073                         stream->interval, urb->interval);
2074                 goto done;
2075         }
2076
2077 #ifdef EHCI_URB_TRACE
2078         ehci_dbg (ehci,
2079                 "submit %p dev%s ep%d%s-iso len %d\n",
2080                 urb, urb->dev->devpath,
2081                 usb_pipeendpoint (urb->pipe),
2082                 usb_pipein (urb->pipe) ? "in" : "out",
2083                 urb->transfer_buffer_length);
2084 #endif
2085
2086         /* allocate SITDs */
2087         status = sitd_urb_transaction (stream, ehci, urb, mem_flags);
2088         if (status < 0) {
2089                 ehci_dbg (ehci, "can't init sitds\n");
2090                 goto done;
2091         }
2092
2093         /* schedule ... need to lock */
2094         spin_lock_irqsave (&ehci->lock, flags);
2095         if (unlikely(!test_bit(HCD_FLAG_HW_ACCESSIBLE,
2096                                &ehci_to_hcd(ehci)->flags))) {
2097                 status = -ESHUTDOWN;
2098                 goto done_not_linked;
2099         }
2100         status = usb_hcd_link_urb_to_ep(ehci_to_hcd(ehci), urb);
2101         if (unlikely(status))
2102                 goto done_not_linked;
2103         status = iso_stream_schedule(ehci, urb, stream);
2104         if (status == 0)
2105                 sitd_link_urb (ehci, urb, ehci->periodic_size << 3, stream);
2106         else
2107                 usb_hcd_unlink_urb_from_ep(ehci_to_hcd(ehci), urb);
2108 done_not_linked:
2109         spin_unlock_irqrestore (&ehci->lock, flags);
2110
2111 done:
2112         if (status < 0)
2113                 iso_stream_put (ehci, stream);
2114         return status;
2115 }
2116
2117 /*-------------------------------------------------------------------------*/
2118
2119 static void free_cached_itd_list(struct ehci_hcd *ehci)
2120 {
2121         struct ehci_itd *itd, *n;
2122
2123         list_for_each_entry_safe(itd, n, &ehci->cached_itd_list, itd_list) {
2124                 struct ehci_iso_stream  *stream = itd->stream;
2125                 itd->stream = NULL;
2126                 list_move(&itd->itd_list, &stream->free_list);
2127                 iso_stream_put(ehci, stream);
2128         }
2129 }
2130
2131 /*-------------------------------------------------------------------------*/
2132
2133 static void
2134 scan_periodic (struct ehci_hcd *ehci)
2135 {
2136         unsigned        now_uframe, frame, clock, clock_frame, mod;
2137         unsigned        modified;
2138
2139         mod = ehci->periodic_size << 3;
2140
2141         /*
2142          * When running, scan from last scan point up to "now"
2143          * else clean up by scanning everything that's left.
2144          * Touches as few pages as possible:  cache-friendly.
2145          */
2146         now_uframe = ehci->next_uframe;
2147         if (HC_IS_RUNNING(ehci_to_hcd(ehci)->state)) {
2148                 clock = ehci_readl(ehci, &ehci->regs->frame_index);
2149                 clock_frame = (clock >> 3) % ehci->periodic_size;
2150         } else  {
2151                 clock = now_uframe + mod - 1;
2152                 clock_frame = -1;
2153         }
2154         if (ehci->clock_frame != clock_frame) {
2155                 free_cached_itd_list(ehci);
2156                 ehci->clock_frame = clock_frame;
2157         }
2158         clock %= mod;
2159         clock_frame = clock >> 3;
2160
2161         for (;;) {
2162                 union ehci_shadow       q, *q_p;
2163                 __hc32                  type, *hw_p;
2164                 unsigned                incomplete = false;
2165
2166                 frame = now_uframe >> 3;
2167
2168 restart:
2169                 /* scan each element in frame's queue for completions */
2170                 q_p = &ehci->pshadow [frame];
2171                 hw_p = &ehci->periodic [frame];
2172                 q.ptr = q_p->ptr;
2173                 type = Q_NEXT_TYPE(ehci, *hw_p);
2174                 modified = 0;
2175
2176                 while (q.ptr != NULL) {
2177                         unsigned                uf;
2178                         union ehci_shadow       temp;
2179                         int                     live;
2180
2181                         live = HC_IS_RUNNING (ehci_to_hcd(ehci)->state);
2182                         switch (hc32_to_cpu(ehci, type)) {
2183                         case Q_TYPE_QH:
2184                                 /* handle any completions */
2185                                 temp.qh = qh_get (q.qh);
2186                                 type = Q_NEXT_TYPE(ehci, q.qh->hw_next);
2187                                 q = q.qh->qh_next;
2188                                 modified = qh_completions (ehci, temp.qh);
2189                                 if (unlikely (list_empty (&temp.qh->qtd_list)))
2190                                         intr_deschedule (ehci, temp.qh);
2191                                 qh_put (temp.qh);
2192                                 break;
2193                         case Q_TYPE_FSTN:
2194                                 /* for "save place" FSTNs, look at QH entries
2195                                  * in the previous frame for completions.
2196                                  */
2197                                 if (q.fstn->hw_prev != EHCI_LIST_END(ehci)) {
2198                                         dbg ("ignoring completions from FSTNs");
2199                                 }
2200                                 type = Q_NEXT_TYPE(ehci, q.fstn->hw_next);
2201                                 q = q.fstn->fstn_next;
2202                                 break;
2203                         case Q_TYPE_ITD:
2204                                 /* If this ITD is still active, leave it for
2205                                  * later processing ... check the next entry.
2206                                  * No need to check for activity unless the
2207                                  * frame is current.
2208                                  */
2209                                 if (frame == clock_frame && live) {
2210                                         rmb();
2211                                         for (uf = 0; uf < 8; uf++) {
2212                                                 if (q.itd->hw_transaction[uf] &
2213                                                             ITD_ACTIVE(ehci))
2214                                                         break;
2215                                         }
2216                                         if (uf < 8) {
2217                                                 incomplete = true;
2218                                                 q_p = &q.itd->itd_next;
2219                                                 hw_p = &q.itd->hw_next;
2220                                                 type = Q_NEXT_TYPE(ehci,
2221                                                         q.itd->hw_next);
2222                                                 q = *q_p;
2223                                                 break;
2224                                         }
2225                                 }
2226
2227                                 /* Take finished ITDs out of the schedule
2228                                  * and process them:  recycle, maybe report
2229                                  * URB completion.  HC won't cache the
2230                                  * pointer for much longer, if at all.
2231                                  */
2232                                 *q_p = q.itd->itd_next;
2233                                 *hw_p = q.itd->hw_next;
2234                                 type = Q_NEXT_TYPE(ehci, q.itd->hw_next);
2235                                 wmb();
2236                                 modified = itd_complete (ehci, q.itd);
2237                                 q = *q_p;
2238                                 break;
2239                         case Q_TYPE_SITD:
2240                                 /* If this SITD is still active, leave it for
2241                                  * later processing ... check the next entry.
2242                                  * No need to check for activity unless the
2243                                  * frame is current.
2244                                  */
2245                                 if (frame == clock_frame && live &&
2246                                                 (q.sitd->hw_results &
2247                                                         SITD_ACTIVE(ehci))) {
2248                                         incomplete = true;
2249                                         q_p = &q.sitd->sitd_next;
2250                                         hw_p = &q.sitd->hw_next;
2251                                         type = Q_NEXT_TYPE(ehci,
2252                                                         q.sitd->hw_next);
2253                                         q = *q_p;
2254                                         break;
2255                                 }
2256
2257                                 /* Take finished SITDs out of the schedule
2258                                  * and process them:  recycle, maybe report
2259                                  * URB completion.
2260                                  */
2261                                 *q_p = q.sitd->sitd_next;
2262                                 *hw_p = q.sitd->hw_next;
2263                                 type = Q_NEXT_TYPE(ehci, q.sitd->hw_next);
2264                                 wmb();
2265                                 modified = sitd_complete (ehci, q.sitd);
2266                                 q = *q_p;
2267                                 break;
2268                         default:
2269                                 dbg ("corrupt type %d frame %d shadow %p",
2270                                         type, frame, q.ptr);
2271                                 // BUG ();
2272                                 q.ptr = NULL;
2273                         }
2274
2275                         /* assume completion callbacks modify the queue */
2276                         if (unlikely (modified)) {
2277                                 if (likely(ehci->periodic_sched > 0))
2278                                         goto restart;
2279                                 /* short-circuit this scan */
2280                                 now_uframe = clock;
2281                                 break;
2282                         }
2283                 }
2284
2285                 /* If we can tell we caught up to the hardware, stop now.
2286                  * We can't advance our scan without collecting the ISO
2287                  * transfers that are still pending in this frame.
2288                  */
2289                 if (incomplete && HC_IS_RUNNING(ehci_to_hcd(ehci)->state)) {
2290                         ehci->next_uframe = now_uframe;
2291                         break;
2292                 }
2293
2294                 // FIXME:  this assumes we won't get lapped when
2295                 // latencies climb; that should be rare, but...
2296                 // detect it, and just go all the way around.
2297                 // FLR might help detect this case, so long as latencies
2298                 // don't exceed periodic_size msec (default 1.024 sec).
2299
2300                 // FIXME:  likewise assumes HC doesn't halt mid-scan
2301
2302                 if (now_uframe == clock) {
2303                         unsigned        now;
2304
2305                         if (!HC_IS_RUNNING (ehci_to_hcd(ehci)->state)
2306                                         || ehci->periodic_sched == 0)
2307                                 break;
2308                         ehci->next_uframe = now_uframe;
2309                         now = ehci_readl(ehci, &ehci->regs->frame_index) % mod;
2310                         if (now_uframe == now)
2311                                 break;
2312
2313                         /* rescan the rest of this frame, then ... */
2314                         clock = now;
2315                         clock_frame = clock >> 3;
2316                         if (ehci->clock_frame != clock_frame) {
2317                                 free_cached_itd_list(ehci);
2318                                 ehci->clock_frame = clock_frame;
2319                         }
2320                 } else {
2321                         now_uframe++;
2322                         now_uframe %= mod;
2323                 }
2324         }
2325 }