1 #include <linux/console.h>
2 #include <linux/errno.h>
3 #include <linux/pci_regs.h>
4 #include <linux/pci_ids.h>
5 #include <linux/usb/ch9.h>
6 #include <linux/usb/ehci_def.h>
7 #include <linux/delay.h>
9 #include <asm/pci-direct.h>
10 #include <asm/fixmap.h>
12 static struct ehci_caps __iomem *ehci_caps;
13 static struct ehci_regs __iomem *ehci_regs;
14 static struct ehci_dbg_port __iomem *ehci_debug;
15 static unsigned int dbgp_endpoint_out;
23 static struct ehci_dev ehci_dev;
25 #define USB_DEBUG_DEVNUM 127
27 #define DBGP_DATA_TOGGLE 0x8800
29 static inline u32 dbgp_pid_update(u32 x, u32 tok)
31 return ((x ^ DBGP_DATA_TOGGLE) & 0xffff00) | (tok & 0xff);
34 static inline u32 dbgp_len_update(u32 x, u32 len)
36 return (x & ~0x0f) | (len & 0x0f);
40 * USB Packet IDs (PIDs)
44 #define USB_PID_OUT 0xe1
45 #define USB_PID_IN 0x69
46 #define USB_PID_SOF 0xa5
47 #define USB_PID_SETUP 0x2d
49 #define USB_PID_ACK 0xd2
50 #define USB_PID_NAK 0x5a
51 #define USB_PID_STALL 0x1e
52 #define USB_PID_NYET 0x96
54 #define USB_PID_DATA0 0xc3
55 #define USB_PID_DATA1 0x4b
56 #define USB_PID_DATA2 0x87
57 #define USB_PID_MDATA 0x0f
59 #define USB_PID_PREAMBLE 0x3c
60 #define USB_PID_ERR 0x3c
61 #define USB_PID_SPLIT 0x78
62 #define USB_PID_PING 0xb4
63 #define USB_PID_UNDEF_0 0xf0
65 #define USB_PID_DATA_TOGGLE 0x88
66 #define DBGP_CLAIM (DBGP_OWNER | DBGP_ENABLED | DBGP_INUSE)
68 #define PCI_CAP_ID_EHCI_DEBUG 0xa
70 #define HUB_ROOT_RESET_TIME 50 /* times are in msec */
71 #define HUB_SHORT_RESET_TIME 10
72 #define HUB_LONG_RESET_TIME 200
73 #define HUB_RESET_TIMEOUT 500
75 #define DBGP_MAX_PACKET 8
77 static int dbgp_wait_until_complete(void)
83 ctrl = readl(&ehci_debug->control);
84 /* Stop when the transaction is finished */
93 * Now that we have observed the completed transaction,
96 writel(ctrl | DBGP_DONE, &ehci_debug->control);
97 return (ctrl & DBGP_ERROR) ? -DBGP_ERRCODE(ctrl) : DBGP_LEN(ctrl);
100 static void __init dbgp_mdelay(int ms)
105 for (i = 0; i < 1000; i++)
110 static void dbgp_breath(void)
112 /* Sleep to give the debug port a chance to breathe */
115 static int dbgp_wait_until_done(unsigned ctrl)
122 writel(ctrl | DBGP_GO, &ehci_debug->control);
123 ret = dbgp_wait_until_complete();
124 pids = readl(&ehci_debug->pids);
125 lpid = DBGP_PID_GET(pids);
131 * If the port is getting full or it has dropped data
132 * start pacing ourselves, not necessary but it's friendly.
134 if ((lpid == USB_PID_NAK) || (lpid == USB_PID_NYET))
137 /* If I get a NACK reissue the transmission */
138 if (lpid == USB_PID_NAK) {
146 static void dbgp_set_data(const void *buf, int size)
148 const unsigned char *bytes = buf;
153 for (i = 0; i < 4 && i < size; i++)
154 lo |= bytes[i] << (8*i);
155 for (; i < 8 && i < size; i++)
156 hi |= bytes[i] << (8*(i - 4));
157 writel(lo, &ehci_debug->data03);
158 writel(hi, &ehci_debug->data47);
161 static void __init dbgp_get_data(void *buf, int size)
163 unsigned char *bytes = buf;
167 lo = readl(&ehci_debug->data03);
168 hi = readl(&ehci_debug->data47);
169 for (i = 0; i < 4 && i < size; i++)
170 bytes[i] = (lo >> (8*i)) & 0xff;
171 for (; i < 8 && i < size; i++)
172 bytes[i] = (hi >> (8*(i - 4))) & 0xff;
175 static int dbgp_bulk_write(unsigned devnum, unsigned endpoint,
176 const char *bytes, int size)
178 u32 pids, addr, ctrl;
181 if (size > DBGP_MAX_PACKET)
184 addr = DBGP_EPADDR(devnum, endpoint);
186 pids = readl(&ehci_debug->pids);
187 pids = dbgp_pid_update(pids, USB_PID_OUT);
189 ctrl = readl(&ehci_debug->control);
190 ctrl = dbgp_len_update(ctrl, size);
194 dbgp_set_data(bytes, size);
195 writel(addr, &ehci_debug->address);
196 writel(pids, &ehci_debug->pids);
198 ret = dbgp_wait_until_done(ctrl);
205 static int __init dbgp_bulk_read(unsigned devnum, unsigned endpoint, void *data,
208 u32 pids, addr, ctrl;
211 if (size > DBGP_MAX_PACKET)
214 addr = DBGP_EPADDR(devnum, endpoint);
216 pids = readl(&ehci_debug->pids);
217 pids = dbgp_pid_update(pids, USB_PID_IN);
219 ctrl = readl(&ehci_debug->control);
220 ctrl = dbgp_len_update(ctrl, size);
224 writel(addr, &ehci_debug->address);
225 writel(pids, &ehci_debug->pids);
226 ret = dbgp_wait_until_done(ctrl);
232 dbgp_get_data(data, size);
236 static int __init dbgp_control_msg(unsigned devnum, int requesttype,
237 int request, int value, int index, void *data, int size)
239 u32 pids, addr, ctrl;
240 struct usb_ctrlrequest req;
244 read = (requesttype & USB_DIR_IN) != 0;
245 if (size > (read ? DBGP_MAX_PACKET:0))
248 /* Compute the control message */
249 req.bRequestType = requesttype;
250 req.bRequest = request;
251 req.wValue = cpu_to_le16(value);
252 req.wIndex = cpu_to_le16(index);
253 req.wLength = cpu_to_le16(size);
255 pids = DBGP_PID_SET(USB_PID_DATA0, USB_PID_SETUP);
256 addr = DBGP_EPADDR(devnum, 0);
258 ctrl = readl(&ehci_debug->control);
259 ctrl = dbgp_len_update(ctrl, sizeof(req));
263 /* Send the setup message */
264 dbgp_set_data(&req, sizeof(req));
265 writel(addr, &ehci_debug->address);
266 writel(pids, &ehci_debug->pids);
267 ret = dbgp_wait_until_done(ctrl);
271 /* Read the result */
272 return dbgp_bulk_read(devnum, 0, data, size);
276 /* Find a PCI capability */
277 static u32 __init find_cap(u32 num, u32 slot, u32 func, int cap)
282 if (!(read_pci_config_16(num, slot, func, PCI_STATUS) &
283 PCI_STATUS_CAP_LIST))
286 pos = read_pci_config_byte(num, slot, func, PCI_CAPABILITY_LIST);
287 for (bytes = 0; bytes < 48 && pos >= 0x40; bytes++) {
291 id = read_pci_config_byte(num, slot, func, pos+PCI_CAP_LIST_ID);
297 pos = read_pci_config_byte(num, slot, func,
298 pos+PCI_CAP_LIST_NEXT);
303 static u32 __init __find_dbgp(u32 bus, u32 slot, u32 func)
307 class = read_pci_config(bus, slot, func, PCI_CLASS_REVISION);
308 if ((class >> 8) != PCI_CLASS_SERIAL_USB_EHCI)
311 return find_cap(bus, slot, func, PCI_CAP_ID_EHCI_DEBUG);
314 static u32 __init find_dbgp(int ehci_num, u32 *rbus, u32 *rslot, u32 *rfunc)
318 for (bus = 0; bus < 256; bus++) {
319 for (slot = 0; slot < 32; slot++) {
320 for (func = 0; func < 8; func++) {
323 cap = __find_dbgp(bus, slot, func);
339 static int __init ehci_reset_port(int port)
342 u32 delay_time, delay;
345 /* Reset the usb debug port */
346 portsc = readl(&ehci_regs->port_status[port - 1]);
348 portsc |= PORT_RESET;
349 writel(portsc, &ehci_regs->port_status[port - 1]);
351 delay = HUB_ROOT_RESET_TIME;
352 for (delay_time = 0; delay_time < HUB_RESET_TIMEOUT;
353 delay_time += delay) {
356 portsc = readl(&ehci_regs->port_status[port - 1]);
357 if (portsc & PORT_RESET) {
358 /* force reset to complete */
360 writel(portsc & ~(PORT_RWC_BITS | PORT_RESET),
361 &ehci_regs->port_status[port - 1]);
363 portsc = readl(&ehci_regs->port_status[port-1]);
364 } while ((portsc & PORT_RESET) && (--loop > 0));
367 /* Device went away? */
368 if (!(portsc & PORT_CONNECT))
371 /* bomb out completely if something weird happend */
372 if ((portsc & PORT_CSC))
375 /* If we've finished resetting, then break out of the loop */
376 if (!(portsc & PORT_RESET) && (portsc & PORT_PE))
382 static int __init ehci_wait_for_port(int port)
387 for (reps = 0; reps < 3; reps++) {
389 status = readl(&ehci_regs->status);
390 if (status & STS_PCD) {
391 ret = ehci_reset_port(port);
400 # define dbgp_printk early_printk
402 static inline void dbgp_printk(const char *fmt, ...) { }
405 typedef void (*set_debug_port_t)(int port);
407 static void __init default_set_debug_port(int port)
411 static set_debug_port_t __initdata set_debug_port = default_set_debug_port;
413 static void __init nvidia_set_debug_port(int port)
416 dword = read_pci_config(ehci_dev.bus, ehci_dev.slot, ehci_dev.func,
418 dword &= ~(0x0f<<12);
419 dword |= ((port & 0x0f)<<12);
420 write_pci_config(ehci_dev.bus, ehci_dev.slot, ehci_dev.func, 0x74,
422 dbgp_printk("set debug port to %d\n", port);
425 static void __init detect_set_debug_port(void)
429 vendorid = read_pci_config(ehci_dev.bus, ehci_dev.slot, ehci_dev.func,
432 if ((vendorid & 0xffff) == 0x10de) {
433 dbgp_printk("using nvidia set_debug_port\n");
434 set_debug_port = nvidia_set_debug_port;
438 static int __init ehci_setup(void)
440 struct usb_debug_descriptor dbgp_desc;
441 u32 cmd, ctrl, status, portsc, hcs_params;
442 u32 debug_port, new_debug_port = 0, n_ports;
454 hcs_params = readl(&ehci_caps->hcs_params);
455 debug_port = HCS_DEBUG_PORT(hcs_params);
456 n_ports = HCS_N_PORTS(hcs_params);
458 dbgp_printk("debug_port: %d\n", debug_port);
459 dbgp_printk("n_ports: %d\n", n_ports);
461 for (i = 1; i <= n_ports; i++) {
462 portsc = readl(&ehci_regs->port_status[i-1]);
463 dbgp_printk("portstatus%d: %08x\n", i, portsc);
466 if (port_map_tried && (new_debug_port != debug_port)) {
468 set_debug_port(new_debug_port);
475 /* Reset the EHCI controller */
476 cmd = readl(&ehci_regs->command);
478 writel(cmd, &ehci_regs->command);
480 cmd = readl(&ehci_regs->command);
481 } while ((cmd & CMD_RESET) && (--loop > 0));
484 dbgp_printk("can not reset ehci\n");
487 dbgp_printk("ehci reset done\n");
489 /* Claim ownership, but do not enable yet */
490 ctrl = readl(&ehci_debug->control);
492 ctrl &= ~(DBGP_ENABLED | DBGP_INUSE);
493 writel(ctrl, &ehci_debug->control);
495 /* Start the ehci running */
496 cmd = readl(&ehci_regs->command);
497 cmd &= ~(CMD_LRESET | CMD_IAAD | CMD_PSE | CMD_ASE | CMD_RESET);
499 writel(cmd, &ehci_regs->command);
501 /* Ensure everything is routed to the EHCI */
502 writel(FLAG_CF, &ehci_regs->configured_flag);
504 /* Wait until the controller is no longer halted */
507 status = readl(&ehci_regs->status);
508 } while ((status & STS_HALT) && (--loop > 0));
511 dbgp_printk("ehci can be started\n");
514 dbgp_printk("ehci started\n");
516 /* Wait for a device to show up in the debug port */
517 ret = ehci_wait_for_port(debug_port);
519 dbgp_printk("No device found in debug port\n");
520 goto next_debug_port;
522 dbgp_printk("ehci wait for port done\n");
524 /* Enable the debug port */
525 ctrl = readl(&ehci_debug->control);
527 writel(ctrl, &ehci_debug->control);
528 ctrl = readl(&ehci_debug->control);
529 if ((ctrl & DBGP_CLAIM) != DBGP_CLAIM) {
530 dbgp_printk("No device in debug port\n");
531 writel(ctrl & ~DBGP_CLAIM, &ehci_debug->control);
534 dbgp_printk("debug ported enabled\n");
536 /* Completely transfer the debug device to the debug controller */
537 portsc = readl(&ehci_regs->port_status[debug_port - 1]);
539 writel(portsc, &ehci_regs->port_status[debug_port - 1]);
543 /* Find the debug device and make it device number 127 */
544 for (devnum = 0; devnum <= 127; devnum++) {
545 ret = dbgp_control_msg(devnum,
546 USB_DIR_IN | USB_TYPE_STANDARD | USB_RECIP_DEVICE,
547 USB_REQ_GET_DESCRIPTOR, (USB_DT_DEBUG << 8), 0,
548 &dbgp_desc, sizeof(dbgp_desc));
553 dbgp_printk("Could not find attached debug device\n");
557 dbgp_printk("Attached device is not a debug device\n");
560 dbgp_endpoint_out = dbgp_desc.bDebugOutEndpoint;
562 /* Move the device to 127 if it isn't already there */
563 if (devnum != USB_DEBUG_DEVNUM) {
564 ret = dbgp_control_msg(devnum,
565 USB_DIR_OUT | USB_TYPE_STANDARD | USB_RECIP_DEVICE,
566 USB_REQ_SET_ADDRESS, USB_DEBUG_DEVNUM, 0, NULL, 0);
568 dbgp_printk("Could not move attached device to %d\n",
572 devnum = USB_DEBUG_DEVNUM;
573 dbgp_printk("debug device renamed to 127\n");
576 /* Enable the debug interface */
577 ret = dbgp_control_msg(USB_DEBUG_DEVNUM,
578 USB_DIR_OUT | USB_TYPE_STANDARD | USB_RECIP_DEVICE,
579 USB_REQ_SET_FEATURE, USB_DEVICE_DEBUG_MODE, 0, NULL, 0);
581 dbgp_printk(" Could not enable the debug device\n");
584 dbgp_printk("debug interface enabled\n");
586 /* Perform a small write to get the even/odd data state in sync
588 ret = dbgp_bulk_write(USB_DEBUG_DEVNUM, dbgp_endpoint_out, " ", 1);
590 dbgp_printk("dbgp_bulk_write failed: %d\n", ret);
593 dbgp_printk("small write doned\n");
597 /* Things didn't work so remove my claim */
598 ctrl = readl(&ehci_debug->control);
599 ctrl &= ~(DBGP_CLAIM | DBGP_OUT);
600 writel(ctrl, &ehci_debug->control);
604 port_map_tried |= (1<<(debug_port - 1));
605 new_debug_port = ((debug_port-1+1)%n_ports) + 1;
606 if (port_map_tried != ((1<<n_ports) - 1)) {
607 set_debug_port(new_debug_port);
611 set_debug_port(new_debug_port);
618 int __init early_dbgp_init(char *s)
620 u32 debug_port, bar, offset;
621 u32 bus, slot, func, cap;
622 void __iomem *ehci_bar;
629 if (!early_pci_allowed())
634 dbgp_num = simple_strtoul(s, &e, 10);
635 dbgp_printk("dbgp_num: %d\n", dbgp_num);
637 cap = find_dbgp(dbgp_num, &bus, &slot, &func);
641 dbgp_printk("Found EHCI debug port on %02x:%02x.%1x\n", bus, slot,
644 debug_port = read_pci_config(bus, slot, func, cap);
645 bar = (debug_port >> 29) & 0x7;
646 bar = (bar * 4) + 0xc;
647 offset = (debug_port >> 16) & 0xfff;
648 dbgp_printk("bar: %02x offset: %03x\n", bar, offset);
649 if (bar != PCI_BASE_ADDRESS_0) {
650 dbgp_printk("only debug ports on bar 1 handled.\n");
655 bar_val = read_pci_config(bus, slot, func, PCI_BASE_ADDRESS_0);
656 dbgp_printk("bar_val: %02x offset: %03x\n", bar_val, offset);
657 if (bar_val & ~PCI_BASE_ADDRESS_MEM_MASK) {
658 dbgp_printk("only simple 32bit mmio bars supported\n");
663 /* double check if the mem space is enabled */
664 byte = read_pci_config_byte(bus, slot, func, 0x04);
667 write_pci_config_byte(bus, slot, func, 0x04, byte);
668 dbgp_printk("mmio for ehci enabled\n");
672 * FIXME I don't have the bar size so just guess PAGE_SIZE is more
673 * than enough. 1K is the biggest I have seen.
675 set_fixmap_nocache(FIX_DBGP_BASE, bar_val & PAGE_MASK);
676 ehci_bar = (void __iomem *)__fix_to_virt(FIX_DBGP_BASE);
677 ehci_bar += bar_val & ~PAGE_MASK;
678 dbgp_printk("ehci_bar: %p\n", ehci_bar);
680 ehci_caps = ehci_bar;
681 ehci_regs = ehci_bar + HC_LENGTH(readl(&ehci_caps->hc_capbase));
682 ehci_debug = ehci_bar + offset;
684 ehci_dev.slot = slot;
685 ehci_dev.func = func;
687 detect_set_debug_port();
691 dbgp_printk("ehci_setup failed\n");
700 static void early_dbgp_write(struct console *con, const char *str, u32 n)
708 if (chunk > DBGP_MAX_PACKET)
709 chunk = DBGP_MAX_PACKET;
710 ret = dbgp_bulk_write(USB_DEBUG_DEVNUM,
711 dbgp_endpoint_out, str, chunk);
717 struct console early_dbgp_console = {
719 .write = early_dbgp_write,
720 .flags = CON_PRINTBUFFER,