drivers/serial/8250_pci.c

   1 /*
   2  *  linux/drivers/char/8250_pci.c
   3  *
   4  *  Probe module for 8250/16550-type PCI serial ports.
   5  *
   6  *  Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o.
   7  *
   8  *  Copyright (C) 2001 Russell King, All Rights Reserved.
   9  *
  10  * This program is free software; you can redistribute it and/or modify
  11  * it under the terms of the GNU General Public License as published by
  12  * the Free Software Foundation; either version 2 of the License.
  13  */
  14 #include <linux/module.h>
  15 #include <linux/init.h>
  16 #include <linux/pci.h>
  17 #include <linux/string.h>
  18 #include <linux/kernel.h>
  19 #include <linux/slab.h>
  20 #include <linux/delay.h>
  21 #include <linux/tty.h>
  22 #include <linux/serial_core.h>
  23 #include <linux/8250_pci.h>
  24 #include <linux/bitops.h>
  25
  26 #include <asm/byteorder.h>
  27 #include <asm/io.h>
  28
  29 #include "8250.h"
  30
  31 #undef SERIAL_DEBUG_PCI
  32
  33 /*
  34  * init function returns:
  35  *  > 0 - number of ports
  36  *  = 0 - use board->num_ports
  37  *  < 0 - error
  38  */
  39 struct pci_serial_quirk {
  40         u32     vendor;
  41         u32     device;
  42         u32     subvendor;
  43         u32     subdevice;
  44         int     (*init)(struct pci_dev *dev);
  45         int     (*setup)(struct serial_private *, struct pciserial_board *,
  46                          struct uart_port *, int);
  47         void    (*exit)(struct pci_dev *dev);
  48 };
  49
  50 #define PCI_NUM_BAR_RESOURCES   6
  51
  52 struct serial_private {
  53         struct pci_dev          *dev;
  54         unsigned int            nr;
  55         void __iomem            *remapped_bar[PCI_NUM_BAR_RESOURCES];
  56         struct pci_serial_quirk *quirk;
  57         int                     line[0];
  58 };
  59
  60 static void moan_device(const char *str, struct pci_dev *dev)
  61 {
  62         printk(KERN_WARNING "%s: %s\n"
  63                KERN_WARNING "Please send the output of lspci -vv, this\n"
  64                KERN_WARNING "message (0x%04x,0x%04x,0x%04x,0x%04x), the\n"
  65                KERN_WARNING "manufacturer and name of serial board or\n"
  66                KERN_WARNING "modem board to rmk+serial@arm.linux.org.uk.\n",
  67                pci_name(dev), str, dev->vendor, dev->device,
  68                dev->subsystem_vendor, dev->subsystem_device);
  69 }
  70
  71 static int
  72 setup_port(struct serial_private *priv, struct uart_port *port,
  73            int bar, int offset, int regshift)
  74 {
  75         struct pci_dev *dev = priv->dev;
  76         unsigned long base, len;
  77
  78         if (bar >= PCI_NUM_BAR_RESOURCES)
  79                 return -EINVAL;
  80
  81         base = pci_resource_start(dev, bar);
  82
  83         if (pci_resource_flags(dev, bar) & IORESOURCE_MEM) {
  84                 len =  pci_resource_len(dev, bar);
  85
  86                 if (!priv->remapped_bar[bar])
  87                         priv->remapped_bar[bar] = ioremap_nocache(base, len);
  88                 if (!priv->remapped_bar[bar])
  89                         return -ENOMEM;
  90
  91                 port->iotype = UPIO_MEM;
  92                 port->iobase = 0;
  93                 port->mapbase = base + offset;
  94                 port->membase = priv->remapped_bar[bar] + offset;
  95                 port->regshift = regshift;
  96         } else {
  97                 port->iotype = UPIO_PORT;
  98                 port->iobase = base + offset;
  99                 port->mapbase = 0;
 100                 port->membase = NULL;
 101                 port->regshift = 0;
 102         }
 103         return 0;
 104 }
 105
 106 /*
 107  * ADDI-DATA GmbH communication cards <info@addi-data.com>
 108  */
 109 static int addidata_apci7800_setup(struct serial_private *priv,
 110                                 struct pciserial_board *board,
 111                                 struct uart_port *port, int idx)
 112 {
 113         unsigned int bar = 0, offset = board->first_offset;
 114         bar = FL_GET_BASE(board->flags);
 115
 116         if (idx < 2) {
 117                 offset += idx * board->uart_offset;
 118         } else if ((idx >= 2) && (idx < 4)) {
 119                 bar += 1;
 120                 offset += ((idx - 2) * board->uart_offset);
 121         } else if ((idx >= 4) && (idx < 6)) {
 122                 bar += 2;
 123                 offset += ((idx - 4) * board->uart_offset);
 124         } else if (idx >= 6) {
 125                 bar += 3;
 126                 offset += ((idx - 6) * board->uart_offset);
 127         }
 128
 129         return setup_port(priv, port, bar, offset, board->reg_shift);
 130 }
 131
 132 /*
 133  * AFAVLAB uses a different mixture of BARs and offsets
 134  * Not that ugly ;) -- HW
 135  */
 136 static int
 137 afavlab_setup(struct serial_private *priv, struct pciserial_board *board,
 138               struct uart_port *port, int idx)
 139 {
 140         unsigned int bar, offset = board->first_offset;
 141
 142         bar = FL_GET_BASE(board->flags);
 143         if (idx < 4)
 144                 bar += idx;
 145         else {
 146                 bar = 4;
 147                 offset += (idx - 4) * board->uart_offset;
 148         }
 149
 150         return setup_port(priv, port, bar, offset, board->reg_shift);
 151 }
 152
 153 /*
 154  * HP's Remote Management Console.  The Diva chip came in several
 155  * different versions.  N-class, L2000 and A500 have two Diva chips, each
 156  * with 3 UARTs (the third UART on the second chip is unused).  Superdome
 157  * and Keystone have one Diva chip with 3 UARTs.  Some later machines have
 158  * one Diva chip, but it has been expanded to 5 UARTs.
 159  */
 160 static int pci_hp_diva_init(struct pci_dev *dev)
 161 {
 162         int rc = 0;
 163
 164         switch (dev->subsystem_device) {
 165         case PCI_DEVICE_ID_HP_DIVA_TOSCA1:
 166         case PCI_DEVICE_ID_HP_DIVA_HALFDOME:
 167         case PCI_DEVICE_ID_HP_DIVA_KEYSTONE:
 168         case PCI_DEVICE_ID_HP_DIVA_EVEREST:
 169                 rc = 3;
 170                 break;
 171         case PCI_DEVICE_ID_HP_DIVA_TOSCA2:
 172                 rc = 2;
 173                 break;
 174         case PCI_DEVICE_ID_HP_DIVA_MAESTRO:
 175                 rc = 4;
 176                 break;
 177         case PCI_DEVICE_ID_HP_DIVA_POWERBAR:
 178         case PCI_DEVICE_ID_HP_DIVA_HURRICANE:
 179                 rc = 1;
 180                 break;
 181         }
 182
 183         return rc;
 184 }
 185
 186 /*
 187  * HP's Diva chip puts the 4th/5th serial port further out, and
 188  * some serial ports are supposed to be hidden on certain models.
 189  */
 190 static int
 191 pci_hp_diva_setup(struct serial_private *priv, struct pciserial_board *board,
 192               struct uart_port *port, int idx)
 193 {
 194         unsigned int offset = board->first_offset;
 195         unsigned int bar = FL_GET_BASE(board->flags);
 196
 197         switch (priv->dev->subsystem_device) {
 198         case PCI_DEVICE_ID_HP_DIVA_MAESTRO:
 199                 if (idx == 3)
 200                         idx++;
 201                 break;
 202         case PCI_DEVICE_ID_HP_DIVA_EVEREST:
 203                 if (idx > 0)
 204                         idx++;
 205                 if (idx > 2)
 206                         idx++;
 207                 break;
 208         }
 209         if (idx > 2)
 210                 offset = 0x18;
 211
 212         offset += idx * board->uart_offset;
 213
 214         return setup_port(priv, port, bar, offset, board->reg_shift);
 215 }
 216
 217 /*
 218  * Added for EKF Intel i960 serial boards
 219  */
 220 static int pci_inteli960ni_init(struct pci_dev *dev)
 221 {
 222         unsigned long oldval;
 223
 224         if (!(dev->subsystem_device & 0x1000))
 225                 return -ENODEV;
 226
 227         /* is firmware started? */
 228         pci_read_config_dword(dev, 0x44, (void *)&oldval);
 229         if (oldval == 0x00001000L) { /* RESET value */
 230                 printk(KERN_DEBUG "Local i960 firmware missing");
 231                 return -ENODEV;
 232         }
 233         return 0;
 234 }
 235
 236 /*
 237  * Some PCI serial cards using the PLX 9050 PCI interface chip require
 238  * that the card interrupt be explicitly enabled or disabled.  This
 239  * seems to be mainly needed on card using the PLX which also use I/O
 240  * mapped memory.
 241  */
 242 static int pci_plx9050_init(struct pci_dev *dev)
 243 {
 244         u8 irq_config;
 245         void __iomem *p;
 246
 247         if ((pci_resource_flags(dev, 0) & IORESOURCE_MEM) == 0) {
 248                 moan_device("no memory in bar 0", dev);
 249                 return 0;
 250         }
 251
 252         irq_config = 0x41;
 253         if (dev->vendor == PCI_VENDOR_ID_PANACOM ||
 254             dev->subsystem_vendor == PCI_SUBVENDOR_ID_EXSYS)
 255                 irq_config = 0x43;
 256
 257         if ((dev->vendor == PCI_VENDOR_ID_PLX) &&
 258             (dev->device == PCI_DEVICE_ID_PLX_ROMULUS))
 259                 /*
 260                  * As the megawolf cards have the int pins active
 261                  * high, and have 2 UART chips, both ints must be
 262                  * enabled on the 9050. Also, the UARTS are set in
 263                  * 16450 mode by default, so we have to enable the
 264                  * 16C950 'enhanced' mode so that we can use the
 265                  * deep FIFOs
 266                  */
 267                 irq_config = 0x5b;
 268         /*
 269          * enable/disable interrupts
 270          */
 271         p = ioremap_nocache(pci_resource_start(dev, 0), 0x80);
 272         if (p == NULL)
 273                 return -ENOMEM;
 274         writel(irq_config, p + 0x4c);
 275
 276         /*
 277          * Read the register back to ensure that it took effect.
 278          */
 279         readl(p + 0x4c);
 280         iounmap(p);
 281
 282         return 0;
 283 }
 284
 285 static void __devexit pci_plx9050_exit(struct pci_dev *dev)
 286 {
 287         u8 __iomem *p;
 288
 289         if ((pci_resource_flags(dev, 0) & IORESOURCE_MEM) == 0)
 290                 return;
 291
 292         /*
 293          * disable interrupts
 294          */
 295         p = ioremap_nocache(pci_resource_start(dev, 0), 0x80);
 296         if (p != NULL) {
 297                 writel(0, p + 0x4c);
 298
 299                 /*
 300                  * Read the register back to ensure that it took effect.
 301                  */
 302                 readl(p + 0x4c);
 303                 iounmap(p);
 304         }
 305 }
 306
 307 /* SBS Technologies Inc. PMC-OCTPRO and P-OCTAL cards */
 308 static int
 309 sbs_setup(struct serial_private *priv, struct pciserial_board *board,
 310                 struct uart_port *port, int idx)
 311 {
 312         unsigned int bar, offset = board->first_offset;
 313
 314         bar = 0;
 315
 316         if (idx < 4) {
 317                 /* first four channels map to 0, 0x100, 0x200, 0x300 */
 318                 offset += idx * board->uart_offset;
 319         } else if (idx < 8) {
 320                 /* last four channels map to 0x1000, 0x1100, 0x1200, 0x1300 */
 321                 offset += idx * board->uart_offset + 0xC00;
 322         } else /* we have only 8 ports on PMC-OCTALPRO */
 323                 return 1;
 324
 325         return setup_port(priv, port, bar, offset, board->reg_shift);
 326 }
 327
 328 /*
 329 * This does initialization for PMC OCTALPRO cards:
 330 * maps the device memory, resets the UARTs (needed, bc
 331 * if the module is removed and inserted again, the card
 332 * is in the sleep mode) and enables global interrupt.
 333 */
 334
 335 /* global control register offset for SBS PMC-OctalPro */
 336 #define OCT_REG_CR_OFF          0x500
 337
 338 static int sbs_init(struct pci_dev *dev)
 339 {
 340         u8 __iomem *p;
 341
 342         p = ioremap_nocache(pci_resource_start(dev, 0),
 343                                                 pci_resource_len(dev, 0));
 344
 345         if (p == NULL)
 346                 return -ENOMEM;
 347         /* Set bit-4 Control Register (UART RESET) in to reset the uarts */
 348         writeb(0x10, p + OCT_REG_CR_OFF);
 349         udelay(50);
 350         writeb(0x0, p + OCT_REG_CR_OFF);
 351
 352         /* Set bit-2 (INTENABLE) of Control Register */
 353         writeb(0x4, p + OCT_REG_CR_OFF);
 354         iounmap(p);
 355
 356         return 0;
 357 }
 358
 359 /*
 360  * Disables the global interrupt of PMC-OctalPro
 361  */
 362
 363 static void __devexit sbs_exit(struct pci_dev *dev)
 364 {
 365         u8 __iomem *p;
 366
 367         p = ioremap_nocache(pci_resource_start(dev, 0),
 368                                         pci_resource_len(dev, 0));
 369         /* FIXME: What if resource_len < OCT_REG_CR_OFF */
 370         if (p != NULL)
 371                 writeb(0, p + OCT_REG_CR_OFF);
 372         iounmap(p);
 373 }
 374
 375 /*
 376  * SIIG serial cards have an PCI interface chip which also controls
 377  * the UART clocking frequency. Each UART can be clocked independently
 378  * (except cards equiped with 4 UARTs) and initial clocking settings
 379  * are stored in the EEPROM chip. It can cause problems because this
 380  * version of serial driver doesn't support differently clocked UART's
 381  * on single PCI card. To prevent this, initialization functions set
 382  * high frequency clocking for all UART's on given card. It is safe (I
 383  * hope) because it doesn't touch EEPROM settings to prevent conflicts
 384  * with other OSes (like M$ DOS).
 385  *
 386  *  SIIG support added by Andrey Panin <pazke@donpac.ru>, 10/1999
 387  *
 388  * There is two family of SIIG serial cards with different PCI
 389  * interface chip and different configuration methods:
 390  *     - 10x cards have control registers in IO and/or memory space;
 391  *     - 20x cards have control registers in standard PCI configuration space.
 392  *
 393  * Note: all 10x cards have PCI device ids 0x10..
 394  *       all 20x cards have PCI device ids 0x20..
 395  *
 396  * There are also Quartet Serial cards which use Oxford Semiconductor
 397  * 16954 quad UART PCI chip clocked by 18.432 MHz quartz.
 398  *
 399  * Note: some SIIG cards are probed by the parport_serial object.
 400  */
 401
 402 #define PCI_DEVICE_ID_SIIG_1S_10x (PCI_DEVICE_ID_SIIG_1S_10x_550 & 0xfffc)
 403 #define PCI_DEVICE_ID_SIIG_2S_10x (PCI_DEVICE_ID_SIIG_2S_10x_550 & 0xfff8)
 404
 405 static int pci_siig10x_init(struct pci_dev *dev)
 406 {
 407         u16 data;
 408         void __iomem *p;
 409
 410         switch (dev->device & 0xfff8) {
 411         case PCI_DEVICE_ID_SIIG_1S_10x: /* 1S */
 412                 data = 0xffdf;
 413                 break;
 414         case PCI_DEVICE_ID_SIIG_2S_10x: /* 2S, 2S1P */
 415                 data = 0xf7ff;
 416                 break;
 417         default:                        /* 1S1P, 4S */
 418                 data = 0xfffb;
 419                 break;
 420         }
 421
 422         p = ioremap_nocache(pci_resource_start(dev, 0), 0x80);
 423         if (p == NULL)
 424                 return -ENOMEM;
 425
 426         writew(readw(p + 0x28) & data, p + 0x28);
 427         readw(p + 0x28);
 428         iounmap(p);
 429         return 0;
 430 }
 431
 432 #define PCI_DEVICE_ID_SIIG_2S_20x (PCI_DEVICE_ID_SIIG_2S_20x_550 & 0xfffc)
 433 #define PCI_DEVICE_ID_SIIG_2S1P_20x (PCI_DEVICE_ID_SIIG_2S1P_20x_550 & 0xfffc)
 434
 435 static int pci_siig20x_init(struct pci_dev *dev)
 436 {
 437         u8 data;
 438
 439         /* Change clock frequency for the first UART. */
 440         pci_read_config_byte(dev, 0x6f, &data);
 441         pci_write_config_byte(dev, 0x6f, data & 0xef);
 442
 443         /* If this card has 2 UART, we have to do the same with second UART. */
 444         if (((dev->device & 0xfffc) == PCI_DEVICE_ID_SIIG_2S_20x) ||
 445             ((dev->device & 0xfffc) == PCI_DEVICE_ID_SIIG_2S1P_20x)) {
 446                 pci_read_config_byte(dev, 0x73, &data);
 447                 pci_write_config_byte(dev, 0x73, data & 0xef);
 448         }
 449         return 0;
 450 }
 451
 452 static int pci_siig_init(struct pci_dev *dev)
 453 {
 454         unsigned int type = dev->device & 0xff00;
 455
 456         if (type == 0x1000)
 457                 return pci_siig10x_init(dev);
 458         else if (type == 0x2000)
 459                 return pci_siig20x_init(dev);
 460
 461         moan_device("Unknown SIIG card", dev);
 462         return -ENODEV;
 463 }
 464
 465 static int pci_siig_setup(struct serial_private *priv,
 466                           struct pciserial_board *board,
 467                           struct uart_port *port, int idx)
 468 {
 469         unsigned int bar = FL_GET_BASE(board->flags) + idx, offset = 0;
 470
 471         if (idx > 3) {
 472                 bar = 4;
 473                 offset = (idx - 4) * 8;
 474         }
 475
 476         return setup_port(priv, port, bar, offset, 0);
 477 }
 478
 479 /*
 480  * Timedia has an explosion of boards, and to avoid the PCI table from
 481  * growing *huge*, we use this function to collapse some 70 entries
 482  * in the PCI table into one, for sanity's and compactness's sake.
 483  */
 484 static const unsigned short timedia_single_port[] = {
 485         0x4025, 0x4027, 0x4028, 0x5025, 0x5027, 0
 486 };
 487
 488 static const unsigned short timedia_dual_port[] = {
 489         0x0002, 0x4036, 0x4037, 0x4038, 0x4078, 0x4079, 0x4085,
 490         0x4088, 0x4089, 0x5037, 0x5078, 0x5079, 0x5085, 0x6079,
 491         0x7079, 0x8079, 0x8137, 0x8138, 0x8237, 0x8238, 0x9079,
 492         0x9137, 0x9138, 0x9237, 0x9238, 0xA079, 0xB079, 0xC079,
 493         0xD079, 0
 494 };
 495
 496 static const unsigned short timedia_quad_port[] = {
 497         0x4055, 0x4056, 0x4095, 0x4096, 0x5056, 0x8156, 0x8157,
 498         0x8256, 0x8257, 0x9056, 0x9156, 0x9157, 0x9158, 0x9159,
 499         0x9256, 0x9257, 0xA056, 0xA157, 0xA158, 0xA159, 0xB056,
 500         0xB157, 0
 501 };
 502
 503 static const unsigned short timedia_eight_port[] = {
 504         0x4065, 0x4066, 0x5065, 0x5066, 0x8166, 0x9066, 0x9166,
 505         0x9167, 0x9168, 0xA066, 0xA167, 0xA168, 0
 506 };
 507
 508 static const struct timedia_struct {
 509         int num;
 510         const unsigned short *ids;
 511 } timedia_data[] = {
 512         { 1, timedia_single_port },
 513         { 2, timedia_dual_port },
 514         { 4, timedia_quad_port },
 515         { 8, timedia_eight_port }
 516 };
 517
 518 static int pci_timedia_init(struct pci_dev *dev)
 519 {
 520         const unsigned short *ids;
 521         int i, j;
 522
 523         for (i = 0; i < ARRAY_SIZE(timedia_data); i++) {
 524                 ids = timedia_data[i].ids;
 525                 for (j = 0; ids[j]; j++)
 526                         if (dev->subsystem_device == ids[j])
 527                                 return timedia_data[i].num;
 528         }
 529         return 0;
 530 }
 531
 532 /*
 533  * Timedia/SUNIX uses a mixture of BARs and offsets
 534  * Ugh, this is ugly as all hell --- TYT
 535  */
 536 static int
 537 pci_timedia_setup(struct serial_private *priv, struct pciserial_board *board,
 538                   struct uart_port *port, int idx)
 539 {
 540         unsigned int bar = 0, offset = board->first_offset;
 541
 542         switch (idx) {
 543         case 0:
 544                 bar = 0;
 545                 break;
 546         case 1:
 547                 offset = board->uart_offset;
 548                 bar = 0;
 549                 break;
 550         case 2:
 551                 bar = 1;
 552                 break;
 553         case 3:
 554                 offset = board->uart_offset;
 555                 /* FALLTHROUGH */
 556         case 4: /* BAR 2 */
 557         case 5: /* BAR 3 */
 558         case 6: /* BAR 4 */
 559         case 7: /* BAR 5 */
 560                 bar = idx - 2;
 561         }
 562
 563         return setup_port(priv, port, bar, offset, board->reg_shift);
 564 }
 565
 566 /*
 567  * Some Titan cards are also a little weird
 568  */
 569 static int
 570 titan_400l_800l_setup(struct serial_private *priv,
 571                       struct pciserial_board *board,
 572                       struct uart_port *port, int idx)
 573 {
 574         unsigned int bar, offset = board->first_offset;
 575
 576         switch (idx) {
 577         case 0:
 578                 bar = 1;
 579                 break;
 580         case 1:
 581                 bar = 2;
 582                 break;
 583         default:
 584                 bar = 4;
 585                 offset = (idx - 2) * board->uart_offset;
 586         }
 587
 588         return setup_port(priv, port, bar, offset, board->reg_shift);
 589 }
 590
 591 static int pci_xircom_init(struct pci_dev *dev)
 592 {
 593         msleep(100);
 594         return 0;
 595 }
 596
 597 static int pci_netmos_init(struct pci_dev *dev)
 598 {
 599         /* subdevice 0x00PS means <P> parallel, <S> serial */
 600         unsigned int num_serial = dev->subsystem_device & 0xf;
 601
 602         if (num_serial == 0)
 603                 return -ENODEV;
 604         return num_serial;
 605 }
 606
 607 /*
 608  * ITE support by Niels de Vos <niels.devos@wincor-nixdorf.com>
 609  *
 610  * These chips are available with optionally one parallel port and up to
 611  * two serial ports. Unfortunately they all have the same product id.
 612  *
 613  * Basic configuration is done over a region of 32 I/O ports. The base
 614  * ioport is called INTA or INTC, depending on docs/other drivers.
 615  *
 616  * The region of the 32 I/O ports is configured in POSIO0R...
 617  */
 618
 619 /* registers */
 620 #define ITE_887x_MISCR          0x9c
 621 #define ITE_887x_INTCBAR        0x78
 622 #define ITE_887x_UARTBAR        0x7c
 623 #define ITE_887x_PS0BAR         0x10
 624 #define ITE_887x_POSIO0         0x60
 625
 626 /* I/O space size */
 627 #define ITE_887x_IOSIZE         32
 628 /* I/O space size (bits 26-24; 8 bytes = 011b) */
 629 #define ITE_887x_POSIO_IOSIZE_8         (3 << 24)
 630 /* I/O space size (bits 26-24; 32 bytes = 101b) */
 631 #define ITE_887x_POSIO_IOSIZE_32        (5 << 24)
 632 /* Decoding speed (1 = slow, 2 = medium, 3 = fast) */
 633 #define ITE_887x_POSIO_SPEED            (3 << 29)
 634 /* enable IO_Space bit */
 635 #define ITE_887x_POSIO_ENABLE           (1 << 31)
 636
 637 static int pci_ite887x_init(struct pci_dev *dev)
 638 {
 639         /* inta_addr are the configuration addresses of the ITE */
 640         static const short inta_addr[] = { 0x2a0, 0x2c0, 0x220, 0x240, 0x1e0,
 641                                                         0x200, 0x280, 0 };
 642         int ret, i, type;
 643         struct resource *iobase = NULL;
 644         u32 miscr, uartbar, ioport;
 645
 646         /* search for the base-ioport */
 647         i = 0;
 648         while (inta_addr[i] && iobase == NULL) {
 649                 iobase = request_region(inta_addr[i], ITE_887x_IOSIZE,
 650                                                                 "ite887x");
 651                 if (iobase != NULL) {
 652                         /* write POSIO0R - speed | size | ioport */
 653                         pci_write_config_dword(dev, ITE_887x_POSIO0,
 654                                 ITE_887x_POSIO_ENABLE | ITE_887x_POSIO_SPEED |
 655                                 ITE_887x_POSIO_IOSIZE_32 | inta_addr[i]);
 656                         /* write INTCBAR - ioport */
 657                         pci_write_config_dword(dev, ITE_887x_INTCBAR,
 658                                                                 inta_addr[i]);
 659                         ret = inb(inta_addr[i]);
 660                         if (ret != 0xff) {
 661                                 /* ioport connected */
 662                                 break;
 663                         }
 664                         release_region(iobase->start, ITE_887x_IOSIZE);
 665                         iobase = NULL;
 666                 }
 667                 i++;
 668         }
 669
 670         if (!inta_addr[i]) {
 671                 printk(KERN_ERR "ite887x: could not find iobase\n");
 672                 return -ENODEV;
 673         }
 674
 675         /* start of undocumented type checking (see parport_pc.c) */
 676         type = inb(iobase->start + 0x18) & 0x0f;
 677
 678         switch (type) {
 679         case 0x2:       /* ITE8871 (1P) */
 680         case 0xa:       /* ITE8875 (1P) */
 681                 ret = 0;
 682                 break;
 683         case 0xe:       /* ITE8872 (2S1P) */
 684                 ret = 2;
 685                 break;
 686         case 0x6:       /* ITE8873 (1S) */
 687                 ret = 1;
 688                 break;
 689         case 0x8:       /* ITE8874 (2S) */
 690                 ret = 2;
 691                 break;
 692         default:
 693                 moan_device("Unknown ITE887x", dev);
 694                 ret = -ENODEV;
 695         }
 696
 697         /* configure all serial ports */
 698         for (i = 0; i < ret; i++) {
 699                 /* read the I/O port from the device */
 700                 pci_read_config_dword(dev, ITE_887x_PS0BAR + (0x4 * (i + 1)),
 701                                                                 &ioport);
 702                 ioport &= 0x0000FF00;   /* the actual base address */
 703                 pci_write_config_dword(dev, ITE_887x_POSIO0 + (0x4 * (i + 1)),
 704                         ITE_887x_POSIO_ENABLE | ITE_887x_POSIO_SPEED |
 705                         ITE_887x_POSIO_IOSIZE_8 | ioport);
 706
 707                 /* write the ioport to the UARTBAR */
 708                 pci_read_config_dword(dev, ITE_887x_UARTBAR, &uartbar);
 709                 uartbar &= ~(0xffff << (16 * i));       /* clear half the reg */
 710                 uartbar |= (ioport << (16 * i));        /* set the ioport */
 711                 pci_write_config_dword(dev, ITE_887x_UARTBAR, uartbar);
 712
 713                 /* get current config */
 714                 pci_read_config_dword(dev, ITE_887x_MISCR, &miscr);
 715                 /* disable interrupts (UARTx_Routing[3:0]) */
 716                 miscr &= ~(0xf << (12 - 4 * i));
 717                 /* activate the UART (UARTx_En) */
 718                 miscr |= 1 << (23 - i);
 719                 /* write new config with activated UART */
 720                 pci_write_config_dword(dev, ITE_887x_MISCR, miscr);
 721         }
 722
 723         if (ret <= 0) {
 724                 /* the device has no UARTs if we get here */
 725                 release_region(iobase->start, ITE_887x_IOSIZE);
 726         }
 727
 728         return ret;
 729 }
 730
 731 static void __devexit pci_ite887x_exit(struct pci_dev *dev)
 732 {
 733         u32 ioport;
 734         /* the ioport is bit 0-15 in POSIO0R */
 735         pci_read_config_dword(dev, ITE_887x_POSIO0, &ioport);
 736         ioport &= 0xffff;
 737         release_region(ioport, ITE_887x_IOSIZE);
 738 }
 739
 740 static int
 741 pci_default_setup(struct serial_private *priv, struct pciserial_board *board,
 742                   struct uart_port *port, int idx)
 743 {
 744         unsigned int bar, offset = board->first_offset, maxnr;
 745
 746         bar = FL_GET_BASE(board->flags);
 747         if (board->flags & FL_BASE_BARS)
 748                 bar += idx;
 749         else
 750                 offset += idx * board->uart_offset;
 751
 752         maxnr = (pci_resource_len(priv->dev, bar) - board->first_offset) >>
 753                 (board->reg_shift + 3);
 754
 755         if (board->flags & FL_REGION_SZ_CAP && idx >= maxnr)
 756                 return 1;
 757
 758         return setup_port(priv, port, bar, offset, board->reg_shift);
 759 }
 760
 761 /* This should be in linux/pci_ids.h */
 762 #define PCI_VENDOR_ID_SBSMODULARIO      0x124B
 763 #define PCI_SUBVENDOR_ID_SBSMODULARIO   0x124B
 764 #define PCI_DEVICE_ID_OCTPRO            0x0001
 765 #define PCI_SUBDEVICE_ID_OCTPRO232      0x0108
 766 #define PCI_SUBDEVICE_ID_OCTPRO422      0x0208
 767 #define PCI_SUBDEVICE_ID_POCTAL232      0x0308
 768 #define PCI_SUBDEVICE_ID_POCTAL422      0x0408
 769
 770 /* Unknown vendors/cards - this should not be in linux/pci_ids.h */
 771 #define PCI_SUBDEVICE_ID_UNKNOWN_0x1584 0x1584
 772
 773 /*
 774  * Master list of serial port init/setup/exit quirks.
 775  * This does not describe the general nature of the port.
 776  * (ie, baud base, number and location of ports, etc)
 777  *
 778  * This list is ordered alphabetically by vendor then device.
 779  * Specific entries must come before more generic entries.
 780  */
 781 static struct pci_serial_quirk pci_serial_quirks[] __refdata = {
 782         /*
 783         * ADDI-DATA GmbH communication cards <info@addi-data.com>
 784         */
 785         {
 786                 .vendor         = PCI_VENDOR_ID_ADDIDATA_OLD,
 787                 .device         = PCI_DEVICE_ID_ADDIDATA_APCI7800,
 788                 .subvendor      = PCI_ANY_ID,
 789                 .subdevice      = PCI_ANY_ID,
 790                 .setup          = addidata_apci7800_setup,
 791         },
 792         /*
 793          * AFAVLAB cards - these may be called via parport_serial
 794          *  It is not clear whether this applies to all products.
 795          */
 796         {
 797                 .vendor         = PCI_VENDOR_ID_AFAVLAB,
 798                 .device         = PCI_ANY_ID,
 799                 .subvendor      = PCI_ANY_ID,
 800                 .subdevice      = PCI_ANY_ID,
 801                 .setup          = afavlab_setup,
 802         },
 803         /*
 804          * HP Diva
 805          */
 806         {
 807                 .vendor         = PCI_VENDOR_ID_HP,
 808                 .device         = PCI_DEVICE_ID_HP_DIVA,
 809                 .subvendor      = PCI_ANY_ID,
 810                 .subdevice      = PCI_ANY_ID,
 811                 .init           = pci_hp_diva_init,
 812                 .setup          = pci_hp_diva_setup,
 813         },
 814         /*
 815          * Intel
 816          */
 817         {
 818                 .vendor         = PCI_VENDOR_ID_INTEL,
 819                 .device         = PCI_DEVICE_ID_INTEL_80960_RP,
 820                 .subvendor      = 0xe4bf,
 821                 .subdevice      = PCI_ANY_ID,
 822                 .init           = pci_inteli960ni_init,
 823                 .setup          = pci_default_setup,
 824         },
 825         /*
 826          * ITE
 827          */
 828         {
 829                 .vendor         = PCI_VENDOR_ID_ITE,
 830                 .device         = PCI_DEVICE_ID_ITE_8872,
 831                 .subvendor      = PCI_ANY_ID,
 832                 .subdevice      = PCI_ANY_ID,
 833                 .init           = pci_ite887x_init,
 834                 .setup          = pci_default_setup,
 835                 .exit           = __devexit_p(pci_ite887x_exit),
 836         },
 837         /*
 838          * Panacom
 839          */
 840         {
 841                 .vendor         = PCI_VENDOR_ID_PANACOM,
 842                 .device         = PCI_DEVICE_ID_PANACOM_QUADMODEM,
 843                 .subvendor      = PCI_ANY_ID,
 844                 .subdevice      = PCI_ANY_ID,
 845                 .init           = pci_plx9050_init,
 846                 .setup          = pci_default_setup,
 847                 .exit           = __devexit_p(pci_plx9050_exit),
 848         },
 849         {
 850                 .vendor         = PCI_VENDOR_ID_PANACOM,
 851                 .device         = PCI_DEVICE_ID_PANACOM_DUALMODEM,
 852                 .subvendor      = PCI_ANY_ID,
 853                 .subdevice      = PCI_ANY_ID,
 854                 .init           = pci_plx9050_init,
 855                 .setup          = pci_default_setup,
 856                 .exit           = __devexit_p(pci_plx9050_exit),
 857         },
 858         /*
 859          * PLX
 860          */
 861         {
 862                 .vendor         = PCI_VENDOR_ID_PLX,
 863                 .device         = PCI_DEVICE_ID_PLX_9030,
 864                 .subvendor      = PCI_SUBVENDOR_ID_PERLE,
 865                 .subdevice      = PCI_ANY_ID,
 866                 .setup          = pci_default_setup,
 867         },
 868         {
 869                 .vendor         = PCI_VENDOR_ID_PLX,
 870                 .device         = PCI_DEVICE_ID_PLX_9050,
 871                 .subvendor      = PCI_SUBVENDOR_ID_EXSYS,
 872                 .subdevice      = PCI_SUBDEVICE_ID_EXSYS_4055,
 873                 .init           = pci_plx9050_init,
 874                 .setup          = pci_default_setup,
 875                 .exit           = __devexit_p(pci_plx9050_exit),
 876         },
 877         {
 878                 .vendor         = PCI_VENDOR_ID_PLX,
 879                 .device         = PCI_DEVICE_ID_PLX_9050,
 880                 .subvendor      = PCI_SUBVENDOR_ID_KEYSPAN,
 881                 .subdevice      = PCI_SUBDEVICE_ID_KEYSPAN_SX2,
 882                 .init           = pci_plx9050_init,
 883                 .setup          = pci_default_setup,
 884                 .exit           = __devexit_p(pci_plx9050_exit),
 885         },
 886         {
 887                 .vendor         = PCI_VENDOR_ID_PLX,
 888                 .device         = PCI_DEVICE_ID_PLX_9050,
 889                 .subvendor      = PCI_VENDOR_ID_PLX,
 890                 .subdevice      = PCI_SUBDEVICE_ID_UNKNOWN_0x1584,
 891                 .init           = pci_plx9050_init,
 892                 .setup          = pci_default_setup,
 893                 .exit           = __devexit_p(pci_plx9050_exit),
 894         },
 895         {
 896                 .vendor         = PCI_VENDOR_ID_PLX,
 897                 .device         = PCI_DEVICE_ID_PLX_ROMULUS,
 898                 .subvendor      = PCI_VENDOR_ID_PLX,
 899                 .subdevice      = PCI_DEVICE_ID_PLX_ROMULUS,
 900                 .init           = pci_plx9050_init,
 901                 .setup          = pci_default_setup,
 902                 .exit           = __devexit_p(pci_plx9050_exit),
 903         },
 904         /*
 905          * SBS Technologies, Inc., PMC-OCTALPRO 232
 906          */
 907         {
 908                 .vendor         = PCI_VENDOR_ID_SBSMODULARIO,
 909                 .device         = PCI_DEVICE_ID_OCTPRO,
 910                 .subvendor      = PCI_SUBVENDOR_ID_SBSMODULARIO,
 911                 .subdevice      = PCI_SUBDEVICE_ID_OCTPRO232,
 912                 .init           = sbs_init,
 913                 .setup          = sbs_setup,
 914                 .exit           = __devexit_p(sbs_exit),
 915         },
 916         /*
 917          * SBS Technologies, Inc., PMC-OCTALPRO 422
 918          */
 919         {
 920                 .vendor         = PCI_VENDOR_ID_SBSMODULARIO,
 921                 .device         = PCI_DEVICE_ID_OCTPRO,
 922                 .subvendor      = PCI_SUBVENDOR_ID_SBSMODULARIO,
 923                 .subdevice      = PCI_SUBDEVICE_ID_OCTPRO422,
 924                 .init           = sbs_init,
 925                 .setup          = sbs_setup,
 926                 .exit           = __devexit_p(sbs_exit),
 927         },
 928         /*
 929          * SBS Technologies, Inc., P-Octal 232
 930          */
 931         {
 932                 .vendor         = PCI_VENDOR_ID_SBSMODULARIO,
 933                 .device         = PCI_DEVICE_ID_OCTPRO,
 934                 .subvendor      = PCI_SUBVENDOR_ID_SBSMODULARIO,
 935                 .subdevice      = PCI_SUBDEVICE_ID_POCTAL232,
 936                 .init           = sbs_init,
 937                 .setup          = sbs_setup,
 938                 .exit           = __devexit_p(sbs_exit),
 939         },
 940         /*
 941          * SBS Technologies, Inc., P-Octal 422
 942          */
 943         {
 944                 .vendor         = PCI_VENDOR_ID_SBSMODULARIO,
 945                 .device         = PCI_DEVICE_ID_OCTPRO,
 946                 .subvendor      = PCI_SUBVENDOR_ID_SBSMODULARIO,
 947                 .subdevice      = PCI_SUBDEVICE_ID_POCTAL422,
 948                 .init           = sbs_init,
 949                 .setup          = sbs_setup,
 950                 .exit           = __devexit_p(sbs_exit),
 951         },
 952         /*
 953          * SIIG cards - these may be called via parport_serial
 954          */
 955         {
 956                 .vendor         = PCI_VENDOR_ID_SIIG,
 957                 .device         = PCI_ANY_ID,
 958                 .subvendor      = PCI_ANY_ID,
 959                 .subdevice      = PCI_ANY_ID,
 960                 .init           = pci_siig_init,
 961                 .setup          = pci_siig_setup,
 962         },
 963         /*
 964          * Titan cards
 965          */
 966         {
 967                 .vendor         = PCI_VENDOR_ID_TITAN,
 968                 .device         = PCI_DEVICE_ID_TITAN_400L,
 969                 .subvendor      = PCI_ANY_ID,
 970                 .subdevice      = PCI_ANY_ID,
 971                 .setup          = titan_400l_800l_setup,
 972         },
 973         {
 974                 .vendor         = PCI_VENDOR_ID_TITAN,
 975                 .device         = PCI_DEVICE_ID_TITAN_800L,
 976                 .subvendor      = PCI_ANY_ID,
 977                 .subdevice      = PCI_ANY_ID,
 978                 .setup          = titan_400l_800l_setup,
 979         },
 980         /*
 981          * Timedia cards
 982          */
 983         {
 984                 .vendor         = PCI_VENDOR_ID_TIMEDIA,
 985                 .device         = PCI_DEVICE_ID_TIMEDIA_1889,
 986                 .subvendor      = PCI_VENDOR_ID_TIMEDIA,
 987                 .subdevice      = PCI_ANY_ID,
 988                 .init           = pci_timedia_init,
 989                 .setup          = pci_timedia_setup,
 990         },
 991         {
 992                 .vendor         = PCI_VENDOR_ID_TIMEDIA,
 993                 .device         = PCI_ANY_ID,
 994                 .subvendor      = PCI_ANY_ID,
 995                 .subdevice      = PCI_ANY_ID,
 996                 .setup          = pci_timedia_setup,
 997         },
 998         /*
 999          * Xircom cards
1000          */
1001         {
1002                 .vendor         = PCI_VENDOR_ID_XIRCOM,
1003                 .device         = PCI_DEVICE_ID_XIRCOM_X3201_MDM,
1004                 .subvendor      = PCI_ANY_ID,
1005                 .subdevice      = PCI_ANY_ID,
1006                 .init           = pci_xircom_init,
1007                 .setup          = pci_default_setup,
1008         },
1009         /*
1010          * Netmos cards - these may be called via parport_serial
1011          */
1012         {
1013                 .vendor         = PCI_VENDOR_ID_NETMOS,
1014                 .device         = PCI_ANY_ID,
1015                 .subvendor      = PCI_ANY_ID,
1016                 .subdevice      = PCI_ANY_ID,
1017                 .init           = pci_netmos_init,
1018                 .setup          = pci_default_setup,
1019         },
1020         /*
1021          * Default "match everything" terminator entry
1022          */
1023         {
1024                 .vendor         = PCI_ANY_ID,
1025                 .device         = PCI_ANY_ID,
1026                 .subvendor      = PCI_ANY_ID,
1027                 .subdevice      = PCI_ANY_ID,
1028                 .setup          = pci_default_setup,
1029         }
1030 };
1031
1032 static inline int quirk_id_matches(u32 quirk_id, u32 dev_id)
1033 {
1034         return quirk_id == PCI_ANY_ID || quirk_id == dev_id;
1035 }
1036
1037 static struct pci_serial_quirk *find_quirk(struct pci_dev *dev)
1038 {
1039         struct pci_serial_quirk *quirk;
1040
1041         for (quirk = pci_serial_quirks; ; quirk++)
1042                 if (quirk_id_matches(quirk->vendor, dev->vendor) &&
1043                     quirk_id_matches(quirk->device, dev->device) &&
1044                     quirk_id_matches(quirk->subvendor, dev->subsystem_vendor) &&
1045                     quirk_id_matches(quirk->subdevice, dev->subsystem_device))
1046                         break;
1047         return quirk;
1048 }
1049
1050 static inline int get_pci_irq(struct pci_dev *dev,
1051                                 struct pciserial_board *board)
1052 {
1053         if (board->flags & FL_NOIRQ)
1054                 return 0;
1055         else
1056                 return dev->irq;
1057 }
1058
1059 /*
1060  * This is the configuration table for all of the PCI serial boards
1061  * which we support.  It is directly indexed by the pci_board_num_t enum
1062  * value, which is encoded in the pci_device_id PCI probe table's
1063  * driver_data member.
1064  *
1065  * The makeup of these names are:
1066  *  pbn_bn{_bt}_n_baud{_offsetinhex}
1067  *
1068  *  bn          = PCI BAR number
1069  *  bt          = Index using PCI BARs
1070  *  n           = number of serial ports
1071  *  baud        = baud rate
1072  *  offsetinhex = offset for each sequential port (in hex)
1073  *
1074  * This table is sorted by (in order): bn, bt, baud, offsetindex, n.
1075  *
1076  * Please note: in theory if n = 1, _bt infix should make no difference.
1077  * ie, pbn_b0_1_115200 is the same as pbn_b0_bt_1_115200
1078  */
1079 enum pci_board_num_t {
1080         pbn_default = 0,
1081
1082         pbn_b0_1_115200,
1083         pbn_b0_2_115200,
1084         pbn_b0_4_115200,
1085         pbn_b0_5_115200,
1086         pbn_b0_8_115200,
1087
1088         pbn_b0_1_921600,
1089         pbn_b0_2_921600,
1090         pbn_b0_4_921600,
1091
1092         pbn_b0_2_1130000,
1093
1094         pbn_b0_4_1152000,
1095
1096         pbn_b0_2_1843200,
1097         pbn_b0_4_1843200,
1098
1099         pbn_b0_2_1843200_200,
1100         pbn_b0_4_1843200_200,
1101         pbn_b0_8_1843200_200,
1102
1103         pbn_b0_bt_1_115200,
1104         pbn_b0_bt_2_115200,
1105         pbn_b0_bt_8_115200,
1106
1107         pbn_b0_bt_1_460800,
1108         pbn_b0_bt_2_460800,
1109         pbn_b0_bt_4_460800,
1110
1111         pbn_b0_bt_1_921600,
1112         pbn_b0_bt_2_921600,
1113         pbn_b0_bt_4_921600,
1114         pbn_b0_bt_8_921600,
1115
1116         pbn_b1_1_115200,
1117         pbn_b1_2_115200,
1118         pbn_b1_4_115200,
1119         pbn_b1_8_115200,
1120
1121         pbn_b1_1_921600,
1122         pbn_b1_2_921600,
1123         pbn_b1_4_921600,
1124         pbn_b1_8_921600,
1125
1126         pbn_b1_2_1250000,
1127
1128         pbn_b1_bt_1_115200,
1129         pbn_b1_bt_2_921600,
1130
1131         pbn_b1_1_1382400,
1132         pbn_b1_2_1382400,
1133         pbn_b1_4_1382400,
1134         pbn_b1_8_1382400,
1135
1136         pbn_b2_1_115200,
1137         pbn_b2_2_115200,
1138         pbn_b2_4_115200,
1139         pbn_b2_8_115200,
1140
1141         pbn_b2_1_460800,
1142         pbn_b2_4_460800,
1143         pbn_b2_8_460800,
1144         pbn_b2_16_460800,
1145
1146         pbn_b2_1_921600,
1147         pbn_b2_4_921600,
1148         pbn_b2_8_921600,
1149
1150         pbn_b2_bt_1_115200,
1151         pbn_b2_bt_2_115200,
1152         pbn_b2_bt_4_115200,
1153
1154         pbn_b2_bt_2_921600,
1155         pbn_b2_bt_4_921600,
1156
1157         pbn_b3_2_115200,
1158         pbn_b3_4_115200,
1159         pbn_b3_8_115200,
1160
1161         /*
1162          * Board-specific versions.
1163          */
1164         pbn_panacom,
1165         pbn_panacom2,
1166         pbn_panacom4,
1167         pbn_exsys_4055,
1168         pbn_plx_romulus,
1169         pbn_oxsemi,
1170         pbn_intel_i960,
1171         pbn_sgi_ioc3,
1172         pbn_computone_4,
1173         pbn_computone_6,
1174         pbn_computone_8,
1175         pbn_sbsxrsio,
1176         pbn_exar_XR17C152,
1177         pbn_exar_XR17C154,
1178         pbn_exar_XR17C158,
1179         pbn_pasemi_1682M,
1180 };
1181
1182 /*
1183  * uart_offset - the space between channels
1184  * reg_shift   - describes how the UART registers are mapped
1185  *               to PCI memory by the card.
1186  * For example IER register on SBS, Inc. PMC-OctPro is located at
1187  * offset 0x10 from the UART base, while UART_IER is defined as 1
1188  * in include/linux/serial_reg.h,
1189  * see first lines of serial_in() and serial_out() in 8250.c
1190 */
1191
1192 static struct pciserial_board pci_boards[] __devinitdata = {
1193         [pbn_default] = {
1194                 .flags          = FL_BASE0,
1195                 .num_ports      = 1,
1196                 .base_baud      = 115200,
1197                 .uart_offset    = 8,
1198         },
1199         [pbn_b0_1_115200] = {
1200                 .flags          = FL_BASE0,
1201                 .num_ports      = 1,
1202                 .base_baud      = 115200,
1203                 .uart_offset    = 8,
1204         },
1205         [pbn_b0_2_115200] = {
1206                 .flags          = FL_BASE0,
1207                 .num_ports      = 2,
1208                 .base_baud      = 115200,
1209                 .uart_offset    = 8,
1210         },
1211         [pbn_b0_4_115200] = {
1212                 .flags          = FL_BASE0,
1213                 .num_ports      = 4,
1214                 .base_baud      = 115200,
1215                 .uart_offset    = 8,
1216         },
1217         [pbn_b0_5_115200] = {
1218                 .flags          = FL_BASE0,
1219                 .num_ports      = 5,
1220                 .base_baud      = 115200,
1221                 .uart_offset    = 8,
1222         },
1223         [pbn_b0_8_115200] = {
1224                 .flags          = FL_BASE0,
1225                 .num_ports      = 8,
1226                 .base_baud      = 115200,
1227                 .uart_offset    = 8,
1228         },
1229         [pbn_b0_1_921600] = {
1230                 .flags          = FL_BASE0,
1231                 .num_ports      = 1,
1232                 .base_baud      = 921600,
1233                 .uart_offset    = 8,
1234         },
1235         [pbn_b0_2_921600] = {
1236                 .flags          = FL_BASE0,
1237                 .num_ports      = 2,
1238                 .base_baud      = 921600,
1239                 .uart_offset    = 8,
1240         },
1241         [pbn_b0_4_921600] = {
1242                 .flags          = FL_BASE0,
1243                 .num_ports      = 4,
1244                 .base_baud      = 921600,
1245                 .uart_offset    = 8,
1246         },
1247
1248         [pbn_b0_2_1130000] = {
1249                 .flags          = FL_BASE0,
1250                 .num_ports      = 2,
1251                 .base_baud      = 1130000,
1252                 .uart_offset    = 8,
1253         },
1254
1255         [pbn_b0_4_1152000] = {
1256                 .flags          = FL_BASE0,
1257                 .num_ports      = 4,
1258                 .base_baud      = 1152000,
1259                 .uart_offset    = 8,
1260         },
1261
1262         [pbn_b0_2_1843200] = {
1263                 .flags          = FL_BASE0,
1264                 .num_ports      = 2,
1265                 .base_baud      = 1843200,
1266                 .uart_offset    = 8,
1267         },
1268         [pbn_b0_4_1843200] = {
1269                 .flags          = FL_BASE0,
1270                 .num_ports      = 4,
1271                 .base_baud      = 1843200,
1272                 .uart_offset    = 8,
1273         },
1274
1275         [pbn_b0_2_1843200_200] = {
1276                 .flags          = FL_BASE0,
1277                 .num_ports      = 2,
1278                 .base_baud      = 1843200,
1279                 .uart_offset    = 0x200,
1280         },
1281         [pbn_b0_4_1843200_200] = {
1282                 .flags          = FL_BASE0,
1283                 .num_ports      = 4,
1284                 .base_baud      = 1843200,
1285                 .uart_offset    = 0x200,
1286         },
1287         [pbn_b0_8_1843200_200] = {
1288                 .flags          = FL_BASE0,
1289                 .num_ports      = 8,
1290                 .base_baud      = 1843200,
1291                 .uart_offset    = 0x200,
1292         },
1293
1294         [pbn_b0_bt_1_115200] = {
1295                 .flags          = FL_BASE0|FL_BASE_BARS,
1296                 .num_ports      = 1,
1297                 .base_baud      = 115200,
1298                 .uart_offset    = 8,
1299         },
1300         [pbn_b0_bt_2_115200] = {
1301                 .flags          = FL_BASE0|FL_BASE_BARS,
1302                 .num_ports      = 2,
1303                 .base_baud      = 115200,
1304                 .uart_offset    = 8,
1305         },
1306         [pbn_b0_bt_8_115200] = {
1307                 .flags          = FL_BASE0|FL_BASE_BARS,
1308                 .num_ports      = 8,
1309                 .base_baud      = 115200,
1310                 .uart_offset    = 8,
1311         },
1312
1313         [pbn_b0_bt_1_460800] = {
1314                 .flags          = FL_BASE0|FL_BASE_BARS,
1315                 .num_ports      = 1,
1316                 .base_baud      = 460800,
1317                 .uart_offset    = 8,
1318         },
1319         [pbn_b0_bt_2_460800] = {
1320                 .flags          = FL_BASE0|FL_BASE_BARS,
1321                 .num_ports      = 2,
1322                 .base_baud      = 460800,
1323                 .uart_offset    = 8,
1324         },
1325         [pbn_b0_bt_4_460800] = {
1326                 .flags          = FL_BASE0|FL_BASE_BARS,
1327                 .num_ports      = 4,
1328                 .base_baud      = 460800,
1329                 .uart_offset    = 8,
1330         },
1331
1332         [pbn_b0_bt_1_921600] = {
1333                 .flags          = FL_BASE0|FL_BASE_BARS,
1334                 .num_ports      = 1,
1335                 .base_baud      = 921600,
1336                 .uart_offset    = 8,
1337         },
1338         [pbn_b0_bt_2_921600] = {
1339                 .flags          = FL_BASE0|FL_BASE_BARS,
1340                 .num_ports      = 2,
1341                 .base_baud      = 921600,
1342                 .uart_offset    = 8,
1343         },
1344         [pbn_b0_bt_4_921600] = {
1345                 .flags          = FL_BASE0|FL_BASE_BARS,
1346                 .num_ports      = 4,
1347                 .base_baud      = 921600,
1348                 .uart_offset    = 8,
1349         },
1350         [pbn_b0_bt_8_921600] = {
1351                 .flags          = FL_BASE0|FL_BASE_BARS,
1352                 .num_ports      = 8,
1353                 .base_baud      = 921600,
1354                 .uart_offset    = 8,
1355         },
1356
1357         [pbn_b1_1_115200] = {
1358                 .flags          = FL_BASE1,
1359                 .num_ports      = 1,
1360                 .base_baud      = 115200,
1361                 .uart_offset    = 8,
1362         },
1363         [pbn_b1_2_115200] = {
1364                 .flags          = FL_BASE1,
1365                 .num_ports      = 2,
1366                 .base_baud      = 115200,
1367                 .uart_offset    = 8,
1368         },
1369         [pbn_b1_4_115200] = {
1370                 .flags          = FL_BASE1,
1371                 .num_ports      = 4,
1372                 .base_baud      = 115200,
1373                 .uart_offset    = 8,
1374         },
1375         [pbn_b1_8_115200] = {
1376                 .flags          = FL_BASE1,
1377                 .num_ports      = 8,
1378                 .base_baud      = 115200,
1379                 .uart_offset    = 8,
1380         },
1381
1382         [pbn_b1_1_921600] = {
1383                 .flags          = FL_BASE1,
1384                 .num_ports      = 1,
1385                 .base_baud      = 921600,
1386                 .uart_offset    = 8,
1387         },
1388         [pbn_b1_2_921600] = {
1389                 .flags          = FL_BASE1,
1390                 .num_ports      = 2,
1391                 .base_baud      = 921600,
1392                 .uart_offset    = 8,
1393         },
1394         [pbn_b1_4_921600] = {
1395                 .flags          = FL_BASE1,
1396                 .num_ports      = 4,
1397                 .base_baud      = 921600,
1398                 .uart_offset    = 8,
1399         },
1400         [pbn_b1_8_921600] = {
1401                 .flags          = FL_BASE1,
1402                 .num_ports      = 8,
1403                 .base_baud      = 921600,
1404                 .uart_offset    = 8,
1405         },
1406         [pbn_b1_2_1250000] = {
1407                 .flags          = FL_BASE1,
1408                 .num_ports      = 2,
1409                 .base_baud      = 1250000,
1410                 .uart_offset    = 8,
1411         },
1412
1413         [pbn_b1_bt_1_115200] = {
1414                 .flags          = FL_BASE1|FL_BASE_BARS,
1415                 .num_ports      = 1,
1416                 .base_baud      = 115200,
1417                 .uart_offset    = 8,
1418         },
1419
1420         [pbn_b1_bt_2_921600] = {
1421                 .flags          = FL_BASE1|FL_BASE_BARS,
1422                 .num_ports      = 2,
1423                 .base_baud      = 921600,
1424                 .uart_offset    = 8,
1425         },
1426
1427         [pbn_b1_1_1382400] = {
1428                 .flags          = FL_BASE1,
1429                 .num_ports      = 1,
1430                 .base_baud      = 1382400,
1431                 .uart_offset    = 8,
1432         },
1433         [pbn_b1_2_1382400] = {
1434                 .flags          = FL_BASE1,
1435                 .num_ports      = 2,
1436                 .base_baud      = 1382400,
1437                 .uart_offset    = 8,
1438         },
1439         [pbn_b1_4_1382400] = {
1440                 .flags          = FL_BASE1,
1441                 .num_ports      = 4,
1442                 .base_baud      = 1382400,
1443                 .uart_offset    = 8,
1444         },
1445         [pbn_b1_8_1382400] = {
1446                 .flags          = FL_BASE1,
1447                 .num_ports      = 8,
1448                 .base_baud      = 1382400,
1449                 .uart_offset    = 8,
1450         },
1451
1452         [pbn_b2_1_115200] = {
1453                 .flags          = FL_BASE2,
1454                 .num_ports      = 1,
1455                 .base_baud      = 115200,
1456                 .uart_offset    = 8,
1457         },
1458         [pbn_b2_2_115200] = {
1459                 .flags          = FL_BASE2,
1460                 .num_ports      = 2,
1461                 .base_baud      = 115200,
1462                 .uart_offset    = 8,
1463         },
1464         [pbn_b2_4_115200] = {
1465                 .flags          = FL_BASE2,
1466                 .num_ports      = 4,
1467                 .base_baud      = 115200,
1468                 .uart_offset    = 8,
1469         },
1470         [pbn_b2_8_115200] = {
1471                 .flags          = FL_BASE2,
1472                 .num_ports      = 8,
1473                 .base_baud      = 115200,
1474                 .uart_offset    = 8,
1475         },
1476
1477         [pbn_b2_1_460800] = {
1478                 .flags          = FL_BASE2,
1479                 .num_ports      = 1,
1480                 .base_baud      = 460800,
1481                 .uart_offset    = 8,
1482         },
1483         [pbn_b2_4_460800] = {
1484                 .flags          = FL_BASE2,
1485                 .num_ports      = 4,
1486                 .base_baud      = 460800,
1487                 .uart_offset    = 8,
1488         },
1489         [pbn_b2_8_460800] = {
1490                 .flags          = FL_BASE2,
1491                 .num_ports      = 8,
1492                 .base_baud      = 460800,
1493                 .uart_offset    = 8,
1494         },
1495         [pbn_b2_16_460800] = {
1496                 .flags          = FL_BASE2,
1497                 .num_ports      = 16,
1498                 .base_baud      = 460800,
1499                 .uart_offset    = 8,
1500          },
1501
1502         [pbn_b2_1_921600] = {
1503                 .flags          = FL_BASE2,
1504                 .num_ports      = 1,
1505                 .base_baud      = 921600,
1506                 .uart_offset    = 8,
1507         },
1508         [pbn_b2_4_921600] = {
1509                 .flags          = FL_BASE2,
1510                 .num_ports      = 4,
1511                 .base_baud      = 921600,
1512                 .uart_offset    = 8,
1513         },
1514         [pbn_b2_8_921600] = {
1515                 .flags          = FL_BASE2,
1516                 .num_ports      = 8,
1517                 .base_baud      = 921600,
1518                 .uart_offset    = 8,
1519         },
1520
1521         [pbn_b2_bt_1_115200] = {
1522                 .flags          = FL_BASE2|FL_BASE_BARS,
1523                 .num_ports      = 1,
1524                 .base_baud      = 115200,
1525                 .uart_offset    = 8,
1526         },
1527         [pbn_b2_bt_2_115200] = {
1528                 .flags          = FL_BASE2|FL_BASE_BARS,
1529                 .num_ports      = 2,
1530                 .base_baud      = 115200,
1531                 .uart_offset    = 8,
1532         },
1533         [pbn_b2_bt_4_115200] = {
1534                 .flags          = FL_BASE2|FL_BASE_BARS,
1535                 .num_ports      = 4,
1536                 .base_baud      = 115200,
1537                 .uart_offset    = 8,
1538         },
1539
1540         [pbn_b2_bt_2_921600] = {
1541                 .flags          = FL_BASE2|FL_BASE_BARS,
1542                 .num_ports      = 2,
1543                 .base_baud      = 921600,
1544                 .uart_offset    = 8,
1545         },
1546         [pbn_b2_bt_4_921600] = {
1547                 .flags          = FL_BASE2|FL_BASE_BARS,
1548                 .num_ports      = 4,
1549                 .base_baud      = 921600,
1550                 .uart_offset    = 8,
1551         },
1552
1553         [pbn_b3_2_115200] = {
1554                 .flags          = FL_BASE3,
1555                 .num_ports      = 2,
1556                 .base_baud      = 115200,
1557                 .uart_offset    = 8,
1558         },
1559         [pbn_b3_4_115200] = {
1560                 .flags          = FL_BASE3,
1561                 .num_ports      = 4,
1562                 .base_baud      = 115200,
1563                 .uart_offset    = 8,
1564         },
1565         [pbn_b3_8_115200] = {
1566                 .flags          = FL_BASE3,
1567                 .num_ports      = 8,
1568                 .base_baud      = 115200,
1569                 .uart_offset    = 8,
1570         },
1571
1572         /*
1573          * Entries following this are board-specific.
1574          */
1575
1576         /*
1577          * Panacom - IOMEM
1578          */
1579         [pbn_panacom] = {
1580                 .flags          = FL_BASE2,
1581                 .num_ports      = 2,
1582                 .base_baud      = 921600,
1583                 .uart_offset    = 0x400,
1584                 .reg_shift      = 7,
1585         },
1586         [pbn_panacom2] = {
1587                 .flags          = FL_BASE2|FL_BASE_BARS,
1588                 .num_ports      = 2,
1589                 .base_baud      = 921600,
1590                 .uart_offset    = 0x400,
1591                 .reg_shift      = 7,
1592         },
1593         [pbn_panacom4] = {
1594                 .flags          = FL_BASE2|FL_BASE_BARS,
1595                 .num_ports      = 4,
1596                 .base_baud      = 921600,
1597                 .uart_offset    = 0x400,
1598                 .reg_shift      = 7,
1599         },
1600
1601         [pbn_exsys_4055] = {
1602                 .flags          = FL_BASE2,
1603                 .num_ports      = 4,
1604                 .base_baud      = 115200,
1605                 .uart_offset    = 8,
1606         },
1607
1608         /* I think this entry is broken - the first_offset looks wrong --rmk */
1609         [pbn_plx_romulus] = {
1610                 .flags          = FL_BASE2,
1611                 .num_ports      = 4,
1612                 .base_baud      = 921600,
1613                 .uart_offset    = 8 << 2,
1614                 .reg_shift      = 2,
1615                 .first_offset   = 0x03,
1616         },
1617
1618         /*
1619          * This board uses the size of PCI Base region 0 to
1620          * signal now many ports are available
1621          */
1622         [pbn_oxsemi] = {
1623                 .flags          = FL_BASE0|FL_REGION_SZ_CAP,
1624                 .num_ports      = 32,
1625                 .base_baud      = 115200,
1626                 .uart_offset    = 8,
1627         },
1628
1629         /*
1630          * EKF addition for i960 Boards form EKF with serial port.
1631          * Max 256 ports.
1632          */
1633         [pbn_intel_i960] = {
1634                 .flags          = FL_BASE0,
1635                 .num_ports      = 32,
1636                 .base_baud      = 921600,
1637                 .uart_offset    = 8 << 2,
1638                 .reg_shift      = 2,
1639                 .first_offset   = 0x10000,
1640         },
1641         [pbn_sgi_ioc3] = {
1642                 .flags          = FL_BASE0|FL_NOIRQ,
1643                 .num_ports      = 1,
1644                 .base_baud      = 458333,
1645                 .uart_offset    = 8,
1646                 .reg_shift      = 0,
1647                 .first_offset   = 0x20178,
1648         },
1649
1650         /*
1651          * Computone - uses IOMEM.
1652          */
1653         [pbn_computone_4] = {
1654                 .flags          = FL_BASE0,
1655                 .num_ports      = 4,
1656                 .base_baud      = 921600,
1657                 .uart_offset    = 0x40,
1658                 .reg_shift      = 2,
1659                 .first_offset   = 0x200,
1660         },
1661         [pbn_computone_6] = {
1662                 .flags          = FL_BASE0,
1663                 .num_ports      = 6,
1664                 .base_baud      = 921600,
1665                 .uart_offset    = 0x40,
1666                 .reg_shift      = 2,
1667                 .first_offset   = 0x200,
1668         },
1669         [pbn_computone_8] = {
1670                 .flags          = FL_BASE0,
1671                 .num_ports      = 8,
1672                 .base_baud      = 921600,
1673                 .uart_offset    = 0x40,
1674                 .reg_shift      = 2,
1675                 .first_offset   = 0x200,
1676         },
1677         [pbn_sbsxrsio] = {
1678                 .flags          = FL_BASE0,
1679                 .num_ports      = 8,
1680                 .base_baud      = 460800,
1681                 .uart_offset    = 256,
1682                 .reg_shift      = 4,
1683         },
1684         /*
1685          * Exar Corp. XR17C15[248] Dual/Quad/Octal UART
1686          *  Only basic 16550A support.
1687          *  XR17C15[24] are not tested, but they should work.
1688          */
1689         [pbn_exar_XR17C152] = {
1690                 .flags          = FL_BASE0,
1691                 .num_ports      = 2,
1692                 .base_baud      = 921600,
1693                 .uart_offset    = 0x200,
1694         },
1695         [pbn_exar_XR17C154] = {
1696                 .flags          = FL_BASE0,
1697                 .num_ports      = 4,
1698                 .base_baud      = 921600,
1699                 .uart_offset    = 0x200,
1700         },
1701         [pbn_exar_XR17C158] = {
1702                 .flags          = FL_BASE0,
1703                 .num_ports      = 8,
1704                 .base_baud      = 921600,
1705                 .uart_offset    = 0x200,
1706         },
1707         /*
1708          * PA Semi PWRficient PA6T-1682M on-chip UART
1709          */
1710         [pbn_pasemi_1682M] = {
1711                 .flags          = FL_BASE0,
1712                 .num_ports      = 1,
1713                 .base_baud      = 8333333,
1714         },
1715 };
1716
1717 static const struct pci_device_id softmodem_blacklist[] = {
1718         { PCI_VDEVICE(AL, 0x5457), }, /* ALi Corporation M5457 AC'97 Modem */
1719 };
1720
1721 /*
1722  * Given a complete unknown PCI device, try to use some heuristics to
1723  * guess what the configuration might be, based on the pitiful PCI
1724  * serial specs.  Returns 0 on success, 1 on failure.
1725  */
1726 static int __devinit
1727 serial_pci_guess_board(struct pci_dev *dev, struct pciserial_board *board)
1728 {
1729         const struct pci_device_id *blacklist;
1730         int num_iomem, num_port, first_port = -1, i;
1731
1732         /*
1733          * If it is not a communications device or the programming
1734          * interface is greater than 6, give up.
1735          *
1736          * (Should we try to make guesses for multiport serial devices
1737          * later?)
1738          */
1739         if ((((dev->class >> 8) != PCI_CLASS_COMMUNICATION_SERIAL) &&
1740              ((dev->class >> 8) != PCI_CLASS_COMMUNICATION_MODEM)) ||
1741             (dev->class & 0xff) > 6)
1742                 return -ENODEV;
1743
1744         /*
1745          * Do not access blacklisted devices that are known not to
1746          * feature serial ports.
1747          */
1748         for (blacklist = softmodem_blacklist;
1749              blacklist < softmodem_blacklist + ARRAY_SIZE(softmodem_blacklist);
1750              blacklist++) {
1751                 if (dev->vendor == blacklist->vendor &&
1752                     dev->device == blacklist->device)
1753                         return -ENODEV;
1754         }
1755
1756         num_iomem = num_port = 0;
1757         for (i = 0; i < PCI_NUM_BAR_RESOURCES; i++) {
1758                 if (pci_resource_flags(dev, i) & IORESOURCE_IO) {
1759                         num_port++;
1760                         if (first_port == -1)
1761                                 first_port = i;
1762                 }
1763                 if (pci_resource_flags(dev, i) & IORESOURCE_MEM)
1764                         num_iomem++;
1765         }
1766
1767         /*
1768          * If there is 1 or 0 iomem regions, and exactly one port,
1769          * use it.  We guess the number of ports based on the IO
1770          * region size.
1771          */
1772         if (num_iomem <= 1 && num_port == 1) {
1773                 board->flags = first_port;
1774                 board->num_ports = pci_resource_len(dev, first_port) / 8;
1775                 return 0;
1776         }
1777
1778         /*
1779          * Now guess if we've got a board which indexes by BARs.
1780          * Each IO BAR should be 8 bytes, and they should follow
1781          * consecutively.
1782          */
1783         first_port = -1;
1784         num_port = 0;
1785         for (i = 0; i < PCI_NUM_BAR_RESOURCES; i++) {
1786                 if (pci_resource_flags(dev, i) & IORESOURCE_IO &&
1787                     pci_resource_len(dev, i) == 8 &&
1788                     (first_port == -1 || (first_port + num_port) == i)) {
1789                         num_port++;
1790                         if (first_port == -1)
1791                                 first_port = i;
1792                 }
1793         }
1794
1795         if (num_port > 1) {
1796                 board->flags = first_port | FL_BASE_BARS;
1797                 board->num_ports = num_port;
1798                 return 0;
1799         }
1800
1801         return -ENODEV;
1802 }
1803
1804 static inline int
1805 serial_pci_matches(struct pciserial_board *board,
1806                    struct pciserial_board *guessed)
1807 {
1808         return
1809             board->num_ports == guessed->num_ports &&
1810             board->base_baud == guessed->base_baud &&
1811             board->uart_offset == guessed->uart_offset &&
1812             board->reg_shift == guessed->reg_shift &&
1813             board->first_offset == guessed->first_offset;
1814 }
1815
1816 struct serial_private *
1817 pciserial_init_ports(struct pci_dev *dev, struct pciserial_board *board)
1818 {
1819         struct uart_port serial_port;
1820         struct serial_private *priv;
1821         struct pci_serial_quirk *quirk;
1822         int rc, nr_ports, i;
1823
1824         nr_ports = board->num_ports;
1825
1826         /*
1827          * Find an init and setup quirks.
1828          */
1829         quirk = find_quirk(dev);
1830
1831         /*
1832          * Run the new-style initialization function.
1833          * The initialization function returns:
1834          *  <0  - error
1835          *   0  - use board->num_ports
1836          *  >0  - number of ports
1837          */
1838         if (quirk->init) {
1839                 rc = quirk->init(dev);
1840                 if (rc < 0) {
1841                         priv = ERR_PTR(rc);
1842                         goto err_out;
1843                 }
1844                 if (rc)
1845                         nr_ports = rc;
1846         }
1847
1848         priv = kzalloc(sizeof(struct serial_private) +
1849                        sizeof(unsigned int) * nr_ports,
1850                        GFP_KERNEL);
1851         if (!priv) {
1852                 priv = ERR_PTR(-ENOMEM);
1853                 goto err_deinit;
1854         }
1855
1856         priv->dev = dev;
1857         priv->quirk = quirk;
1858
1859         memset(&serial_port, 0, sizeof(struct uart_port));
1860         serial_port.flags = UPF_SKIP_TEST | UPF_BOOT_AUTOCONF | UPF_SHARE_IRQ;
1861         serial_port.uartclk = board->base_baud * 16;
1862         serial_port.irq = get_pci_irq(dev, board);
1863         serial_port.dev = &dev->dev;
1864
1865         for (i = 0; i < nr_ports; i++) {
1866                 if (quirk->setup(priv, board, &serial_port, i))
1867                         break;
1868
1869 #ifdef SERIAL_DEBUG_PCI
1870                 printk(KERN_DEBUG "Setup PCI port: port %x, irq %d, type %d\n",
1871                        serial_port.iobase, serial_port.irq, serial_port.iotype);
1872 #endif
1873
1874                 priv->line[i] = serial8250_register_port(&serial_port);
1875                 if (priv->line[i] < 0) {
1876                         printk(KERN_WARNING "Couldn't register serial port %s: %d\n", pci_name(dev), priv->line[i]);
1877                         break;
1878                 }
1879         }
1880         priv->nr = i;
1881         return priv;
1882
1883 err_deinit:
1884         if (quirk->exit)
1885                 quirk->exit(dev);
1886 err_out:
1887         return priv;
1888 }
1889 EXPORT_SYMBOL_GPL(pciserial_init_ports);
1890
1891 void pciserial_remove_ports(struct serial_private *priv)
1892 {
1893         struct pci_serial_quirk *quirk;
1894         int i;
1895
1896         for (i = 0; i < priv->nr; i++)
1897                 serial8250_unregister_port(priv->line[i]);
1898
1899         for (i = 0; i < PCI_NUM_BAR_RESOURCES; i++) {
1900                 if (priv->remapped_bar[i])
1901                         iounmap(priv->remapped_bar[i]);
1902                 priv->remapped_bar[i] = NULL;
1903         }
1904
1905         /*
1906          * Find the exit quirks.
1907          */
1908         quirk = find_quirk(priv->dev);
1909         if (quirk->exit)
1910                 quirk->exit(priv->dev);
1911
1912         kfree(priv);
1913 }
1914 EXPORT_SYMBOL_GPL(pciserial_remove_ports);
1915
1916 void pciserial_suspend_ports(struct serial_private *priv)
1917 {
1918         int i;
1919
1920         for (i = 0; i < priv->nr; i++)
1921                 if (priv->line[i] >= 0)
1922                         serial8250_suspend_port(priv->line[i]);
1923 }
1924 EXPORT_SYMBOL_GPL(pciserial_suspend_ports);
1925
1926 void pciserial_resume_ports(struct serial_private *priv)
1927 {
1928         int i;
1929
1930         /*
1931          * Ensure that the board is correctly configured.
1932          */
1933         if (priv->quirk->init)
1934                 priv->quirk->init(priv->dev);
1935
1936         for (i = 0; i < priv->nr; i++)
1937                 if (priv->line[i] >= 0)
1938                         serial8250_resume_port(priv->line[i]);
1939 }
1940 EXPORT_SYMBOL_GPL(pciserial_resume_ports);
1941
1942 /*
1943  * Probe one serial board.  Unfortunately, there is no rhyme nor reason
1944  * to the arrangement of serial ports on a PCI card.
1945  */
1946 static int __devinit
1947 pciserial_init_one(struct pci_dev *dev, const struct pci_device_id *ent)
1948 {
1949         struct serial_private *priv;
1950         struct pciserial_board *board, tmp;
1951         int rc;
1952
1953         if (ent->driver_data >= ARRAY_SIZE(pci_boards)) {
1954                 printk(KERN_ERR "pci_init_one: invalid driver_data: %ld\n",
1955                         ent->driver_data);
1956                 return -EINVAL;
1957         }
1958
1959         board = &pci_boards[ent->driver_data];
1960
1961         rc = pci_enable_device(dev);
1962         if (rc)
1963                 return rc;
1964
1965         if (ent->driver_data == pbn_default) {
1966                 /*
1967                  * Use a copy of the pci_board entry for this;
1968                  * avoid changing entries in the table.
1969                  */
1970                 memcpy(&tmp, board, sizeof(struct pciserial_board));
1971                 board = &tmp;
1972
1973                 /*
1974                  * We matched one of our class entries.  Try to
1975                  * determine the parameters of this board.
1976                  */
1977                 rc = serial_pci_guess_board(dev, board);
1978                 if (rc)
1979                         goto disable;
1980         } else {
1981                 /*
1982                  * We matched an explicit entry.  If we are able to
1983                  * detect this boards settings with our heuristic,
1984                  * then we no longer need this entry.
1985                  */
1986                 memcpy(&tmp, &pci_boards[pbn_default],
1987                        sizeof(struct pciserial_board));
1988                 rc = serial_pci_guess_board(dev, &tmp);
1989                 if (rc == 0 && serial_pci_matches(board, &tmp))
1990                         moan_device("Redundant entry in serial pci_table.",
1991                                     dev);
1992         }
1993
1994         priv = pciserial_init_ports(dev, board);
1995         if (!IS_ERR(priv)) {
1996                 pci_set_drvdata(dev, priv);
1997                 return 0;
1998         }
1999
2000         rc = PTR_ERR(priv);
2001
2002  disable:
2003         pci_disable_device(dev);
2004         return rc;
2005 }
2006
2007 static void __devexit pciserial_remove_one(struct pci_dev *dev)
2008 {
2009         struct serial_private *priv = pci_get_drvdata(dev);
2010
2011         pci_set_drvdata(dev, NULL);
2012
2013         pciserial_remove_ports(priv);
2014
2015         pci_disable_device(dev);
2016 }
2017
2018 #ifdef CONFIG_PM
2019 static int pciserial_suspend_one(struct pci_dev *dev, pm_message_t state)
2020 {
2021         struct serial_private *priv = pci_get_drvdata(dev);
2022
2023         if (priv)
2024                 pciserial_suspend_ports(priv);
2025
2026         pci_save_state(dev);
2027         pci_set_power_state(dev, pci_choose_state(dev, state));
2028         return 0;
2029 }
2030
2031 static int pciserial_resume_one(struct pci_dev *dev)
2032 {
2033         int err;
2034         struct serial_private *priv = pci_get_drvdata(dev);
2035
2036         pci_set_power_state(dev, PCI_D0);
2037         pci_restore_state(dev);
2038
2039         if (priv) {
2040                 /*
2041                  * The device may have been disabled.  Re-enable it.
2042                  */
2043                 err = pci_enable_device(dev);
2044                 if (err)
2045                         return err;
2046
2047                 pciserial_resume_ports(priv);
2048         }
2049         return 0;
2050 }
2051 #endif
2052
2053 static struct pci_device_id serial_pci_tbl[] = {
2054         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V960,
2055                 PCI_SUBVENDOR_ID_CONNECT_TECH,
2056                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_232, 0, 0,
2057                 pbn_b1_8_1382400 },
2058         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V960,
2059                 PCI_SUBVENDOR_ID_CONNECT_TECH,
2060                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_232, 0, 0,
2061                 pbn_b1_4_1382400 },
2062         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V960,
2063                 PCI_SUBVENDOR_ID_CONNECT_TECH,
2064                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_232, 0, 0,
2065                 pbn_b1_2_1382400 },
2066         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
2067                 PCI_SUBVENDOR_ID_CONNECT_TECH,
2068                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_232, 0, 0,
2069                 pbn_b1_8_1382400 },
2070         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
2071                 PCI_SUBVENDOR_ID_CONNECT_TECH,
2072                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_232, 0, 0,
2073                 pbn_b1_4_1382400 },
2074         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
2075                 PCI_SUBVENDOR_ID_CONNECT_TECH,
2076                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_232, 0, 0,
2077                 pbn_b1_2_1382400 },
2078         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
2079                 PCI_SUBVENDOR_ID_CONNECT_TECH,
2080                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_485, 0, 0,
2081                 pbn_b1_8_921600 },
2082         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
2083                 PCI_SUBVENDOR_ID_CONNECT_TECH,
2084                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_485_4_4, 0, 0,
2085                 pbn_b1_8_921600 },
2086         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
2087                 PCI_SUBVENDOR_ID_CONNECT_TECH,
2088                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_485, 0, 0,
2089                 pbn_b1_4_921600 },
2090         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
2091                 PCI_SUBVENDOR_ID_CONNECT_TECH,
2092                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_485_2_2, 0, 0,
2093                 pbn_b1_4_921600 },
2094         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
2095                 PCI_SUBVENDOR_ID_CONNECT_TECH,
2096                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_485, 0, 0,
2097                 pbn_b1_2_921600 },
2098         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
2099                 PCI_SUBVENDOR_ID_CONNECT_TECH,
2100                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_485_2_6, 0, 0,
2101                 pbn_b1_8_921600 },
2102         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
2103                 PCI_SUBVENDOR_ID_CONNECT_TECH,
2104                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH081101V1, 0, 0,
2105                 pbn_b1_8_921600 },
2106         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
2107                 PCI_SUBVENDOR_ID_CONNECT_TECH,
2108                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH041101V1, 0, 0,
2109                 pbn_b1_4_921600 },
2110         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
2111                 PCI_SUBVENDOR_ID_CONNECT_TECH,
2112                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_20MHZ, 0, 0,
2113                 pbn_b1_2_1250000 },
2114         {       PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
2115                 PCI_SUBVENDOR_ID_CONNECT_TECH,
2116                 PCI_SUBDEVICE_ID_CONNECT_TECH_TITAN_2, 0, 0,
2117                 pbn_b0_2_1843200 },
2118         {       PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
2119                 PCI_SUBVENDOR_ID_CONNECT_TECH,
2120                 PCI_SUBDEVICE_ID_CONNECT_TECH_TITAN_4, 0, 0,
2121                 pbn_b0_4_1843200 },
2122         {       PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
2123                 PCI_VENDOR_ID_AFAVLAB,
2124                 PCI_SUBDEVICE_ID_AFAVLAB_P061, 0, 0,
2125                 pbn_b0_4_1152000 },
2126         {       PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152,
2127                 PCI_SUBVENDOR_ID_CONNECT_TECH,
2128                 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2_232, 0, 0,
2129                 pbn_b0_2_1843200_200 },
2130         {       PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C154,
2131                 PCI_SUBVENDOR_ID_CONNECT_TECH,
2132                 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4_232, 0, 0,
2133                 pbn_b0_4_1843200_200 },
2134         {       PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C158,
2135                 PCI_SUBVENDOR_ID_CONNECT_TECH,
2136                 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_8_232, 0, 0,
2137                 pbn_b0_8_1843200_200 },
2138         {       PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152,
2139                 PCI_SUBVENDOR_ID_CONNECT_TECH,
2140                 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_1_1, 0, 0,
2141                 pbn_b0_2_1843200_200 },
2142         {       PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C154,
2143                 PCI_SUBVENDOR_ID_CONNECT_TECH,
2144                 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2_2, 0, 0,
2145                 pbn_b0_4_1843200_200 },
2146         {       PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C158,
2147                 PCI_SUBVENDOR_ID_CONNECT_TECH,
2148                 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4_4, 0, 0,
2149                 pbn_b0_8_1843200_200 },
2150         {       PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152,
2151                 PCI_SUBVENDOR_ID_CONNECT_TECH,
2152                 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2, 0, 0,
2153                 pbn_b0_2_1843200_200 },
2154         {       PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C154,
2155                 PCI_SUBVENDOR_ID_CONNECT_TECH,
2156                 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4, 0, 0,
2157                 pbn_b0_4_1843200_200 },
2158         {       PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C158,
2159                 PCI_SUBVENDOR_ID_CONNECT_TECH,
2160                 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_8, 0, 0,
2161                 pbn_b0_8_1843200_200 },
2162         {       PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152,
2163                 PCI_SUBVENDOR_ID_CONNECT_TECH,
2164                 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2_485, 0, 0,
2165                 pbn_b0_2_1843200_200 },
2166         {       PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C154,
2167                 PCI_SUBVENDOR_ID_CONNECT_TECH,
2168                 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4_485, 0, 0,
2169                 pbn_b0_4_1843200_200 },
2170         {       PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C158,
2171                 PCI_SUBVENDOR_ID_CONNECT_TECH,
2172                 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_8_485, 0, 0,
2173                 pbn_b0_8_1843200_200 },
2174
2175         {       PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_U530,
2176                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2177                 pbn_b2_bt_1_115200 },
2178         {       PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM2,
2179                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2180                 pbn_b2_bt_2_115200 },
2181         {       PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM422,
2182                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2183                 pbn_b2_bt_4_115200 },
2184         {       PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM232,
2185                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2186                 pbn_b2_bt_2_115200 },
2187         {       PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_COMM4,
2188                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2189                 pbn_b2_bt_4_115200 },
2190         {       PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_COMM8,
2191                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2192                 pbn_b2_8_115200 },
2193         {       PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM8,
2194                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2195                 pbn_b2_8_115200 },
2196
2197         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_GTEK_SERIAL2,
2198                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2199                 pbn_b2_bt_2_115200 },
2200         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_SPCOM200,
2201                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2202                 pbn_b2_bt_2_921600 },
2203         /*
2204          * VScom SPCOM800, from sl@s.pl
2205          */
2206         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_SPCOM800,
2207                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2208                 pbn_b2_8_921600 },
2209         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_1077,
2210                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2211                 pbn_b2_4_921600 },
2212         /* Unknown card - subdevice 0x1584 */
2213         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
2214                 PCI_VENDOR_ID_PLX,
2215                 PCI_SUBDEVICE_ID_UNKNOWN_0x1584, 0, 0,
2216                 pbn_b0_4_115200 },
2217         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
2218                 PCI_SUBVENDOR_ID_KEYSPAN,
2219                 PCI_SUBDEVICE_ID_KEYSPAN_SX2, 0, 0,
2220                 pbn_panacom },
2221         {       PCI_VENDOR_ID_PANACOM, PCI_DEVICE_ID_PANACOM_QUADMODEM,
2222                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2223                 pbn_panacom4 },
2224         {       PCI_VENDOR_ID_PANACOM, PCI_DEVICE_ID_PANACOM_DUALMODEM,
2225                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2226                 pbn_panacom2 },
2227         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9030,
2228                 PCI_VENDOR_ID_ESDGMBH,
2229                 PCI_DEVICE_ID_ESDGMBH_CPCIASIO4, 0, 0,
2230                 pbn_b2_4_115200 },
2231         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
2232                 PCI_SUBVENDOR_ID_CHASE_PCIFAST,
2233                 PCI_SUBDEVICE_ID_CHASE_PCIFAST4, 0, 0,
2234                 pbn_b2_4_460800 },
2235         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
2236                 PCI_SUBVENDOR_ID_CHASE_PCIFAST,
2237                 PCI_SUBDEVICE_ID_CHASE_PCIFAST8, 0, 0,
2238                 pbn_b2_8_460800 },
2239         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
2240                 PCI_SUBVENDOR_ID_CHASE_PCIFAST,
2241                 PCI_SUBDEVICE_ID_CHASE_PCIFAST16, 0, 0,
2242                 pbn_b2_16_460800 },
2243         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
2244                 PCI_SUBVENDOR_ID_CHASE_PCIFAST,
2245                 PCI_SUBDEVICE_ID_CHASE_PCIFAST16FMC, 0, 0,
2246                 pbn_b2_16_460800 },
2247         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
2248                 PCI_SUBVENDOR_ID_CHASE_PCIRAS,
2249                 PCI_SUBDEVICE_ID_CHASE_PCIRAS4, 0, 0,
2250                 pbn_b2_4_460800 },
2251         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
2252                 PCI_SUBVENDOR_ID_CHASE_PCIRAS,
2253                 PCI_SUBDEVICE_ID_CHASE_PCIRAS8, 0, 0,
2254                 pbn_b2_8_460800 },
2255         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
2256                 PCI_SUBVENDOR_ID_EXSYS,
2257                 PCI_SUBDEVICE_ID_EXSYS_4055, 0, 0,
2258                 pbn_exsys_4055 },
2259         /*
2260          * Megawolf Romulus PCI Serial Card, from Mike Hudson
2261          * (Exoray@isys.ca)
2262          */
2263         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_ROMULUS,
2264                 0x10b5, 0x106a, 0, 0,
2265                 pbn_plx_romulus },
2266         {       PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSC100,
2267                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2268                 pbn_b1_4_115200 },
2269         {       PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSC100,
2270                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2271                 pbn_b1_2_115200 },
2272         {       PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_ESC100D,
2273                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2274                 pbn_b1_8_115200 },
2275         {       PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_ESC100M,
2276                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2277                 pbn_b1_8_115200 },
2278         {       PCI_VENDOR_ID_SPECIALIX, PCI_DEVICE_ID_OXSEMI_16PCI954,
2279                 PCI_VENDOR_ID_SPECIALIX, PCI_SUBDEVICE_ID_SPECIALIX_SPEED4,
2280                 0, 0,
2281                 pbn_b0_4_921600 },
2282         {       PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
2283                 PCI_SUBVENDOR_ID_SIIG, PCI_SUBDEVICE_ID_SIIG_QUARTET_SERIAL,
2284                 0, 0,
2285                 pbn_b0_4_1152000 },
2286
2287                 /*
2288                  * The below card is a little controversial since it is the
2289                  * subject of a PCI vendor/device ID clash.  (See
2290                  * www.ussg.iu.edu/hypermail/linux/kernel/0303.1/0516.html).
2291                  * For now just used the hex ID 0x950a.
2292                  */
2293         {       PCI_VENDOR_ID_OXSEMI, 0x950a,
2294                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2295                 pbn_b0_2_1130000 },
2296         {       PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
2297                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2298                 pbn_b0_4_115200 },
2299         {       PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI952,
2300                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2301                 pbn_b0_bt_2_921600 },
2302
2303         /*
2304          * SBS Technologies, Inc. P-Octal and PMC-OCTPRO cards,
2305          * from skokodyn@yahoo.com
2306          */
2307         {       PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO,
2308                 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_OCTPRO232, 0, 0,
2309                 pbn_sbsxrsio },
2310         {       PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO,
2311                 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_OCTPRO422, 0, 0,
2312                 pbn_sbsxrsio },
2313         {       PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO,
2314                 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_POCTAL232, 0, 0,
2315                 pbn_sbsxrsio },
2316         {       PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO,
2317                 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_POCTAL422, 0, 0,
2318                 pbn_sbsxrsio },
2319
2320         /*
2321          * Digitan DS560-558, from jimd@esoft.com
2322          */
2323         {       PCI_VENDOR_ID_ATT, PCI_DEVICE_ID_ATT_VENUS_MODEM,
2324                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2325                 pbn_b1_1_115200 },
2326
2327         /*
2328          * Titan Electronic cards
2329          *  The 400L and 800L have a custom setup quirk.
2330          */
2331         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_100,
2332                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2333                 pbn_b0_1_921600 },
2334         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200,
2335                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2336                 pbn_b0_2_921600 },
2337         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400,
2338                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2339                 pbn_b0_4_921600 },
2340         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800B,
2341                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2342                 pbn_b0_4_921600 },
2343         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_100L,
2344                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2345                 pbn_b1_1_921600 },
2346         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200L,
2347                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2348                 pbn_b1_bt_2_921600 },
2349         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400L,
2350                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2351                 pbn_b0_bt_4_921600 },
2352         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800L,
2353                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2354                 pbn_b0_bt_8_921600 },
2355
2356         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_10x_550,
2357                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2358                 pbn_b2_1_460800 },
2359         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_10x_650,
2360                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2361                 pbn_b2_1_460800 },
2362         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_10x_850,
2363                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2364                 pbn_b2_1_460800 },
2365         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_10x_550,
2366                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2367                 pbn_b2_bt_2_921600 },
2368         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_10x_650,
2369                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2370                 pbn_b2_bt_2_921600 },
2371         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_10x_850,
2372                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2373                 pbn_b2_bt_2_921600 },
2374         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_10x_550,
2375                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2376                 pbn_b2_bt_4_921600 },
2377         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_10x_650,
2378                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2379                 pbn_b2_bt_4_921600 },
2380         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_10x_850,
2381                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2382                 pbn_b2_bt_4_921600 },
2383         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_20x_550,
2384                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2385                 pbn_b0_1_921600 },
2386         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_20x_650,
2387                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2388                 pbn_b0_1_921600 },
2389         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_20x_850,
2390                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2391                 pbn_b0_1_921600 },
2392         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_20x_550,
2393                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2394                 pbn_b0_bt_2_921600 },
2395         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_20x_650,
2396                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2397                 pbn_b0_bt_2_921600 },
2398         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_20x_850,
2399                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2400                 pbn_b0_bt_2_921600 },
2401         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_20x_550,
2402                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2403                 pbn_b0_bt_4_921600 },
2404         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_20x_650,
2405                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2406                 pbn_b0_bt_4_921600 },
2407         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_20x_850,
2408                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2409                 pbn_b0_bt_4_921600 },
2410         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_8S_20x_550,
2411                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2412                 pbn_b0_bt_8_921600 },
2413         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_8S_20x_650,
2414                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2415                 pbn_b0_bt_8_921600 },
2416         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_8S_20x_850,
2417                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2418                 pbn_b0_bt_8_921600 },
2419
2420         /*
2421          * Computone devices submitted by Doug McNash dmcnash@computone.com
2422          */
2423         {       PCI_VENDOR_ID_COMPUTONE, PCI_DEVICE_ID_COMPUTONE_PG,
2424                 PCI_SUBVENDOR_ID_COMPUTONE, PCI_SUBDEVICE_ID_COMPUTONE_PG4,
2425                 0, 0, pbn_computone_4 },
2426         {       PCI_VENDOR_ID_COMPUTONE, PCI_DEVICE_ID_COMPUTONE_PG,
2427                 PCI_SUBVENDOR_ID_COMPUTONE, PCI_SUBDEVICE_ID_COMPUTONE_PG8,
2428                 0, 0, pbn_computone_8 },
2429         {       PCI_VENDOR_ID_COMPUTONE, PCI_DEVICE_ID_COMPUTONE_PG,
2430                 PCI_SUBVENDOR_ID_COMPUTONE, PCI_SUBDEVICE_ID_COMPUTONE_PG6,
2431                 0, 0, pbn_computone_6 },
2432
2433         {       PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI95N,
2434                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2435                 pbn_oxsemi },
2436         {       PCI_VENDOR_ID_TIMEDIA, PCI_DEVICE_ID_TIMEDIA_1889,
2437                 PCI_VENDOR_ID_TIMEDIA, PCI_ANY_ID, 0, 0,
2438                 pbn_b0_bt_1_921600 },
2439
2440         /*
2441          * AFAVLAB serial card, from Harald Welte <laforge@gnumonks.org>
2442          */
2443         {       PCI_VENDOR_ID_AFAVLAB, PCI_DEVICE_ID_AFAVLAB_P028,
2444                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2445                 pbn_b0_bt_8_115200 },
2446         {       PCI_VENDOR_ID_AFAVLAB, PCI_DEVICE_ID_AFAVLAB_P030,
2447                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2448                 pbn_b0_bt_8_115200 },
2449
2450         {       PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_DSERIAL,
2451                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2452                 pbn_b0_bt_2_115200 },
2453         {       PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUATRO_A,
2454                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2455                 pbn_b0_bt_2_115200 },
2456         {       PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUATRO_B,
2457                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2458                 pbn_b0_bt_2_115200 },
2459         {       PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_OCTO_A,
2460                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2461                 pbn_b0_bt_4_460800 },
2462         {       PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_OCTO_B,
2463                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2464                 pbn_b0_bt_4_460800 },
2465         {       PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_PORT_PLUS,
2466                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2467                 pbn_b0_bt_2_460800 },
2468         {       PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUAD_A,
2469                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2470                 pbn_b0_bt_2_460800 },
2471         {       PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUAD_B,
2472                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2473                 pbn_b0_bt_2_460800 },
2474         {       PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_SSERIAL,
2475                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2476                 pbn_b0_bt_1_115200 },
2477         {       PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_PORT_650,
2478                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2479                 pbn_b0_bt_1_460800 },
2480
2481         /*
2482          * Korenix Jetcard F0/F1 cards (JC1204, JC1208, JC1404, JC1408).
2483          * Cards are identified by their subsystem vendor IDs, which
2484          * (in hex) match the model number.
2485          *
2486          * Note that JC140x are RS422/485 cards which require ox950
2487          * ACR = 0x10, and as such are not currently fully supported.
2488          */
2489         {       PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF0,
2490                 0x1204, 0x0004, 0, 0,
2491                 pbn_b0_4_921600 },
2492         {       PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF0,
2493                 0x1208, 0x0004, 0, 0,
2494                 pbn_b0_4_921600 },
2495 /*      {       PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF0,
2496                 0x1402, 0x0002, 0, 0,
2497                 pbn_b0_2_921600 }, */
2498 /*      {       PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF0,
2499                 0x1404, 0x0004, 0, 0,
2500                 pbn_b0_4_921600 }, */
2501         {       PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF1,
2502                 0x1208, 0x0004, 0, 0,
2503                 pbn_b0_4_921600 },
2504
2505         /*
2506          * Dell Remote Access Card 4 - Tim_T_Murphy@Dell.com
2507          */
2508         {       PCI_VENDOR_ID_DELL, PCI_DEVICE_ID_DELL_RAC4,
2509                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2510                 pbn_b1_1_1382400 },
2511
2512         /*
2513          * Dell Remote Access Card III - Tim_T_Murphy@Dell.com
2514          */
2515         {       PCI_VENDOR_ID_DELL, PCI_DEVICE_ID_DELL_RACIII,
2516                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2517                 pbn_b1_1_1382400 },
2518
2519         /*
2520          * RAStel 2 port modem, gerg@moreton.com.au
2521          */
2522         {       PCI_VENDOR_ID_MORETON, PCI_DEVICE_ID_RASTEL_2PORT,
2523                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2524                 pbn_b2_bt_2_115200 },
2525
2526         /*
2527          * EKF addition for i960 Boards form EKF with serial port
2528          */
2529         {       PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80960_RP,
2530                 0xE4BF, PCI_ANY_ID, 0, 0,
2531                 pbn_intel_i960 },
2532
2533         /*
2534          * Xircom Cardbus/Ethernet combos
2535          */
2536         {       PCI_VENDOR_ID_XIRCOM, PCI_DEVICE_ID_XIRCOM_X3201_MDM,
2537                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2538                 pbn_b0_1_115200 },
2539         /*
2540          * Xircom RBM56G cardbus modem - Dirk Arnold (temp entry)
2541          */
2542         {       PCI_VENDOR_ID_XIRCOM, PCI_DEVICE_ID_XIRCOM_RBM56G,
2543                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2544                 pbn_b0_1_115200 },
2545
2546         /*
2547          * Untested PCI modems, sent in from various folks...
2548          */
2549
2550         /*
2551          * Elsa Model 56K PCI Modem, from Andreas Rath <arh@01019freenet.de>
2552          */
2553         {       PCI_VENDOR_ID_ROCKWELL, 0x1004,
2554                 0x1048, 0x1500, 0, 0,
2555                 pbn_b1_1_115200 },
2556
2557         {       PCI_VENDOR_ID_SGI, PCI_DEVICE_ID_SGI_IOC3,
2558                 0xFF00, 0, 0, 0,
2559                 pbn_sgi_ioc3 },
2560
2561         /*
2562          * HP Diva card
2563          */
2564         {       PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA,
2565                 PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA_RMP3, 0, 0,
2566                 pbn_b1_1_115200 },
2567         {       PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA,
2568                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2569                 pbn_b0_5_115200 },
2570         {       PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA_AUX,
2571                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2572                 pbn_b2_1_115200 },
2573
2574         {       PCI_VENDOR_ID_DCI, PCI_DEVICE_ID_DCI_PCCOM2,
2575                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2576                 pbn_b3_2_115200 },
2577         {       PCI_VENDOR_ID_DCI, PCI_DEVICE_ID_DCI_PCCOM4,
2578                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2579                 pbn_b3_4_115200 },
2580         {       PCI_VENDOR_ID_DCI, PCI_DEVICE_ID_DCI_PCCOM8,
2581                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2582                 pbn_b3_8_115200 },
2583
2584         /*
2585          * Exar Corp. XR17C15[248] Dual/Quad/Octal UART
2586          */
2587         {       PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152,
2588                 PCI_ANY_ID, PCI_ANY_ID,
2589                 0,
2590                 0, pbn_exar_XR17C152 },
2591         {       PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C154,
2592                 PCI_ANY_ID, PCI_ANY_ID,
2593                 0,
2594                 0, pbn_exar_XR17C154 },
2595         {       PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C158,
2596                 PCI_ANY_ID, PCI_ANY_ID,
2597                 0,
2598                 0, pbn_exar_XR17C158 },
2599
2600         /*
2601          * Topic TP560 Data/Fax/Voice 56k modem (reported by Evan Clarke)
2602          */
2603         {       PCI_VENDOR_ID_TOPIC, PCI_DEVICE_ID_TOPIC_TP560,
2604                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2605                 pbn_b0_1_115200 },
2606         /*
2607          * ITE
2608          */
2609         {       PCI_VENDOR_ID_ITE, PCI_DEVICE_ID_ITE_8872,
2610                 PCI_ANY_ID, PCI_ANY_ID,
2611                 0, 0,
2612                 pbn_b1_bt_1_115200 },
2613
2614         /*
2615          * IntaShield IS-200
2616          */
2617         {       PCI_VENDOR_ID_INTASHIELD, PCI_DEVICE_ID_INTASHIELD_IS200,
2618                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,   /* 135a.0811 */
2619                 pbn_b2_2_115200 },
2620         /*
2621          * IntaShield IS-400
2622          */
2623         {       PCI_VENDOR_ID_INTASHIELD, PCI_DEVICE_ID_INTASHIELD_IS400,
2624                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,    /* 135a.0dc0 */
2625                 pbn_b2_4_115200 },
2626         /*
2627          * Perle PCI-RAS cards
2628          */
2629         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9030,
2630                 PCI_SUBVENDOR_ID_PERLE, PCI_SUBDEVICE_ID_PCI_RAS4,
2631                 0, 0, pbn_b2_4_921600 },
2632         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9030,
2633                 PCI_SUBVENDOR_ID_PERLE, PCI_SUBDEVICE_ID_PCI_RAS8,
2634                 0, 0, pbn_b2_8_921600 },
2635
2636         /*
2637          * Mainpine series cards: Fairly standard layout but fools
2638          * parts of the autodetect in some cases and uses otherwise
2639          * unmatched communications subclasses in the PCI Express case
2640          */
2641
2642         {       /* RockForceDUO */
2643                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
2644                 PCI_VENDOR_ID_MAINPINE, 0x0200,
2645                 0, 0, pbn_b0_2_115200 },
2646         {       /* RockForceQUATRO */
2647                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
2648                 PCI_VENDOR_ID_MAINPINE, 0x0300,
2649                 0, 0, pbn_b0_4_115200 },
2650         {       /* RockForceDUO+ */
2651                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
2652                 PCI_VENDOR_ID_MAINPINE, 0x0400,
2653                 0, 0, pbn_b0_2_115200 },
2654         {       /* RockForceQUATRO+ */
2655                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
2656                 PCI_VENDOR_ID_MAINPINE, 0x0500,
2657                 0, 0, pbn_b0_4_115200 },
2658         {       /* RockForce+ */
2659                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
2660                 PCI_VENDOR_ID_MAINPINE, 0x0600,
2661                 0, 0, pbn_b0_2_115200 },
2662         {       /* RockForce+ */
2663                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
2664                 PCI_VENDOR_ID_MAINPINE, 0x0700,
2665                 0, 0, pbn_b0_4_115200 },
2666         {       /* RockForceOCTO+ */
2667                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
2668                 PCI_VENDOR_ID_MAINPINE, 0x0800,
2669                 0, 0, pbn_b0_8_115200 },
2670         {       /* RockForceDUO+ */
2671                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
2672                 PCI_VENDOR_ID_MAINPINE, 0x0C00,
2673                 0, 0, pbn_b0_2_115200 },
2674         {       /* RockForceQUARTRO+ */
2675                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
2676                 PCI_VENDOR_ID_MAINPINE, 0x0D00,
2677                 0, 0, pbn_b0_4_115200 },
2678         {       /* RockForceOCTO+ */
2679                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
2680                 PCI_VENDOR_ID_MAINPINE, 0x1D00,
2681                 0, 0, pbn_b0_8_115200 },
2682         {       /* RockForceD1 */
2683                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
2684                 PCI_VENDOR_ID_MAINPINE, 0x2000,
2685                 0, 0, pbn_b0_1_115200 },
2686         {       /* RockForceF1 */
2687                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
2688                 PCI_VENDOR_ID_MAINPINE, 0x2100,
2689                 0, 0, pbn_b0_1_115200 },
2690         {       /* RockForceD2 */
2691                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
2692                 PCI_VENDOR_ID_MAINPINE, 0x2200,
2693                 0, 0, pbn_b0_2_115200 },
2694         {       /* RockForceF2 */
2695                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
2696                 PCI_VENDOR_ID_MAINPINE, 0x2300,
2697                 0, 0, pbn_b0_2_115200 },
2698         {       /* RockForceD4 */
2699                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
2700                 PCI_VENDOR_ID_MAINPINE, 0x2400,
2701                 0, 0, pbn_b0_4_115200 },
2702         {       /* RockForceF4 */
2703                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
2704                 PCI_VENDOR_ID_MAINPINE, 0x2500,
2705                 0, 0, pbn_b0_4_115200 },
2706         {       /* RockForceD8 */
2707                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
2708                 PCI_VENDOR_ID_MAINPINE, 0x2600,
2709                 0, 0, pbn_b0_8_115200 },
2710         {       /* RockForceF8 */
2711                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
2712                 PCI_VENDOR_ID_MAINPINE, 0x2700,
2713                 0, 0, pbn_b0_8_115200 },
2714         {       /* IQ Express D1 */
2715                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
2716                 PCI_VENDOR_ID_MAINPINE, 0x3000,
2717                 0, 0, pbn_b0_1_115200 },
2718         {       /* IQ Express F1 */
2719                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
2720                 PCI_VENDOR_ID_MAINPINE, 0x3100,
2721                 0, 0, pbn_b0_1_115200 },
2722         {       /* IQ Express D2 */
2723                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
2724                 PCI_VENDOR_ID_MAINPINE, 0x3200,
2725                 0, 0, pbn_b0_2_115200 },
2726         {       /* IQ Express F2 */
2727                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
2728                 PCI_VENDOR_ID_MAINPINE, 0x3300,
2729                 0, 0, pbn_b0_2_115200 },
2730         {       /* IQ Express D4 */
2731                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
2732                 PCI_VENDOR_ID_MAINPINE, 0x3400,
2733                 0, 0, pbn_b0_4_115200 },
2734         {       /* IQ Express F4 */
2735                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
2736                 PCI_VENDOR_ID_MAINPINE, 0x3500,
2737                 0, 0, pbn_b0_4_115200 },
2738         {       /* IQ Express D8 */
2739                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
2740                 PCI_VENDOR_ID_MAINPINE, 0x3C00,
2741                 0, 0, pbn_b0_8_115200 },
2742         {       /* IQ Express F8 */
2743                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
2744                 PCI_VENDOR_ID_MAINPINE, 0x3D00,
2745                 0, 0, pbn_b0_8_115200 },
2746
2747
2748         /*
2749          * PA Semi PA6T-1682M on-chip UART
2750          */
2751         {       PCI_VENDOR_ID_PASEMI, 0xa004,
2752                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2753                 pbn_pasemi_1682M },
2754
2755         /*
2756         * ADDI-DATA GmbH communication cards <info@addi-data.com>
2757         */
2758         {       PCI_VENDOR_ID_ADDIDATA,
2759                 PCI_DEVICE_ID_ADDIDATA_APCI7500,
2760                 PCI_ANY_ID,
2761                 PCI_ANY_ID,
2762                 0,
2763                 0,
2764                 pbn_b0_4_115200 },
2765
2766         {       PCI_VENDOR_ID_ADDIDATA,
2767                 PCI_DEVICE_ID_ADDIDATA_APCI7420,
2768                 PCI_ANY_ID,
2769                 PCI_ANY_ID,
2770                 0,
2771                 0,
2772                 pbn_b0_2_115200 },
2773
2774         {       PCI_VENDOR_ID_ADDIDATA,
2775                 PCI_DEVICE_ID_ADDIDATA_APCI7300,
2776                 PCI_ANY_ID,
2777                 PCI_ANY_ID,
2778                 0,
2779                 0,
2780                 pbn_b0_1_115200 },
2781
2782         {       PCI_VENDOR_ID_ADDIDATA_OLD,
2783                 PCI_DEVICE_ID_ADDIDATA_APCI7800,
2784                 PCI_ANY_ID,
2785                 PCI_ANY_ID,
2786                 0,
2787                 0,
2788                 pbn_b1_8_115200 },
2789
2790         {       PCI_VENDOR_ID_ADDIDATA,
2791                 PCI_DEVICE_ID_ADDIDATA_APCI7500_2,
2792                 PCI_ANY_ID,
2793                 PCI_ANY_ID,
2794                 0,
2795                 0,
2796                 pbn_b0_4_115200 },
2797
2798         {       PCI_VENDOR_ID_ADDIDATA,
2799                 PCI_DEVICE_ID_ADDIDATA_APCI7420_2,
2800                 PCI_ANY_ID,
2801                 PCI_ANY_ID,
2802                 0,
2803                 0,
2804                 pbn_b0_2_115200 },
2805
2806         {       PCI_VENDOR_ID_ADDIDATA,
2807                 PCI_DEVICE_ID_ADDIDATA_APCI7300_2,
2808                 PCI_ANY_ID,
2809                 PCI_ANY_ID,
2810                 0,
2811                 0,
2812                 pbn_b0_1_115200 },
2813
2814         {       PCI_VENDOR_ID_ADDIDATA,
2815                 PCI_DEVICE_ID_ADDIDATA_APCI7500_3,
2816                 PCI_ANY_ID,
2817                 PCI_ANY_ID,
2818                 0,
2819                 0,
2820                 pbn_b0_4_115200 },
2821
2822         {       PCI_VENDOR_ID_ADDIDATA,
2823                 PCI_DEVICE_ID_ADDIDATA_APCI7420_3,
2824                 PCI_ANY_ID,
2825                 PCI_ANY_ID,
2826                 0,
2827                 0,
2828                 pbn_b0_2_115200 },
2829
2830         {       PCI_VENDOR_ID_ADDIDATA,
2831                 PCI_DEVICE_ID_ADDIDATA_APCI7300_3,
2832                 PCI_ANY_ID,
2833                 PCI_ANY_ID,
2834                 0,
2835                 0,
2836                 pbn_b0_1_115200 },
2837
2838         {       PCI_VENDOR_ID_ADDIDATA,
2839                 PCI_DEVICE_ID_ADDIDATA_APCI7800_3,
2840                 PCI_ANY_ID,
2841                 PCI_ANY_ID,
2842                 0,
2843                 0,
2844                 pbn_b0_8_115200 },
2845
2846         /*
2847          * These entries match devices with class COMMUNICATION_SERIAL,
2848          * COMMUNICATION_MODEM or COMMUNICATION_MULTISERIAL
2849          */
2850         {       PCI_ANY_ID, PCI_ANY_ID,
2851                 PCI_ANY_ID, PCI_ANY_ID,
2852                 PCI_CLASS_COMMUNICATION_SERIAL << 8,
2853                 0xffff00, pbn_default },
2854         {       PCI_ANY_ID, PCI_ANY_ID,
2855                 PCI_ANY_ID, PCI_ANY_ID,
2856                 PCI_CLASS_COMMUNICATION_MODEM << 8,
2857                 0xffff00, pbn_default },
2858         {       PCI_ANY_ID, PCI_ANY_ID,
2859                 PCI_ANY_ID, PCI_ANY_ID,
2860                 PCI_CLASS_COMMUNICATION_MULTISERIAL << 8,
2861                 0xffff00, pbn_default },
2862         { 0, }
2863 };
2864
2865 static struct pci_driver serial_pci_driver = {
2866         .name           = "serial",
2867         .probe          = pciserial_init_one,
2868         .remove         = __devexit_p(pciserial_remove_one),
2869 #ifdef CONFIG_PM
2870         .suspend        = pciserial_suspend_one,
2871         .resume         = pciserial_resume_one,
2872 #endif
2873         .id_table       = serial_pci_tbl,
2874 };
2875
2876 static int __init serial8250_pci_init(void)
2877 {
2878         return pci_register_driver(&serial_pci_driver);
2879 }
2880
2881 static void __exit serial8250_pci_exit(void)
2882 {
2883         pci_unregister_driver(&serial_pci_driver);
2884 }
2885
2886 module_init(serial8250_pci_init);
2887 module_exit(serial8250_pci_exit);
2888
2889 MODULE_LICENSE("GPL");
2890 MODULE_DESCRIPTION("Generic 8250/16x50 PCI serial probe module");
2891 MODULE_DEVICE_TABLE(pci, serial_pci_tbl);