drivers/serial/8250_pci.c

   1 /*
   2  *  linux/drivers/char/8250_pci.c
   3  *
   4  *  Probe module for 8250/16550-type PCI serial ports.
   5  *
   6  *  Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o.
   7  *
   8  *  Copyright (C) 2001 Russell King, All Rights Reserved.
   9  *
  10  * This program is free software; you can redistribute it and/or modify
  11  * it under the terms of the GNU General Public License as published by
  12  * the Free Software Foundation; either version 2 of the License.
  13  *
  14  *  $Id: 8250_pci.c,v 1.28 2002/11/02 11:14:18 rmk Exp $
  15  */
  16 #include <linux/module.h>
  17 #include <linux/init.h>
  18 #include <linux/pci.h>
  19 #include <linux/sched.h>
  20 #include <linux/string.h>
  21 #include <linux/kernel.h>
  22 #include <linux/slab.h>
  23 #include <linux/delay.h>
  24 #include <linux/tty.h>
  25 #include <linux/serial_core.h>
  26 #include <linux/8250_pci.h>
  27 #include <linux/bitops.h>
  28
  29 #include <asm/byteorder.h>
  30 #include <asm/io.h>
  31
  32 #include "8250.h"
  33
  34 #undef SERIAL_DEBUG_PCI
  35
  36 /*
  37  * init function returns:
  38  *  > 0 - number of ports
  39  *  = 0 - use board->num_ports
  40  *  < 0 - error
  41  */
  42 struct pci_serial_quirk {
  43         u32     vendor;
  44         u32     device;
  45         u32     subvendor;
  46         u32     subdevice;
  47         int     (*init)(struct pci_dev *dev);
  48         int     (*setup)(struct serial_private *, struct pciserial_board *,
  49                          struct uart_port *, int);
  50         void    (*exit)(struct pci_dev *dev);
  51 };
  52
  53 #define PCI_NUM_BAR_RESOURCES   6
  54
  55 struct serial_private {
  56         struct pci_dev          *dev;
  57         unsigned int            nr;
  58         void __iomem            *remapped_bar[PCI_NUM_BAR_RESOURCES];
  59         struct pci_serial_quirk *quirk;
  60         int                     line[0];
  61 };
  62
  63 static void moan_device(const char *str, struct pci_dev *dev)
  64 {
  65         printk(KERN_WARNING "%s: %s\n"
  66                KERN_WARNING "Please send the output of lspci -vv, this\n"
  67                KERN_WARNING "message (0x%04x,0x%04x,0x%04x,0x%04x), the\n"
  68                KERN_WARNING "manufacturer and name of serial board or\n"
  69                KERN_WARNING "modem board to rmk+serial@arm.linux.org.uk.\n",
  70                pci_name(dev), str, dev->vendor, dev->device,
  71                dev->subsystem_vendor, dev->subsystem_device);
  72 }
  73
  74 static int
  75 setup_port(struct serial_private *priv, struct uart_port *port,
  76            int bar, int offset, int regshift)
  77 {
  78         struct pci_dev *dev = priv->dev;
  79         unsigned long base, len;
  80
  81         if (bar >= PCI_NUM_BAR_RESOURCES)
  82                 return -EINVAL;
  83
  84         base = pci_resource_start(dev, bar);
  85
  86         if (pci_resource_flags(dev, bar) & IORESOURCE_MEM) {
  87                 len =  pci_resource_len(dev, bar);
  88
  89                 if (!priv->remapped_bar[bar])
  90                         priv->remapped_bar[bar] = ioremap(base, len);
  91                 if (!priv->remapped_bar[bar])
  92                         return -ENOMEM;
  93
  94                 port->iotype = UPIO_MEM;
  95                 port->iobase = 0;
  96                 port->mapbase = base + offset;
  97                 port->membase = priv->remapped_bar[bar] + offset;
  98                 port->regshift = regshift;
  99         } else {
 100                 port->iotype = UPIO_PORT;
 101                 port->iobase = base + offset;
 102                 port->mapbase = 0;
 103                 port->membase = NULL;
 104                 port->regshift = 0;
 105         }
 106         return 0;
 107 }
 108
 109 /*
 110  * AFAVLAB uses a different mixture of BARs and offsets
 111  * Not that ugly ;) -- HW
 112  */
 113 static int
 114 afavlab_setup(struct serial_private *priv, struct pciserial_board *board,
 115               struct uart_port *port, int idx)
 116 {
 117         unsigned int bar, offset = board->first_offset;
 118
 119         bar = FL_GET_BASE(board->flags);
 120         if (idx < 4)
 121                 bar += idx;
 122         else {
 123                 bar = 4;
 124                 offset += (idx - 4) * board->uart_offset;
 125         }
 126
 127         return setup_port(priv, port, bar, offset, board->reg_shift);
 128 }
 129
 130 /*
 131  * HP's Remote Management Console.  The Diva chip came in several
 132  * different versions.  N-class, L2000 and A500 have two Diva chips, each
 133  * with 3 UARTs (the third UART on the second chip is unused).  Superdome
 134  * and Keystone have one Diva chip with 3 UARTs.  Some later machines have
 135  * one Diva chip, but it has been expanded to 5 UARTs.
 136  */
 137 static int __devinit pci_hp_diva_init(struct pci_dev *dev)
 138 {
 139         int rc = 0;
 140
 141         switch (dev->subsystem_device) {
 142         case PCI_DEVICE_ID_HP_DIVA_TOSCA1:
 143         case PCI_DEVICE_ID_HP_DIVA_HALFDOME:
 144         case PCI_DEVICE_ID_HP_DIVA_KEYSTONE:
 145         case PCI_DEVICE_ID_HP_DIVA_EVEREST:
 146                 rc = 3;
 147                 break;
 148         case PCI_DEVICE_ID_HP_DIVA_TOSCA2:
 149                 rc = 2;
 150                 break;
 151         case PCI_DEVICE_ID_HP_DIVA_MAESTRO:
 152                 rc = 4;
 153                 break;
 154         case PCI_DEVICE_ID_HP_DIVA_POWERBAR:
 155                 rc = 1;
 156                 break;
 157         }
 158
 159         return rc;
 160 }
 161
 162 /*
 163  * HP's Diva chip puts the 4th/5th serial port further out, and
 164  * some serial ports are supposed to be hidden on certain models.
 165  */
 166 static int
 167 pci_hp_diva_setup(struct serial_private *priv, struct pciserial_board *board,
 168               struct uart_port *port, int idx)
 169 {
 170         unsigned int offset = board->first_offset;
 171         unsigned int bar = FL_GET_BASE(board->flags);
 172
 173         switch (priv->dev->subsystem_device) {
 174         case PCI_DEVICE_ID_HP_DIVA_MAESTRO:
 175                 if (idx == 3)
 176                         idx++;
 177                 break;
 178         case PCI_DEVICE_ID_HP_DIVA_EVEREST:
 179                 if (idx > 0)
 180                         idx++;
 181                 if (idx > 2)
 182                         idx++;
 183                 break;
 184         }
 185         if (idx > 2)
 186                 offset = 0x18;
 187
 188         offset += idx * board->uart_offset;
 189
 190         return setup_port(priv, port, bar, offset, board->reg_shift);
 191 }
 192
 193 /*
 194  * Added for EKF Intel i960 serial boards
 195  */
 196 static int __devinit pci_inteli960ni_init(struct pci_dev *dev)
 197 {
 198         unsigned long oldval;
 199
 200         if (!(dev->subsystem_device & 0x1000))
 201                 return -ENODEV;
 202
 203         /* is firmware started? */
 204         pci_read_config_dword(dev, 0x44, (void*) &oldval);
 205         if (oldval == 0x00001000L) { /* RESET value */
 206                 printk(KERN_DEBUG "Local i960 firmware missing");
 207                 return -ENODEV;
 208         }
 209         return 0;
 210 }
 211
 212 /*
 213  * Some PCI serial cards using the PLX 9050 PCI interface chip require
 214  * that the card interrupt be explicitly enabled or disabled.  This
 215  * seems to be mainly needed on card using the PLX which also use I/O
 216  * mapped memory.
 217  */
 218 static int __devinit pci_plx9050_init(struct pci_dev *dev)
 219 {
 220         u8 irq_config;
 221         void __iomem *p;
 222
 223         if ((pci_resource_flags(dev, 0) & IORESOURCE_MEM) == 0) {
 224                 moan_device("no memory in bar 0", dev);
 225                 return 0;
 226         }
 227
 228         irq_config = 0x41;
 229         if (dev->vendor == PCI_VENDOR_ID_PANACOM)
 230                 irq_config = 0x43;
 231         if ((dev->vendor == PCI_VENDOR_ID_PLX) &&
 232             (dev->device == PCI_DEVICE_ID_PLX_ROMULUS)) {
 233                 /*
 234                  * As the megawolf cards have the int pins active
 235                  * high, and have 2 UART chips, both ints must be
 236                  * enabled on the 9050. Also, the UARTS are set in
 237                  * 16450 mode by default, so we have to enable the
 238                  * 16C950 'enhanced' mode so that we can use the
 239                  * deep FIFOs
 240                  */
 241                 irq_config = 0x5b;
 242         }
 243
 244         /*
 245          * enable/disable interrupts
 246          */
 247         p = ioremap(pci_resource_start(dev, 0), 0x80);
 248         if (p == NULL)
 249                 return -ENOMEM;
 250         writel(irq_config, p + 0x4c);
 251
 252         /*
 253          * Read the register back to ensure that it took effect.
 254          */
 255         readl(p + 0x4c);
 256         iounmap(p);
 257
 258         return 0;
 259 }
 260
 261 static void __devexit pci_plx9050_exit(struct pci_dev *dev)
 262 {
 263         u8 __iomem *p;
 264
 265         if ((pci_resource_flags(dev, 0) & IORESOURCE_MEM) == 0)
 266                 return;
 267
 268         /*
 269          * disable interrupts
 270          */
 271         p = ioremap(pci_resource_start(dev, 0), 0x80);
 272         if (p != NULL) {
 273                 writel(0, p + 0x4c);
 274
 275                 /*
 276                  * Read the register back to ensure that it took effect.
 277                  */
 278                 readl(p + 0x4c);
 279                 iounmap(p);
 280         }
 281 }
 282
 283 /* SBS Technologies Inc. PMC-OCTPRO and P-OCTAL cards */
 284 static int
 285 sbs_setup(struct serial_private *priv, struct pciserial_board *board,
 286                 struct uart_port *port, int idx)
 287 {
 288         unsigned int bar, offset = board->first_offset;
 289
 290         bar = 0;
 291
 292         if (idx < 4) {
 293                 /* first four channels map to 0, 0x100, 0x200, 0x300 */
 294                 offset += idx * board->uart_offset;
 295         } else if (idx < 8) {
 296                 /* last four channels map to 0x1000, 0x1100, 0x1200, 0x1300 */
 297                 offset += idx * board->uart_offset + 0xC00;
 298         } else /* we have only 8 ports on PMC-OCTALPRO */
 299                 return 1;
 300
 301         return setup_port(priv, port, bar, offset, board->reg_shift);
 302 }
 303
 304 /*
 305 * This does initialization for PMC OCTALPRO cards:
 306 * maps the device memory, resets the UARTs (needed, bc
 307 * if the module is removed and inserted again, the card
 308 * is in the sleep mode) and enables global interrupt.
 309 */
 310
 311 /* global control register offset for SBS PMC-OctalPro */
 312 #define OCT_REG_CR_OFF          0x500
 313
 314 static int __devinit sbs_init(struct pci_dev *dev)
 315 {
 316         u8 __iomem *p;
 317
 318         p = ioremap(pci_resource_start(dev, 0),pci_resource_len(dev,0));
 319
 320         if (p == NULL)
 321                 return -ENOMEM;
 322         /* Set bit-4 Control Register (UART RESET) in to reset the uarts */
 323         writeb(0x10,p + OCT_REG_CR_OFF);
 324         udelay(50);
 325         writeb(0x0,p + OCT_REG_CR_OFF);
 326
 327         /* Set bit-2 (INTENABLE) of Control Register */
 328         writeb(0x4, p + OCT_REG_CR_OFF);
 329         iounmap(p);
 330
 331         return 0;
 332 }
 333
 334 /*
 335  * Disables the global interrupt of PMC-OctalPro
 336  */
 337
 338 static void __devexit sbs_exit(struct pci_dev *dev)
 339 {
 340         u8 __iomem *p;
 341
 342         p = ioremap(pci_resource_start(dev, 0),pci_resource_len(dev,0));
 343         if (p != NULL) {
 344                 writeb(0, p + OCT_REG_CR_OFF);
 345         }
 346         iounmap(p);
 347 }
 348
 349 /*
 350  * SIIG serial cards have an PCI interface chip which also controls
 351  * the UART clocking frequency. Each UART can be clocked independently
 352  * (except cards equiped with 4 UARTs) and initial clocking settings
 353  * are stored in the EEPROM chip. It can cause problems because this
 354  * version of serial driver doesn't support differently clocked UART's
 355  * on single PCI card. To prevent this, initialization functions set
 356  * high frequency clocking for all UART's on given card. It is safe (I
 357  * hope) because it doesn't touch EEPROM settings to prevent conflicts
 358  * with other OSes (like M$ DOS).
 359  *
 360  *  SIIG support added by Andrey Panin <pazke@donpac.ru>, 10/1999
 361  *
 362  * There is two family of SIIG serial cards with different PCI
 363  * interface chip and different configuration methods:
 364  *     - 10x cards have control registers in IO and/or memory space;
 365  *     - 20x cards have control registers in standard PCI configuration space.
 366  *
 367  * Note: all 10x cards have PCI device ids 0x10..
 368  *       all 20x cards have PCI device ids 0x20..
 369  *
 370  * There are also Quartet Serial cards which use Oxford Semiconductor
 371  * 16954 quad UART PCI chip clocked by 18.432 MHz quartz.
 372  *
 373  * Note: some SIIG cards are probed by the parport_serial object.
 374  */
 375
 376 #define PCI_DEVICE_ID_SIIG_1S_10x (PCI_DEVICE_ID_SIIG_1S_10x_550 & 0xfffc)
 377 #define PCI_DEVICE_ID_SIIG_2S_10x (PCI_DEVICE_ID_SIIG_2S_10x_550 & 0xfff8)
 378
 379 static int pci_siig10x_init(struct pci_dev *dev)
 380 {
 381         u16 data;
 382         void __iomem *p;
 383
 384         switch (dev->device & 0xfff8) {
 385         case PCI_DEVICE_ID_SIIG_1S_10x: /* 1S */
 386                 data = 0xffdf;
 387                 break;
 388         case PCI_DEVICE_ID_SIIG_2S_10x: /* 2S, 2S1P */
 389                 data = 0xf7ff;
 390                 break;
 391         default:                        /* 1S1P, 4S */
 392                 data = 0xfffb;
 393                 break;
 394         }
 395
 396         p = ioremap(pci_resource_start(dev, 0), 0x80);
 397         if (p == NULL)
 398                 return -ENOMEM;
 399
 400         writew(readw(p + 0x28) & data, p + 0x28);
 401         readw(p + 0x28);
 402         iounmap(p);
 403         return 0;
 404 }
 405
 406 #define PCI_DEVICE_ID_SIIG_2S_20x (PCI_DEVICE_ID_SIIG_2S_20x_550 & 0xfffc)
 407 #define PCI_DEVICE_ID_SIIG_2S1P_20x (PCI_DEVICE_ID_SIIG_2S1P_20x_550 & 0xfffc)
 408
 409 static int pci_siig20x_init(struct pci_dev *dev)
 410 {
 411         u8 data;
 412
 413         /* Change clock frequency for the first UART. */
 414         pci_read_config_byte(dev, 0x6f, &data);
 415         pci_write_config_byte(dev, 0x6f, data & 0xef);
 416
 417         /* If this card has 2 UART, we have to do the same with second UART. */
 418         if (((dev->device & 0xfffc) == PCI_DEVICE_ID_SIIG_2S_20x) ||
 419             ((dev->device & 0xfffc) == PCI_DEVICE_ID_SIIG_2S1P_20x)) {
 420                 pci_read_config_byte(dev, 0x73, &data);
 421                 pci_write_config_byte(dev, 0x73, data & 0xef);
 422         }
 423         return 0;
 424 }
 425
 426 static int pci_siig_init(struct pci_dev *dev)
 427 {
 428         unsigned int type = dev->device & 0xff00;
 429
 430         if (type == 0x1000)
 431                 return pci_siig10x_init(dev);
 432         else if (type == 0x2000)
 433                 return pci_siig20x_init(dev);
 434
 435         moan_device("Unknown SIIG card", dev);
 436         return -ENODEV;
 437 }
 438
 439 /*
 440  * Timedia has an explosion of boards, and to avoid the PCI table from
 441  * growing *huge*, we use this function to collapse some 70 entries
 442  * in the PCI table into one, for sanity's and compactness's sake.
 443  */
 444 static unsigned short timedia_single_port[] = {
 445         0x4025, 0x4027, 0x4028, 0x5025, 0x5027, 0
 446 };
 447
 448 static unsigned short timedia_dual_port[] = {
 449         0x0002, 0x4036, 0x4037, 0x4038, 0x4078, 0x4079, 0x4085,
 450         0x4088, 0x4089, 0x5037, 0x5078, 0x5079, 0x5085, 0x6079,
 451         0x7079, 0x8079, 0x8137, 0x8138, 0x8237, 0x8238, 0x9079,
 452         0x9137, 0x9138, 0x9237, 0x9238, 0xA079, 0xB079, 0xC079,
 453         0xD079, 0
 454 };
 455
 456 static unsigned short timedia_quad_port[] = {
 457         0x4055, 0x4056, 0x4095, 0x4096, 0x5056, 0x8156, 0x8157,
 458         0x8256, 0x8257, 0x9056, 0x9156, 0x9157, 0x9158, 0x9159,
 459         0x9256, 0x9257, 0xA056, 0xA157, 0xA158, 0xA159, 0xB056,
 460         0xB157, 0
 461 };
 462
 463 static unsigned short timedia_eight_port[] = {
 464         0x4065, 0x4066, 0x5065, 0x5066, 0x8166, 0x9066, 0x9166,
 465         0x9167, 0x9168, 0xA066, 0xA167, 0xA168, 0
 466 };
 467
 468 static struct timedia_struct {
 469         int num;
 470         unsigned short *ids;
 471 } timedia_data[] = {
 472         { 1, timedia_single_port },
 473         { 2, timedia_dual_port },
 474         { 4, timedia_quad_port },
 475         { 8, timedia_eight_port },
 476         { 0, NULL }
 477 };
 478
 479 static int __devinit pci_timedia_init(struct pci_dev *dev)
 480 {
 481         unsigned short *ids;
 482         int i, j;
 483
 484         for (i = 0; timedia_data[i].num; i++) {
 485                 ids = timedia_data[i].ids;
 486                 for (j = 0; ids[j]; j++)
 487                         if (dev->subsystem_device == ids[j])
 488                                 return timedia_data[i].num;
 489         }
 490         return 0;
 491 }
 492
 493 /*
 494  * Timedia/SUNIX uses a mixture of BARs and offsets
 495  * Ugh, this is ugly as all hell --- TYT
 496  */
 497 static int
 498 pci_timedia_setup(struct serial_private *priv, struct pciserial_board *board,
 499                   struct uart_port *port, int idx)
 500 {
 501         unsigned int bar = 0, offset = board->first_offset;
 502
 503         switch (idx) {
 504         case 0:
 505                 bar = 0;
 506                 break;
 507         case 1:
 508                 offset = board->uart_offset;
 509                 bar = 0;
 510                 break;
 511         case 2:
 512                 bar = 1;
 513                 break;
 514         case 3:
 515                 offset = board->uart_offset;
 516                 bar = 1;
 517         case 4: /* BAR 2 */
 518         case 5: /* BAR 3 */
 519         case 6: /* BAR 4 */
 520         case 7: /* BAR 5 */
 521                 bar = idx - 2;
 522         }
 523
 524         return setup_port(priv, port, bar, offset, board->reg_shift);
 525 }
 526
 527 /*
 528  * Some Titan cards are also a little weird
 529  */
 530 static int
 531 titan_400l_800l_setup(struct serial_private *priv,
 532                       struct pciserial_board *board,
 533                       struct uart_port *port, int idx)
 534 {
 535         unsigned int bar, offset = board->first_offset;
 536
 537         switch (idx) {
 538         case 0:
 539                 bar = 1;
 540                 break;
 541         case 1:
 542                 bar = 2;
 543                 break;
 544         default:
 545                 bar = 4;
 546                 offset = (idx - 2) * board->uart_offset;
 547         }
 548
 549         return setup_port(priv, port, bar, offset, board->reg_shift);
 550 }
 551
 552 static int __devinit pci_xircom_init(struct pci_dev *dev)
 553 {
 554         msleep(100);
 555         return 0;
 556 }
 557
 558 static int __devinit pci_netmos_init(struct pci_dev *dev)
 559 {
 560         /* subdevice 0x00PS means <P> parallel, <S> serial */
 561         unsigned int num_serial = dev->subsystem_device & 0xf;
 562
 563         if (num_serial == 0)
 564                 return -ENODEV;
 565         return num_serial;
 566 }
 567
 568 static int
 569 pci_default_setup(struct serial_private *priv, struct pciserial_board *board,
 570                   struct uart_port *port, int idx)
 571 {
 572         unsigned int bar, offset = board->first_offset, maxnr;
 573
 574         bar = FL_GET_BASE(board->flags);
 575         if (board->flags & FL_BASE_BARS)
 576                 bar += idx;
 577         else
 578                 offset += idx * board->uart_offset;
 579
 580         maxnr = (pci_resource_len(priv->dev, bar) - board->first_offset) /
 581                 (8 << board->reg_shift);
 582
 583         if (board->flags & FL_REGION_SZ_CAP && idx >= maxnr)
 584                 return 1;
 585
 586         return setup_port(priv, port, bar, offset, board->reg_shift);
 587 }
 588
 589 /* This should be in linux/pci_ids.h */
 590 #define PCI_VENDOR_ID_SBSMODULARIO      0x124B
 591 #define PCI_SUBVENDOR_ID_SBSMODULARIO   0x124B
 592 #define PCI_DEVICE_ID_OCTPRO            0x0001
 593 #define PCI_SUBDEVICE_ID_OCTPRO232      0x0108
 594 #define PCI_SUBDEVICE_ID_OCTPRO422      0x0208
 595 #define PCI_SUBDEVICE_ID_POCTAL232      0x0308
 596 #define PCI_SUBDEVICE_ID_POCTAL422      0x0408
 597
 598 /*
 599  * Master list of serial port init/setup/exit quirks.
 600  * This does not describe the general nature of the port.
 601  * (ie, baud base, number and location of ports, etc)
 602  *
 603  * This list is ordered alphabetically by vendor then device.
 604  * Specific entries must come before more generic entries.
 605  */
 606 static struct pci_serial_quirk pci_serial_quirks[] = {
 607         /*
 608          * AFAVLAB cards.
 609          *  It is not clear whether this applies to all products.
 610          */
 611         {
 612                 .vendor         = PCI_VENDOR_ID_AFAVLAB,
 613                 .device         = PCI_ANY_ID,
 614                 .subvendor      = PCI_ANY_ID,
 615                 .subdevice      = PCI_ANY_ID,
 616                 .setup          = afavlab_setup,
 617         },
 618         /*
 619          * HP Diva
 620          */
 621         {
 622                 .vendor         = PCI_VENDOR_ID_HP,
 623                 .device         = PCI_DEVICE_ID_HP_DIVA,
 624                 .subvendor      = PCI_ANY_ID,
 625                 .subdevice      = PCI_ANY_ID,
 626                 .init           = pci_hp_diva_init,
 627                 .setup          = pci_hp_diva_setup,
 628         },
 629         /*
 630          * Intel
 631          */
 632         {
 633                 .vendor         = PCI_VENDOR_ID_INTEL,
 634                 .device         = PCI_DEVICE_ID_INTEL_80960_RP,
 635                 .subvendor      = 0xe4bf,
 636                 .subdevice      = PCI_ANY_ID,
 637                 .init           = pci_inteli960ni_init,
 638                 .setup          = pci_default_setup,
 639         },
 640         /*
 641          * Panacom
 642          */
 643         {
 644                 .vendor         = PCI_VENDOR_ID_PANACOM,
 645                 .device         = PCI_DEVICE_ID_PANACOM_QUADMODEM,
 646                 .subvendor      = PCI_ANY_ID,
 647                 .subdevice      = PCI_ANY_ID,
 648                 .init           = pci_plx9050_init,
 649                 .setup          = pci_default_setup,
 650                 .exit           = __devexit_p(pci_plx9050_exit),
 651         },
 652         {
 653                 .vendor         = PCI_VENDOR_ID_PANACOM,
 654                 .device         = PCI_DEVICE_ID_PANACOM_DUALMODEM,
 655                 .subvendor      = PCI_ANY_ID,
 656                 .subdevice      = PCI_ANY_ID,
 657                 .init           = pci_plx9050_init,
 658                 .setup          = pci_default_setup,
 659                 .exit           = __devexit_p(pci_plx9050_exit),
 660         },
 661         /*
 662          * PLX
 663          */
 664         {
 665                 .vendor         = PCI_VENDOR_ID_PLX,
 666                 .device         = PCI_DEVICE_ID_PLX_9050,
 667                 .subvendor      = PCI_SUBVENDOR_ID_KEYSPAN,
 668                 .subdevice      = PCI_SUBDEVICE_ID_KEYSPAN_SX2,
 669                 .init           = pci_plx9050_init,
 670                 .setup          = pci_default_setup,
 671                 .exit           = __devexit_p(pci_plx9050_exit),
 672         },
 673         {
 674                 .vendor         = PCI_VENDOR_ID_PLX,
 675                 .device         = PCI_DEVICE_ID_PLX_ROMULUS,
 676                 .subvendor      = PCI_VENDOR_ID_PLX,
 677                 .subdevice      = PCI_DEVICE_ID_PLX_ROMULUS,
 678                 .init           = pci_plx9050_init,
 679                 .setup          = pci_default_setup,
 680                 .exit           = __devexit_p(pci_plx9050_exit),
 681         },
 682         /*
 683          * SBS Technologies, Inc., PMC-OCTALPRO 232
 684          */
 685         {
 686                 .vendor         = PCI_VENDOR_ID_SBSMODULARIO,
 687                 .device         = PCI_DEVICE_ID_OCTPRO,
 688                 .subvendor      = PCI_SUBVENDOR_ID_SBSMODULARIO,
 689                 .subdevice      = PCI_SUBDEVICE_ID_OCTPRO232,
 690                 .init           = sbs_init,
 691                 .setup          = sbs_setup,
 692                 .exit           = __devexit_p(sbs_exit),
 693         },
 694         /*
 695          * SBS Technologies, Inc., PMC-OCTALPRO 422
 696          */
 697         {
 698                 .vendor         = PCI_VENDOR_ID_SBSMODULARIO,
 699                 .device         = PCI_DEVICE_ID_OCTPRO,
 700                 .subvendor      = PCI_SUBVENDOR_ID_SBSMODULARIO,
 701                 .subdevice      = PCI_SUBDEVICE_ID_OCTPRO422,
 702                 .init           = sbs_init,
 703                 .setup          = sbs_setup,
 704                 .exit           = __devexit_p(sbs_exit),
 705         },
 706         /*
 707          * SBS Technologies, Inc., P-Octal 232
 708          */
 709         {
 710                 .vendor         = PCI_VENDOR_ID_SBSMODULARIO,
 711                 .device         = PCI_DEVICE_ID_OCTPRO,
 712                 .subvendor      = PCI_SUBVENDOR_ID_SBSMODULARIO,
 713                 .subdevice      = PCI_SUBDEVICE_ID_POCTAL232,
 714                 .init           = sbs_init,
 715                 .setup          = sbs_setup,
 716                 .exit           = __devexit_p(sbs_exit),
 717         },
 718         /*
 719          * SBS Technologies, Inc., P-Octal 422
 720          */
 721         {
 722                 .vendor         = PCI_VENDOR_ID_SBSMODULARIO,
 723                 .device         = PCI_DEVICE_ID_OCTPRO,
 724                 .subvendor      = PCI_SUBVENDOR_ID_SBSMODULARIO,
 725                 .subdevice      = PCI_SUBDEVICE_ID_POCTAL422,
 726                 .init           = sbs_init,
 727                 .setup          = sbs_setup,
 728                 .exit           = __devexit_p(sbs_exit),
 729         },
 730         /*
 731          * SIIG cards.
 732          */
 733         {
 734                 .vendor         = PCI_VENDOR_ID_SIIG,
 735                 .device         = PCI_ANY_ID,
 736                 .subvendor      = PCI_ANY_ID,
 737                 .subdevice      = PCI_ANY_ID,
 738                 .init           = pci_siig_init,
 739                 .setup          = pci_default_setup,
 740         },
 741         /*
 742          * Titan cards
 743          */
 744         {
 745                 .vendor         = PCI_VENDOR_ID_TITAN,
 746                 .device         = PCI_DEVICE_ID_TITAN_400L,
 747                 .subvendor      = PCI_ANY_ID,
 748                 .subdevice      = PCI_ANY_ID,
 749                 .setup          = titan_400l_800l_setup,
 750         },
 751         {
 752                 .vendor         = PCI_VENDOR_ID_TITAN,
 753                 .device         = PCI_DEVICE_ID_TITAN_800L,
 754                 .subvendor      = PCI_ANY_ID,
 755                 .subdevice      = PCI_ANY_ID,
 756                 .setup          = titan_400l_800l_setup,
 757         },
 758         /*
 759          * Timedia cards
 760          */
 761         {
 762                 .vendor         = PCI_VENDOR_ID_TIMEDIA,
 763                 .device         = PCI_DEVICE_ID_TIMEDIA_1889,
 764                 .subvendor      = PCI_VENDOR_ID_TIMEDIA,
 765                 .subdevice      = PCI_ANY_ID,
 766                 .init           = pci_timedia_init,
 767                 .setup          = pci_timedia_setup,
 768         },
 769         {
 770                 .vendor         = PCI_VENDOR_ID_TIMEDIA,
 771                 .device         = PCI_ANY_ID,
 772                 .subvendor      = PCI_ANY_ID,
 773                 .subdevice      = PCI_ANY_ID,
 774                 .setup          = pci_timedia_setup,
 775         },
 776         /*
 777          * Xircom cards
 778          */
 779         {
 780                 .vendor         = PCI_VENDOR_ID_XIRCOM,
 781                 .device         = PCI_DEVICE_ID_XIRCOM_X3201_MDM,
 782                 .subvendor      = PCI_ANY_ID,
 783                 .subdevice      = PCI_ANY_ID,
 784                 .init           = pci_xircom_init,
 785                 .setup          = pci_default_setup,
 786         },
 787         /*
 788          * Netmos cards
 789          */
 790         {
 791                 .vendor         = PCI_VENDOR_ID_NETMOS,
 792                 .device         = PCI_ANY_ID,
 793                 .subvendor      = PCI_ANY_ID,
 794                 .subdevice      = PCI_ANY_ID,
 795                 .init           = pci_netmos_init,
 796                 .setup          = pci_default_setup,
 797         },
 798         /*
 799          * Default "match everything" terminator entry
 800          */
 801         {
 802                 .vendor         = PCI_ANY_ID,
 803                 .device         = PCI_ANY_ID,
 804                 .subvendor      = PCI_ANY_ID,
 805                 .subdevice      = PCI_ANY_ID,
 806                 .setup          = pci_default_setup,
 807         }
 808 };
 809
 810 static inline int quirk_id_matches(u32 quirk_id, u32 dev_id)
 811 {
 812         return quirk_id == PCI_ANY_ID || quirk_id == dev_id;
 813 }
 814
 815 static struct pci_serial_quirk *find_quirk(struct pci_dev *dev)
 816 {
 817         struct pci_serial_quirk *quirk;
 818
 819         for (quirk = pci_serial_quirks; ; quirk++)
 820                 if (quirk_id_matches(quirk->vendor, dev->vendor) &&
 821                     quirk_id_matches(quirk->device, dev->device) &&
 822                     quirk_id_matches(quirk->subvendor, dev->subsystem_vendor) &&
 823                     quirk_id_matches(quirk->subdevice, dev->subsystem_device))
 824                         break;
 825         return quirk;
 826 }
 827
 828 static _INLINE_ int
 829 get_pci_irq(struct pci_dev *dev, struct pciserial_board *board)
 830 {
 831         if (board->flags & FL_NOIRQ)
 832                 return 0;
 833         else
 834                 return dev->irq;
 835 }
 836
 837 /*
 838  * This is the configuration table for all of the PCI serial boards
 839  * which we support.  It is directly indexed by the pci_board_num_t enum
 840  * value, which is encoded in the pci_device_id PCI probe table's
 841  * driver_data member.
 842  *
 843  * The makeup of these names are:
 844  *  pbn_bn{_bt}_n_baud
 845  *
 846  *  bn   = PCI BAR number
 847  *  bt   = Index using PCI BARs
 848  *  n    = number of serial ports
 849  *  baud = baud rate
 850  *
 851  * This table is sorted by (in order): baud, bt, bn, n.
 852  *
 853  * Please note: in theory if n = 1, _bt infix should make no difference.
 854  * ie, pbn_b0_1_115200 is the same as pbn_b0_bt_1_115200
 855  */
 856 enum pci_board_num_t {
 857         pbn_default = 0,
 858
 859         pbn_b0_1_115200,
 860         pbn_b0_2_115200,
 861         pbn_b0_4_115200,
 862         pbn_b0_5_115200,
 863
 864         pbn_b0_1_921600,
 865         pbn_b0_2_921600,
 866         pbn_b0_4_921600,
 867
 868         pbn_b0_4_1152000,
 869
 870         pbn_b0_bt_1_115200,
 871         pbn_b0_bt_2_115200,
 872         pbn_b0_bt_8_115200,
 873
 874         pbn_b0_bt_1_460800,
 875         pbn_b0_bt_2_460800,
 876         pbn_b0_bt_4_460800,
 877
 878         pbn_b0_bt_1_921600,
 879         pbn_b0_bt_2_921600,
 880         pbn_b0_bt_4_921600,
 881         pbn_b0_bt_8_921600,
 882
 883         pbn_b1_1_115200,
 884         pbn_b1_2_115200,
 885         pbn_b1_4_115200,
 886         pbn_b1_8_115200,
 887
 888         pbn_b1_1_921600,
 889         pbn_b1_2_921600,
 890         pbn_b1_4_921600,
 891         pbn_b1_8_921600,
 892
 893         pbn_b1_bt_2_921600,
 894
 895         pbn_b1_1_1382400,
 896         pbn_b1_2_1382400,
 897         pbn_b1_4_1382400,
 898         pbn_b1_8_1382400,
 899
 900         pbn_b2_1_115200,
 901         pbn_b2_8_115200,
 902
 903         pbn_b2_1_460800,
 904         pbn_b2_4_460800,
 905         pbn_b2_8_460800,
 906         pbn_b2_16_460800,
 907
 908         pbn_b2_1_921600,
 909         pbn_b2_4_921600,
 910         pbn_b2_8_921600,
 911
 912         pbn_b2_bt_1_115200,
 913         pbn_b2_bt_2_115200,
 914         pbn_b2_bt_4_115200,
 915
 916         pbn_b2_bt_2_921600,
 917         pbn_b2_bt_4_921600,
 918
 919         pbn_b3_4_115200,
 920         pbn_b3_8_115200,
 921
 922         /*
 923          * Board-specific versions.
 924          */
 925         pbn_panacom,
 926         pbn_panacom2,
 927         pbn_panacom4,
 928         pbn_plx_romulus,
 929         pbn_oxsemi,
 930         pbn_intel_i960,
 931         pbn_sgi_ioc3,
 932         pbn_nec_nile4,
 933         pbn_computone_4,
 934         pbn_computone_6,
 935         pbn_computone_8,
 936         pbn_sbsxrsio,
 937         pbn_exar_XR17C152,
 938         pbn_exar_XR17C154,
 939         pbn_exar_XR17C158,
 940 };
 941
 942 /*
 943  * uart_offset - the space between channels
 944  * reg_shift   - describes how the UART registers are mapped
 945  *               to PCI memory by the card.
 946  * For example IER register on SBS, Inc. PMC-OctPro is located at
 947  * offset 0x10 from the UART base, while UART_IER is defined as 1
 948  * in include/linux/serial_reg.h,
 949  * see first lines of serial_in() and serial_out() in 8250.c
 950 */
 951
 952 static struct pciserial_board pci_boards[] __devinitdata = {
 953         [pbn_default] = {
 954                 .flags          = FL_BASE0,
 955                 .num_ports      = 1,
 956                 .base_baud      = 115200,
 957                 .uart_offset    = 8,
 958         },
 959         [pbn_b0_1_115200] = {
 960                 .flags          = FL_BASE0,
 961                 .num_ports      = 1,
 962                 .base_baud      = 115200,
 963                 .uart_offset    = 8,
 964         },
 965         [pbn_b0_2_115200] = {
 966                 .flags          = FL_BASE0,
 967                 .num_ports      = 2,
 968                 .base_baud      = 115200,
 969                 .uart_offset    = 8,
 970         },
 971         [pbn_b0_4_115200] = {
 972                 .flags          = FL_BASE0,
 973                 .num_ports      = 4,
 974                 .base_baud      = 115200,
 975                 .uart_offset    = 8,
 976         },
 977         [pbn_b0_5_115200] = {
 978                 .flags          = FL_BASE0,
 979                 .num_ports      = 5,
 980                 .base_baud      = 115200,
 981                 .uart_offset    = 8,
 982         },
 983
 984         [pbn_b0_1_921600] = {
 985                 .flags          = FL_BASE0,
 986                 .num_ports      = 1,
 987                 .base_baud      = 921600,
 988                 .uart_offset    = 8,
 989         },
 990         [pbn_b0_2_921600] = {
 991                 .flags          = FL_BASE0,
 992                 .num_ports      = 2,
 993                 .base_baud      = 921600,
 994                 .uart_offset    = 8,
 995         },
 996         [pbn_b0_4_921600] = {
 997                 .flags          = FL_BASE0,
 998                 .num_ports      = 4,
 999                 .base_baud      = 921600,
1000                 .uart_offset    = 8,
1001         },
1002         [pbn_b0_4_1152000] = {
1003                 .flags          = FL_BASE0,
1004                 .num_ports      = 4,
1005                 .base_baud      = 1152000,
1006                 .uart_offset    = 8,
1007         },
1008
1009         [pbn_b0_bt_1_115200] = {
1010                 .flags          = FL_BASE0|FL_BASE_BARS,
1011                 .num_ports      = 1,
1012                 .base_baud      = 115200,
1013                 .uart_offset    = 8,
1014         },
1015         [pbn_b0_bt_2_115200] = {
1016                 .flags          = FL_BASE0|FL_BASE_BARS,
1017                 .num_ports      = 2,
1018                 .base_baud      = 115200,
1019                 .uart_offset    = 8,
1020         },
1021         [pbn_b0_bt_8_115200] = {
1022                 .flags          = FL_BASE0|FL_BASE_BARS,
1023                 .num_ports      = 8,
1024                 .base_baud      = 115200,
1025                 .uart_offset    = 8,
1026         },
1027
1028         [pbn_b0_bt_1_460800] = {
1029                 .flags          = FL_BASE0|FL_BASE_BARS,
1030                 .num_ports      = 1,
1031                 .base_baud      = 460800,
1032                 .uart_offset    = 8,
1033         },
1034         [pbn_b0_bt_2_460800] = {
1035                 .flags          = FL_BASE0|FL_BASE_BARS,
1036                 .num_ports      = 2,
1037                 .base_baud      = 460800,
1038                 .uart_offset    = 8,
1039         },
1040         [pbn_b0_bt_4_460800] = {
1041                 .flags          = FL_BASE0|FL_BASE_BARS,
1042                 .num_ports      = 4,
1043                 .base_baud      = 460800,
1044                 .uart_offset    = 8,
1045         },
1046
1047         [pbn_b0_bt_1_921600] = {
1048                 .flags          = FL_BASE0|FL_BASE_BARS,
1049                 .num_ports      = 1,
1050                 .base_baud      = 921600,
1051                 .uart_offset    = 8,
1052         },
1053         [pbn_b0_bt_2_921600] = {
1054                 .flags          = FL_BASE0|FL_BASE_BARS,
1055                 .num_ports      = 2,
1056                 .base_baud      = 921600,
1057                 .uart_offset    = 8,
1058         },
1059         [pbn_b0_bt_4_921600] = {
1060                 .flags          = FL_BASE0|FL_BASE_BARS,
1061                 .num_ports      = 4,
1062                 .base_baud      = 921600,
1063                 .uart_offset    = 8,
1064         },
1065         [pbn_b0_bt_8_921600] = {
1066                 .flags          = FL_BASE0|FL_BASE_BARS,
1067                 .num_ports      = 8,
1068                 .base_baud      = 921600,
1069                 .uart_offset    = 8,
1070         },
1071
1072         [pbn_b1_1_115200] = {
1073                 .flags          = FL_BASE1,
1074                 .num_ports      = 1,
1075                 .base_baud      = 115200,
1076                 .uart_offset    = 8,
1077         },
1078         [pbn_b1_2_115200] = {
1079                 .flags          = FL_BASE1,
1080                 .num_ports      = 2,
1081                 .base_baud      = 115200,
1082                 .uart_offset    = 8,
1083         },
1084         [pbn_b1_4_115200] = {
1085                 .flags          = FL_BASE1,
1086                 .num_ports      = 4,
1087                 .base_baud      = 115200,
1088                 .uart_offset    = 8,
1089         },
1090         [pbn_b1_8_115200] = {
1091                 .flags          = FL_BASE1,
1092                 .num_ports      = 8,
1093                 .base_baud      = 115200,
1094                 .uart_offset    = 8,
1095         },
1096
1097         [pbn_b1_1_921600] = {
1098                 .flags          = FL_BASE1,
1099                 .num_ports      = 1,
1100                 .base_baud      = 921600,
1101                 .uart_offset    = 8,
1102         },
1103         [pbn_b1_2_921600] = {
1104                 .flags          = FL_BASE1,
1105                 .num_ports      = 2,
1106                 .base_baud      = 921600,
1107                 .uart_offset    = 8,
1108         },
1109         [pbn_b1_4_921600] = {
1110                 .flags          = FL_BASE1,
1111                 .num_ports      = 4,
1112                 .base_baud      = 921600,
1113                 .uart_offset    = 8,
1114         },
1115         [pbn_b1_8_921600] = {
1116                 .flags          = FL_BASE1,
1117                 .num_ports      = 8,
1118                 .base_baud      = 921600,
1119                 .uart_offset    = 8,
1120         },
1121
1122         [pbn_b1_bt_2_921600] = {
1123                 .flags          = FL_BASE1|FL_BASE_BARS,
1124                 .num_ports      = 2,
1125                 .base_baud      = 921600,
1126                 .uart_offset    = 8,
1127         },
1128
1129         [pbn_b1_1_1382400] = {
1130                 .flags          = FL_BASE1,
1131                 .num_ports      = 1,
1132                 .base_baud      = 1382400,
1133                 .uart_offset    = 8,
1134         },
1135         [pbn_b1_2_1382400] = {
1136                 .flags          = FL_BASE1,
1137                 .num_ports      = 2,
1138                 .base_baud      = 1382400,
1139                 .uart_offset    = 8,
1140         },
1141         [pbn_b1_4_1382400] = {
1142                 .flags          = FL_BASE1,
1143                 .num_ports      = 4,
1144                 .base_baud      = 1382400,
1145                 .uart_offset    = 8,
1146         },
1147         [pbn_b1_8_1382400] = {
1148                 .flags          = FL_BASE1,
1149                 .num_ports      = 8,
1150                 .base_baud      = 1382400,
1151                 .uart_offset    = 8,
1152         },
1153
1154         [pbn_b2_1_115200] = {
1155                 .flags          = FL_BASE2,
1156                 .num_ports      = 1,
1157                 .base_baud      = 115200,
1158                 .uart_offset    = 8,
1159         },
1160         [pbn_b2_8_115200] = {
1161                 .flags          = FL_BASE2,
1162                 .num_ports      = 8,
1163                 .base_baud      = 115200,
1164                 .uart_offset    = 8,
1165         },
1166
1167         [pbn_b2_1_460800] = {
1168                 .flags          = FL_BASE2,
1169                 .num_ports      = 1,
1170                 .base_baud      = 460800,
1171                 .uart_offset    = 8,
1172         },
1173         [pbn_b2_4_460800] = {
1174                 .flags          = FL_BASE2,
1175                 .num_ports      = 4,
1176                 .base_baud      = 460800,
1177                 .uart_offset    = 8,
1178         },
1179         [pbn_b2_8_460800] = {
1180                 .flags          = FL_BASE2,
1181                 .num_ports      = 8,
1182                 .base_baud      = 460800,
1183                 .uart_offset    = 8,
1184         },
1185         [pbn_b2_16_460800] = {
1186                 .flags          = FL_BASE2,
1187                 .num_ports      = 16,
1188                 .base_baud      = 460800,
1189                 .uart_offset    = 8,
1190          },
1191
1192         [pbn_b2_1_921600] = {
1193                 .flags          = FL_BASE2,
1194                 .num_ports      = 1,
1195                 .base_baud      = 921600,
1196                 .uart_offset    = 8,
1197         },
1198         [pbn_b2_4_921600] = {
1199                 .flags          = FL_BASE2,
1200                 .num_ports      = 4,
1201                 .base_baud      = 921600,
1202                 .uart_offset    = 8,
1203         },
1204         [pbn_b2_8_921600] = {
1205                 .flags          = FL_BASE2,
1206                 .num_ports      = 8,
1207                 .base_baud      = 921600,
1208                 .uart_offset    = 8,
1209         },
1210
1211         [pbn_b2_bt_1_115200] = {
1212                 .flags          = FL_BASE2|FL_BASE_BARS,
1213                 .num_ports      = 1,
1214                 .base_baud      = 115200,
1215                 .uart_offset    = 8,
1216         },
1217         [pbn_b2_bt_2_115200] = {
1218                 .flags          = FL_BASE2|FL_BASE_BARS,
1219                 .num_ports      = 2,
1220                 .base_baud      = 115200,
1221                 .uart_offset    = 8,
1222         },
1223         [pbn_b2_bt_4_115200] = {
1224                 .flags          = FL_BASE2|FL_BASE_BARS,
1225                 .num_ports      = 4,
1226                 .base_baud      = 115200,
1227                 .uart_offset    = 8,
1228         },
1229
1230         [pbn_b2_bt_2_921600] = {
1231                 .flags          = FL_BASE2|FL_BASE_BARS,
1232                 .num_ports      = 2,
1233                 .base_baud      = 921600,
1234                 .uart_offset    = 8,
1235         },
1236         [pbn_b2_bt_4_921600] = {
1237                 .flags          = FL_BASE2|FL_BASE_BARS,
1238                 .num_ports      = 4,
1239                 .base_baud      = 921600,
1240                 .uart_offset    = 8,
1241         },
1242
1243         [pbn_b3_4_115200] = {
1244                 .flags          = FL_BASE3,
1245                 .num_ports      = 4,
1246                 .base_baud      = 115200,
1247                 .uart_offset    = 8,
1248         },
1249         [pbn_b3_8_115200] = {
1250                 .flags          = FL_BASE3,
1251                 .num_ports      = 8,
1252                 .base_baud      = 115200,
1253                 .uart_offset    = 8,
1254         },
1255
1256         /*
1257          * Entries following this are board-specific.
1258          */
1259
1260         /*
1261          * Panacom - IOMEM
1262          */
1263         [pbn_panacom] = {
1264                 .flags          = FL_BASE2,
1265                 .num_ports      = 2,
1266                 .base_baud      = 921600,
1267                 .uart_offset    = 0x400,
1268                 .reg_shift      = 7,
1269         },
1270         [pbn_panacom2] = {
1271                 .flags          = FL_BASE2|FL_BASE_BARS,
1272                 .num_ports      = 2,
1273                 .base_baud      = 921600,
1274                 .uart_offset    = 0x400,
1275                 .reg_shift      = 7,
1276         },
1277         [pbn_panacom4] = {
1278                 .flags          = FL_BASE2|FL_BASE_BARS,
1279                 .num_ports      = 4,
1280                 .base_baud      = 921600,
1281                 .uart_offset    = 0x400,
1282                 .reg_shift      = 7,
1283         },
1284
1285         /* I think this entry is broken - the first_offset looks wrong --rmk */
1286         [pbn_plx_romulus] = {
1287                 .flags          = FL_BASE2,
1288                 .num_ports      = 4,
1289                 .base_baud      = 921600,
1290                 .uart_offset    = 8 << 2,
1291                 .reg_shift      = 2,
1292                 .first_offset   = 0x03,
1293         },
1294
1295         /*
1296          * This board uses the size of PCI Base region 0 to
1297          * signal now many ports are available
1298          */
1299         [pbn_oxsemi] = {
1300                 .flags          = FL_BASE0|FL_REGION_SZ_CAP,
1301                 .num_ports      = 32,
1302                 .base_baud      = 115200,
1303                 .uart_offset    = 8,
1304         },
1305
1306         /*
1307          * EKF addition for i960 Boards form EKF with serial port.
1308          * Max 256 ports.
1309          */
1310         [pbn_intel_i960] = {
1311                 .flags          = FL_BASE0,
1312                 .num_ports      = 32,
1313                 .base_baud      = 921600,
1314                 .uart_offset    = 8 << 2,
1315                 .reg_shift      = 2,
1316                 .first_offset   = 0x10000,
1317         },
1318         [pbn_sgi_ioc3] = {
1319                 .flags          = FL_BASE0|FL_NOIRQ,
1320                 .num_ports      = 1,
1321                 .base_baud      = 458333,
1322                 .uart_offset    = 8,
1323                 .reg_shift      = 0,
1324                 .first_offset   = 0x20178,
1325         },
1326
1327         /*
1328          * NEC Vrc-5074 (Nile 4) builtin UART.
1329          */
1330         [pbn_nec_nile4] = {
1331                 .flags          = FL_BASE0,
1332                 .num_ports      = 1,
1333                 .base_baud      = 520833,
1334                 .uart_offset    = 8 << 3,
1335                 .reg_shift      = 3,
1336                 .first_offset   = 0x300,
1337         },
1338
1339         /*
1340          * Computone - uses IOMEM.
1341          */
1342         [pbn_computone_4] = {
1343                 .flags          = FL_BASE0,
1344                 .num_ports      = 4,
1345                 .base_baud      = 921600,
1346                 .uart_offset    = 0x40,
1347                 .reg_shift      = 2,
1348                 .first_offset   = 0x200,
1349         },
1350         [pbn_computone_6] = {
1351                 .flags          = FL_BASE0,
1352                 .num_ports      = 6,
1353                 .base_baud      = 921600,
1354                 .uart_offset    = 0x40,
1355                 .reg_shift      = 2,
1356                 .first_offset   = 0x200,
1357         },
1358         [pbn_computone_8] = {
1359                 .flags          = FL_BASE0,
1360                 .num_ports      = 8,
1361                 .base_baud      = 921600,
1362                 .uart_offset    = 0x40,
1363                 .reg_shift      = 2,
1364                 .first_offset   = 0x200,
1365         },
1366         [pbn_sbsxrsio] = {
1367                 .flags          = FL_BASE0,
1368                 .num_ports      = 8,
1369                 .base_baud      = 460800,
1370                 .uart_offset    = 256,
1371                 .reg_shift      = 4,
1372         },
1373         /*
1374          * Exar Corp. XR17C15[248] Dual/Quad/Octal UART
1375          *  Only basic 16550A support.
1376          *  XR17C15[24] are not tested, but they should work.
1377          */
1378         [pbn_exar_XR17C152] = {
1379                 .flags          = FL_BASE0,
1380                 .num_ports      = 2,
1381                 .base_baud      = 921600,
1382                 .uart_offset    = 0x200,
1383         },
1384         [pbn_exar_XR17C154] = {
1385                 .flags          = FL_BASE0,
1386                 .num_ports      = 4,
1387                 .base_baud      = 921600,
1388                 .uart_offset    = 0x200,
1389         },
1390         [pbn_exar_XR17C158] = {
1391                 .flags          = FL_BASE0,
1392                 .num_ports      = 8,
1393                 .base_baud      = 921600,
1394                 .uart_offset    = 0x200,
1395         },
1396 };
1397
1398 /*
1399  * Given a complete unknown PCI device, try to use some heuristics to
1400  * guess what the configuration might be, based on the pitiful PCI
1401  * serial specs.  Returns 0 on success, 1 on failure.
1402  */
1403 static int __devinit
1404 serial_pci_guess_board(struct pci_dev *dev, struct pciserial_board *board)
1405 {
1406         int num_iomem, num_port, first_port = -1, i;
1407
1408         /*
1409          * If it is not a communications device or the programming
1410          * interface is greater than 6, give up.
1411          *
1412          * (Should we try to make guesses for multiport serial devices
1413          * later?)
1414          */
1415         if ((((dev->class >> 8) != PCI_CLASS_COMMUNICATION_SERIAL) &&
1416              ((dev->class >> 8) != PCI_CLASS_COMMUNICATION_MODEM)) ||
1417             (dev->class & 0xff) > 6)
1418                 return -ENODEV;
1419
1420         num_iomem = num_port = 0;
1421         for (i = 0; i < PCI_NUM_BAR_RESOURCES; i++) {
1422                 if (pci_resource_flags(dev, i) & IORESOURCE_IO) {
1423                         num_port++;
1424                         if (first_port == -1)
1425                                 first_port = i;
1426                 }
1427                 if (pci_resource_flags(dev, i) & IORESOURCE_MEM)
1428                         num_iomem++;
1429         }
1430
1431         /*
1432          * If there is 1 or 0 iomem regions, and exactly one port,
1433          * use it.  We guess the number of ports based on the IO
1434          * region size.
1435          */
1436         if (num_iomem <= 1 && num_port == 1) {
1437                 board->flags = first_port;
1438                 board->num_ports = pci_resource_len(dev, first_port) / 8;
1439                 return 0;
1440         }
1441
1442         /*
1443          * Now guess if we've got a board which indexes by BARs.
1444          * Each IO BAR should be 8 bytes, and they should follow
1445          * consecutively.
1446          */
1447         first_port = -1;
1448         num_port = 0;
1449         for (i = 0; i < PCI_NUM_BAR_RESOURCES; i++) {
1450                 if (pci_resource_flags(dev, i) & IORESOURCE_IO &&
1451                     pci_resource_len(dev, i) == 8 &&
1452                     (first_port == -1 || (first_port + num_port) == i)) {
1453                         num_port++;
1454                         if (first_port == -1)
1455                                 first_port = i;
1456                 }
1457         }
1458
1459         if (num_port > 1) {
1460                 board->flags = first_port | FL_BASE_BARS;
1461                 board->num_ports = num_port;
1462                 return 0;
1463         }
1464
1465         return -ENODEV;
1466 }
1467
1468 static inline int
1469 serial_pci_matches(struct pciserial_board *board,
1470                    struct pciserial_board *guessed)
1471 {
1472         return
1473             board->num_ports == guessed->num_ports &&
1474             board->base_baud == guessed->base_baud &&
1475             board->uart_offset == guessed->uart_offset &&
1476             board->reg_shift == guessed->reg_shift &&
1477             board->first_offset == guessed->first_offset;
1478 }
1479
1480 struct serial_private *
1481 pciserial_init_ports(struct pci_dev *dev, struct pciserial_board *board)
1482 {
1483         struct uart_port serial_port;
1484         struct serial_private *priv;
1485         struct pci_serial_quirk *quirk;
1486         int rc, nr_ports, i;
1487
1488         nr_ports = board->num_ports;
1489
1490         /*
1491          * Find an init and setup quirks.
1492          */
1493         quirk = find_quirk(dev);
1494
1495         /*
1496          * Run the new-style initialization function.
1497          * The initialization function returns:
1498          *  <0  - error
1499          *   0  - use board->num_ports
1500          *  >0  - number of ports
1501          */
1502         if (quirk->init) {
1503                 rc = quirk->init(dev);
1504                 if (rc < 0) {
1505                         priv = ERR_PTR(rc);
1506                         goto err_out;
1507                 }
1508                 if (rc)
1509                         nr_ports = rc;
1510         }
1511
1512         priv = kmalloc(sizeof(struct serial_private) +
1513                        sizeof(unsigned int) * nr_ports,
1514                        GFP_KERNEL);
1515         if (!priv) {
1516                 priv = ERR_PTR(-ENOMEM);
1517                 goto err_deinit;
1518         }
1519
1520         memset(priv, 0, sizeof(struct serial_private) +
1521                         sizeof(unsigned int) * nr_ports);
1522
1523         priv->dev = dev;
1524         priv->quirk = quirk;
1525
1526         memset(&serial_port, 0, sizeof(struct uart_port));
1527         serial_port.flags = UPF_SKIP_TEST | UPF_BOOT_AUTOCONF | UPF_SHARE_IRQ;
1528         serial_port.uartclk = board->base_baud * 16;
1529         serial_port.irq = get_pci_irq(dev, board);
1530         serial_port.dev = &dev->dev;
1531
1532         for (i = 0; i < nr_ports; i++) {
1533                 if (quirk->setup(priv, board, &serial_port, i))
1534                         break;
1535
1536 #ifdef SERIAL_DEBUG_PCI
1537                 printk("Setup PCI port: port %x, irq %d, type %d\n",
1538                        serial_port.iobase, serial_port.irq, serial_port.iotype);
1539 #endif
1540
1541                 priv->line[i] = serial8250_register_port(&serial_port);
1542                 if (priv->line[i] < 0) {
1543                         printk(KERN_WARNING "Couldn't register serial port %s: %d\n", pci_name(dev), priv->line[i]);
1544                         break;
1545                 }
1546         }
1547
1548         priv->nr = i;
1549
1550         return priv;
1551
1552  err_deinit:
1553         if (quirk->exit)
1554                 quirk->exit(dev);
1555  err_out:
1556         return priv;
1557 }
1558 EXPORT_SYMBOL_GPL(pciserial_init_ports);
1559
1560 void pciserial_remove_ports(struct serial_private *priv)
1561 {
1562         struct pci_serial_quirk *quirk;
1563         int i;
1564
1565         for (i = 0; i < priv->nr; i++)
1566                 serial8250_unregister_port(priv->line[i]);
1567
1568         for (i = 0; i < PCI_NUM_BAR_RESOURCES; i++) {
1569                 if (priv->remapped_bar[i])
1570                         iounmap(priv->remapped_bar[i]);
1571                 priv->remapped_bar[i] = NULL;
1572         }
1573
1574         /*
1575          * Find the exit quirks.
1576          */
1577         quirk = find_quirk(priv->dev);
1578         if (quirk->exit)
1579                 quirk->exit(priv->dev);
1580
1581         kfree(priv);
1582 }
1583 EXPORT_SYMBOL_GPL(pciserial_remove_ports);
1584
1585 void pciserial_suspend_ports(struct serial_private *priv)
1586 {
1587         int i;
1588
1589         for (i = 0; i < priv->nr; i++)
1590                 if (priv->line[i] >= 0)
1591                         serial8250_suspend_port(priv->line[i]);
1592 }
1593 EXPORT_SYMBOL_GPL(pciserial_suspend_ports);
1594
1595 void pciserial_resume_ports(struct serial_private *priv)
1596 {
1597         int i;
1598
1599         /*
1600          * Ensure that the board is correctly configured.
1601          */
1602         if (priv->quirk->init)
1603                 priv->quirk->init(priv->dev);
1604
1605         for (i = 0; i < priv->nr; i++)
1606                 if (priv->line[i] >= 0)
1607                         serial8250_resume_port(priv->line[i]);
1608 }
1609 EXPORT_SYMBOL_GPL(pciserial_resume_ports);
1610
1611 /*
1612  * Probe one serial board.  Unfortunately, there is no rhyme nor reason
1613  * to the arrangement of serial ports on a PCI card.
1614  */
1615 static int __devinit
1616 pciserial_init_one(struct pci_dev *dev, const struct pci_device_id *ent)
1617 {
1618         struct serial_private *priv;
1619         struct pciserial_board *board, tmp;
1620         int rc;
1621
1622         if (ent->driver_data >= ARRAY_SIZE(pci_boards)) {
1623                 printk(KERN_ERR "pci_init_one: invalid driver_data: %ld\n",
1624                         ent->driver_data);
1625                 return -EINVAL;
1626         }
1627
1628         board = &pci_boards[ent->driver_data];
1629
1630         rc = pci_enable_device(dev);
1631         if (rc)
1632                 return rc;
1633
1634         if (ent->driver_data == pbn_default) {
1635                 /*
1636                  * Use a copy of the pci_board entry for this;
1637                  * avoid changing entries in the table.
1638                  */
1639                 memcpy(&tmp, board, sizeof(struct pciserial_board));
1640                 board = &tmp;
1641
1642                 /*
1643                  * We matched one of our class entries.  Try to
1644                  * determine the parameters of this board.
1645                  */
1646                 rc = serial_pci_guess_board(dev, board);
1647                 if (rc)
1648                         goto disable;
1649         } else {
1650                 /*
1651                  * We matched an explicit entry.  If we are able to
1652                  * detect this boards settings with our heuristic,
1653                  * then we no longer need this entry.
1654                  */
1655                 memcpy(&tmp, &pci_boards[pbn_default],
1656                        sizeof(struct pciserial_board));
1657                 rc = serial_pci_guess_board(dev, &tmp);
1658                 if (rc == 0 && serial_pci_matches(board, &tmp))
1659                         moan_device("Redundant entry in serial pci_table.",
1660                                     dev);
1661         }
1662
1663         priv = pciserial_init_ports(dev, board);
1664         if (!IS_ERR(priv)) {
1665                 pci_set_drvdata(dev, priv);
1666                 return 0;
1667         }
1668
1669         rc = PTR_ERR(priv);
1670
1671  disable:
1672         pci_disable_device(dev);
1673         return rc;
1674 }
1675
1676 static void __devexit pciserial_remove_one(struct pci_dev *dev)
1677 {
1678         struct serial_private *priv = pci_get_drvdata(dev);
1679
1680         pci_set_drvdata(dev, NULL);
1681
1682         pciserial_remove_ports(priv);
1683
1684         pci_disable_device(dev);
1685 }
1686
1687 static int pciserial_suspend_one(struct pci_dev *dev, pm_message_t state)
1688 {
1689         struct serial_private *priv = pci_get_drvdata(dev);
1690
1691         if (priv)
1692                 pciserial_suspend_ports(priv);
1693
1694         pci_save_state(dev);
1695         pci_set_power_state(dev, pci_choose_state(dev, state));
1696         return 0;
1697 }
1698
1699 static int pciserial_resume_one(struct pci_dev *dev)
1700 {
1701         struct serial_private *priv = pci_get_drvdata(dev);
1702
1703         pci_set_power_state(dev, PCI_D0);
1704         pci_restore_state(dev);
1705
1706         if (priv) {
1707                 /*
1708                  * The device may have been disabled.  Re-enable it.
1709                  */
1710                 pci_enable_device(dev);
1711
1712                 pciserial_resume_ports(priv);
1713         }
1714         return 0;
1715 }
1716
1717 static struct pci_device_id serial_pci_tbl[] = {
1718         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V960,
1719                 PCI_SUBVENDOR_ID_CONNECT_TECH,
1720                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_232, 0, 0,
1721                 pbn_b1_8_1382400 },
1722         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V960,
1723                 PCI_SUBVENDOR_ID_CONNECT_TECH,
1724                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_232, 0, 0,
1725                 pbn_b1_4_1382400 },
1726         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V960,
1727                 PCI_SUBVENDOR_ID_CONNECT_TECH,
1728                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_232, 0, 0,
1729                 pbn_b1_2_1382400 },
1730         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
1731                 PCI_SUBVENDOR_ID_CONNECT_TECH,
1732                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_232, 0, 0,
1733                 pbn_b1_8_1382400 },
1734         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
1735                 PCI_SUBVENDOR_ID_CONNECT_TECH,
1736                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_232, 0, 0,
1737                 pbn_b1_4_1382400 },
1738         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
1739                 PCI_SUBVENDOR_ID_CONNECT_TECH,
1740                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_232, 0, 0,
1741                 pbn_b1_2_1382400 },
1742         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
1743                 PCI_SUBVENDOR_ID_CONNECT_TECH,
1744                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_485, 0, 0,
1745                 pbn_b1_8_921600 },
1746         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
1747                 PCI_SUBVENDOR_ID_CONNECT_TECH,
1748                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_485_4_4, 0, 0,
1749                 pbn_b1_8_921600 },
1750         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
1751                 PCI_SUBVENDOR_ID_CONNECT_TECH,
1752                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_485, 0, 0,
1753                 pbn_b1_4_921600 },
1754         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
1755                 PCI_SUBVENDOR_ID_CONNECT_TECH,
1756                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_485_2_2, 0, 0,
1757                 pbn_b1_4_921600 },
1758         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
1759                 PCI_SUBVENDOR_ID_CONNECT_TECH,
1760                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_485, 0, 0,
1761                 pbn_b1_2_921600 },
1762         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
1763                 PCI_SUBVENDOR_ID_CONNECT_TECH,
1764                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_485_2_6, 0, 0,
1765                 pbn_b1_8_921600 },
1766         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
1767                 PCI_SUBVENDOR_ID_CONNECT_TECH,
1768                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH081101V1, 0, 0,
1769                 pbn_b1_8_921600 },
1770         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
1771                 PCI_SUBVENDOR_ID_CONNECT_TECH,
1772                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH041101V1, 0, 0,
1773                 pbn_b1_4_921600 },
1774
1775         {       PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_U530,
1776                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1777                 pbn_b2_bt_1_115200 },
1778         {       PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM2,
1779                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1780                 pbn_b2_bt_2_115200 },
1781         {       PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM422,
1782                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1783                 pbn_b2_bt_4_115200 },
1784         {       PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM232,
1785                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1786                 pbn_b2_bt_2_115200 },
1787         {       PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_COMM4,
1788                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1789                 pbn_b2_bt_4_115200 },
1790         {       PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_COMM8,
1791                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1792                 pbn_b2_8_115200 },
1793         {       PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM8,
1794                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1795                 pbn_b2_8_115200 },
1796
1797         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_GTEK_SERIAL2,
1798                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1799                 pbn_b2_bt_2_115200 },
1800         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_SPCOM200,
1801                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1802                 pbn_b2_bt_2_921600 },
1803         /*
1804          * VScom SPCOM800, from sl@s.pl
1805          */
1806         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_SPCOM800,
1807                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1808                 pbn_b2_8_921600 },
1809         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_1077,
1810                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1811                 pbn_b2_4_921600 },
1812         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
1813                 PCI_SUBVENDOR_ID_KEYSPAN,
1814                 PCI_SUBDEVICE_ID_KEYSPAN_SX2, 0, 0,
1815                 pbn_panacom },
1816         {       PCI_VENDOR_ID_PANACOM, PCI_DEVICE_ID_PANACOM_QUADMODEM,
1817                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1818                 pbn_panacom4 },
1819         {       PCI_VENDOR_ID_PANACOM, PCI_DEVICE_ID_PANACOM_DUALMODEM,
1820                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1821                 pbn_panacom2 },
1822         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
1823                 PCI_SUBVENDOR_ID_CHASE_PCIFAST,
1824                 PCI_SUBDEVICE_ID_CHASE_PCIFAST4, 0, 0,
1825                 pbn_b2_4_460800 },
1826         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
1827                 PCI_SUBVENDOR_ID_CHASE_PCIFAST,
1828                 PCI_SUBDEVICE_ID_CHASE_PCIFAST8, 0, 0,
1829                 pbn_b2_8_460800 },
1830         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
1831                 PCI_SUBVENDOR_ID_CHASE_PCIFAST,
1832                 PCI_SUBDEVICE_ID_CHASE_PCIFAST16, 0, 0,
1833                 pbn_b2_16_460800 },
1834         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
1835                 PCI_SUBVENDOR_ID_CHASE_PCIFAST,
1836                 PCI_SUBDEVICE_ID_CHASE_PCIFAST16FMC, 0, 0,
1837                 pbn_b2_16_460800 },
1838         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
1839                 PCI_SUBVENDOR_ID_CHASE_PCIRAS,
1840                 PCI_SUBDEVICE_ID_CHASE_PCIRAS4, 0, 0,
1841                 pbn_b2_4_460800 },
1842         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
1843                 PCI_SUBVENDOR_ID_CHASE_PCIRAS,
1844                 PCI_SUBDEVICE_ID_CHASE_PCIRAS8, 0, 0,
1845                 pbn_b2_8_460800 },
1846         /*
1847          * Megawolf Romulus PCI Serial Card, from Mike Hudson
1848          * (Exoray@isys.ca)
1849          */
1850         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_ROMULUS,
1851                 0x10b5, 0x106a, 0, 0,
1852                 pbn_plx_romulus },
1853         {       PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSC100,
1854                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1855                 pbn_b1_4_115200 },
1856         {       PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSC100,
1857                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1858                 pbn_b1_2_115200 },
1859         {       PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_ESC100D,
1860                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1861                 pbn_b1_8_115200 },
1862         {       PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_ESC100M,
1863                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1864                 pbn_b1_8_115200 },
1865         {       PCI_VENDOR_ID_SPECIALIX, PCI_DEVICE_ID_OXSEMI_16PCI954,
1866                 PCI_VENDOR_ID_SPECIALIX, PCI_SUBDEVICE_ID_SPECIALIX_SPEED4, 0, 0,
1867                 pbn_b0_4_921600 },
1868         {       PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
1869                 PCI_SUBVENDOR_ID_SIIG, PCI_SUBDEVICE_ID_SIIG_QUARTET_SERIAL, 0, 0,
1870                 pbn_b0_4_1152000 },
1871         {       PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
1872                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1873                 pbn_b0_4_115200 },
1874         {       PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI952,
1875                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1876                 pbn_b0_bt_2_921600 },
1877
1878         /*
1879          * SBS Technologies, Inc. P-Octal and PMC-OCTPRO cards,
1880          * from skokodyn@yahoo.com
1881          */
1882         {       PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO,
1883                 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_OCTPRO232, 0, 0,
1884                 pbn_sbsxrsio },
1885         {       PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO,
1886                 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_OCTPRO422, 0, 0,
1887                 pbn_sbsxrsio },
1888         {       PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO,
1889                 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_POCTAL232, 0, 0,
1890                 pbn_sbsxrsio },
1891         {       PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO,
1892                 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_POCTAL422, 0, 0,
1893                 pbn_sbsxrsio },
1894
1895         /*
1896          * Digitan DS560-558, from jimd@esoft.com
1897          */
1898         {       PCI_VENDOR_ID_ATT, PCI_DEVICE_ID_ATT_VENUS_MODEM,
1899                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1900                 pbn_b1_1_115200 },
1901
1902         /*
1903          * Titan Electronic cards
1904          *  The 400L and 800L have a custom setup quirk.
1905          */
1906         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_100,
1907                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1908                 pbn_b0_1_921600 },
1909         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200,
1910                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1911                 pbn_b0_2_921600 },
1912         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400,
1913                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1914                 pbn_b0_4_921600 },
1915         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800B,
1916                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1917                 pbn_b0_4_921600 },
1918         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_100L,
1919                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1920                 pbn_b1_1_921600 },
1921         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200L,
1922                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1923                 pbn_b1_bt_2_921600 },
1924         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400L,
1925                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1926                 pbn_b0_bt_4_921600 },
1927         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800L,
1928                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1929                 pbn_b0_bt_8_921600 },
1930
1931         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_10x_550,
1932                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1933                 pbn_b2_1_460800 },
1934         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_10x_650,
1935                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1936                 pbn_b2_1_460800 },
1937         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_10x_850,
1938                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1939                 pbn_b2_1_460800 },
1940         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_10x_550,
1941                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1942                 pbn_b2_bt_2_921600 },
1943         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_10x_650,
1944                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1945                 pbn_b2_bt_2_921600 },
1946         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_10x_850,
1947                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1948                 pbn_b2_bt_2_921600 },
1949         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_10x_550,
1950                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1951                 pbn_b2_bt_4_921600 },
1952         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_10x_650,
1953                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1954                 pbn_b2_bt_4_921600 },
1955         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_10x_850,
1956                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1957                 pbn_b2_bt_4_921600 },
1958         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_20x_550,
1959                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1960                 pbn_b0_1_921600 },
1961         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_20x_650,
1962                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1963                 pbn_b0_1_921600 },
1964         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_20x_850,
1965                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1966                 pbn_b0_1_921600 },
1967         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_20x_550,
1968                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1969                 pbn_b0_bt_2_921600 },
1970         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_20x_650,
1971                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1972                 pbn_b0_bt_2_921600 },
1973         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_20x_850,
1974                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1975                 pbn_b0_bt_2_921600 },
1976         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_20x_550,
1977                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1978                 pbn_b0_bt_4_921600 },
1979         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_20x_650,
1980                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1981                 pbn_b0_bt_4_921600 },
1982         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_20x_850,
1983                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1984                 pbn_b0_bt_4_921600 },
1985
1986         /*
1987          * Computone devices submitted by Doug McNash dmcnash@computone.com
1988          */
1989         {       PCI_VENDOR_ID_COMPUTONE, PCI_DEVICE_ID_COMPUTONE_PG,
1990                 PCI_SUBVENDOR_ID_COMPUTONE, PCI_SUBDEVICE_ID_COMPUTONE_PG4,
1991                 0, 0, pbn_computone_4 },
1992         {       PCI_VENDOR_ID_COMPUTONE, PCI_DEVICE_ID_COMPUTONE_PG,
1993                 PCI_SUBVENDOR_ID_COMPUTONE, PCI_SUBDEVICE_ID_COMPUTONE_PG8,
1994                 0, 0, pbn_computone_8 },
1995         {       PCI_VENDOR_ID_COMPUTONE, PCI_DEVICE_ID_COMPUTONE_PG,
1996                 PCI_SUBVENDOR_ID_COMPUTONE, PCI_SUBDEVICE_ID_COMPUTONE_PG6,
1997                 0, 0, pbn_computone_6 },
1998
1999         {       PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI95N,
2000                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2001                 pbn_oxsemi },
2002         {       PCI_VENDOR_ID_TIMEDIA, PCI_DEVICE_ID_TIMEDIA_1889,
2003                 PCI_VENDOR_ID_TIMEDIA, PCI_ANY_ID, 0, 0,
2004                 pbn_b0_bt_1_921600 },
2005
2006         /*
2007          * AFAVLAB serial card, from Harald Welte <laforge@gnumonks.org>
2008          */
2009         {       PCI_VENDOR_ID_AFAVLAB, PCI_DEVICE_ID_AFAVLAB_P028,
2010                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2011                 pbn_b0_bt_8_115200 },
2012         {       PCI_VENDOR_ID_AFAVLAB, PCI_DEVICE_ID_AFAVLAB_P030,
2013                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2014                 pbn_b0_bt_8_115200 },
2015
2016         {       PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_DSERIAL,
2017                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2018                 pbn_b0_bt_2_115200 },
2019         {       PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUATRO_A,
2020                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2021                 pbn_b0_bt_2_115200 },
2022         {       PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUATRO_B,
2023                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2024                 pbn_b0_bt_2_115200 },
2025         {       PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_OCTO_A,
2026                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2027                 pbn_b0_bt_4_460800 },
2028         {       PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_OCTO_B,
2029                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2030                 pbn_b0_bt_4_460800 },
2031         {       PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_PORT_PLUS,
2032                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2033                 pbn_b0_bt_2_460800 },
2034         {       PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUAD_A,
2035                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2036                 pbn_b0_bt_2_460800 },
2037         {       PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUAD_B,
2038                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2039                 pbn_b0_bt_2_460800 },
2040         {       PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_SSERIAL,
2041                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2042                 pbn_b0_bt_1_115200 },
2043         {       PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_PORT_650,
2044                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2045                 pbn_b0_bt_1_460800 },
2046
2047         /*
2048          * Dell Remote Access Card 4 - Tim_T_Murphy@Dell.com
2049          */
2050         {       PCI_VENDOR_ID_DELL, PCI_DEVICE_ID_DELL_RAC4,
2051                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2052                 pbn_b1_1_1382400 },
2053
2054         /*
2055          * Dell Remote Access Card III - Tim_T_Murphy@Dell.com
2056          */
2057         {       PCI_VENDOR_ID_DELL, PCI_DEVICE_ID_DELL_RACIII,
2058                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2059                 pbn_b1_1_1382400 },
2060
2061         /*
2062          * RAStel 2 port modem, gerg@moreton.com.au
2063          */
2064         {       PCI_VENDOR_ID_MORETON, PCI_DEVICE_ID_RASTEL_2PORT,
2065                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2066                 pbn_b2_bt_2_115200 },
2067
2068         /*
2069          * EKF addition for i960 Boards form EKF with serial port
2070          */
2071         {       PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80960_RP,
2072                 0xE4BF, PCI_ANY_ID, 0, 0,
2073                 pbn_intel_i960 },
2074
2075         /*
2076          * Xircom Cardbus/Ethernet combos
2077          */
2078         {       PCI_VENDOR_ID_XIRCOM, PCI_DEVICE_ID_XIRCOM_X3201_MDM,
2079                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2080                 pbn_b0_1_115200 },
2081         /*
2082          * Xircom RBM56G cardbus modem - Dirk Arnold (temp entry)
2083          */
2084         {       PCI_VENDOR_ID_XIRCOM, PCI_DEVICE_ID_XIRCOM_RBM56G,
2085                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2086                 pbn_b0_1_115200 },
2087
2088         /*
2089          * Untested PCI modems, sent in from various folks...
2090          */
2091
2092         /*
2093          * Elsa Model 56K PCI Modem, from Andreas Rath <arh@01019freenet.de>
2094          */
2095         {       PCI_VENDOR_ID_ROCKWELL, 0x1004,
2096                 0x1048, 0x1500, 0, 0,
2097                 pbn_b1_1_115200 },
2098
2099         {       PCI_VENDOR_ID_SGI, PCI_DEVICE_ID_SGI_IOC3,
2100                 0xFF00, 0, 0, 0,
2101                 pbn_sgi_ioc3 },
2102
2103         /*
2104          * HP Diva card
2105          */
2106         {       PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA,
2107                 PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA_RMP3, 0, 0,
2108                 pbn_b1_1_115200 },
2109         {       PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA,
2110                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2111                 pbn_b0_5_115200 },
2112         {       PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA_AUX,
2113                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2114                 pbn_b2_1_115200 },
2115
2116         /*
2117          * NEC Vrc-5074 (Nile 4) builtin UART.
2118          */
2119         {       PCI_VENDOR_ID_NEC, PCI_DEVICE_ID_NEC_NILE4,
2120                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2121                 pbn_nec_nile4 },
2122
2123         {       PCI_VENDOR_ID_DCI, PCI_DEVICE_ID_DCI_PCCOM4,
2124                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2125                 pbn_b3_4_115200 },
2126         {       PCI_VENDOR_ID_DCI, PCI_DEVICE_ID_DCI_PCCOM8,
2127                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2128                 pbn_b3_8_115200 },
2129
2130         /*
2131          * Exar Corp. XR17C15[248] Dual/Quad/Octal UART
2132          */
2133         {       PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152,
2134                 PCI_ANY_ID, PCI_ANY_ID,
2135                 0,
2136                 0, pbn_exar_XR17C152 },
2137         {       PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C154,
2138                 PCI_ANY_ID, PCI_ANY_ID,
2139                 0,
2140                 0, pbn_exar_XR17C154 },
2141         {       PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C158,
2142                 PCI_ANY_ID, PCI_ANY_ID,
2143                 0,
2144                 0, pbn_exar_XR17C158 },
2145
2146         /*
2147          * Topic TP560 Data/Fax/Voice 56k modem (reported by Evan Clarke)
2148          */
2149         {       PCI_VENDOR_ID_TOPIC, PCI_DEVICE_ID_TOPIC_TP560,
2150                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2151                 pbn_b0_1_115200 },
2152
2153         /*
2154          * These entries match devices with class COMMUNICATION_SERIAL,
2155          * COMMUNICATION_MODEM or COMMUNICATION_MULTISERIAL
2156          */
2157         {       PCI_ANY_ID, PCI_ANY_ID,
2158                 PCI_ANY_ID, PCI_ANY_ID,
2159                 PCI_CLASS_COMMUNICATION_SERIAL << 8,
2160                 0xffff00, pbn_default },
2161         {       PCI_ANY_ID, PCI_ANY_ID,
2162                 PCI_ANY_ID, PCI_ANY_ID,
2163                 PCI_CLASS_COMMUNICATION_MODEM << 8,
2164                 0xffff00, pbn_default },
2165         {       PCI_ANY_ID, PCI_ANY_ID,
2166                 PCI_ANY_ID, PCI_ANY_ID,
2167                 PCI_CLASS_COMMUNICATION_MULTISERIAL << 8,
2168                 0xffff00, pbn_default },
2169         { 0, }
2170 };
2171
2172 static struct pci_driver serial_pci_driver = {
2173         .name           = "serial",
2174         .probe          = pciserial_init_one,
2175         .remove         = __devexit_p(pciserial_remove_one),
2176         .suspend        = pciserial_suspend_one,
2177         .resume         = pciserial_resume_one,
2178         .id_table       = serial_pci_tbl,
2179 };
2180
2181 static int __init serial8250_pci_init(void)
2182 {
2183         return pci_register_driver(&serial_pci_driver);
2184 }
2185
2186 static void __exit serial8250_pci_exit(void)
2187 {
2188         pci_unregister_driver(&serial_pci_driver);
2189 }
2190
2191 module_init(serial8250_pci_init);
2192 module_exit(serial8250_pci_exit);
2193
2194 MODULE_LICENSE("GPL");
2195 MODULE_DESCRIPTION("Generic 8250/16x50 PCI serial probe module");
2196 MODULE_DEVICE_TABLE(pci, serial_pci_tbl);