Merge branch 'master'
[linux-2.6.git] / drivers / scsi / sata_sx4.c
1 /*
2  *  sata_sx4.c - Promise SATA
3  *
4  *  Maintained by:  Jeff Garzik <jgarzik@pobox.com>
5  *                  Please ALWAYS copy linux-ide@vger.kernel.org
6  *                  on emails.
7  *
8  *  Copyright 2003-2004 Red Hat, Inc.
9  *
10  *
11  *  This program is free software; you can redistribute it and/or modify
12  *  it under the terms of the GNU General Public License as published by
13  *  the Free Software Foundation; either version 2, or (at your option)
14  *  any later version.
15  *
16  *  This program is distributed in the hope that it will be useful,
17  *  but WITHOUT ANY WARRANTY; without even the implied warranty of
18  *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
19  *  GNU General Public License for more details.
20  *
21  *  You should have received a copy of the GNU General Public License
22  *  along with this program; see the file COPYING.  If not, write to
23  *  the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
24  *
25  *
26  *  libata documentation is available via 'make {ps|pdf}docs',
27  *  as Documentation/DocBook/libata.*
28  *
29  *  Hardware documentation available under NDA.
30  *
31  */
32
33 #include <linux/kernel.h>
34 #include <linux/module.h>
35 #include <linux/pci.h>
36 #include <linux/init.h>
37 #include <linux/blkdev.h>
38 #include <linux/delay.h>
39 #include <linux/interrupt.h>
40 #include <linux/sched.h>
41 #include <linux/device.h>
42 #include "scsi.h"
43 #include <scsi/scsi_host.h>
44 #include <linux/libata.h>
45 #include <asm/io.h>
46 #include "sata_promise.h"
47
48 #define DRV_NAME        "sata_sx4"
49 #define DRV_VERSION     "0.7"
50
51
52 enum {
53         PDC_PRD_TBL             = 0x44, /* Direct command DMA table addr */
54
55         PDC_PKT_SUBMIT          = 0x40, /* Command packet pointer addr */
56         PDC_HDMA_PKT_SUBMIT     = 0x100, /* Host DMA packet pointer addr */
57         PDC_INT_SEQMASK         = 0x40, /* Mask of asserted SEQ INTs */
58         PDC_HDMA_CTLSTAT        = 0x12C, /* Host DMA control / status */
59
60         PDC_20621_SEQCTL        = 0x400,
61         PDC_20621_SEQMASK       = 0x480,
62         PDC_20621_GENERAL_CTL   = 0x484,
63         PDC_20621_PAGE_SIZE     = (32 * 1024),
64
65         /* chosen, not constant, values; we design our own DIMM mem map */
66         PDC_20621_DIMM_WINDOW   = 0x0C, /* page# for 32K DIMM window */
67         PDC_20621_DIMM_BASE     = 0x00200000,
68         PDC_20621_DIMM_DATA     = (64 * 1024),
69         PDC_DIMM_DATA_STEP      = (256 * 1024),
70         PDC_DIMM_WINDOW_STEP    = (8 * 1024),
71         PDC_DIMM_HOST_PRD       = (6 * 1024),
72         PDC_DIMM_HOST_PKT       = (128 * 0),
73         PDC_DIMM_HPKT_PRD       = (128 * 1),
74         PDC_DIMM_ATA_PKT        = (128 * 2),
75         PDC_DIMM_APKT_PRD       = (128 * 3),
76         PDC_DIMM_HEADER_SZ      = PDC_DIMM_APKT_PRD + 128,
77         PDC_PAGE_WINDOW         = 0x40,
78         PDC_PAGE_DATA           = PDC_PAGE_WINDOW +
79                                   (PDC_20621_DIMM_DATA / PDC_20621_PAGE_SIZE),
80         PDC_PAGE_SET            = PDC_DIMM_DATA_STEP / PDC_20621_PAGE_SIZE,
81
82         PDC_CHIP0_OFS           = 0xC0000, /* offset of chip #0 */
83
84         PDC_20621_ERR_MASK      = (1<<19) | (1<<20) | (1<<21) | (1<<22) |
85                                   (1<<23),
86
87         board_20621             = 0,    /* FastTrak S150 SX4 */
88
89         PDC_RESET               = (1 << 11), /* HDMA reset */
90
91         PDC_MAX_HDMA            = 32,
92         PDC_HDMA_Q_MASK         = (PDC_MAX_HDMA - 1),
93
94         PDC_DIMM0_SPD_DEV_ADDRESS     = 0x50,
95         PDC_DIMM1_SPD_DEV_ADDRESS     = 0x51,
96         PDC_MAX_DIMM_MODULE           = 0x02,
97         PDC_I2C_CONTROL_OFFSET        = 0x48,
98         PDC_I2C_ADDR_DATA_OFFSET      = 0x4C,
99         PDC_DIMM0_CONTROL_OFFSET      = 0x80,
100         PDC_DIMM1_CONTROL_OFFSET      = 0x84,
101         PDC_SDRAM_CONTROL_OFFSET      = 0x88,
102         PDC_I2C_WRITE                 = 0x00000000,
103         PDC_I2C_READ                  = 0x00000040,
104         PDC_I2C_START                 = 0x00000080,
105         PDC_I2C_MASK_INT              = 0x00000020,
106         PDC_I2C_COMPLETE              = 0x00010000,
107         PDC_I2C_NO_ACK                = 0x00100000,
108         PDC_DIMM_SPD_SUBADDRESS_START = 0x00,
109         PDC_DIMM_SPD_SUBADDRESS_END   = 0x7F,
110         PDC_DIMM_SPD_ROW_NUM          = 3,
111         PDC_DIMM_SPD_COLUMN_NUM       = 4,
112         PDC_DIMM_SPD_MODULE_ROW       = 5,
113         PDC_DIMM_SPD_TYPE             = 11,
114         PDC_DIMM_SPD_FRESH_RATE       = 12,
115         PDC_DIMM_SPD_BANK_NUM         = 17,
116         PDC_DIMM_SPD_CAS_LATENCY      = 18,
117         PDC_DIMM_SPD_ATTRIBUTE        = 21,
118         PDC_DIMM_SPD_ROW_PRE_CHARGE   = 27,
119         PDC_DIMM_SPD_ROW_ACTIVE_DELAY = 28,
120         PDC_DIMM_SPD_RAS_CAS_DELAY    = 29,
121         PDC_DIMM_SPD_ACTIVE_PRECHARGE = 30,
122         PDC_DIMM_SPD_SYSTEM_FREQ      = 126,
123         PDC_CTL_STATUS                = 0x08,
124         PDC_DIMM_WINDOW_CTLR          = 0x0C,
125         PDC_TIME_CONTROL              = 0x3C,
126         PDC_TIME_PERIOD               = 0x40,
127         PDC_TIME_COUNTER              = 0x44,
128         PDC_GENERAL_CTLR              = 0x484,
129         PCI_PLL_INIT                  = 0x8A531824,
130         PCI_X_TCOUNT                  = 0xEE1E5CFF
131 };
132
133
134 struct pdc_port_priv {
135         u8                      dimm_buf[(ATA_PRD_SZ * ATA_MAX_PRD) + 512];
136         u8                      *pkt;
137         dma_addr_t              pkt_dma;
138 };
139
140 struct pdc_host_priv {
141         void                    __iomem *dimm_mmio;
142
143         unsigned int            doing_hdma;
144         unsigned int            hdma_prod;
145         unsigned int            hdma_cons;
146         struct {
147                 struct ata_queued_cmd *qc;
148                 unsigned int    seq;
149                 unsigned long   pkt_ofs;
150         } hdma[32];
151 };
152
153
154 static int pdc_sata_init_one (struct pci_dev *pdev, const struct pci_device_id *ent);
155 static irqreturn_t pdc20621_interrupt (int irq, void *dev_instance, struct pt_regs *regs);
156 static void pdc_eng_timeout(struct ata_port *ap);
157 static void pdc_20621_phy_reset (struct ata_port *ap);
158 static int pdc_port_start(struct ata_port *ap);
159 static void pdc_port_stop(struct ata_port *ap);
160 static void pdc20621_qc_prep(struct ata_queued_cmd *qc);
161 static void pdc_tf_load_mmio(struct ata_port *ap, const struct ata_taskfile *tf);
162 static void pdc_exec_command_mmio(struct ata_port *ap, const struct ata_taskfile *tf);
163 static void pdc20621_host_stop(struct ata_host_set *host_set);
164 static unsigned int pdc20621_dimm_init(struct ata_probe_ent *pe);
165 static int pdc20621_detect_dimm(struct ata_probe_ent *pe);
166 static unsigned int pdc20621_i2c_read(struct ata_probe_ent *pe,
167                                       u32 device, u32 subaddr, u32 *pdata);
168 static int pdc20621_prog_dimm0(struct ata_probe_ent *pe);
169 static unsigned int pdc20621_prog_dimm_global(struct ata_probe_ent *pe);
170 #ifdef ATA_VERBOSE_DEBUG
171 static void pdc20621_get_from_dimm(struct ata_probe_ent *pe,
172                                    void *psource, u32 offset, u32 size);
173 #endif
174 static void pdc20621_put_to_dimm(struct ata_probe_ent *pe,
175                                  void *psource, u32 offset, u32 size);
176 static void pdc20621_irq_clear(struct ata_port *ap);
177 static int pdc20621_qc_issue_prot(struct ata_queued_cmd *qc);
178
179
180 static Scsi_Host_Template pdc_sata_sht = {
181         .module                 = THIS_MODULE,
182         .name                   = DRV_NAME,
183         .ioctl                  = ata_scsi_ioctl,
184         .queuecommand           = ata_scsi_queuecmd,
185         .eh_strategy_handler    = ata_scsi_error,
186         .can_queue              = ATA_DEF_QUEUE,
187         .this_id                = ATA_SHT_THIS_ID,
188         .sg_tablesize           = LIBATA_MAX_PRD,
189         .max_sectors            = ATA_MAX_SECTORS,
190         .cmd_per_lun            = ATA_SHT_CMD_PER_LUN,
191         .emulated               = ATA_SHT_EMULATED,
192         .use_clustering         = ATA_SHT_USE_CLUSTERING,
193         .proc_name              = DRV_NAME,
194         .dma_boundary           = ATA_DMA_BOUNDARY,
195         .slave_configure        = ata_scsi_slave_config,
196         .bios_param             = ata_std_bios_param,
197         .ordered_flush          = 1,
198 };
199
200 static const struct ata_port_operations pdc_20621_ops = {
201         .port_disable           = ata_port_disable,
202         .tf_load                = pdc_tf_load_mmio,
203         .tf_read                = ata_tf_read,
204         .check_status           = ata_check_status,
205         .exec_command           = pdc_exec_command_mmio,
206         .dev_select             = ata_std_dev_select,
207         .phy_reset              = pdc_20621_phy_reset,
208         .qc_prep                = pdc20621_qc_prep,
209         .qc_issue               = pdc20621_qc_issue_prot,
210         .eng_timeout            = pdc_eng_timeout,
211         .irq_handler            = pdc20621_interrupt,
212         .irq_clear              = pdc20621_irq_clear,
213         .port_start             = pdc_port_start,
214         .port_stop              = pdc_port_stop,
215         .host_stop              = pdc20621_host_stop,
216 };
217
218 static struct ata_port_info pdc_port_info[] = {
219         /* board_20621 */
220         {
221                 .sht            = &pdc_sata_sht,
222                 .host_flags     = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY |
223                                   ATA_FLAG_SRST | ATA_FLAG_MMIO |
224                                   ATA_FLAG_PIO_POLLING,
225                 .pio_mask       = 0x1f, /* pio0-4 */
226                 .mwdma_mask     = 0x07, /* mwdma0-2 */
227                 .udma_mask      = 0x7f, /* udma0-6 ; FIXME */
228                 .port_ops       = &pdc_20621_ops,
229         },
230
231 };
232
233 static struct pci_device_id pdc_sata_pci_tbl[] = {
234         { PCI_VENDOR_ID_PROMISE, 0x6622, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
235           board_20621 },
236         { }     /* terminate list */
237 };
238
239
240 static struct pci_driver pdc_sata_pci_driver = {
241         .name                   = DRV_NAME,
242         .id_table               = pdc_sata_pci_tbl,
243         .probe                  = pdc_sata_init_one,
244         .remove                 = ata_pci_remove_one,
245 };
246
247
248 static void pdc20621_host_stop(struct ata_host_set *host_set)
249 {
250         struct pci_dev *pdev = to_pci_dev(host_set->dev);
251         struct pdc_host_priv *hpriv = host_set->private_data;
252         void __iomem *dimm_mmio = hpriv->dimm_mmio;
253
254         pci_iounmap(pdev, dimm_mmio);
255         kfree(hpriv);
256
257         pci_iounmap(pdev, host_set->mmio_base);
258 }
259
260 static int pdc_port_start(struct ata_port *ap)
261 {
262         struct device *dev = ap->host_set->dev;
263         struct pdc_port_priv *pp;
264         int rc;
265
266         rc = ata_port_start(ap);
267         if (rc)
268                 return rc;
269
270         pp = kmalloc(sizeof(*pp), GFP_KERNEL);
271         if (!pp) {
272                 rc = -ENOMEM;
273                 goto err_out;
274         }
275         memset(pp, 0, sizeof(*pp));
276
277         pp->pkt = dma_alloc_coherent(dev, 128, &pp->pkt_dma, GFP_KERNEL);
278         if (!pp->pkt) {
279                 rc = -ENOMEM;
280                 goto err_out_kfree;
281         }
282
283         ap->private_data = pp;
284
285         return 0;
286
287 err_out_kfree:
288         kfree(pp);
289 err_out:
290         ata_port_stop(ap);
291         return rc;
292 }
293
294
295 static void pdc_port_stop(struct ata_port *ap)
296 {
297         struct device *dev = ap->host_set->dev;
298         struct pdc_port_priv *pp = ap->private_data;
299
300         ap->private_data = NULL;
301         dma_free_coherent(dev, 128, pp->pkt, pp->pkt_dma);
302         kfree(pp);
303         ata_port_stop(ap);
304 }
305
306
307 static void pdc_20621_phy_reset (struct ata_port *ap)
308 {
309         VPRINTK("ENTER\n");
310         ap->cbl = ATA_CBL_SATA;
311         ata_port_probe(ap);
312         ata_bus_reset(ap);
313 }
314
315 static inline void pdc20621_ata_sg(struct ata_taskfile *tf, u8 *buf,
316                                            unsigned int portno,
317                                            unsigned int total_len)
318 {
319         u32 addr;
320         unsigned int dw = PDC_DIMM_APKT_PRD >> 2;
321         u32 *buf32 = (u32 *) buf;
322
323         /* output ATA packet S/G table */
324         addr = PDC_20621_DIMM_BASE + PDC_20621_DIMM_DATA +
325                (PDC_DIMM_DATA_STEP * portno);
326         VPRINTK("ATA sg addr 0x%x, %d\n", addr, addr);
327         buf32[dw] = cpu_to_le32(addr);
328         buf32[dw + 1] = cpu_to_le32(total_len | ATA_PRD_EOT);
329
330         VPRINTK("ATA PSG @ %x == (0x%x, 0x%x)\n",
331                 PDC_20621_DIMM_BASE +
332                        (PDC_DIMM_WINDOW_STEP * portno) +
333                        PDC_DIMM_APKT_PRD,
334                 buf32[dw], buf32[dw + 1]);
335 }
336
337 static inline void pdc20621_host_sg(struct ata_taskfile *tf, u8 *buf,
338                                             unsigned int portno,
339                                             unsigned int total_len)
340 {
341         u32 addr;
342         unsigned int dw = PDC_DIMM_HPKT_PRD >> 2;
343         u32 *buf32 = (u32 *) buf;
344
345         /* output Host DMA packet S/G table */
346         addr = PDC_20621_DIMM_BASE + PDC_20621_DIMM_DATA +
347                (PDC_DIMM_DATA_STEP * portno);
348
349         buf32[dw] = cpu_to_le32(addr);
350         buf32[dw + 1] = cpu_to_le32(total_len | ATA_PRD_EOT);
351
352         VPRINTK("HOST PSG @ %x == (0x%x, 0x%x)\n",
353                 PDC_20621_DIMM_BASE +
354                        (PDC_DIMM_WINDOW_STEP * portno) +
355                        PDC_DIMM_HPKT_PRD,
356                 buf32[dw], buf32[dw + 1]);
357 }
358
359 static inline unsigned int pdc20621_ata_pkt(struct ata_taskfile *tf,
360                                             unsigned int devno, u8 *buf,
361                                             unsigned int portno)
362 {
363         unsigned int i, dw;
364         u32 *buf32 = (u32 *) buf;
365         u8 dev_reg;
366
367         unsigned int dimm_sg = PDC_20621_DIMM_BASE +
368                                (PDC_DIMM_WINDOW_STEP * portno) +
369                                PDC_DIMM_APKT_PRD;
370         VPRINTK("ENTER, dimm_sg == 0x%x, %d\n", dimm_sg, dimm_sg);
371
372         i = PDC_DIMM_ATA_PKT;
373
374         /*
375          * Set up ATA packet
376          */
377         if ((tf->protocol == ATA_PROT_DMA) && (!(tf->flags & ATA_TFLAG_WRITE)))
378                 buf[i++] = PDC_PKT_READ;
379         else if (tf->protocol == ATA_PROT_NODATA)
380                 buf[i++] = PDC_PKT_NODATA;
381         else
382                 buf[i++] = 0;
383         buf[i++] = 0;                   /* reserved */
384         buf[i++] = portno + 1;          /* seq. id */
385         buf[i++] = 0xff;                /* delay seq. id */
386
387         /* dimm dma S/G, and next-pkt */
388         dw = i >> 2;
389         if (tf->protocol == ATA_PROT_NODATA)
390                 buf32[dw] = 0;
391         else
392                 buf32[dw] = cpu_to_le32(dimm_sg);
393         buf32[dw + 1] = 0;
394         i += 8;
395
396         if (devno == 0)
397                 dev_reg = ATA_DEVICE_OBS;
398         else
399                 dev_reg = ATA_DEVICE_OBS | ATA_DEV1;
400
401         /* select device */
402         buf[i++] = (1 << 5) | PDC_PKT_CLEAR_BSY | ATA_REG_DEVICE;
403         buf[i++] = dev_reg;
404
405         /* device control register */
406         buf[i++] = (1 << 5) | PDC_REG_DEVCTL;
407         buf[i++] = tf->ctl;
408
409         return i;
410 }
411
412 static inline void pdc20621_host_pkt(struct ata_taskfile *tf, u8 *buf,
413                                      unsigned int portno)
414 {
415         unsigned int dw;
416         u32 tmp, *buf32 = (u32 *) buf;
417
418         unsigned int host_sg = PDC_20621_DIMM_BASE +
419                                (PDC_DIMM_WINDOW_STEP * portno) +
420                                PDC_DIMM_HOST_PRD;
421         unsigned int dimm_sg = PDC_20621_DIMM_BASE +
422                                (PDC_DIMM_WINDOW_STEP * portno) +
423                                PDC_DIMM_HPKT_PRD;
424         VPRINTK("ENTER, dimm_sg == 0x%x, %d\n", dimm_sg, dimm_sg);
425         VPRINTK("host_sg == 0x%x, %d\n", host_sg, host_sg);
426
427         dw = PDC_DIMM_HOST_PKT >> 2;
428
429         /*
430          * Set up Host DMA packet
431          */
432         if ((tf->protocol == ATA_PROT_DMA) && (!(tf->flags & ATA_TFLAG_WRITE)))
433                 tmp = PDC_PKT_READ;
434         else
435                 tmp = 0;
436         tmp |= ((portno + 1 + 4) << 16);        /* seq. id */
437         tmp |= (0xff << 24);                    /* delay seq. id */
438         buf32[dw + 0] = cpu_to_le32(tmp);
439         buf32[dw + 1] = cpu_to_le32(host_sg);
440         buf32[dw + 2] = cpu_to_le32(dimm_sg);
441         buf32[dw + 3] = 0;
442
443         VPRINTK("HOST PKT @ %x == (0x%x 0x%x 0x%x 0x%x)\n",
444                 PDC_20621_DIMM_BASE + (PDC_DIMM_WINDOW_STEP * portno) +
445                         PDC_DIMM_HOST_PKT,
446                 buf32[dw + 0],
447                 buf32[dw + 1],
448                 buf32[dw + 2],
449                 buf32[dw + 3]);
450 }
451
452 static void pdc20621_dma_prep(struct ata_queued_cmd *qc)
453 {
454         struct scatterlist *sg = qc->sg;
455         struct ata_port *ap = qc->ap;
456         struct pdc_port_priv *pp = ap->private_data;
457         void __iomem *mmio = ap->host_set->mmio_base;
458         struct pdc_host_priv *hpriv = ap->host_set->private_data;
459         void __iomem *dimm_mmio = hpriv->dimm_mmio;
460         unsigned int portno = ap->port_no;
461         unsigned int i, last, idx, total_len = 0, sgt_len;
462         u32 *buf = (u32 *) &pp->dimm_buf[PDC_DIMM_HEADER_SZ];
463
464         assert(qc->flags & ATA_QCFLAG_DMAMAP);
465
466         VPRINTK("ata%u: ENTER\n", ap->id);
467
468         /* hard-code chip #0 */
469         mmio += PDC_CHIP0_OFS;
470
471         /*
472          * Build S/G table
473          */
474         last = qc->n_elem;
475         idx = 0;
476         for (i = 0; i < last; i++) {
477                 buf[idx++] = cpu_to_le32(sg_dma_address(&sg[i]));
478                 buf[idx++] = cpu_to_le32(sg_dma_len(&sg[i]));
479                 total_len += sg_dma_len(&sg[i]);
480         }
481         buf[idx - 1] |= cpu_to_le32(ATA_PRD_EOT);
482         sgt_len = idx * 4;
483
484         /*
485          * Build ATA, host DMA packets
486          */
487         pdc20621_host_sg(&qc->tf, &pp->dimm_buf[0], portno, total_len);
488         pdc20621_host_pkt(&qc->tf, &pp->dimm_buf[0], portno);
489
490         pdc20621_ata_sg(&qc->tf, &pp->dimm_buf[0], portno, total_len);
491         i = pdc20621_ata_pkt(&qc->tf, qc->dev->devno, &pp->dimm_buf[0], portno);
492
493         if (qc->tf.flags & ATA_TFLAG_LBA48)
494                 i = pdc_prep_lba48(&qc->tf, &pp->dimm_buf[0], i);
495         else
496                 i = pdc_prep_lba28(&qc->tf, &pp->dimm_buf[0], i);
497
498         pdc_pkt_footer(&qc->tf, &pp->dimm_buf[0], i);
499
500         /* copy three S/G tables and two packets to DIMM MMIO window */
501         memcpy_toio(dimm_mmio + (portno * PDC_DIMM_WINDOW_STEP),
502                     &pp->dimm_buf, PDC_DIMM_HEADER_SZ);
503         memcpy_toio(dimm_mmio + (portno * PDC_DIMM_WINDOW_STEP) +
504                     PDC_DIMM_HOST_PRD,
505                     &pp->dimm_buf[PDC_DIMM_HEADER_SZ], sgt_len);
506
507         /* force host FIFO dump */
508         writel(0x00000001, mmio + PDC_20621_GENERAL_CTL);
509
510         readl(dimm_mmio);       /* MMIO PCI posting flush */
511
512         VPRINTK("ata pkt buf ofs %u, prd size %u, mmio copied\n", i, sgt_len);
513 }
514
515 static void pdc20621_nodata_prep(struct ata_queued_cmd *qc)
516 {
517         struct ata_port *ap = qc->ap;
518         struct pdc_port_priv *pp = ap->private_data;
519         void __iomem *mmio = ap->host_set->mmio_base;
520         struct pdc_host_priv *hpriv = ap->host_set->private_data;
521         void __iomem *dimm_mmio = hpriv->dimm_mmio;
522         unsigned int portno = ap->port_no;
523         unsigned int i;
524
525         VPRINTK("ata%u: ENTER\n", ap->id);
526
527         /* hard-code chip #0 */
528         mmio += PDC_CHIP0_OFS;
529
530         i = pdc20621_ata_pkt(&qc->tf, qc->dev->devno, &pp->dimm_buf[0], portno);
531
532         if (qc->tf.flags & ATA_TFLAG_LBA48)
533                 i = pdc_prep_lba48(&qc->tf, &pp->dimm_buf[0], i);
534         else
535                 i = pdc_prep_lba28(&qc->tf, &pp->dimm_buf[0], i);
536
537         pdc_pkt_footer(&qc->tf, &pp->dimm_buf[0], i);
538
539         /* copy three S/G tables and two packets to DIMM MMIO window */
540         memcpy_toio(dimm_mmio + (portno * PDC_DIMM_WINDOW_STEP),
541                     &pp->dimm_buf, PDC_DIMM_HEADER_SZ);
542
543         /* force host FIFO dump */
544         writel(0x00000001, mmio + PDC_20621_GENERAL_CTL);
545
546         readl(dimm_mmio);       /* MMIO PCI posting flush */
547
548         VPRINTK("ata pkt buf ofs %u, mmio copied\n", i);
549 }
550
551 static void pdc20621_qc_prep(struct ata_queued_cmd *qc)
552 {
553         switch (qc->tf.protocol) {
554         case ATA_PROT_DMA:
555                 pdc20621_dma_prep(qc);
556                 break;
557         case ATA_PROT_NODATA:
558                 pdc20621_nodata_prep(qc);
559                 break;
560         default:
561                 break;
562         }
563 }
564
565 static void __pdc20621_push_hdma(struct ata_queued_cmd *qc,
566                                  unsigned int seq,
567                                  u32 pkt_ofs)
568 {
569         struct ata_port *ap = qc->ap;
570         struct ata_host_set *host_set = ap->host_set;
571         void __iomem *mmio = host_set->mmio_base;
572
573         /* hard-code chip #0 */
574         mmio += PDC_CHIP0_OFS;
575
576         writel(0x00000001, mmio + PDC_20621_SEQCTL + (seq * 4));
577         readl(mmio + PDC_20621_SEQCTL + (seq * 4));     /* flush */
578
579         writel(pkt_ofs, mmio + PDC_HDMA_PKT_SUBMIT);
580         readl(mmio + PDC_HDMA_PKT_SUBMIT);      /* flush */
581 }
582
583 static void pdc20621_push_hdma(struct ata_queued_cmd *qc,
584                                 unsigned int seq,
585                                 u32 pkt_ofs)
586 {
587         struct ata_port *ap = qc->ap;
588         struct pdc_host_priv *pp = ap->host_set->private_data;
589         unsigned int idx = pp->hdma_prod & PDC_HDMA_Q_MASK;
590
591         if (!pp->doing_hdma) {
592                 __pdc20621_push_hdma(qc, seq, pkt_ofs);
593                 pp->doing_hdma = 1;
594                 return;
595         }
596
597         pp->hdma[idx].qc = qc;
598         pp->hdma[idx].seq = seq;
599         pp->hdma[idx].pkt_ofs = pkt_ofs;
600         pp->hdma_prod++;
601 }
602
603 static void pdc20621_pop_hdma(struct ata_queued_cmd *qc)
604 {
605         struct ata_port *ap = qc->ap;
606         struct pdc_host_priv *pp = ap->host_set->private_data;
607         unsigned int idx = pp->hdma_cons & PDC_HDMA_Q_MASK;
608
609         /* if nothing on queue, we're done */
610         if (pp->hdma_prod == pp->hdma_cons) {
611                 pp->doing_hdma = 0;
612                 return;
613         }
614
615         __pdc20621_push_hdma(pp->hdma[idx].qc, pp->hdma[idx].seq,
616                              pp->hdma[idx].pkt_ofs);
617         pp->hdma_cons++;
618 }
619
620 #ifdef ATA_VERBOSE_DEBUG
621 static void pdc20621_dump_hdma(struct ata_queued_cmd *qc)
622 {
623         struct ata_port *ap = qc->ap;
624         unsigned int port_no = ap->port_no;
625         struct pdc_host_priv *hpriv = ap->host_set->private_data;
626         void *dimm_mmio = hpriv->dimm_mmio;
627
628         dimm_mmio += (port_no * PDC_DIMM_WINDOW_STEP);
629         dimm_mmio += PDC_DIMM_HOST_PKT;
630
631         printk(KERN_ERR "HDMA[0] == 0x%08X\n", readl(dimm_mmio));
632         printk(KERN_ERR "HDMA[1] == 0x%08X\n", readl(dimm_mmio + 4));
633         printk(KERN_ERR "HDMA[2] == 0x%08X\n", readl(dimm_mmio + 8));
634         printk(KERN_ERR "HDMA[3] == 0x%08X\n", readl(dimm_mmio + 12));
635 }
636 #else
637 static inline void pdc20621_dump_hdma(struct ata_queued_cmd *qc) { }
638 #endif /* ATA_VERBOSE_DEBUG */
639
640 static void pdc20621_packet_start(struct ata_queued_cmd *qc)
641 {
642         struct ata_port *ap = qc->ap;
643         struct ata_host_set *host_set = ap->host_set;
644         unsigned int port_no = ap->port_no;
645         void __iomem *mmio = host_set->mmio_base;
646         unsigned int rw = (qc->tf.flags & ATA_TFLAG_WRITE);
647         u8 seq = (u8) (port_no + 1);
648         unsigned int port_ofs;
649
650         /* hard-code chip #0 */
651         mmio += PDC_CHIP0_OFS;
652
653         VPRINTK("ata%u: ENTER\n", ap->id);
654
655         wmb();                  /* flush PRD, pkt writes */
656
657         port_ofs = PDC_20621_DIMM_BASE + (PDC_DIMM_WINDOW_STEP * port_no);
658
659         /* if writing, we (1) DMA to DIMM, then (2) do ATA command */
660         if (rw && qc->tf.protocol == ATA_PROT_DMA) {
661                 seq += 4;
662
663                 pdc20621_dump_hdma(qc);
664                 pdc20621_push_hdma(qc, seq, port_ofs + PDC_DIMM_HOST_PKT);
665                 VPRINTK("queued ofs 0x%x (%u), seq %u\n",
666                         port_ofs + PDC_DIMM_HOST_PKT,
667                         port_ofs + PDC_DIMM_HOST_PKT,
668                         seq);
669         } else {
670                 writel(0x00000001, mmio + PDC_20621_SEQCTL + (seq * 4));
671                 readl(mmio + PDC_20621_SEQCTL + (seq * 4));     /* flush */
672
673                 writel(port_ofs + PDC_DIMM_ATA_PKT,
674                        (void __iomem *) ap->ioaddr.cmd_addr + PDC_PKT_SUBMIT);
675                 readl((void __iomem *) ap->ioaddr.cmd_addr + PDC_PKT_SUBMIT);
676                 VPRINTK("submitted ofs 0x%x (%u), seq %u\n",
677                         port_ofs + PDC_DIMM_ATA_PKT,
678                         port_ofs + PDC_DIMM_ATA_PKT,
679                         seq);
680         }
681 }
682
683 static int pdc20621_qc_issue_prot(struct ata_queued_cmd *qc)
684 {
685         switch (qc->tf.protocol) {
686         case ATA_PROT_DMA:
687         case ATA_PROT_NODATA:
688                 pdc20621_packet_start(qc);
689                 return 0;
690
691         case ATA_PROT_ATAPI_DMA:
692                 BUG();
693                 break;
694
695         default:
696                 break;
697         }
698
699         return ata_qc_issue_prot(qc);
700 }
701
702 static inline unsigned int pdc20621_host_intr( struct ata_port *ap,
703                                           struct ata_queued_cmd *qc,
704                                           unsigned int doing_hdma,
705                                           void __iomem *mmio)
706 {
707         unsigned int port_no = ap->port_no;
708         unsigned int port_ofs =
709                 PDC_20621_DIMM_BASE + (PDC_DIMM_WINDOW_STEP * port_no);
710         u8 status;
711         unsigned int handled = 0;
712
713         VPRINTK("ENTER\n");
714
715         if ((qc->tf.protocol == ATA_PROT_DMA) &&        /* read */
716             (!(qc->tf.flags & ATA_TFLAG_WRITE))) {
717
718                 /* step two - DMA from DIMM to host */
719                 if (doing_hdma) {
720                         VPRINTK("ata%u: read hdma, 0x%x 0x%x\n", ap->id,
721                                 readl(mmio + 0x104), readl(mmio + PDC_HDMA_CTLSTAT));
722                         /* get drive status; clear intr; complete txn */
723                         ata_qc_complete(qc, ac_err_mask(ata_wait_idle(ap)));
724                         pdc20621_pop_hdma(qc);
725                 }
726
727                 /* step one - exec ATA command */
728                 else {
729                         u8 seq = (u8) (port_no + 1 + 4);
730                         VPRINTK("ata%u: read ata, 0x%x 0x%x\n", ap->id,
731                                 readl(mmio + 0x104), readl(mmio + PDC_HDMA_CTLSTAT));
732
733                         /* submit hdma pkt */
734                         pdc20621_dump_hdma(qc);
735                         pdc20621_push_hdma(qc, seq,
736                                            port_ofs + PDC_DIMM_HOST_PKT);
737                 }
738                 handled = 1;
739
740         } else if (qc->tf.protocol == ATA_PROT_DMA) {   /* write */
741
742                 /* step one - DMA from host to DIMM */
743                 if (doing_hdma) {
744                         u8 seq = (u8) (port_no + 1);
745                         VPRINTK("ata%u: write hdma, 0x%x 0x%x\n", ap->id,
746                                 readl(mmio + 0x104), readl(mmio + PDC_HDMA_CTLSTAT));
747
748                         /* submit ata pkt */
749                         writel(0x00000001, mmio + PDC_20621_SEQCTL + (seq * 4));
750                         readl(mmio + PDC_20621_SEQCTL + (seq * 4));
751                         writel(port_ofs + PDC_DIMM_ATA_PKT,
752                                (void __iomem *) ap->ioaddr.cmd_addr + PDC_PKT_SUBMIT);
753                         readl((void __iomem *) ap->ioaddr.cmd_addr + PDC_PKT_SUBMIT);
754                 }
755
756                 /* step two - execute ATA command */
757                 else {
758                         VPRINTK("ata%u: write ata, 0x%x 0x%x\n", ap->id,
759                                 readl(mmio + 0x104), readl(mmio + PDC_HDMA_CTLSTAT));
760                         /* get drive status; clear intr; complete txn */
761                         ata_qc_complete(qc, ac_err_mask(ata_wait_idle(ap)));
762                         pdc20621_pop_hdma(qc);
763                 }
764                 handled = 1;
765
766         /* command completion, but no data xfer */
767         } else if (qc->tf.protocol == ATA_PROT_NODATA) {
768
769                 status = ata_busy_wait(ap, ATA_BUSY | ATA_DRQ, 1000);
770                 DPRINTK("BUS_NODATA (drv_stat 0x%X)\n", status);
771                 ata_qc_complete(qc, ac_err_mask(status));
772                 handled = 1;
773
774         } else {
775                 ap->stats.idle_irq++;
776         }
777
778         return handled;
779 }
780
781 static void pdc20621_irq_clear(struct ata_port *ap)
782 {
783         struct ata_host_set *host_set = ap->host_set;
784         void __iomem *mmio = host_set->mmio_base;
785
786         mmio += PDC_CHIP0_OFS;
787
788         readl(mmio + PDC_20621_SEQMASK);
789 }
790
791 static irqreturn_t pdc20621_interrupt (int irq, void *dev_instance, struct pt_regs *regs)
792 {
793         struct ata_host_set *host_set = dev_instance;
794         struct ata_port *ap;
795         u32 mask = 0;
796         unsigned int i, tmp, port_no;
797         unsigned int handled = 0;
798         void __iomem *mmio_base;
799
800         VPRINTK("ENTER\n");
801
802         if (!host_set || !host_set->mmio_base) {
803                 VPRINTK("QUICK EXIT\n");
804                 return IRQ_NONE;
805         }
806
807         mmio_base = host_set->mmio_base;
808
809         /* reading should also clear interrupts */
810         mmio_base += PDC_CHIP0_OFS;
811         mask = readl(mmio_base + PDC_20621_SEQMASK);
812         VPRINTK("mask == 0x%x\n", mask);
813
814         if (mask == 0xffffffff) {
815                 VPRINTK("QUICK EXIT 2\n");
816                 return IRQ_NONE;
817         }
818         mask &= 0xffff;         /* only 16 tags possible */
819         if (!mask) {
820                 VPRINTK("QUICK EXIT 3\n");
821                 return IRQ_NONE;
822         }
823
824         spin_lock(&host_set->lock);
825
826         for (i = 1; i < 9; i++) {
827                 port_no = i - 1;
828                 if (port_no > 3)
829                         port_no -= 4;
830                 if (port_no >= host_set->n_ports)
831                         ap = NULL;
832                 else
833                         ap = host_set->ports[port_no];
834                 tmp = mask & (1 << i);
835                 VPRINTK("seq %u, port_no %u, ap %p, tmp %x\n", i, port_no, ap, tmp);
836                 if (tmp && ap &&
837                     !(ap->flags & ATA_FLAG_PORT_DISABLED)) {
838                         struct ata_queued_cmd *qc;
839
840                         qc = ata_qc_from_tag(ap, ap->active_tag);
841                         if (qc && (!(qc->tf.flags & ATA_TFLAG_POLLING)))
842                                 handled += pdc20621_host_intr(ap, qc, (i > 4),
843                                                               mmio_base);
844                 }
845         }
846
847         spin_unlock(&host_set->lock);
848
849         VPRINTK("mask == 0x%x\n", mask);
850
851         VPRINTK("EXIT\n");
852
853         return IRQ_RETVAL(handled);
854 }
855
856 static void pdc_eng_timeout(struct ata_port *ap)
857 {
858         u8 drv_stat;
859         struct ata_host_set *host_set = ap->host_set;
860         struct ata_queued_cmd *qc;
861         unsigned long flags;
862
863         DPRINTK("ENTER\n");
864
865         spin_lock_irqsave(&host_set->lock, flags);
866
867         qc = ata_qc_from_tag(ap, ap->active_tag);
868         if (!qc) {
869                 printk(KERN_ERR "ata%u: BUG: timeout without command\n",
870                        ap->id);
871                 goto out;
872         }
873
874         /* hack alert!  We cannot use the supplied completion
875          * function from inside the ->eh_strategy_handler() thread.
876          * libata is the only user of ->eh_strategy_handler() in
877          * any kernel, so the default scsi_done() assumes it is
878          * not being called from the SCSI EH.
879          */
880         qc->scsidone = scsi_finish_command;
881
882         switch (qc->tf.protocol) {
883         case ATA_PROT_DMA:
884         case ATA_PROT_NODATA:
885                 printk(KERN_ERR "ata%u: command timeout\n", ap->id);
886                 ata_qc_complete(qc, __ac_err_mask(ata_wait_idle(ap)));
887                 break;
888
889         default:
890                 drv_stat = ata_busy_wait(ap, ATA_BUSY | ATA_DRQ, 1000);
891
892                 printk(KERN_ERR "ata%u: unknown timeout, cmd 0x%x stat 0x%x\n",
893                        ap->id, qc->tf.command, drv_stat);
894
895                 ata_qc_complete(qc, ac_err_mask(drv_stat));
896                 break;
897         }
898
899 out:
900         spin_unlock_irqrestore(&host_set->lock, flags);
901         DPRINTK("EXIT\n");
902 }
903
904 static void pdc_tf_load_mmio(struct ata_port *ap, const struct ata_taskfile *tf)
905 {
906         WARN_ON (tf->protocol == ATA_PROT_DMA ||
907                  tf->protocol == ATA_PROT_NODATA);
908         ata_tf_load(ap, tf);
909 }
910
911
912 static void pdc_exec_command_mmio(struct ata_port *ap, const struct ata_taskfile *tf)
913 {
914         WARN_ON (tf->protocol == ATA_PROT_DMA ||
915                  tf->protocol == ATA_PROT_NODATA);
916         ata_exec_command(ap, tf);
917 }
918
919
920 static void pdc_sata_setup_port(struct ata_ioports *port, unsigned long base)
921 {
922         port->cmd_addr          = base;
923         port->data_addr         = base;
924         port->feature_addr      =
925         port->error_addr        = base + 0x4;
926         port->nsect_addr        = base + 0x8;
927         port->lbal_addr         = base + 0xc;
928         port->lbam_addr         = base + 0x10;
929         port->lbah_addr         = base + 0x14;
930         port->device_addr       = base + 0x18;
931         port->command_addr      =
932         port->status_addr       = base + 0x1c;
933         port->altstatus_addr    =
934         port->ctl_addr          = base + 0x38;
935 }
936
937
938 #ifdef ATA_VERBOSE_DEBUG
939 static void pdc20621_get_from_dimm(struct ata_probe_ent *pe, void *psource,
940                                    u32 offset, u32 size)
941 {
942         u32 window_size;
943         u16 idx;
944         u8 page_mask;
945         long dist;
946         void __iomem *mmio = pe->mmio_base;
947         struct pdc_host_priv *hpriv = pe->private_data;
948         void __iomem *dimm_mmio = hpriv->dimm_mmio;
949
950         /* hard-code chip #0 */
951         mmio += PDC_CHIP0_OFS;
952
953         page_mask = 0x00;
954         window_size = 0x2000 * 4; /* 32K byte uchar size */
955         idx = (u16) (offset / window_size);
956
957         writel(0x01, mmio + PDC_GENERAL_CTLR);
958         readl(mmio + PDC_GENERAL_CTLR);
959         writel(((idx) << page_mask), mmio + PDC_DIMM_WINDOW_CTLR);
960         readl(mmio + PDC_DIMM_WINDOW_CTLR);
961
962         offset -= (idx * window_size);
963         idx++;
964         dist = ((long) (window_size - (offset + size))) >= 0 ? size :
965                 (long) (window_size - offset);
966         memcpy_fromio((char *) psource, (char *) (dimm_mmio + offset / 4),
967                       dist);
968
969         psource += dist;
970         size -= dist;
971         for (; (long) size >= (long) window_size ;) {
972                 writel(0x01, mmio + PDC_GENERAL_CTLR);
973                 readl(mmio + PDC_GENERAL_CTLR);
974                 writel(((idx) << page_mask), mmio + PDC_DIMM_WINDOW_CTLR);
975                 readl(mmio + PDC_DIMM_WINDOW_CTLR);
976                 memcpy_fromio((char *) psource, (char *) (dimm_mmio),
977                               window_size / 4);
978                 psource += window_size;
979                 size -= window_size;
980                 idx ++;
981         }
982
983         if (size) {
984                 writel(0x01, mmio + PDC_GENERAL_CTLR);
985                 readl(mmio + PDC_GENERAL_CTLR);
986                 writel(((idx) << page_mask), mmio + PDC_DIMM_WINDOW_CTLR);
987                 readl(mmio + PDC_DIMM_WINDOW_CTLR);
988                 memcpy_fromio((char *) psource, (char *) (dimm_mmio),
989                               size / 4);
990         }
991 }
992 #endif
993
994
995 static void pdc20621_put_to_dimm(struct ata_probe_ent *pe, void *psource,
996                                  u32 offset, u32 size)
997 {
998         u32 window_size;
999         u16 idx;
1000         u8 page_mask;
1001         long dist;
1002         void __iomem *mmio = pe->mmio_base;
1003         struct pdc_host_priv *hpriv = pe->private_data;
1004         void __iomem *dimm_mmio = hpriv->dimm_mmio;
1005
1006         /* hard-code chip #0 */
1007         mmio += PDC_CHIP0_OFS;
1008
1009         page_mask = 0x00;
1010         window_size = 0x2000 * 4;       /* 32K byte uchar size */
1011         idx = (u16) (offset / window_size);
1012
1013         writel(((idx) << page_mask), mmio + PDC_DIMM_WINDOW_CTLR);
1014         readl(mmio + PDC_DIMM_WINDOW_CTLR);
1015         offset -= (idx * window_size);
1016         idx++;
1017         dist = ((long)(s32)(window_size - (offset + size))) >= 0 ? size :
1018                 (long) (window_size - offset);
1019         memcpy_toio(dimm_mmio + offset / 4, psource, dist);
1020         writel(0x01, mmio + PDC_GENERAL_CTLR);
1021         readl(mmio + PDC_GENERAL_CTLR);
1022
1023         psource += dist;
1024         size -= dist;
1025         for (; (long) size >= (long) window_size ;) {
1026                 writel(((idx) << page_mask), mmio + PDC_DIMM_WINDOW_CTLR);
1027                 readl(mmio + PDC_DIMM_WINDOW_CTLR);
1028                 memcpy_toio(dimm_mmio, psource, window_size / 4);
1029                 writel(0x01, mmio + PDC_GENERAL_CTLR);
1030                 readl(mmio + PDC_GENERAL_CTLR);
1031                 psource += window_size;
1032                 size -= window_size;
1033                 idx ++;
1034         }
1035
1036         if (size) {
1037                 writel(((idx) << page_mask), mmio + PDC_DIMM_WINDOW_CTLR);
1038                 readl(mmio + PDC_DIMM_WINDOW_CTLR);
1039                 memcpy_toio(dimm_mmio, psource, size / 4);
1040                 writel(0x01, mmio + PDC_GENERAL_CTLR);
1041                 readl(mmio + PDC_GENERAL_CTLR);
1042         }
1043 }
1044
1045
1046 static unsigned int pdc20621_i2c_read(struct ata_probe_ent *pe, u32 device,
1047                                       u32 subaddr, u32 *pdata)
1048 {
1049         void __iomem *mmio = pe->mmio_base;
1050         u32 i2creg  = 0;
1051         u32 status;
1052         u32 count =0;
1053
1054         /* hard-code chip #0 */
1055         mmio += PDC_CHIP0_OFS;
1056
1057         i2creg |= device << 24;
1058         i2creg |= subaddr << 16;
1059
1060         /* Set the device and subaddress */
1061         writel(i2creg, mmio + PDC_I2C_ADDR_DATA_OFFSET);
1062         readl(mmio + PDC_I2C_ADDR_DATA_OFFSET);
1063
1064         /* Write Control to perform read operation, mask int */
1065         writel(PDC_I2C_READ | PDC_I2C_START | PDC_I2C_MASK_INT,
1066                mmio + PDC_I2C_CONTROL_OFFSET);
1067
1068         for (count = 0; count <= 1000; count ++) {
1069                 status = readl(mmio + PDC_I2C_CONTROL_OFFSET);
1070                 if (status & PDC_I2C_COMPLETE) {
1071                         status = readl(mmio + PDC_I2C_ADDR_DATA_OFFSET);
1072                         break;
1073                 } else if (count == 1000)
1074                         return 0;
1075         }
1076
1077         *pdata = (status >> 8) & 0x000000ff;
1078         return 1;
1079 }
1080
1081
1082 static int pdc20621_detect_dimm(struct ata_probe_ent *pe)
1083 {
1084         u32 data=0 ;
1085         if (pdc20621_i2c_read(pe, PDC_DIMM0_SPD_DEV_ADDRESS,
1086                              PDC_DIMM_SPD_SYSTEM_FREQ, &data)) {
1087                 if (data == 100)
1088                         return 100;
1089         } else
1090                 return 0;
1091
1092         if (pdc20621_i2c_read(pe, PDC_DIMM0_SPD_DEV_ADDRESS, 9, &data)) {
1093                 if(data <= 0x75)
1094                         return 133;
1095         } else
1096                 return 0;
1097
1098         return 0;
1099 }
1100
1101
1102 static int pdc20621_prog_dimm0(struct ata_probe_ent *pe)
1103 {
1104         u32 spd0[50];
1105         u32 data = 0;
1106         int size, i;
1107         u8 bdimmsize;
1108         void __iomem *mmio = pe->mmio_base;
1109         static const struct {
1110                 unsigned int reg;
1111                 unsigned int ofs;
1112         } pdc_i2c_read_data [] = {
1113                 { PDC_DIMM_SPD_TYPE, 11 },
1114                 { PDC_DIMM_SPD_FRESH_RATE, 12 },
1115                 { PDC_DIMM_SPD_COLUMN_NUM, 4 },
1116                 { PDC_DIMM_SPD_ATTRIBUTE, 21 },
1117                 { PDC_DIMM_SPD_ROW_NUM, 3 },
1118                 { PDC_DIMM_SPD_BANK_NUM, 17 },
1119                 { PDC_DIMM_SPD_MODULE_ROW, 5 },
1120                 { PDC_DIMM_SPD_ROW_PRE_CHARGE, 27 },
1121                 { PDC_DIMM_SPD_ROW_ACTIVE_DELAY, 28 },
1122                 { PDC_DIMM_SPD_RAS_CAS_DELAY, 29 },
1123                 { PDC_DIMM_SPD_ACTIVE_PRECHARGE, 30 },
1124                 { PDC_DIMM_SPD_CAS_LATENCY, 18 },
1125         };
1126
1127         /* hard-code chip #0 */
1128         mmio += PDC_CHIP0_OFS;
1129
1130         for(i=0; i<ARRAY_SIZE(pdc_i2c_read_data); i++)
1131                 pdc20621_i2c_read(pe, PDC_DIMM0_SPD_DEV_ADDRESS,
1132                                   pdc_i2c_read_data[i].reg,
1133                                   &spd0[pdc_i2c_read_data[i].ofs]);
1134
1135         data |= (spd0[4] - 8) | ((spd0[21] != 0) << 3) | ((spd0[3]-11) << 4);
1136         data |= ((spd0[17] / 4) << 6) | ((spd0[5] / 2) << 7) |
1137                 ((((spd0[27] + 9) / 10) - 1) << 8) ;
1138         data |= (((((spd0[29] > spd0[28])
1139                     ? spd0[29] : spd0[28]) + 9) / 10) - 1) << 10;
1140         data |= ((spd0[30] - spd0[29] + 9) / 10 - 2) << 12;
1141
1142         if (spd0[18] & 0x08)
1143                 data |= ((0x03) << 14);
1144         else if (spd0[18] & 0x04)
1145                 data |= ((0x02) << 14);
1146         else if (spd0[18] & 0x01)
1147                 data |= ((0x01) << 14);
1148         else
1149                 data |= (0 << 14);
1150
1151         /*
1152            Calculate the size of bDIMMSize (power of 2) and
1153            merge the DIMM size by program start/end address.
1154         */
1155
1156         bdimmsize = spd0[4] + (spd0[5] / 2) + spd0[3] + (spd0[17] / 2) + 3;
1157         size = (1 << bdimmsize) >> 20;  /* size = xxx(MB) */
1158         data |= (((size / 16) - 1) << 16);
1159         data |= (0 << 23);
1160         data |= 8;
1161         writel(data, mmio + PDC_DIMM0_CONTROL_OFFSET);
1162         readl(mmio + PDC_DIMM0_CONTROL_OFFSET);
1163         return size;
1164 }
1165
1166
1167 static unsigned int pdc20621_prog_dimm_global(struct ata_probe_ent *pe)
1168 {
1169         u32 data, spd0;
1170         int error, i;
1171         void __iomem *mmio = pe->mmio_base;
1172
1173         /* hard-code chip #0 */
1174         mmio += PDC_CHIP0_OFS;
1175
1176         /*
1177           Set To Default : DIMM Module Global Control Register (0x022259F1)
1178           DIMM Arbitration Disable (bit 20)
1179           DIMM Data/Control Output Driving Selection (bit12 - bit15)
1180           Refresh Enable (bit 17)
1181         */
1182
1183         data = 0x022259F1;
1184         writel(data, mmio + PDC_SDRAM_CONTROL_OFFSET);
1185         readl(mmio + PDC_SDRAM_CONTROL_OFFSET);
1186
1187         /* Turn on for ECC */
1188         pdc20621_i2c_read(pe, PDC_DIMM0_SPD_DEV_ADDRESS,
1189                           PDC_DIMM_SPD_TYPE, &spd0);
1190         if (spd0 == 0x02) {
1191                 data |= (0x01 << 16);
1192                 writel(data, mmio + PDC_SDRAM_CONTROL_OFFSET);
1193                 readl(mmio + PDC_SDRAM_CONTROL_OFFSET);
1194                 printk(KERN_ERR "Local DIMM ECC Enabled\n");
1195         }
1196
1197         /* DIMM Initialization Select/Enable (bit 18/19) */
1198         data &= (~(1<<18));
1199         data |= (1<<19);
1200         writel(data, mmio + PDC_SDRAM_CONTROL_OFFSET);
1201
1202         error = 1;
1203         for (i = 1; i <= 10; i++) {   /* polling ~5 secs */
1204                 data = readl(mmio + PDC_SDRAM_CONTROL_OFFSET);
1205                 if (!(data & (1<<19))) {
1206                         error = 0;
1207                         break;
1208                 }
1209                 msleep(i*100);
1210         }
1211         return error;
1212 }
1213
1214
1215 static unsigned int pdc20621_dimm_init(struct ata_probe_ent *pe)
1216 {
1217         int speed, size, length;
1218         u32 addr,spd0,pci_status;
1219         u32 tmp=0;
1220         u32 time_period=0;
1221         u32 tcount=0;
1222         u32 ticks=0;
1223         u32 clock=0;
1224         u32 fparam=0;
1225         void __iomem *mmio = pe->mmio_base;
1226
1227         /* hard-code chip #0 */
1228         mmio += PDC_CHIP0_OFS;
1229
1230         /* Initialize PLL based upon PCI Bus Frequency */
1231
1232         /* Initialize Time Period Register */
1233         writel(0xffffffff, mmio + PDC_TIME_PERIOD);
1234         time_period = readl(mmio + PDC_TIME_PERIOD);
1235         VPRINTK("Time Period Register (0x40): 0x%x\n", time_period);
1236
1237         /* Enable timer */
1238         writel(0x00001a0, mmio + PDC_TIME_CONTROL);
1239         readl(mmio + PDC_TIME_CONTROL);
1240
1241         /* Wait 3 seconds */
1242         msleep(3000);
1243
1244         /*
1245            When timer is enabled, counter is decreased every internal
1246            clock cycle.
1247         */
1248
1249         tcount = readl(mmio + PDC_TIME_COUNTER);
1250         VPRINTK("Time Counter Register (0x44): 0x%x\n", tcount);
1251
1252         /*
1253            If SX4 is on PCI-X bus, after 3 seconds, the timer counter
1254            register should be >= (0xffffffff - 3x10^8).
1255         */
1256         if(tcount >= PCI_X_TCOUNT) {
1257                 ticks = (time_period - tcount);
1258                 VPRINTK("Num counters 0x%x (%d)\n", ticks, ticks);
1259
1260                 clock = (ticks / 300000);
1261                 VPRINTK("10 * Internal clk = 0x%x (%d)\n", clock, clock);
1262
1263                 clock = (clock * 33);
1264                 VPRINTK("10 * Internal clk * 33 = 0x%x (%d)\n", clock, clock);
1265
1266                 /* PLL F Param (bit 22:16) */
1267                 fparam = (1400000 / clock) - 2;
1268                 VPRINTK("PLL F Param: 0x%x (%d)\n", fparam, fparam);
1269
1270                 /* OD param = 0x2 (bit 31:30), R param = 0x5 (bit 29:25) */
1271                 pci_status = (0x8a001824 | (fparam << 16));
1272         } else
1273                 pci_status = PCI_PLL_INIT;
1274
1275         /* Initialize PLL. */
1276         VPRINTK("pci_status: 0x%x\n", pci_status);
1277         writel(pci_status, mmio + PDC_CTL_STATUS);
1278         readl(mmio + PDC_CTL_STATUS);
1279
1280         /*
1281            Read SPD of DIMM by I2C interface,
1282            and program the DIMM Module Controller.
1283         */
1284         if (!(speed = pdc20621_detect_dimm(pe))) {
1285                 printk(KERN_ERR "Detect Local DIMM Fail\n");
1286                 return 1;       /* DIMM error */
1287         }
1288         VPRINTK("Local DIMM Speed = %d\n", speed);
1289
1290         /* Programming DIMM0 Module Control Register (index_CID0:80h) */
1291         size = pdc20621_prog_dimm0(pe);
1292         VPRINTK("Local DIMM Size = %dMB\n",size);
1293
1294         /* Programming DIMM Module Global Control Register (index_CID0:88h) */
1295         if (pdc20621_prog_dimm_global(pe)) {
1296                 printk(KERN_ERR "Programming DIMM Module Global Control Register Fail\n");
1297                 return 1;
1298         }
1299
1300 #ifdef ATA_VERBOSE_DEBUG
1301         {
1302                 u8 test_parttern1[40] = {0x55,0xAA,'P','r','o','m','i','s','e',' ',
1303                                 'N','o','t',' ','Y','e','t',' ','D','e','f','i','n','e','d',' ',
1304                                  '1','.','1','0',
1305                                 '9','8','0','3','1','6','1','2',0,0};
1306                 u8 test_parttern2[40] = {0};
1307
1308                 pdc20621_put_to_dimm(pe, (void *) test_parttern2, 0x10040, 40);
1309                 pdc20621_put_to_dimm(pe, (void *) test_parttern2, 0x40, 40);
1310
1311                 pdc20621_put_to_dimm(pe, (void *) test_parttern1, 0x10040, 40);
1312                 pdc20621_get_from_dimm(pe, (void *) test_parttern2, 0x40, 40);
1313                 printk(KERN_ERR "%x, %x, %s\n", test_parttern2[0],
1314                        test_parttern2[1], &(test_parttern2[2]));
1315                 pdc20621_get_from_dimm(pe, (void *) test_parttern2, 0x10040,
1316                                        40);
1317                 printk(KERN_ERR "%x, %x, %s\n", test_parttern2[0],
1318                        test_parttern2[1], &(test_parttern2[2]));
1319
1320                 pdc20621_put_to_dimm(pe, (void *) test_parttern1, 0x40, 40);
1321                 pdc20621_get_from_dimm(pe, (void *) test_parttern2, 0x40, 40);
1322                 printk(KERN_ERR "%x, %x, %s\n", test_parttern2[0],
1323                        test_parttern2[1], &(test_parttern2[2]));
1324         }
1325 #endif
1326
1327         /* ECC initiliazation. */
1328
1329         pdc20621_i2c_read(pe, PDC_DIMM0_SPD_DEV_ADDRESS,
1330                           PDC_DIMM_SPD_TYPE, &spd0);
1331         if (spd0 == 0x02) {
1332                 VPRINTK("Start ECC initialization\n");
1333                 addr = 0;
1334                 length = size * 1024 * 1024;
1335                 while (addr < length) {
1336                         pdc20621_put_to_dimm(pe, (void *) &tmp, addr,
1337                                              sizeof(u32));
1338                         addr += sizeof(u32);
1339                 }
1340                 VPRINTK("Finish ECC initialization\n");
1341         }
1342         return 0;
1343 }
1344
1345
1346 static void pdc_20621_init(struct ata_probe_ent *pe)
1347 {
1348         u32 tmp;
1349         void __iomem *mmio = pe->mmio_base;
1350
1351         /* hard-code chip #0 */
1352         mmio += PDC_CHIP0_OFS;
1353
1354         /*
1355          * Select page 0x40 for our 32k DIMM window
1356          */
1357         tmp = readl(mmio + PDC_20621_DIMM_WINDOW) & 0xffff0000;
1358         tmp |= PDC_PAGE_WINDOW; /* page 40h; arbitrarily selected */
1359         writel(tmp, mmio + PDC_20621_DIMM_WINDOW);
1360
1361         /*
1362          * Reset Host DMA
1363          */
1364         tmp = readl(mmio + PDC_HDMA_CTLSTAT);
1365         tmp |= PDC_RESET;
1366         writel(tmp, mmio + PDC_HDMA_CTLSTAT);
1367         readl(mmio + PDC_HDMA_CTLSTAT);         /* flush */
1368
1369         udelay(10);
1370
1371         tmp = readl(mmio + PDC_HDMA_CTLSTAT);
1372         tmp &= ~PDC_RESET;
1373         writel(tmp, mmio + PDC_HDMA_CTLSTAT);
1374         readl(mmio + PDC_HDMA_CTLSTAT);         /* flush */
1375 }
1376
1377 static int pdc_sata_init_one (struct pci_dev *pdev, const struct pci_device_id *ent)
1378 {
1379         static int printed_version;
1380         struct ata_probe_ent *probe_ent = NULL;
1381         unsigned long base;
1382         void __iomem *mmio_base;
1383         void __iomem *dimm_mmio = NULL;
1384         struct pdc_host_priv *hpriv = NULL;
1385         unsigned int board_idx = (unsigned int) ent->driver_data;
1386         int pci_dev_busy = 0;
1387         int rc;
1388
1389         if (!printed_version++)
1390                 dev_printk(KERN_DEBUG, &pdev->dev, "version " DRV_VERSION "\n");
1391
1392         /*
1393          * If this driver happens to only be useful on Apple's K2, then
1394          * we should check that here as it has a normal Serverworks ID
1395          */
1396         rc = pci_enable_device(pdev);
1397         if (rc)
1398                 return rc;
1399
1400         rc = pci_request_regions(pdev, DRV_NAME);
1401         if (rc) {
1402                 pci_dev_busy = 1;
1403                 goto err_out;
1404         }
1405
1406         rc = pci_set_dma_mask(pdev, ATA_DMA_MASK);
1407         if (rc)
1408                 goto err_out_regions;
1409         rc = pci_set_consistent_dma_mask(pdev, ATA_DMA_MASK);
1410         if (rc)
1411                 goto err_out_regions;
1412
1413         probe_ent = kmalloc(sizeof(*probe_ent), GFP_KERNEL);
1414         if (probe_ent == NULL) {
1415                 rc = -ENOMEM;
1416                 goto err_out_regions;
1417         }
1418
1419         memset(probe_ent, 0, sizeof(*probe_ent));
1420         probe_ent->dev = pci_dev_to_dev(pdev);
1421         INIT_LIST_HEAD(&probe_ent->node);
1422
1423         mmio_base = pci_iomap(pdev, 3, 0);
1424         if (mmio_base == NULL) {
1425                 rc = -ENOMEM;
1426                 goto err_out_free_ent;
1427         }
1428         base = (unsigned long) mmio_base;
1429
1430         hpriv = kmalloc(sizeof(*hpriv), GFP_KERNEL);
1431         if (!hpriv) {
1432                 rc = -ENOMEM;
1433                 goto err_out_iounmap;
1434         }
1435         memset(hpriv, 0, sizeof(*hpriv));
1436
1437         dimm_mmio = pci_iomap(pdev, 4, 0);
1438         if (!dimm_mmio) {
1439                 kfree(hpriv);
1440                 rc = -ENOMEM;
1441                 goto err_out_iounmap;
1442         }
1443
1444         hpriv->dimm_mmio = dimm_mmio;
1445
1446         probe_ent->sht          = pdc_port_info[board_idx].sht;
1447         probe_ent->host_flags   = pdc_port_info[board_idx].host_flags;
1448         probe_ent->pio_mask     = pdc_port_info[board_idx].pio_mask;
1449         probe_ent->mwdma_mask   = pdc_port_info[board_idx].mwdma_mask;
1450         probe_ent->udma_mask    = pdc_port_info[board_idx].udma_mask;
1451         probe_ent->port_ops     = pdc_port_info[board_idx].port_ops;
1452
1453         probe_ent->irq = pdev->irq;
1454         probe_ent->irq_flags = SA_SHIRQ;
1455         probe_ent->mmio_base = mmio_base;
1456
1457         probe_ent->private_data = hpriv;
1458         base += PDC_CHIP0_OFS;
1459
1460         probe_ent->n_ports = 4;
1461         pdc_sata_setup_port(&probe_ent->port[0], base + 0x200);
1462         pdc_sata_setup_port(&probe_ent->port[1], base + 0x280);
1463         pdc_sata_setup_port(&probe_ent->port[2], base + 0x300);
1464         pdc_sata_setup_port(&probe_ent->port[3], base + 0x380);
1465
1466         pci_set_master(pdev);
1467
1468         /* initialize adapter */
1469         /* initialize local dimm */
1470         if (pdc20621_dimm_init(probe_ent)) {
1471                 rc = -ENOMEM;
1472                 goto err_out_iounmap_dimm;
1473         }
1474         pdc_20621_init(probe_ent);
1475
1476         /* FIXME: check ata_device_add return value */
1477         ata_device_add(probe_ent);
1478         kfree(probe_ent);
1479
1480         return 0;
1481
1482 err_out_iounmap_dimm:           /* only get to this label if 20621 */
1483         kfree(hpriv);
1484         pci_iounmap(pdev, dimm_mmio);
1485 err_out_iounmap:
1486         pci_iounmap(pdev, mmio_base);
1487 err_out_free_ent:
1488         kfree(probe_ent);
1489 err_out_regions:
1490         pci_release_regions(pdev);
1491 err_out:
1492         if (!pci_dev_busy)
1493                 pci_disable_device(pdev);
1494         return rc;
1495 }
1496
1497
1498 static int __init pdc_sata_init(void)
1499 {
1500         return pci_module_init(&pdc_sata_pci_driver);
1501 }
1502
1503
1504 static void __exit pdc_sata_exit(void)
1505 {
1506         pci_unregister_driver(&pdc_sata_pci_driver);
1507 }
1508
1509
1510 MODULE_AUTHOR("Jeff Garzik");
1511 MODULE_DESCRIPTION("Promise SATA low-level driver");
1512 MODULE_LICENSE("GPL");
1513 MODULE_DEVICE_TABLE(pci, pdc_sata_pci_tbl);
1514 MODULE_VERSION(DRV_VERSION);
1515
1516 module_init(pdc_sata_init);
1517 module_exit(pdc_sata_exit);