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Merge branch 'x86-txt-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git...
[linux-2.6.git] / drivers / pci / intel-iommu.c
1 /*
2  * Copyright (c) 2006, Intel Corporation.
3  *
4  * This program is free software; you can redistribute it and/or modify it
5  * under the terms and conditions of the GNU General Public License,
6  * version 2, as published by the Free Software Foundation.
7  *
8  * This program is distributed in the hope it will be useful, but WITHOUT
9  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
11  * more details.
12  *
13  * You should have received a copy of the GNU General Public License along with
14  * this program; if not, write to the Free Software Foundation, Inc., 59 Temple
15  * Place - Suite 330, Boston, MA 02111-1307 USA.
16  *
17  * Copyright (C) 2006-2008 Intel Corporation
18  * Author: Ashok Raj <ashok.raj@intel.com>
19  * Author: Shaohua Li <shaohua.li@intel.com>
20  * Author: Anil S Keshavamurthy <anil.s.keshavamurthy@intel.com>
21  * Author: Fenghua Yu <fenghua.yu@intel.com>
22  */
23
24 #include <linux/init.h>
25 #include <linux/bitmap.h>
26 #include <linux/debugfs.h>
27 #include <linux/slab.h>
28 #include <linux/irq.h>
29 #include <linux/interrupt.h>
30 #include <linux/spinlock.h>
31 #include <linux/pci.h>
32 #include <linux/dmar.h>
33 #include <linux/dma-mapping.h>
34 #include <linux/mempool.h>
35 #include <linux/timer.h>
36 #include <linux/iova.h>
37 #include <linux/iommu.h>
38 #include <linux/intel-iommu.h>
39 #include <linux/sysdev.h>
40 #include <linux/tboot.h>
41 #include <asm/cacheflush.h>
42 #include <asm/iommu.h>
43 #include "pci.h"
44
45 #define ROOT_SIZE               VTD_PAGE_SIZE
46 #define CONTEXT_SIZE            VTD_PAGE_SIZE
47
48 #define IS_GFX_DEVICE(pdev) ((pdev->class >> 16) == PCI_BASE_CLASS_DISPLAY)
49 #define IS_ISA_DEVICE(pdev) ((pdev->class >> 8) == PCI_CLASS_BRIDGE_ISA)
50
51 #define IOAPIC_RANGE_START      (0xfee00000)
52 #define IOAPIC_RANGE_END        (0xfeefffff)
53 #define IOVA_START_ADDR         (0x1000)
54
55 #define DEFAULT_DOMAIN_ADDRESS_WIDTH 48
56
57 #define MAX_AGAW_WIDTH 64
58
59 #define DOMAIN_MAX_ADDR(gaw) ((((u64)1) << gaw) - 1)
60 #define DOMAIN_MAX_PFN(gaw)  ((((u64)1) << (gaw-VTD_PAGE_SHIFT)) - 1)
61
62 #define IOVA_PFN(addr)          ((addr) >> PAGE_SHIFT)
63 #define DMA_32BIT_PFN           IOVA_PFN(DMA_BIT_MASK(32))
64 #define DMA_64BIT_PFN           IOVA_PFN(DMA_BIT_MASK(64))
65
66
67 /* VT-d pages must always be _smaller_ than MM pages. Otherwise things
68    are never going to work. */
69 static inline unsigned long dma_to_mm_pfn(unsigned long dma_pfn)
70 {
71         return dma_pfn >> (PAGE_SHIFT - VTD_PAGE_SHIFT);
72 }
73
74 static inline unsigned long mm_to_dma_pfn(unsigned long mm_pfn)
75 {
76         return mm_pfn << (PAGE_SHIFT - VTD_PAGE_SHIFT);
77 }
78 static inline unsigned long page_to_dma_pfn(struct page *pg)
79 {
80         return mm_to_dma_pfn(page_to_pfn(pg));
81 }
82 static inline unsigned long virt_to_dma_pfn(void *p)
83 {
84         return page_to_dma_pfn(virt_to_page(p));
85 }
86
87 /* global iommu list, set NULL for ignored DMAR units */
88 static struct intel_iommu **g_iommus;
89
90 static int rwbf_quirk;
91
92 /*
93  * 0: Present
94  * 1-11: Reserved
95  * 12-63: Context Ptr (12 - (haw-1))
96  * 64-127: Reserved
97  */
98 struct root_entry {
99         u64     val;
100         u64     rsvd1;
101 };
102 #define ROOT_ENTRY_NR (VTD_PAGE_SIZE/sizeof(struct root_entry))
103 static inline bool root_present(struct root_entry *root)
104 {
105         return (root->val & 1);
106 }
107 static inline void set_root_present(struct root_entry *root)
108 {
109         root->val |= 1;
110 }
111 static inline void set_root_value(struct root_entry *root, unsigned long value)
112 {
113         root->val |= value & VTD_PAGE_MASK;
114 }
115
116 static inline struct context_entry *
117 get_context_addr_from_root(struct root_entry *root)
118 {
119         return (struct context_entry *)
120                 (root_present(root)?phys_to_virt(
121                 root->val & VTD_PAGE_MASK) :
122                 NULL);
123 }
124
125 /*
126  * low 64 bits:
127  * 0: present
128  * 1: fault processing disable
129  * 2-3: translation type
130  * 12-63: address space root
131  * high 64 bits:
132  * 0-2: address width
133  * 3-6: aval
134  * 8-23: domain id
135  */
136 struct context_entry {
137         u64 lo;
138         u64 hi;
139 };
140
141 static inline bool context_present(struct context_entry *context)
142 {
143         return (context->lo & 1);
144 }
145 static inline void context_set_present(struct context_entry *context)
146 {
147         context->lo |= 1;
148 }
149
150 static inline void context_set_fault_enable(struct context_entry *context)
151 {
152         context->lo &= (((u64)-1) << 2) | 1;
153 }
154
155 static inline void context_set_translation_type(struct context_entry *context,
156                                                 unsigned long value)
157 {
158         context->lo &= (((u64)-1) << 4) | 3;
159         context->lo |= (value & 3) << 2;
160 }
161
162 static inline void context_set_address_root(struct context_entry *context,
163                                             unsigned long value)
164 {
165         context->lo |= value & VTD_PAGE_MASK;
166 }
167
168 static inline void context_set_address_width(struct context_entry *context,
169                                              unsigned long value)
170 {
171         context->hi |= value & 7;
172 }
173
174 static inline void context_set_domain_id(struct context_entry *context,
175                                          unsigned long value)
176 {
177         context->hi |= (value & ((1 << 16) - 1)) << 8;
178 }
179
180 static inline void context_clear_entry(struct context_entry *context)
181 {
182         context->lo = 0;
183         context->hi = 0;
184 }
185
186 /*
187  * 0: readable
188  * 1: writable
189  * 2-6: reserved
190  * 7: super page
191  * 8-10: available
192  * 11: snoop behavior
193  * 12-63: Host physcial address
194  */
195 struct dma_pte {
196         u64 val;
197 };
198
199 static inline void dma_clear_pte(struct dma_pte *pte)
200 {
201         pte->val = 0;
202 }
203
204 static inline void dma_set_pte_readable(struct dma_pte *pte)
205 {
206         pte->val |= DMA_PTE_READ;
207 }
208
209 static inline void dma_set_pte_writable(struct dma_pte *pte)
210 {
211         pte->val |= DMA_PTE_WRITE;
212 }
213
214 static inline void dma_set_pte_snp(struct dma_pte *pte)
215 {
216         pte->val |= DMA_PTE_SNP;
217 }
218
219 static inline void dma_set_pte_prot(struct dma_pte *pte, unsigned long prot)
220 {
221         pte->val = (pte->val & ~3) | (prot & 3);
222 }
223
224 static inline u64 dma_pte_addr(struct dma_pte *pte)
225 {
226 #ifdef CONFIG_64BIT
227         return pte->val & VTD_PAGE_MASK;
228 #else
229         /* Must have a full atomic 64-bit read */
230         return  __cmpxchg64(pte, 0ULL, 0ULL) & VTD_PAGE_MASK;
231 #endif
232 }
233
234 static inline void dma_set_pte_pfn(struct dma_pte *pte, unsigned long pfn)
235 {
236         pte->val |= (uint64_t)pfn << VTD_PAGE_SHIFT;
237 }
238
239 static inline bool dma_pte_present(struct dma_pte *pte)
240 {
241         return (pte->val & 3) != 0;
242 }
243
244 static inline int first_pte_in_page(struct dma_pte *pte)
245 {
246         return !((unsigned long)pte & ~VTD_PAGE_MASK);
247 }
248
249 /*
250  * This domain is a statically identity mapping domain.
251  *      1. This domain creats a static 1:1 mapping to all usable memory.
252  *      2. It maps to each iommu if successful.
253  *      3. Each iommu mapps to this domain if successful.
254  */
255 struct dmar_domain *si_domain;
256
257 /* devices under the same p2p bridge are owned in one domain */
258 #define DOMAIN_FLAG_P2P_MULTIPLE_DEVICES (1 << 0)
259
260 /* domain represents a virtual machine, more than one devices
261  * across iommus may be owned in one domain, e.g. kvm guest.
262  */
263 #define DOMAIN_FLAG_VIRTUAL_MACHINE     (1 << 1)
264
265 /* si_domain contains mulitple devices */
266 #define DOMAIN_FLAG_STATIC_IDENTITY     (1 << 2)
267
268 struct dmar_domain {
269         int     id;                     /* domain id */
270         unsigned long iommu_bmp;        /* bitmap of iommus this domain uses*/
271
272         struct list_head devices;       /* all devices' list */
273         struct iova_domain iovad;       /* iova's that belong to this domain */
274
275         struct dma_pte  *pgd;           /* virtual address */
276         int             gaw;            /* max guest address width */
277
278         /* adjusted guest address width, 0 is level 2 30-bit */
279         int             agaw;
280
281         int             flags;          /* flags to find out type of domain */
282
283         int             iommu_coherency;/* indicate coherency of iommu access */
284         int             iommu_snooping; /* indicate snooping control feature*/
285         int             iommu_count;    /* reference count of iommu */
286         spinlock_t      iommu_lock;     /* protect iommu set in domain */
287         u64             max_addr;       /* maximum mapped address */
288 };
289
290 /* PCI domain-device relationship */
291 struct device_domain_info {
292         struct list_head link;  /* link to domain siblings */
293         struct list_head global; /* link to global list */
294         int segment;            /* PCI domain */
295         u8 bus;                 /* PCI bus number */
296         u8 devfn;               /* PCI devfn number */
297         struct pci_dev *dev; /* it's NULL for PCIE-to-PCI bridge */
298         struct intel_iommu *iommu; /* IOMMU used by this device */
299         struct dmar_domain *domain; /* pointer to domain */
300 };
301
302 static void flush_unmaps_timeout(unsigned long data);
303
304 DEFINE_TIMER(unmap_timer,  flush_unmaps_timeout, 0, 0);
305
306 #define HIGH_WATER_MARK 250
307 struct deferred_flush_tables {
308         int next;
309         struct iova *iova[HIGH_WATER_MARK];
310         struct dmar_domain *domain[HIGH_WATER_MARK];
311 };
312
313 static struct deferred_flush_tables *deferred_flush;
314
315 /* bitmap for indexing intel_iommus */
316 static int g_num_of_iommus;
317
318 static DEFINE_SPINLOCK(async_umap_flush_lock);
319 static LIST_HEAD(unmaps_to_do);
320
321 static int timer_on;
322 static long list_size;
323
324 static void domain_remove_dev_info(struct dmar_domain *domain);
325
326 #ifdef CONFIG_DMAR_DEFAULT_ON
327 int dmar_disabled = 0;
328 #else
329 int dmar_disabled = 1;
330 #endif /*CONFIG_DMAR_DEFAULT_ON*/
331
332 static int __initdata dmar_map_gfx = 1;
333 static int dmar_forcedac;
334 static int intel_iommu_strict;
335
336 #define DUMMY_DEVICE_DOMAIN_INFO ((struct device_domain_info *)(-1))
337 static DEFINE_SPINLOCK(device_domain_lock);
338 static LIST_HEAD(device_domain_list);
339
340 static struct iommu_ops intel_iommu_ops;
341
342 static int __init intel_iommu_setup(char *str)
343 {
344         if (!str)
345                 return -EINVAL;
346         while (*str) {
347                 if (!strncmp(str, "on", 2)) {
348                         dmar_disabled = 0;
349                         printk(KERN_INFO "Intel-IOMMU: enabled\n");
350                 } else if (!strncmp(str, "off", 3)) {
351                         dmar_disabled = 1;
352                         printk(KERN_INFO "Intel-IOMMU: disabled\n");
353                 } else if (!strncmp(str, "igfx_off", 8)) {
354                         dmar_map_gfx = 0;
355                         printk(KERN_INFO
356                                 "Intel-IOMMU: disable GFX device mapping\n");
357                 } else if (!strncmp(str, "forcedac", 8)) {
358                         printk(KERN_INFO
359                                 "Intel-IOMMU: Forcing DAC for PCI devices\n");
360                         dmar_forcedac = 1;
361                 } else if (!strncmp(str, "strict", 6)) {
362                         printk(KERN_INFO
363                                 "Intel-IOMMU: disable batched IOTLB flush\n");
364                         intel_iommu_strict = 1;
365                 }
366
367                 str += strcspn(str, ",");
368                 while (*str == ',')
369                         str++;
370         }
371         return 0;
372 }
373 __setup("intel_iommu=", intel_iommu_setup);
374
375 static struct kmem_cache *iommu_domain_cache;
376 static struct kmem_cache *iommu_devinfo_cache;
377 static struct kmem_cache *iommu_iova_cache;
378
379 static inline void *iommu_kmem_cache_alloc(struct kmem_cache *cachep)
380 {
381         unsigned int flags;
382         void *vaddr;
383
384         /* trying to avoid low memory issues */
385         flags = current->flags & PF_MEMALLOC;
386         current->flags |= PF_MEMALLOC;
387         vaddr = kmem_cache_alloc(cachep, GFP_ATOMIC);
388         current->flags &= (~PF_MEMALLOC | flags);
389         return vaddr;
390 }
391
392
393 static inline void *alloc_pgtable_page(void)
394 {
395         unsigned int flags;
396         void *vaddr;
397
398         /* trying to avoid low memory issues */
399         flags = current->flags & PF_MEMALLOC;
400         current->flags |= PF_MEMALLOC;
401         vaddr = (void *)get_zeroed_page(GFP_ATOMIC);
402         current->flags &= (~PF_MEMALLOC | flags);
403         return vaddr;
404 }
405
406 static inline void free_pgtable_page(void *vaddr)
407 {
408         free_page((unsigned long)vaddr);
409 }
410
411 static inline void *alloc_domain_mem(void)
412 {
413         return iommu_kmem_cache_alloc(iommu_domain_cache);
414 }
415
416 static void free_domain_mem(void *vaddr)
417 {
418         kmem_cache_free(iommu_domain_cache, vaddr);
419 }
420
421 static inline void * alloc_devinfo_mem(void)
422 {
423         return iommu_kmem_cache_alloc(iommu_devinfo_cache);
424 }
425
426 static inline void free_devinfo_mem(void *vaddr)
427 {
428         kmem_cache_free(iommu_devinfo_cache, vaddr);
429 }
430
431 struct iova *alloc_iova_mem(void)
432 {
433         return iommu_kmem_cache_alloc(iommu_iova_cache);
434 }
435
436 void free_iova_mem(struct iova *iova)
437 {
438         kmem_cache_free(iommu_iova_cache, iova);
439 }
440
441
442 static inline int width_to_agaw(int width);
443
444 static int __iommu_calculate_agaw(struct intel_iommu *iommu, int max_gaw)
445 {
446         unsigned long sagaw;
447         int agaw = -1;
448
449         sagaw = cap_sagaw(iommu->cap);
450         for (agaw = width_to_agaw(max_gaw);
451              agaw >= 0; agaw--) {
452                 if (test_bit(agaw, &sagaw))
453                         break;
454         }
455
456         return agaw;
457 }
458
459 /*
460  * Calculate max SAGAW for each iommu.
461  */
462 int iommu_calculate_max_sagaw(struct intel_iommu *iommu)
463 {
464         return __iommu_calculate_agaw(iommu, MAX_AGAW_WIDTH);
465 }
466
467 /*
468  * calculate agaw for each iommu.
469  * "SAGAW" may be different across iommus, use a default agaw, and
470  * get a supported less agaw for iommus that don't support the default agaw.
471  */
472 int iommu_calculate_agaw(struct intel_iommu *iommu)
473 {
474         return __iommu_calculate_agaw(iommu, DEFAULT_DOMAIN_ADDRESS_WIDTH);
475 }
476
477 /* This functionin only returns single iommu in a domain */
478 static struct intel_iommu *domain_get_iommu(struct dmar_domain *domain)
479 {
480         int iommu_id;
481
482         /* si_domain and vm domain should not get here. */
483         BUG_ON(domain->flags & DOMAIN_FLAG_VIRTUAL_MACHINE);
484         BUG_ON(domain->flags & DOMAIN_FLAG_STATIC_IDENTITY);
485
486         iommu_id = find_first_bit(&domain->iommu_bmp, g_num_of_iommus);
487         if (iommu_id < 0 || iommu_id >= g_num_of_iommus)
488                 return NULL;
489
490         return g_iommus[iommu_id];
491 }
492
493 static void domain_update_iommu_coherency(struct dmar_domain *domain)
494 {
495         int i;
496
497         domain->iommu_coherency = 1;
498
499         i = find_first_bit(&domain->iommu_bmp, g_num_of_iommus);
500         for (; i < g_num_of_iommus; ) {
501                 if (!ecap_coherent(g_iommus[i]->ecap)) {
502                         domain->iommu_coherency = 0;
503                         break;
504                 }
505                 i = find_next_bit(&domain->iommu_bmp, g_num_of_iommus, i+1);
506         }
507 }
508
509 static void domain_update_iommu_snooping(struct dmar_domain *domain)
510 {
511         int i;
512
513         domain->iommu_snooping = 1;
514
515         i = find_first_bit(&domain->iommu_bmp, g_num_of_iommus);
516         for (; i < g_num_of_iommus; ) {
517                 if (!ecap_sc_support(g_iommus[i]->ecap)) {
518                         domain->iommu_snooping = 0;
519                         break;
520                 }
521                 i = find_next_bit(&domain->iommu_bmp, g_num_of_iommus, i+1);
522         }
523 }
524
525 /* Some capabilities may be different across iommus */
526 static void domain_update_iommu_cap(struct dmar_domain *domain)
527 {
528         domain_update_iommu_coherency(domain);
529         domain_update_iommu_snooping(domain);
530 }
531
532 static struct intel_iommu *device_to_iommu(int segment, u8 bus, u8 devfn)
533 {
534         struct dmar_drhd_unit *drhd = NULL;
535         int i;
536
537         for_each_drhd_unit(drhd) {
538                 if (drhd->ignored)
539                         continue;
540                 if (segment != drhd->segment)
541                         continue;
542
543                 for (i = 0; i < drhd->devices_cnt; i++) {
544                         if (drhd->devices[i] &&
545                             drhd->devices[i]->bus->number == bus &&
546                             drhd->devices[i]->devfn == devfn)
547                                 return drhd->iommu;
548                         if (drhd->devices[i] &&
549                             drhd->devices[i]->subordinate &&
550                             drhd->devices[i]->subordinate->number <= bus &&
551                             drhd->devices[i]->subordinate->subordinate >= bus)
552                                 return drhd->iommu;
553                 }
554
555                 if (drhd->include_all)
556                         return drhd->iommu;
557         }
558
559         return NULL;
560 }
561
562 static void domain_flush_cache(struct dmar_domain *domain,
563                                void *addr, int size)
564 {
565         if (!domain->iommu_coherency)
566                 clflush_cache_range(addr, size);
567 }
568
569 /* Gets context entry for a given bus and devfn */
570 static struct context_entry * device_to_context_entry(struct intel_iommu *iommu,
571                 u8 bus, u8 devfn)
572 {
573         struct root_entry *root;
574         struct context_entry *context;
575         unsigned long phy_addr;
576         unsigned long flags;
577
578         spin_lock_irqsave(&iommu->lock, flags);
579         root = &iommu->root_entry[bus];
580         context = get_context_addr_from_root(root);
581         if (!context) {
582                 context = (struct context_entry *)alloc_pgtable_page();
583                 if (!context) {
584                         spin_unlock_irqrestore(&iommu->lock, flags);
585                         return NULL;
586                 }
587                 __iommu_flush_cache(iommu, (void *)context, CONTEXT_SIZE);
588                 phy_addr = virt_to_phys((void *)context);
589                 set_root_value(root, phy_addr);
590                 set_root_present(root);
591                 __iommu_flush_cache(iommu, root, sizeof(*root));
592         }
593         spin_unlock_irqrestore(&iommu->lock, flags);
594         return &context[devfn];
595 }
596
597 static int device_context_mapped(struct intel_iommu *iommu, u8 bus, u8 devfn)
598 {
599         struct root_entry *root;
600         struct context_entry *context;
601         int ret;
602         unsigned long flags;
603
604         spin_lock_irqsave(&iommu->lock, flags);
605         root = &iommu->root_entry[bus];
606         context = get_context_addr_from_root(root);
607         if (!context) {
608                 ret = 0;
609                 goto out;
610         }
611         ret = context_present(&context[devfn]);
612 out:
613         spin_unlock_irqrestore(&iommu->lock, flags);
614         return ret;
615 }
616
617 static void clear_context_table(struct intel_iommu *iommu, u8 bus, u8 devfn)
618 {
619         struct root_entry *root;
620         struct context_entry *context;
621         unsigned long flags;
622
623         spin_lock_irqsave(&iommu->lock, flags);
624         root = &iommu->root_entry[bus];
625         context = get_context_addr_from_root(root);
626         if (context) {
627                 context_clear_entry(&context[devfn]);
628                 __iommu_flush_cache(iommu, &context[devfn], \
629                         sizeof(*context));
630         }
631         spin_unlock_irqrestore(&iommu->lock, flags);
632 }
633
634 static void free_context_table(struct intel_iommu *iommu)
635 {
636         struct root_entry *root;
637         int i;
638         unsigned long flags;
639         struct context_entry *context;
640
641         spin_lock_irqsave(&iommu->lock, flags);
642         if (!iommu->root_entry) {
643                 goto out;
644         }
645         for (i = 0; i < ROOT_ENTRY_NR; i++) {
646                 root = &iommu->root_entry[i];
647                 context = get_context_addr_from_root(root);
648                 if (context)
649                         free_pgtable_page(context);
650         }
651         free_pgtable_page(iommu->root_entry);
652         iommu->root_entry = NULL;
653 out:
654         spin_unlock_irqrestore(&iommu->lock, flags);
655 }
656
657 /* page table handling */
658 #define LEVEL_STRIDE            (9)
659 #define LEVEL_MASK              (((u64)1 << LEVEL_STRIDE) - 1)
660
661 static inline int agaw_to_level(int agaw)
662 {
663         return agaw + 2;
664 }
665
666 static inline int agaw_to_width(int agaw)
667 {
668         return 30 + agaw * LEVEL_STRIDE;
669
670 }
671
672 static inline int width_to_agaw(int width)
673 {
674         return (width - 30) / LEVEL_STRIDE;
675 }
676
677 static inline unsigned int level_to_offset_bits(int level)
678 {
679         return (level - 1) * LEVEL_STRIDE;
680 }
681
682 static inline int pfn_level_offset(unsigned long pfn, int level)
683 {
684         return (pfn >> level_to_offset_bits(level)) & LEVEL_MASK;
685 }
686
687 static inline unsigned long level_mask(int level)
688 {
689         return -1UL << level_to_offset_bits(level);
690 }
691
692 static inline unsigned long level_size(int level)
693 {
694         return 1UL << level_to_offset_bits(level);
695 }
696
697 static inline unsigned long align_to_level(unsigned long pfn, int level)
698 {
699         return (pfn + level_size(level) - 1) & level_mask(level);
700 }
701
702 static struct dma_pte *pfn_to_dma_pte(struct dmar_domain *domain,
703                                       unsigned long pfn)
704 {
705         int addr_width = agaw_to_width(domain->agaw) - VTD_PAGE_SHIFT;
706         struct dma_pte *parent, *pte = NULL;
707         int level = agaw_to_level(domain->agaw);
708         int offset;
709
710         BUG_ON(!domain->pgd);
711         BUG_ON(addr_width < BITS_PER_LONG && pfn >> addr_width);
712         parent = domain->pgd;
713
714         while (level > 0) {
715                 void *tmp_page;
716
717                 offset = pfn_level_offset(pfn, level);
718                 pte = &parent[offset];
719                 if (level == 1)
720                         break;
721
722                 if (!dma_pte_present(pte)) {
723                         uint64_t pteval;
724
725                         tmp_page = alloc_pgtable_page();
726
727                         if (!tmp_page)
728                                 return NULL;
729
730                         domain_flush_cache(domain, tmp_page, VTD_PAGE_SIZE);
731                         pteval = (virt_to_dma_pfn(tmp_page) << VTD_PAGE_SHIFT) | DMA_PTE_READ | DMA_PTE_WRITE;
732                         if (cmpxchg64(&pte->val, 0ULL, pteval)) {
733                                 /* Someone else set it while we were thinking; use theirs. */
734                                 free_pgtable_page(tmp_page);
735                         } else {
736                                 dma_pte_addr(pte);
737                                 domain_flush_cache(domain, pte, sizeof(*pte));
738                         }
739                 }
740                 parent = phys_to_virt(dma_pte_addr(pte));
741                 level--;
742         }
743
744         return pte;
745 }
746
747 /* return address's pte at specific level */
748 static struct dma_pte *dma_pfn_level_pte(struct dmar_domain *domain,
749                                          unsigned long pfn,
750                                          int level)
751 {
752         struct dma_pte *parent, *pte = NULL;
753         int total = agaw_to_level(domain->agaw);
754         int offset;
755
756         parent = domain->pgd;
757         while (level <= total) {
758                 offset = pfn_level_offset(pfn, total);
759                 pte = &parent[offset];
760                 if (level == total)
761                         return pte;
762
763                 if (!dma_pte_present(pte))
764                         break;
765                 parent = phys_to_virt(dma_pte_addr(pte));
766                 total--;
767         }
768         return NULL;
769 }
770
771 /* clear last level pte, a tlb flush should be followed */
772 static void dma_pte_clear_range(struct dmar_domain *domain,
773                                 unsigned long start_pfn,
774                                 unsigned long last_pfn)
775 {
776         int addr_width = agaw_to_width(domain->agaw) - VTD_PAGE_SHIFT;
777         struct dma_pte *first_pte, *pte;
778
779         BUG_ON(addr_width < BITS_PER_LONG && start_pfn >> addr_width);
780         BUG_ON(addr_width < BITS_PER_LONG && last_pfn >> addr_width);
781
782         /* we don't need lock here; nobody else touches the iova range */
783         while (start_pfn <= last_pfn) {
784                 first_pte = pte = dma_pfn_level_pte(domain, start_pfn, 1);
785                 if (!pte) {
786                         start_pfn = align_to_level(start_pfn + 1, 2);
787                         continue;
788                 }
789                 do { 
790                         dma_clear_pte(pte);
791                         start_pfn++;
792                         pte++;
793                 } while (start_pfn <= last_pfn && !first_pte_in_page(pte));
794
795                 domain_flush_cache(domain, first_pte,
796                                    (void *)pte - (void *)first_pte);
797         }
798 }
799
800 /* free page table pages. last level pte should already be cleared */
801 static void dma_pte_free_pagetable(struct dmar_domain *domain,
802                                    unsigned long start_pfn,
803                                    unsigned long last_pfn)
804 {
805         int addr_width = agaw_to_width(domain->agaw) - VTD_PAGE_SHIFT;
806         struct dma_pte *first_pte, *pte;
807         int total = agaw_to_level(domain->agaw);
808         int level;
809         unsigned long tmp;
810
811         BUG_ON(addr_width < BITS_PER_LONG && start_pfn >> addr_width);
812         BUG_ON(addr_width < BITS_PER_LONG && last_pfn >> addr_width);
813
814         /* We don't need lock here; nobody else touches the iova range */
815         level = 2;
816         while (level <= total) {
817                 tmp = align_to_level(start_pfn, level);
818
819                 /* If we can't even clear one PTE at this level, we're done */
820                 if (tmp + level_size(level) - 1 > last_pfn)
821                         return;
822
823                 while (tmp + level_size(level) - 1 <= last_pfn) {
824                         first_pte = pte = dma_pfn_level_pte(domain, tmp, level);
825                         if (!pte) {
826                                 tmp = align_to_level(tmp + 1, level + 1);
827                                 continue;
828                         }
829                         do {
830                                 if (dma_pte_present(pte)) {
831                                         free_pgtable_page(phys_to_virt(dma_pte_addr(pte)));
832                                         dma_clear_pte(pte);
833                                 }
834                                 pte++;
835                                 tmp += level_size(level);
836                         } while (!first_pte_in_page(pte) &&
837                                  tmp + level_size(level) - 1 <= last_pfn);
838
839                         domain_flush_cache(domain, first_pte,
840                                            (void *)pte - (void *)first_pte);
841                         
842                 }
843                 level++;
844         }
845         /* free pgd */
846         if (start_pfn == 0 && last_pfn == DOMAIN_MAX_PFN(domain->gaw)) {
847                 free_pgtable_page(domain->pgd);
848                 domain->pgd = NULL;
849         }
850 }
851
852 /* iommu handling */
853 static int iommu_alloc_root_entry(struct intel_iommu *iommu)
854 {
855         struct root_entry *root;
856         unsigned long flags;
857
858         root = (struct root_entry *)alloc_pgtable_page();
859         if (!root)
860                 return -ENOMEM;
861
862         __iommu_flush_cache(iommu, root, ROOT_SIZE);
863
864         spin_lock_irqsave(&iommu->lock, flags);
865         iommu->root_entry = root;
866         spin_unlock_irqrestore(&iommu->lock, flags);
867
868         return 0;
869 }
870
871 static void iommu_set_root_entry(struct intel_iommu *iommu)
872 {
873         void *addr;
874         u32 sts;
875         unsigned long flag;
876
877         addr = iommu->root_entry;
878
879         spin_lock_irqsave(&iommu->register_lock, flag);
880         dmar_writeq(iommu->reg + DMAR_RTADDR_REG, virt_to_phys(addr));
881
882         writel(iommu->gcmd | DMA_GCMD_SRTP, iommu->reg + DMAR_GCMD_REG);
883
884         /* Make sure hardware complete it */
885         IOMMU_WAIT_OP(iommu, DMAR_GSTS_REG,
886                       readl, (sts & DMA_GSTS_RTPS), sts);
887
888         spin_unlock_irqrestore(&iommu->register_lock, flag);
889 }
890
891 static void iommu_flush_write_buffer(struct intel_iommu *iommu)
892 {
893         u32 val;
894         unsigned long flag;
895
896         if (!rwbf_quirk && !cap_rwbf(iommu->cap))
897                 return;
898
899         spin_lock_irqsave(&iommu->register_lock, flag);
900         writel(iommu->gcmd | DMA_GCMD_WBF, iommu->reg + DMAR_GCMD_REG);
901
902         /* Make sure hardware complete it */
903         IOMMU_WAIT_OP(iommu, DMAR_GSTS_REG,
904                       readl, (!(val & DMA_GSTS_WBFS)), val);
905
906         spin_unlock_irqrestore(&iommu->register_lock, flag);
907 }
908
909 /* return value determine if we need a write buffer flush */
910 static void __iommu_flush_context(struct intel_iommu *iommu,
911                                   u16 did, u16 source_id, u8 function_mask,
912                                   u64 type)
913 {
914         u64 val = 0;
915         unsigned long flag;
916
917         switch (type) {
918         case DMA_CCMD_GLOBAL_INVL:
919                 val = DMA_CCMD_GLOBAL_INVL;
920                 break;
921         case DMA_CCMD_DOMAIN_INVL:
922                 val = DMA_CCMD_DOMAIN_INVL|DMA_CCMD_DID(did);
923                 break;
924         case DMA_CCMD_DEVICE_INVL:
925                 val = DMA_CCMD_DEVICE_INVL|DMA_CCMD_DID(did)
926                         | DMA_CCMD_SID(source_id) | DMA_CCMD_FM(function_mask);
927                 break;
928         default:
929                 BUG();
930         }
931         val |= DMA_CCMD_ICC;
932
933         spin_lock_irqsave(&iommu->register_lock, flag);
934         dmar_writeq(iommu->reg + DMAR_CCMD_REG, val);
935
936         /* Make sure hardware complete it */
937         IOMMU_WAIT_OP(iommu, DMAR_CCMD_REG,
938                 dmar_readq, (!(val & DMA_CCMD_ICC)), val);
939
940         spin_unlock_irqrestore(&iommu->register_lock, flag);
941 }
942
943 /* return value determine if we need a write buffer flush */
944 static void __iommu_flush_iotlb(struct intel_iommu *iommu, u16 did,
945                                 u64 addr, unsigned int size_order, u64 type)
946 {
947         int tlb_offset = ecap_iotlb_offset(iommu->ecap);
948         u64 val = 0, val_iva = 0;
949         unsigned long flag;
950
951         switch (type) {
952         case DMA_TLB_GLOBAL_FLUSH:
953                 /* global flush doesn't need set IVA_REG */
954                 val = DMA_TLB_GLOBAL_FLUSH|DMA_TLB_IVT;
955                 break;
956         case DMA_TLB_DSI_FLUSH:
957                 val = DMA_TLB_DSI_FLUSH|DMA_TLB_IVT|DMA_TLB_DID(did);
958                 break;
959         case DMA_TLB_PSI_FLUSH:
960                 val = DMA_TLB_PSI_FLUSH|DMA_TLB_IVT|DMA_TLB_DID(did);
961                 /* Note: always flush non-leaf currently */
962                 val_iva = size_order | addr;
963                 break;
964         default:
965                 BUG();
966         }
967         /* Note: set drain read/write */
968 #if 0
969         /*
970          * This is probably to be super secure.. Looks like we can
971          * ignore it without any impact.
972          */
973         if (cap_read_drain(iommu->cap))
974                 val |= DMA_TLB_READ_DRAIN;
975 #endif
976         if (cap_write_drain(iommu->cap))
977                 val |= DMA_TLB_WRITE_DRAIN;
978
979         spin_lock_irqsave(&iommu->register_lock, flag);
980         /* Note: Only uses first TLB reg currently */
981         if (val_iva)
982                 dmar_writeq(iommu->reg + tlb_offset, val_iva);
983         dmar_writeq(iommu->reg + tlb_offset + 8, val);
984
985         /* Make sure hardware complete it */
986         IOMMU_WAIT_OP(iommu, tlb_offset + 8,
987                 dmar_readq, (!(val & DMA_TLB_IVT)), val);
988
989         spin_unlock_irqrestore(&iommu->register_lock, flag);
990
991         /* check IOTLB invalidation granularity */
992         if (DMA_TLB_IAIG(val) == 0)
993                 printk(KERN_ERR"IOMMU: flush IOTLB failed\n");
994         if (DMA_TLB_IAIG(val) != DMA_TLB_IIRG(type))
995                 pr_debug("IOMMU: tlb flush request %Lx, actual %Lx\n",
996                         (unsigned long long)DMA_TLB_IIRG(type),
997                         (unsigned long long)DMA_TLB_IAIG(val));
998 }
999
1000 static struct device_domain_info *iommu_support_dev_iotlb(
1001         struct dmar_domain *domain, int segment, u8 bus, u8 devfn)
1002 {
1003         int found = 0;
1004         unsigned long flags;
1005         struct device_domain_info *info;
1006         struct intel_iommu *iommu = device_to_iommu(segment, bus, devfn);
1007
1008         if (!ecap_dev_iotlb_support(iommu->ecap))
1009                 return NULL;
1010
1011         if (!iommu->qi)
1012                 return NULL;
1013
1014         spin_lock_irqsave(&device_domain_lock, flags);
1015         list_for_each_entry(info, &domain->devices, link)
1016                 if (info->bus == bus && info->devfn == devfn) {
1017                         found = 1;
1018                         break;
1019                 }
1020         spin_unlock_irqrestore(&device_domain_lock, flags);
1021
1022         if (!found || !info->dev)
1023                 return NULL;
1024
1025         if (!pci_find_ext_capability(info->dev, PCI_EXT_CAP_ID_ATS))
1026                 return NULL;
1027
1028         if (!dmar_find_matched_atsr_unit(info->dev))
1029                 return NULL;
1030
1031         info->iommu = iommu;
1032
1033         return info;
1034 }
1035
1036 static void iommu_enable_dev_iotlb(struct device_domain_info *info)
1037 {
1038         if (!info)
1039                 return;
1040
1041         pci_enable_ats(info->dev, VTD_PAGE_SHIFT);
1042 }
1043
1044 static void iommu_disable_dev_iotlb(struct device_domain_info *info)
1045 {
1046         if (!info->dev || !pci_ats_enabled(info->dev))
1047                 return;
1048
1049         pci_disable_ats(info->dev);
1050 }
1051
1052 static void iommu_flush_dev_iotlb(struct dmar_domain *domain,
1053                                   u64 addr, unsigned mask)
1054 {
1055         u16 sid, qdep;
1056         unsigned long flags;
1057         struct device_domain_info *info;
1058
1059         spin_lock_irqsave(&device_domain_lock, flags);
1060         list_for_each_entry(info, &domain->devices, link) {
1061                 if (!info->dev || !pci_ats_enabled(info->dev))
1062                         continue;
1063
1064                 sid = info->bus << 8 | info->devfn;
1065                 qdep = pci_ats_queue_depth(info->dev);
1066                 qi_flush_dev_iotlb(info->iommu, sid, qdep, addr, mask);
1067         }
1068         spin_unlock_irqrestore(&device_domain_lock, flags);
1069 }
1070
1071 static void iommu_flush_iotlb_psi(struct intel_iommu *iommu, u16 did,
1072                                   unsigned long pfn, unsigned int pages)
1073 {
1074         unsigned int mask = ilog2(__roundup_pow_of_two(pages));
1075         uint64_t addr = (uint64_t)pfn << VTD_PAGE_SHIFT;
1076
1077         BUG_ON(pages == 0);
1078
1079         /*
1080          * Fallback to domain selective flush if no PSI support or the size is
1081          * too big.
1082          * PSI requires page size to be 2 ^ x, and the base address is naturally
1083          * aligned to the size
1084          */
1085         if (!cap_pgsel_inv(iommu->cap) || mask > cap_max_amask_val(iommu->cap))
1086                 iommu->flush.flush_iotlb(iommu, did, 0, 0,
1087                                                 DMA_TLB_DSI_FLUSH);
1088         else
1089                 iommu->flush.flush_iotlb(iommu, did, addr, mask,
1090                                                 DMA_TLB_PSI_FLUSH);
1091
1092         /*
1093          * In caching mode, domain ID 0 is reserved for non-present to present
1094          * mapping flush. Device IOTLB doesn't need to be flushed in this case.
1095          */
1096         if (!cap_caching_mode(iommu->cap) || did)
1097                 iommu_flush_dev_iotlb(iommu->domains[did], addr, mask);
1098 }
1099
1100 static void iommu_disable_protect_mem_regions(struct intel_iommu *iommu)
1101 {
1102         u32 pmen;
1103         unsigned long flags;
1104
1105         spin_lock_irqsave(&iommu->register_lock, flags);
1106         pmen = readl(iommu->reg + DMAR_PMEN_REG);
1107         pmen &= ~DMA_PMEN_EPM;
1108         writel(pmen, iommu->reg + DMAR_PMEN_REG);
1109
1110         /* wait for the protected region status bit to clear */
1111         IOMMU_WAIT_OP(iommu, DMAR_PMEN_REG,
1112                 readl, !(pmen & DMA_PMEN_PRS), pmen);
1113
1114         spin_unlock_irqrestore(&iommu->register_lock, flags);
1115 }
1116
1117 static int iommu_enable_translation(struct intel_iommu *iommu)
1118 {
1119         u32 sts;
1120         unsigned long flags;
1121
1122         spin_lock_irqsave(&iommu->register_lock, flags);
1123         iommu->gcmd |= DMA_GCMD_TE;
1124         writel(iommu->gcmd, iommu->reg + DMAR_GCMD_REG);
1125
1126         /* Make sure hardware complete it */
1127         IOMMU_WAIT_OP(iommu, DMAR_GSTS_REG,
1128                       readl, (sts & DMA_GSTS_TES), sts);
1129
1130         spin_unlock_irqrestore(&iommu->register_lock, flags);
1131         return 0;
1132 }
1133
1134 static int iommu_disable_translation(struct intel_iommu *iommu)
1135 {
1136         u32 sts;
1137         unsigned long flag;
1138
1139         spin_lock_irqsave(&iommu->register_lock, flag);
1140         iommu->gcmd &= ~DMA_GCMD_TE;
1141         writel(iommu->gcmd, iommu->reg + DMAR_GCMD_REG);
1142
1143         /* Make sure hardware complete it */
1144         IOMMU_WAIT_OP(iommu, DMAR_GSTS_REG,
1145                       readl, (!(sts & DMA_GSTS_TES)), sts);
1146
1147         spin_unlock_irqrestore(&iommu->register_lock, flag);
1148         return 0;
1149 }
1150
1151
1152 static int iommu_init_domains(struct intel_iommu *iommu)
1153 {
1154         unsigned long ndomains;
1155         unsigned long nlongs;
1156
1157         ndomains = cap_ndoms(iommu->cap);
1158         pr_debug("Number of Domains supportd <%ld>\n", ndomains);
1159         nlongs = BITS_TO_LONGS(ndomains);
1160
1161         /* TBD: there might be 64K domains,
1162          * consider other allocation for future chip
1163          */
1164         iommu->domain_ids = kcalloc(nlongs, sizeof(unsigned long), GFP_KERNEL);
1165         if (!iommu->domain_ids) {
1166                 printk(KERN_ERR "Allocating domain id array failed\n");
1167                 return -ENOMEM;
1168         }
1169         iommu->domains = kcalloc(ndomains, sizeof(struct dmar_domain *),
1170                         GFP_KERNEL);
1171         if (!iommu->domains) {
1172                 printk(KERN_ERR "Allocating domain array failed\n");
1173                 kfree(iommu->domain_ids);
1174                 return -ENOMEM;
1175         }
1176
1177         spin_lock_init(&iommu->lock);
1178
1179         /*
1180          * if Caching mode is set, then invalid translations are tagged
1181          * with domainid 0. Hence we need to pre-allocate it.
1182          */
1183         if (cap_caching_mode(iommu->cap))
1184                 set_bit(0, iommu->domain_ids);
1185         return 0;
1186 }
1187
1188
1189 static void domain_exit(struct dmar_domain *domain);
1190 static void vm_domain_exit(struct dmar_domain *domain);
1191
1192 void free_dmar_iommu(struct intel_iommu *iommu)
1193 {
1194         struct dmar_domain *domain;
1195         int i;
1196         unsigned long flags;
1197
1198         i = find_first_bit(iommu->domain_ids, cap_ndoms(iommu->cap));
1199         for (; i < cap_ndoms(iommu->cap); ) {
1200                 domain = iommu->domains[i];
1201                 clear_bit(i, iommu->domain_ids);
1202
1203                 spin_lock_irqsave(&domain->iommu_lock, flags);
1204                 if (--domain->iommu_count == 0) {
1205                         if (domain->flags & DOMAIN_FLAG_VIRTUAL_MACHINE)
1206                                 vm_domain_exit(domain);
1207                         else
1208                                 domain_exit(domain);
1209                 }
1210                 spin_unlock_irqrestore(&domain->iommu_lock, flags);
1211
1212                 i = find_next_bit(iommu->domain_ids,
1213                         cap_ndoms(iommu->cap), i+1);
1214         }
1215
1216         if (iommu->gcmd & DMA_GCMD_TE)
1217                 iommu_disable_translation(iommu);
1218
1219         if (iommu->irq) {
1220                 set_irq_data(iommu->irq, NULL);
1221                 /* This will mask the irq */
1222                 free_irq(iommu->irq, iommu);
1223                 destroy_irq(iommu->irq);
1224         }
1225
1226         kfree(iommu->domains);
1227         kfree(iommu->domain_ids);
1228
1229         g_iommus[iommu->seq_id] = NULL;
1230
1231         /* if all iommus are freed, free g_iommus */
1232         for (i = 0; i < g_num_of_iommus; i++) {
1233                 if (g_iommus[i])
1234                         break;
1235         }
1236
1237         if (i == g_num_of_iommus)
1238                 kfree(g_iommus);
1239
1240         /* free context mapping */
1241         free_context_table(iommu);
1242 }
1243
1244 static struct dmar_domain *alloc_domain(void)
1245 {
1246         struct dmar_domain *domain;
1247
1248         domain = alloc_domain_mem();
1249         if (!domain)
1250                 return NULL;
1251
1252         memset(&domain->iommu_bmp, 0, sizeof(unsigned long));
1253         domain->flags = 0;
1254
1255         return domain;
1256 }
1257
1258 static int iommu_attach_domain(struct dmar_domain *domain,
1259                                struct intel_iommu *iommu)
1260 {
1261         int num;
1262         unsigned long ndomains;
1263         unsigned long flags;
1264
1265         ndomains = cap_ndoms(iommu->cap);
1266
1267         spin_lock_irqsave(&iommu->lock, flags);
1268
1269         num = find_first_zero_bit(iommu->domain_ids, ndomains);
1270         if (num >= ndomains) {
1271                 spin_unlock_irqrestore(&iommu->lock, flags);
1272                 printk(KERN_ERR "IOMMU: no free domain ids\n");
1273                 return -ENOMEM;
1274         }
1275
1276         domain->id = num;
1277         set_bit(num, iommu->domain_ids);
1278         set_bit(iommu->seq_id, &domain->iommu_bmp);
1279         iommu->domains[num] = domain;
1280         spin_unlock_irqrestore(&iommu->lock, flags);
1281
1282         return 0;
1283 }
1284
1285 static void iommu_detach_domain(struct dmar_domain *domain,
1286                                 struct intel_iommu *iommu)
1287 {
1288         unsigned long flags;
1289         int num, ndomains;
1290         int found = 0;
1291
1292         spin_lock_irqsave(&iommu->lock, flags);
1293         ndomains = cap_ndoms(iommu->cap);
1294         num = find_first_bit(iommu->domain_ids, ndomains);
1295         for (; num < ndomains; ) {
1296                 if (iommu->domains[num] == domain) {
1297                         found = 1;
1298                         break;
1299                 }
1300                 num = find_next_bit(iommu->domain_ids,
1301                                     cap_ndoms(iommu->cap), num+1);
1302         }
1303
1304         if (found) {
1305                 clear_bit(num, iommu->domain_ids);
1306                 clear_bit(iommu->seq_id, &domain->iommu_bmp);
1307                 iommu->domains[num] = NULL;
1308         }
1309         spin_unlock_irqrestore(&iommu->lock, flags);
1310 }
1311
1312 static struct iova_domain reserved_iova_list;
1313 static struct lock_class_key reserved_alloc_key;
1314 static struct lock_class_key reserved_rbtree_key;
1315
1316 static void dmar_init_reserved_ranges(void)
1317 {
1318         struct pci_dev *pdev = NULL;
1319         struct iova *iova;
1320         int i;
1321
1322         init_iova_domain(&reserved_iova_list, DMA_32BIT_PFN);
1323
1324         lockdep_set_class(&reserved_iova_list.iova_alloc_lock,
1325                 &reserved_alloc_key);
1326         lockdep_set_class(&reserved_iova_list.iova_rbtree_lock,
1327                 &reserved_rbtree_key);
1328
1329         /* IOAPIC ranges shouldn't be accessed by DMA */
1330         iova = reserve_iova(&reserved_iova_list, IOVA_PFN(IOAPIC_RANGE_START),
1331                 IOVA_PFN(IOAPIC_RANGE_END));
1332         if (!iova)
1333                 printk(KERN_ERR "Reserve IOAPIC range failed\n");
1334
1335         /* Reserve all PCI MMIO to avoid peer-to-peer access */
1336         for_each_pci_dev(pdev) {
1337                 struct resource *r;
1338
1339                 for (i = 0; i < PCI_NUM_RESOURCES; i++) {
1340                         r = &pdev->resource[i];
1341                         if (!r->flags || !(r->flags & IORESOURCE_MEM))
1342                                 continue;
1343                         iova = reserve_iova(&reserved_iova_list,
1344                                             IOVA_PFN(r->start),
1345                                             IOVA_PFN(r->end));
1346                         if (!iova)
1347                                 printk(KERN_ERR "Reserve iova failed\n");
1348                 }
1349         }
1350
1351 }
1352
1353 static void domain_reserve_special_ranges(struct dmar_domain *domain)
1354 {
1355         copy_reserved_iova(&reserved_iova_list, &domain->iovad);
1356 }
1357
1358 static inline int guestwidth_to_adjustwidth(int gaw)
1359 {
1360         int agaw;
1361         int r = (gaw - 12) % 9;
1362
1363         if (r == 0)
1364                 agaw = gaw;
1365         else
1366                 agaw = gaw + 9 - r;
1367         if (agaw > 64)
1368                 agaw = 64;
1369         return agaw;
1370 }
1371
1372 static int domain_init(struct dmar_domain *domain, int guest_width)
1373 {
1374         struct intel_iommu *iommu;
1375         int adjust_width, agaw;
1376         unsigned long sagaw;
1377
1378         init_iova_domain(&domain->iovad, DMA_32BIT_PFN);
1379         spin_lock_init(&domain->iommu_lock);
1380
1381         domain_reserve_special_ranges(domain);
1382
1383         /* calculate AGAW */
1384         iommu = domain_get_iommu(domain);
1385         if (guest_width > cap_mgaw(iommu->cap))
1386                 guest_width = cap_mgaw(iommu->cap);
1387         domain->gaw = guest_width;
1388         adjust_width = guestwidth_to_adjustwidth(guest_width);
1389         agaw = width_to_agaw(adjust_width);
1390         sagaw = cap_sagaw(iommu->cap);
1391         if (!test_bit(agaw, &sagaw)) {
1392                 /* hardware doesn't support it, choose a bigger one */
1393                 pr_debug("IOMMU: hardware doesn't support agaw %d\n", agaw);
1394                 agaw = find_next_bit(&sagaw, 5, agaw);
1395                 if (agaw >= 5)
1396                         return -ENODEV;
1397         }
1398         domain->agaw = agaw;
1399         INIT_LIST_HEAD(&domain->devices);
1400
1401         if (ecap_coherent(iommu->ecap))
1402                 domain->iommu_coherency = 1;
1403         else
1404                 domain->iommu_coherency = 0;
1405
1406         if (ecap_sc_support(iommu->ecap))
1407                 domain->iommu_snooping = 1;
1408         else
1409                 domain->iommu_snooping = 0;
1410
1411         domain->iommu_count = 1;
1412
1413         /* always allocate the top pgd */
1414         domain->pgd = (struct dma_pte *)alloc_pgtable_page();
1415         if (!domain->pgd)
1416                 return -ENOMEM;
1417         __iommu_flush_cache(iommu, domain->pgd, PAGE_SIZE);
1418         return 0;
1419 }
1420
1421 static void domain_exit(struct dmar_domain *domain)
1422 {
1423         struct dmar_drhd_unit *drhd;
1424         struct intel_iommu *iommu;
1425
1426         /* Domain 0 is reserved, so dont process it */
1427         if (!domain)
1428                 return;
1429
1430         domain_remove_dev_info(domain);
1431         /* destroy iovas */
1432         put_iova_domain(&domain->iovad);
1433
1434         /* clear ptes */
1435         dma_pte_clear_range(domain, 0, DOMAIN_MAX_PFN(domain->gaw));
1436
1437         /* free page tables */
1438         dma_pte_free_pagetable(domain, 0, DOMAIN_MAX_PFN(domain->gaw));
1439
1440         for_each_active_iommu(iommu, drhd)
1441                 if (test_bit(iommu->seq_id, &domain->iommu_bmp))
1442                         iommu_detach_domain(domain, iommu);
1443
1444         free_domain_mem(domain);
1445 }
1446
1447 static int domain_context_mapping_one(struct dmar_domain *domain, int segment,
1448                                  u8 bus, u8 devfn, int translation)
1449 {
1450         struct context_entry *context;
1451         unsigned long flags;
1452         struct intel_iommu *iommu;
1453         struct dma_pte *pgd;
1454         unsigned long num;
1455         unsigned long ndomains;
1456         int id;
1457         int agaw;
1458         struct device_domain_info *info = NULL;
1459
1460         pr_debug("Set context mapping for %02x:%02x.%d\n",
1461                 bus, PCI_SLOT(devfn), PCI_FUNC(devfn));
1462
1463         BUG_ON(!domain->pgd);
1464         BUG_ON(translation != CONTEXT_TT_PASS_THROUGH &&
1465                translation != CONTEXT_TT_MULTI_LEVEL);
1466
1467         iommu = device_to_iommu(segment, bus, devfn);
1468         if (!iommu)
1469                 return -ENODEV;
1470
1471         context = device_to_context_entry(iommu, bus, devfn);
1472         if (!context)
1473                 return -ENOMEM;
1474         spin_lock_irqsave(&iommu->lock, flags);
1475         if (context_present(context)) {
1476                 spin_unlock_irqrestore(&iommu->lock, flags);
1477                 return 0;
1478         }
1479
1480         id = domain->id;
1481         pgd = domain->pgd;
1482
1483         if (domain->flags & DOMAIN_FLAG_VIRTUAL_MACHINE ||
1484             domain->flags & DOMAIN_FLAG_STATIC_IDENTITY) {
1485                 int found = 0;
1486
1487                 /* find an available domain id for this device in iommu */
1488                 ndomains = cap_ndoms(iommu->cap);
1489                 num = find_first_bit(iommu->domain_ids, ndomains);
1490                 for (; num < ndomains; ) {
1491                         if (iommu->domains[num] == domain) {
1492                                 id = num;
1493                                 found = 1;
1494                                 break;
1495                         }
1496                         num = find_next_bit(iommu->domain_ids,
1497                                             cap_ndoms(iommu->cap), num+1);
1498                 }
1499
1500                 if (found == 0) {
1501                         num = find_first_zero_bit(iommu->domain_ids, ndomains);
1502                         if (num >= ndomains) {
1503                                 spin_unlock_irqrestore(&iommu->lock, flags);
1504                                 printk(KERN_ERR "IOMMU: no free domain ids\n");
1505                                 return -EFAULT;
1506                         }
1507
1508                         set_bit(num, iommu->domain_ids);
1509                         iommu->domains[num] = domain;
1510                         id = num;
1511                 }
1512
1513                 /* Skip top levels of page tables for
1514                  * iommu which has less agaw than default.
1515                  */
1516                 for (agaw = domain->agaw; agaw != iommu->agaw; agaw--) {
1517                         pgd = phys_to_virt(dma_pte_addr(pgd));
1518                         if (!dma_pte_present(pgd)) {
1519                                 spin_unlock_irqrestore(&iommu->lock, flags);
1520                                 return -ENOMEM;
1521                         }
1522                 }
1523         }
1524
1525         context_set_domain_id(context, id);
1526
1527         if (translation != CONTEXT_TT_PASS_THROUGH) {
1528                 info = iommu_support_dev_iotlb(domain, segment, bus, devfn);
1529                 translation = info ? CONTEXT_TT_DEV_IOTLB :
1530                                      CONTEXT_TT_MULTI_LEVEL;
1531         }
1532         /*
1533          * In pass through mode, AW must be programmed to indicate the largest
1534          * AGAW value supported by hardware. And ASR is ignored by hardware.
1535          */
1536         if (unlikely(translation == CONTEXT_TT_PASS_THROUGH))
1537                 context_set_address_width(context, iommu->msagaw);
1538         else {
1539                 context_set_address_root(context, virt_to_phys(pgd));
1540                 context_set_address_width(context, iommu->agaw);
1541         }
1542
1543         context_set_translation_type(context, translation);
1544         context_set_fault_enable(context);
1545         context_set_present(context);
1546         domain_flush_cache(domain, context, sizeof(*context));
1547
1548         /*
1549          * It's a non-present to present mapping. If hardware doesn't cache
1550          * non-present entry we only need to flush the write-buffer. If the
1551          * _does_ cache non-present entries, then it does so in the special
1552          * domain #0, which we have to flush:
1553          */
1554         if (cap_caching_mode(iommu->cap)) {
1555                 iommu->flush.flush_context(iommu, 0,
1556                                            (((u16)bus) << 8) | devfn,
1557                                            DMA_CCMD_MASK_NOBIT,
1558                                            DMA_CCMD_DEVICE_INVL);
1559                 iommu->flush.flush_iotlb(iommu, 0, 0, 0, DMA_TLB_DSI_FLUSH);
1560         } else {
1561                 iommu_flush_write_buffer(iommu);
1562         }
1563         iommu_enable_dev_iotlb(info);
1564         spin_unlock_irqrestore(&iommu->lock, flags);
1565
1566         spin_lock_irqsave(&domain->iommu_lock, flags);
1567         if (!test_and_set_bit(iommu->seq_id, &domain->iommu_bmp)) {
1568                 domain->iommu_count++;
1569                 domain_update_iommu_cap(domain);
1570         }
1571         spin_unlock_irqrestore(&domain->iommu_lock, flags);
1572         return 0;
1573 }
1574
1575 static int
1576 domain_context_mapping(struct dmar_domain *domain, struct pci_dev *pdev,
1577                         int translation)
1578 {
1579         int ret;
1580         struct pci_dev *tmp, *parent;
1581
1582         ret = domain_context_mapping_one(domain, pci_domain_nr(pdev->bus),
1583                                          pdev->bus->number, pdev->devfn,
1584                                          translation);
1585         if (ret)
1586                 return ret;
1587
1588         /* dependent device mapping */
1589         tmp = pci_find_upstream_pcie_bridge(pdev);
1590         if (!tmp)
1591                 return 0;
1592         /* Secondary interface's bus number and devfn 0 */
1593         parent = pdev->bus->self;
1594         while (parent != tmp) {
1595                 ret = domain_context_mapping_one(domain,
1596                                                  pci_domain_nr(parent->bus),
1597                                                  parent->bus->number,
1598                                                  parent->devfn, translation);
1599                 if (ret)
1600                         return ret;
1601                 parent = parent->bus->self;
1602         }
1603         if (tmp->is_pcie) /* this is a PCIE-to-PCI bridge */
1604                 return domain_context_mapping_one(domain,
1605                                         pci_domain_nr(tmp->subordinate),
1606                                         tmp->subordinate->number, 0,
1607                                         translation);
1608         else /* this is a legacy PCI bridge */
1609                 return domain_context_mapping_one(domain,
1610                                                   pci_domain_nr(tmp->bus),
1611                                                   tmp->bus->number,
1612                                                   tmp->devfn,
1613                                                   translation);
1614 }
1615
1616 static int domain_context_mapped(struct pci_dev *pdev)
1617 {
1618         int ret;
1619         struct pci_dev *tmp, *parent;
1620         struct intel_iommu *iommu;
1621
1622         iommu = device_to_iommu(pci_domain_nr(pdev->bus), pdev->bus->number,
1623                                 pdev->devfn);
1624         if (!iommu)
1625                 return -ENODEV;
1626
1627         ret = device_context_mapped(iommu, pdev->bus->number, pdev->devfn);
1628         if (!ret)
1629                 return ret;
1630         /* dependent device mapping */
1631         tmp = pci_find_upstream_pcie_bridge(pdev);
1632         if (!tmp)
1633                 return ret;
1634         /* Secondary interface's bus number and devfn 0 */
1635         parent = pdev->bus->self;
1636         while (parent != tmp) {
1637                 ret = device_context_mapped(iommu, parent->bus->number,
1638                                             parent->devfn);
1639                 if (!ret)
1640                         return ret;
1641                 parent = parent->bus->self;
1642         }
1643         if (tmp->is_pcie)
1644                 return device_context_mapped(iommu, tmp->subordinate->number,
1645                                              0);
1646         else
1647                 return device_context_mapped(iommu, tmp->bus->number,
1648                                              tmp->devfn);
1649 }
1650
1651 /* Returns a number of VTD pages, but aligned to MM page size */
1652 static inline unsigned long aligned_nrpages(unsigned long host_addr,
1653                                             size_t size)
1654 {
1655         host_addr &= ~PAGE_MASK;
1656         return PAGE_ALIGN(host_addr + size) >> VTD_PAGE_SHIFT;
1657 }
1658
1659 static int __domain_mapping(struct dmar_domain *domain, unsigned long iov_pfn,
1660                             struct scatterlist *sg, unsigned long phys_pfn,
1661                             unsigned long nr_pages, int prot)
1662 {
1663         struct dma_pte *first_pte = NULL, *pte = NULL;
1664         phys_addr_t uninitialized_var(pteval);
1665         int addr_width = agaw_to_width(domain->agaw) - VTD_PAGE_SHIFT;
1666         unsigned long sg_res;
1667
1668         BUG_ON(addr_width < BITS_PER_LONG && (iov_pfn + nr_pages - 1) >> addr_width);
1669
1670         if ((prot & (DMA_PTE_READ|DMA_PTE_WRITE)) == 0)
1671                 return -EINVAL;
1672
1673         prot &= DMA_PTE_READ | DMA_PTE_WRITE | DMA_PTE_SNP;
1674
1675         if (sg)
1676                 sg_res = 0;
1677         else {
1678                 sg_res = nr_pages + 1;
1679                 pteval = ((phys_addr_t)phys_pfn << VTD_PAGE_SHIFT) | prot;
1680         }
1681
1682         while (nr_pages--) {
1683                 uint64_t tmp;
1684
1685                 if (!sg_res) {
1686                         sg_res = aligned_nrpages(sg->offset, sg->length);
1687                         sg->dma_address = ((dma_addr_t)iov_pfn << VTD_PAGE_SHIFT) + sg->offset;
1688                         sg->dma_length = sg->length;
1689                         pteval = page_to_phys(sg_page(sg)) | prot;
1690                 }
1691                 if (!pte) {
1692                         first_pte = pte = pfn_to_dma_pte(domain, iov_pfn);
1693                         if (!pte)
1694                                 return -ENOMEM;
1695                 }
1696                 /* We don't need lock here, nobody else
1697                  * touches the iova range
1698                  */
1699                 tmp = cmpxchg64_local(&pte->val, 0ULL, pteval);
1700                 if (tmp) {
1701                         static int dumps = 5;
1702                         printk(KERN_CRIT "ERROR: DMA PTE for vPFN 0x%lx already set (to %llx not %llx)\n",
1703                                iov_pfn, tmp, (unsigned long long)pteval);
1704                         if (dumps) {
1705                                 dumps--;
1706                                 debug_dma_dump_mappings(NULL);
1707                         }
1708                         WARN_ON(1);
1709                 }
1710                 pte++;
1711                 if (!nr_pages || first_pte_in_page(pte)) {
1712                         domain_flush_cache(domain, first_pte,
1713                                            (void *)pte - (void *)first_pte);
1714                         pte = NULL;
1715                 }
1716                 iov_pfn++;
1717                 pteval += VTD_PAGE_SIZE;
1718                 sg_res--;
1719                 if (!sg_res)
1720                         sg = sg_next(sg);
1721         }
1722         return 0;
1723 }
1724
1725 static inline int domain_sg_mapping(struct dmar_domain *domain, unsigned long iov_pfn,
1726                                     struct scatterlist *sg, unsigned long nr_pages,
1727                                     int prot)
1728 {
1729         return __domain_mapping(domain, iov_pfn, sg, 0, nr_pages, prot);
1730 }
1731
1732 static inline int domain_pfn_mapping(struct dmar_domain *domain, unsigned long iov_pfn,
1733                                      unsigned long phys_pfn, unsigned long nr_pages,
1734                                      int prot)
1735 {
1736         return __domain_mapping(domain, iov_pfn, NULL, phys_pfn, nr_pages, prot);
1737 }
1738
1739 static void iommu_detach_dev(struct intel_iommu *iommu, u8 bus, u8 devfn)
1740 {
1741         if (!iommu)
1742                 return;
1743
1744         clear_context_table(iommu, bus, devfn);
1745         iommu->flush.flush_context(iommu, 0, 0, 0,
1746                                            DMA_CCMD_GLOBAL_INVL);
1747         iommu->flush.flush_iotlb(iommu, 0, 0, 0, DMA_TLB_GLOBAL_FLUSH);
1748 }
1749
1750 static void domain_remove_dev_info(struct dmar_domain *domain)
1751 {
1752         struct device_domain_info *info;
1753         unsigned long flags;
1754         struct intel_iommu *iommu;
1755
1756         spin_lock_irqsave(&device_domain_lock, flags);
1757         while (!list_empty(&domain->devices)) {
1758                 info = list_entry(domain->devices.next,
1759                         struct device_domain_info, link);
1760                 list_del(&info->link);
1761                 list_del(&info->global);
1762                 if (info->dev)
1763                         info->dev->dev.archdata.iommu = NULL;
1764                 spin_unlock_irqrestore(&device_domain_lock, flags);
1765
1766                 iommu_disable_dev_iotlb(info);
1767                 iommu = device_to_iommu(info->segment, info->bus, info->devfn);
1768                 iommu_detach_dev(iommu, info->bus, info->devfn);
1769                 free_devinfo_mem(info);
1770
1771                 spin_lock_irqsave(&device_domain_lock, flags);
1772         }
1773         spin_unlock_irqrestore(&device_domain_lock, flags);
1774 }
1775
1776 /*
1777  * find_domain
1778  * Note: we use struct pci_dev->dev.archdata.iommu stores the info
1779  */
1780 static struct dmar_domain *
1781 find_domain(struct pci_dev *pdev)
1782 {
1783         struct device_domain_info *info;
1784
1785         /* No lock here, assumes no domain exit in normal case */
1786         info = pdev->dev.archdata.iommu;
1787         if (info)
1788                 return info->domain;
1789         return NULL;
1790 }
1791
1792 /* domain is initialized */
1793 static struct dmar_domain *get_domain_for_dev(struct pci_dev *pdev, int gaw)
1794 {
1795         struct dmar_domain *domain, *found = NULL;
1796         struct intel_iommu *iommu;
1797         struct dmar_drhd_unit *drhd;
1798         struct device_domain_info *info, *tmp;
1799         struct pci_dev *dev_tmp;
1800         unsigned long flags;
1801         int bus = 0, devfn = 0;
1802         int segment;
1803         int ret;
1804
1805         domain = find_domain(pdev);
1806         if (domain)
1807                 return domain;
1808
1809         segment = pci_domain_nr(pdev->bus);
1810
1811         dev_tmp = pci_find_upstream_pcie_bridge(pdev);
1812         if (dev_tmp) {
1813                 if (dev_tmp->is_pcie) {
1814                         bus = dev_tmp->subordinate->number;
1815                         devfn = 0;
1816                 } else {
1817                         bus = dev_tmp->bus->number;
1818                         devfn = dev_tmp->devfn;
1819                 }
1820                 spin_lock_irqsave(&device_domain_lock, flags);
1821                 list_for_each_entry(info, &device_domain_list, global) {
1822                         if (info->segment == segment &&
1823                             info->bus == bus && info->devfn == devfn) {
1824                                 found = info->domain;
1825                                 break;
1826                         }
1827                 }
1828                 spin_unlock_irqrestore(&device_domain_lock, flags);
1829                 /* pcie-pci bridge already has a domain, uses it */
1830                 if (found) {
1831                         domain = found;
1832                         goto found_domain;
1833                 }
1834         }
1835
1836         domain = alloc_domain();
1837         if (!domain)
1838                 goto error;
1839
1840         /* Allocate new domain for the device */
1841         drhd = dmar_find_matched_drhd_unit(pdev);
1842         if (!drhd) {
1843                 printk(KERN_ERR "IOMMU: can't find DMAR for device %s\n",
1844                         pci_name(pdev));
1845                 return NULL;
1846         }
1847         iommu = drhd->iommu;
1848
1849         ret = iommu_attach_domain(domain, iommu);
1850         if (ret) {
1851                 domain_exit(domain);
1852                 goto error;
1853         }
1854
1855         if (domain_init(domain, gaw)) {
1856                 domain_exit(domain);
1857                 goto error;
1858         }
1859
1860         /* register pcie-to-pci device */
1861         if (dev_tmp) {
1862                 info = alloc_devinfo_mem();
1863                 if (!info) {
1864                         domain_exit(domain);
1865                         goto error;
1866                 }
1867                 info->segment = segment;
1868                 info->bus = bus;
1869                 info->devfn = devfn;
1870                 info->dev = NULL;
1871                 info->domain = domain;
1872                 /* This domain is shared by devices under p2p bridge */
1873                 domain->flags |= DOMAIN_FLAG_P2P_MULTIPLE_DEVICES;
1874
1875                 /* pcie-to-pci bridge already has a domain, uses it */
1876                 found = NULL;
1877                 spin_lock_irqsave(&device_domain_lock, flags);
1878                 list_for_each_entry(tmp, &device_domain_list, global) {
1879                         if (tmp->segment == segment &&
1880                             tmp->bus == bus && tmp->devfn == devfn) {
1881                                 found = tmp->domain;
1882                                 break;
1883                         }
1884                 }
1885                 if (found) {
1886                         free_devinfo_mem(info);
1887                         domain_exit(domain);
1888                         domain = found;
1889                 } else {
1890                         list_add(&info->link, &domain->devices);
1891                         list_add(&info->global, &device_domain_list);
1892                 }
1893                 spin_unlock_irqrestore(&device_domain_lock, flags);
1894         }
1895
1896 found_domain:
1897         info = alloc_devinfo_mem();
1898         if (!info)
1899                 goto error;
1900         info->segment = segment;
1901         info->bus = pdev->bus->number;
1902         info->devfn = pdev->devfn;
1903         info->dev = pdev;
1904         info->domain = domain;
1905         spin_lock_irqsave(&device_domain_lock, flags);
1906         /* somebody is fast */
1907         found = find_domain(pdev);
1908         if (found != NULL) {
1909                 spin_unlock_irqrestore(&device_domain_lock, flags);
1910                 if (found != domain) {
1911                         domain_exit(domain);
1912                         domain = found;
1913                 }
1914                 free_devinfo_mem(info);
1915                 return domain;
1916         }
1917         list_add(&info->link, &domain->devices);
1918         list_add(&info->global, &device_domain_list);
1919         pdev->dev.archdata.iommu = info;
1920         spin_unlock_irqrestore(&device_domain_lock, flags);
1921         return domain;
1922 error:
1923         /* recheck it here, maybe others set it */
1924         return find_domain(pdev);
1925 }
1926
1927 static int iommu_identity_mapping;
1928
1929 static int iommu_domain_identity_map(struct dmar_domain *domain,
1930                                      unsigned long long start,
1931                                      unsigned long long end)
1932 {
1933         unsigned long first_vpfn = start >> VTD_PAGE_SHIFT;
1934         unsigned long last_vpfn = end >> VTD_PAGE_SHIFT;
1935
1936         if (!reserve_iova(&domain->iovad, dma_to_mm_pfn(first_vpfn),
1937                           dma_to_mm_pfn(last_vpfn))) {
1938                 printk(KERN_ERR "IOMMU: reserve iova failed\n");
1939                 return -ENOMEM;
1940         }
1941
1942         pr_debug("Mapping reserved region %llx-%llx for domain %d\n",
1943                  start, end, domain->id);
1944         /*
1945          * RMRR range might have overlap with physical memory range,
1946          * clear it first
1947          */
1948         dma_pte_clear_range(domain, first_vpfn, last_vpfn);
1949
1950         return domain_pfn_mapping(domain, first_vpfn, first_vpfn,
1951                                   last_vpfn - first_vpfn + 1,
1952                                   DMA_PTE_READ|DMA_PTE_WRITE);
1953 }
1954
1955 static int iommu_prepare_identity_map(struct pci_dev *pdev,
1956                                       unsigned long long start,
1957                                       unsigned long long end)
1958 {
1959         struct dmar_domain *domain;
1960         int ret;
1961
1962         printk(KERN_INFO
1963                "IOMMU: Setting identity map for device %s [0x%Lx - 0x%Lx]\n",
1964                pci_name(pdev), start, end);
1965
1966         domain = get_domain_for_dev(pdev, DEFAULT_DOMAIN_ADDRESS_WIDTH);
1967         if (!domain)
1968                 return -ENOMEM;
1969
1970         ret = iommu_domain_identity_map(domain, start, end);
1971         if (ret)
1972                 goto error;
1973
1974         /* context entry init */
1975         ret = domain_context_mapping(domain, pdev, CONTEXT_TT_MULTI_LEVEL);
1976         if (ret)
1977                 goto error;
1978
1979         return 0;
1980
1981  error:
1982         domain_exit(domain);
1983         return ret;
1984 }
1985
1986 static inline int iommu_prepare_rmrr_dev(struct dmar_rmrr_unit *rmrr,
1987         struct pci_dev *pdev)
1988 {
1989         if (pdev->dev.archdata.iommu == DUMMY_DEVICE_DOMAIN_INFO)
1990                 return 0;
1991         return iommu_prepare_identity_map(pdev, rmrr->base_address,
1992                 rmrr->end_address + 1);
1993 }
1994
1995 #ifdef CONFIG_DMAR_FLOPPY_WA
1996 static inline void iommu_prepare_isa(void)
1997 {
1998         struct pci_dev *pdev;
1999         int ret;
2000
2001         pdev = pci_get_class(PCI_CLASS_BRIDGE_ISA << 8, NULL);
2002         if (!pdev)
2003                 return;
2004
2005         printk(KERN_INFO "IOMMU: Prepare 0-16MiB unity mapping for LPC\n");
2006         ret = iommu_prepare_identity_map(pdev, 0, 16*1024*1024);
2007
2008         if (ret)
2009                 printk(KERN_ERR "IOMMU: Failed to create 0-16MiB identity map; "
2010                        "floppy might not work\n");
2011
2012 }
2013 #else
2014 static inline void iommu_prepare_isa(void)
2015 {
2016         return;
2017 }
2018 #endif /* !CONFIG_DMAR_FLPY_WA */
2019
2020 /* Initialize each context entry as pass through.*/
2021 static int __init init_context_pass_through(void)
2022 {
2023         struct pci_dev *pdev = NULL;
2024         struct dmar_domain *domain;
2025         int ret;
2026
2027         for_each_pci_dev(pdev) {
2028                 domain = get_domain_for_dev(pdev, DEFAULT_DOMAIN_ADDRESS_WIDTH);
2029                 ret = domain_context_mapping(domain, pdev,
2030                                              CONTEXT_TT_PASS_THROUGH);
2031                 if (ret)
2032                         return ret;
2033         }
2034         return 0;
2035 }
2036
2037 static int md_domain_init(struct dmar_domain *domain, int guest_width);
2038
2039 static int __init si_domain_work_fn(unsigned long start_pfn,
2040                                     unsigned long end_pfn, void *datax)
2041 {
2042         int *ret = datax;
2043
2044         *ret = iommu_domain_identity_map(si_domain,
2045                                          (uint64_t)start_pfn << PAGE_SHIFT,
2046                                          (uint64_t)end_pfn << PAGE_SHIFT);
2047         return *ret;
2048
2049 }
2050
2051 static int si_domain_init(void)
2052 {
2053         struct dmar_drhd_unit *drhd;
2054         struct intel_iommu *iommu;
2055         int nid, ret = 0;
2056
2057         si_domain = alloc_domain();
2058         if (!si_domain)
2059                 return -EFAULT;
2060
2061         pr_debug("Identity mapping domain is domain %d\n", si_domain->id);
2062
2063         for_each_active_iommu(iommu, drhd) {
2064                 ret = iommu_attach_domain(si_domain, iommu);
2065                 if (ret) {
2066                         domain_exit(si_domain);
2067                         return -EFAULT;
2068                 }
2069         }
2070
2071         if (md_domain_init(si_domain, DEFAULT_DOMAIN_ADDRESS_WIDTH)) {
2072                 domain_exit(si_domain);
2073                 return -EFAULT;
2074         }
2075
2076         si_domain->flags = DOMAIN_FLAG_STATIC_IDENTITY;
2077
2078         for_each_online_node(nid) {
2079                 work_with_active_regions(nid, si_domain_work_fn, &ret);
2080                 if (ret)
2081                         return ret;
2082         }
2083
2084         return 0;
2085 }
2086
2087 static void domain_remove_one_dev_info(struct dmar_domain *domain,
2088                                           struct pci_dev *pdev);
2089 static int identity_mapping(struct pci_dev *pdev)
2090 {
2091         struct device_domain_info *info;
2092
2093         if (likely(!iommu_identity_mapping))
2094                 return 0;
2095
2096
2097         list_for_each_entry(info, &si_domain->devices, link)
2098                 if (info->dev == pdev)
2099                         return 1;
2100         return 0;
2101 }
2102
2103 static int domain_add_dev_info(struct dmar_domain *domain,
2104                                   struct pci_dev *pdev)
2105 {
2106         struct device_domain_info *info;
2107         unsigned long flags;
2108
2109         info = alloc_devinfo_mem();
2110         if (!info)
2111                 return -ENOMEM;
2112
2113         info->segment = pci_domain_nr(pdev->bus);
2114         info->bus = pdev->bus->number;
2115         info->devfn = pdev->devfn;
2116         info->dev = pdev;
2117         info->domain = domain;
2118
2119         spin_lock_irqsave(&device_domain_lock, flags);
2120         list_add(&info->link, &domain->devices);
2121         list_add(&info->global, &device_domain_list);
2122         pdev->dev.archdata.iommu = info;
2123         spin_unlock_irqrestore(&device_domain_lock, flags);
2124
2125         return 0;
2126 }
2127
2128 static int iommu_should_identity_map(struct pci_dev *pdev, int startup)
2129 {
2130         if (iommu_identity_mapping == 2)
2131                 return IS_GFX_DEVICE(pdev);
2132
2133         /*
2134          * We want to start off with all devices in the 1:1 domain, and
2135          * take them out later if we find they can't access all of memory.
2136          *
2137          * However, we can't do this for PCI devices behind bridges,
2138          * because all PCI devices behind the same bridge will end up
2139          * with the same source-id on their transactions.
2140          *
2141          * Practically speaking, we can't change things around for these
2142          * devices at run-time, because we can't be sure there'll be no
2143          * DMA transactions in flight for any of their siblings.
2144          * 
2145          * So PCI devices (unless they're on the root bus) as well as
2146          * their parent PCI-PCI or PCIe-PCI bridges must be left _out_ of
2147          * the 1:1 domain, just in _case_ one of their siblings turns out
2148          * not to be able to map all of memory.
2149          */
2150         if (!pdev->is_pcie) {
2151                 if (!pci_is_root_bus(pdev->bus))
2152                         return 0;
2153                 if (pdev->class >> 8 == PCI_CLASS_BRIDGE_PCI)
2154                         return 0;
2155         } else if (pdev->pcie_type == PCI_EXP_TYPE_PCI_BRIDGE)
2156                 return 0;
2157
2158         /* 
2159          * At boot time, we don't yet know if devices will be 64-bit capable.
2160          * Assume that they will -- if they turn out not to be, then we can 
2161          * take them out of the 1:1 domain later.
2162          */
2163         if (!startup)
2164                 return pdev->dma_mask > DMA_BIT_MASK(32);
2165
2166         return 1;
2167 }
2168
2169 static int iommu_prepare_static_identity_mapping(void)
2170 {
2171         struct pci_dev *pdev = NULL;
2172         int ret;
2173
2174         ret = si_domain_init();
2175         if (ret)
2176                 return -EFAULT;
2177
2178         for_each_pci_dev(pdev) {
2179                 if (iommu_should_identity_map(pdev, 1)) {
2180                         printk(KERN_INFO "IOMMU: identity mapping for device %s\n",
2181                                pci_name(pdev));
2182
2183                         ret = domain_context_mapping(si_domain, pdev,
2184                                                      CONTEXT_TT_MULTI_LEVEL);
2185                         if (ret)
2186                                 return ret;
2187                         ret = domain_add_dev_info(si_domain, pdev);
2188                         if (ret)
2189                                 return ret;
2190                 }
2191         }
2192
2193         return 0;
2194 }
2195
2196 int __init init_dmars(void)
2197 {
2198         struct dmar_drhd_unit *drhd;
2199         struct dmar_rmrr_unit *rmrr;
2200         struct pci_dev *pdev;
2201         struct intel_iommu *iommu;
2202         int i, ret;
2203         int pass_through = 1;
2204
2205         /*
2206          * In case pass through can not be enabled, iommu tries to use identity
2207          * mapping.
2208          */
2209         if (iommu_pass_through)
2210                 iommu_identity_mapping = 1;
2211
2212         /*
2213          * for each drhd
2214          *    allocate root
2215          *    initialize and program root entry to not present
2216          * endfor
2217          */
2218         for_each_drhd_unit(drhd) {
2219                 g_num_of_iommus++;
2220                 /*
2221                  * lock not needed as this is only incremented in the single
2222                  * threaded kernel __init code path all other access are read
2223                  * only
2224                  */
2225         }
2226
2227         g_iommus = kcalloc(g_num_of_iommus, sizeof(struct intel_iommu *),
2228                         GFP_KERNEL);
2229         if (!g_iommus) {
2230                 printk(KERN_ERR "Allocating global iommu array failed\n");
2231                 ret = -ENOMEM;
2232                 goto error;
2233         }
2234
2235         deferred_flush = kzalloc(g_num_of_iommus *
2236                 sizeof(struct deferred_flush_tables), GFP_KERNEL);
2237         if (!deferred_flush) {
2238                 kfree(g_iommus);
2239                 ret = -ENOMEM;
2240                 goto error;
2241         }
2242
2243         for_each_drhd_unit(drhd) {
2244                 if (drhd->ignored)
2245                         continue;
2246
2247                 iommu = drhd->iommu;
2248                 g_iommus[iommu->seq_id] = iommu;
2249
2250                 ret = iommu_init_domains(iommu);
2251                 if (ret)
2252                         goto error;
2253
2254                 /*
2255                  * TBD:
2256                  * we could share the same root & context tables
2257                  * amoung all IOMMU's. Need to Split it later.
2258                  */
2259                 ret = iommu_alloc_root_entry(iommu);
2260                 if (ret) {
2261                         printk(KERN_ERR "IOMMU: allocate root entry failed\n");
2262                         goto error;
2263                 }
2264                 if (!ecap_pass_through(iommu->ecap))
2265                         pass_through = 0;
2266         }
2267         if (iommu_pass_through)
2268                 if (!pass_through) {
2269                         printk(KERN_INFO
2270                                "Pass Through is not supported by hardware.\n");
2271                         iommu_pass_through = 0;
2272                 }
2273
2274         /*
2275          * Start from the sane iommu hardware state.
2276          */
2277         for_each_drhd_unit(drhd) {
2278                 if (drhd->ignored)
2279                         continue;
2280
2281                 iommu = drhd->iommu;
2282
2283                 /*
2284                  * If the queued invalidation is already initialized by us
2285                  * (for example, while enabling interrupt-remapping) then
2286                  * we got the things already rolling from a sane state.
2287                  */
2288                 if (iommu->qi)
2289                         continue;
2290
2291                 /*
2292                  * Clear any previous faults.
2293                  */
2294                 dmar_fault(-1, iommu);
2295                 /*
2296                  * Disable queued invalidation if supported and already enabled
2297                  * before OS handover.
2298                  */
2299                 dmar_disable_qi(iommu);
2300         }
2301
2302         for_each_drhd_unit(drhd) {
2303                 if (drhd->ignored)
2304                         continue;
2305
2306                 iommu = drhd->iommu;
2307
2308                 if (dmar_enable_qi(iommu)) {
2309                         /*
2310                          * Queued Invalidate not enabled, use Register Based
2311                          * Invalidate
2312                          */
2313                         iommu->flush.flush_context = __iommu_flush_context;
2314                         iommu->flush.flush_iotlb = __iommu_flush_iotlb;
2315                         printk(KERN_INFO "IOMMU 0x%Lx: using Register based "
2316                                "invalidation\n",
2317                                (unsigned long long)drhd->reg_base_addr);
2318                 } else {
2319                         iommu->flush.flush_context = qi_flush_context;
2320                         iommu->flush.flush_iotlb = qi_flush_iotlb;
2321                         printk(KERN_INFO "IOMMU 0x%Lx: using Queued "
2322                                "invalidation\n",
2323                                (unsigned long long)drhd->reg_base_addr);
2324                 }
2325         }
2326
2327         /*
2328          * If pass through is set and enabled, context entries of all pci
2329          * devices are intialized by pass through translation type.
2330          */
2331         if (iommu_pass_through) {
2332                 ret = init_context_pass_through();
2333                 if (ret) {
2334                         printk(KERN_ERR "IOMMU: Pass through init failed.\n");
2335                         iommu_pass_through = 0;
2336                 }
2337         }
2338
2339         /*
2340          * If pass through is not set or not enabled, setup context entries for
2341          * identity mappings for rmrr, gfx, and isa and may fall back to static
2342          * identity mapping if iommu_identity_mapping is set.
2343          */
2344         if (!iommu_pass_through) {
2345 #ifdef CONFIG_DMAR_BROKEN_GFX_WA
2346                 if (!iommu_identity_mapping)
2347                         iommu_identity_mapping = 2;
2348 #endif
2349                 if (iommu_identity_mapping)
2350                         iommu_prepare_static_identity_mapping();
2351                 /*
2352                  * For each rmrr
2353                  *   for each dev attached to rmrr
2354                  *   do
2355                  *     locate drhd for dev, alloc domain for dev
2356                  *     allocate free domain
2357                  *     allocate page table entries for rmrr
2358                  *     if context not allocated for bus
2359                  *           allocate and init context
2360                  *           set present in root table for this bus
2361                  *     init context with domain, translation etc
2362                  *    endfor
2363                  * endfor
2364                  */
2365                 printk(KERN_INFO "IOMMU: Setting RMRR:\n");
2366                 for_each_rmrr_units(rmrr) {
2367                         for (i = 0; i < rmrr->devices_cnt; i++) {
2368                                 pdev = rmrr->devices[i];
2369                                 /*
2370                                  * some BIOS lists non-exist devices in DMAR
2371                                  * table.
2372                                  */
2373                                 if (!pdev)
2374                                         continue;
2375                                 ret = iommu_prepare_rmrr_dev(rmrr, pdev);
2376                                 if (ret)
2377                                         printk(KERN_ERR
2378                                  "IOMMU: mapping reserved region failed\n");
2379                         }
2380                 }
2381
2382                 iommu_prepare_isa();
2383         }
2384
2385         /*
2386          * for each drhd
2387          *   enable fault log
2388          *   global invalidate context cache
2389          *   global invalidate iotlb
2390          *   enable translation
2391          */
2392         for_each_drhd_unit(drhd) {
2393                 if (drhd->ignored)
2394                         continue;
2395                 iommu = drhd->iommu;
2396
2397                 iommu_flush_write_buffer(iommu);
2398
2399                 ret = dmar_set_interrupt(iommu);
2400                 if (ret)
2401                         goto error;
2402
2403                 iommu_set_root_entry(iommu);
2404
2405                 iommu->flush.flush_context(iommu, 0, 0, 0, DMA_CCMD_GLOBAL_INVL);
2406                 iommu->flush.flush_iotlb(iommu, 0, 0, 0, DMA_TLB_GLOBAL_FLUSH);
2407                 iommu_disable_protect_mem_regions(iommu);
2408
2409                 ret = iommu_enable_translation(iommu);
2410                 if (ret)
2411                         goto error;
2412         }
2413
2414         return 0;
2415 error:
2416         for_each_drhd_unit(drhd) {
2417                 if (drhd->ignored)
2418                         continue;
2419                 iommu = drhd->iommu;
2420                 free_iommu(iommu);
2421         }
2422         kfree(g_iommus);
2423         return ret;
2424 }
2425
2426 /* This takes a number of _MM_ pages, not VTD pages */
2427 static struct iova *intel_alloc_iova(struct device *dev,
2428                                      struct dmar_domain *domain,
2429                                      unsigned long nrpages, uint64_t dma_mask)
2430 {
2431         struct pci_dev *pdev = to_pci_dev(dev);
2432         struct iova *iova = NULL;
2433
2434         /* Restrict dma_mask to the width that the iommu can handle */
2435         dma_mask = min_t(uint64_t, DOMAIN_MAX_ADDR(domain->gaw), dma_mask);
2436
2437         if (!dmar_forcedac && dma_mask > DMA_BIT_MASK(32)) {
2438                 /*
2439                  * First try to allocate an io virtual address in
2440                  * DMA_BIT_MASK(32) and if that fails then try allocating
2441                  * from higher range
2442                  */
2443                 iova = alloc_iova(&domain->iovad, nrpages,
2444                                   IOVA_PFN(DMA_BIT_MASK(32)), 1);
2445                 if (iova)
2446                         return iova;
2447         }
2448         iova = alloc_iova(&domain->iovad, nrpages, IOVA_PFN(dma_mask), 1);
2449         if (unlikely(!iova)) {
2450                 printk(KERN_ERR "Allocating %ld-page iova for %s failed",
2451                        nrpages, pci_name(pdev));
2452                 return NULL;
2453         }
2454
2455         return iova;
2456 }
2457
2458 static struct dmar_domain *
2459 get_valid_domain_for_dev(struct pci_dev *pdev)
2460 {
2461         struct dmar_domain *domain;
2462         int ret;
2463
2464         domain = get_domain_for_dev(pdev,
2465                         DEFAULT_DOMAIN_ADDRESS_WIDTH);
2466         if (!domain) {
2467                 printk(KERN_ERR
2468                         "Allocating domain for %s failed", pci_name(pdev));
2469                 return NULL;
2470         }
2471
2472         /* make sure context mapping is ok */
2473         if (unlikely(!domain_context_mapped(pdev))) {
2474                 ret = domain_context_mapping(domain, pdev,
2475                                              CONTEXT_TT_MULTI_LEVEL);
2476                 if (ret) {
2477                         printk(KERN_ERR
2478                                 "Domain context map for %s failed",
2479                                 pci_name(pdev));
2480                         return NULL;
2481                 }
2482         }
2483
2484         return domain;
2485 }
2486
2487 static int iommu_dummy(struct pci_dev *pdev)
2488 {
2489         return pdev->dev.archdata.iommu == DUMMY_DEVICE_DOMAIN_INFO;
2490 }
2491
2492 /* Check if the pdev needs to go through non-identity map and unmap process.*/
2493 static int iommu_no_mapping(struct device *dev)
2494 {
2495         struct pci_dev *pdev;
2496         int found;
2497
2498         if (unlikely(dev->bus != &pci_bus_type))
2499                 return 1;
2500
2501         pdev = to_pci_dev(dev);
2502         if (iommu_dummy(pdev))
2503                 return 1;
2504
2505         if (!iommu_identity_mapping)
2506                 return 0;
2507
2508         found = identity_mapping(pdev);
2509         if (found) {
2510                 if (iommu_should_identity_map(pdev, 0))
2511                         return 1;
2512                 else {
2513                         /*
2514                          * 32 bit DMA is removed from si_domain and fall back
2515                          * to non-identity mapping.
2516                          */
2517                         domain_remove_one_dev_info(si_domain, pdev);
2518                         printk(KERN_INFO "32bit %s uses non-identity mapping\n",
2519                                pci_name(pdev));
2520                         return 0;
2521                 }
2522         } else {
2523                 /*
2524                  * In case of a detached 64 bit DMA device from vm, the device
2525                  * is put into si_domain for identity mapping.
2526                  */
2527                 if (iommu_should_identity_map(pdev, 0)) {
2528                         int ret;
2529                         ret = domain_add_dev_info(si_domain, pdev);
2530                         if (ret)
2531                                 return 0;
2532                         ret = domain_context_mapping(si_domain, pdev, CONTEXT_TT_MULTI_LEVEL);
2533                         if (!ret) {
2534                                 printk(KERN_INFO "64bit %s uses identity mapping\n",
2535                                        pci_name(pdev));
2536                                 return 1;
2537                         }
2538                 }
2539         }
2540
2541         return 0;
2542 }
2543
2544 static dma_addr_t __intel_map_single(struct device *hwdev, phys_addr_t paddr,
2545                                      size_t size, int dir, u64 dma_mask)
2546 {
2547         struct pci_dev *pdev = to_pci_dev(hwdev);
2548         struct dmar_domain *domain;
2549         phys_addr_t start_paddr;
2550         struct iova *iova;
2551         int prot = 0;
2552         int ret;
2553         struct intel_iommu *iommu;
2554         unsigned long paddr_pfn = paddr >> PAGE_SHIFT;
2555
2556         BUG_ON(dir == DMA_NONE);
2557
2558         if (iommu_no_mapping(hwdev))
2559                 return paddr;
2560
2561         domain = get_valid_domain_for_dev(pdev);
2562         if (!domain)
2563                 return 0;
2564
2565         iommu = domain_get_iommu(domain);
2566         size = aligned_nrpages(paddr, size);
2567
2568         iova = intel_alloc_iova(hwdev, domain, dma_to_mm_pfn(size),
2569                                 pdev->dma_mask);
2570         if (!iova)
2571                 goto error;
2572
2573         /*
2574          * Check if DMAR supports zero-length reads on write only
2575          * mappings..
2576          */
2577         if (dir == DMA_TO_DEVICE || dir == DMA_BIDIRECTIONAL || \
2578                         !cap_zlr(iommu->cap))
2579                 prot |= DMA_PTE_READ;
2580         if (dir == DMA_FROM_DEVICE || dir == DMA_BIDIRECTIONAL)
2581                 prot |= DMA_PTE_WRITE;
2582         /*
2583          * paddr - (paddr + size) might be partial page, we should map the whole
2584          * page.  Note: if two part of one page are separately mapped, we
2585          * might have two guest_addr mapping to the same host paddr, but this
2586          * is not a big problem
2587          */
2588         ret = domain_pfn_mapping(domain, mm_to_dma_pfn(iova->pfn_lo),
2589                                  mm_to_dma_pfn(paddr_pfn), size, prot);
2590         if (ret)
2591                 goto error;
2592
2593         /* it's a non-present to present mapping. Only flush if caching mode */
2594         if (cap_caching_mode(iommu->cap))
2595                 iommu_flush_iotlb_psi(iommu, 0, mm_to_dma_pfn(iova->pfn_lo), size);
2596         else
2597                 iommu_flush_write_buffer(iommu);
2598
2599         start_paddr = (phys_addr_t)iova->pfn_lo << PAGE_SHIFT;
2600         start_paddr += paddr & ~PAGE_MASK;
2601         return start_paddr;
2602
2603 error:
2604         if (iova)
2605                 __free_iova(&domain->iovad, iova);
2606         printk(KERN_ERR"Device %s request: %zx@%llx dir %d --- failed\n",
2607                 pci_name(pdev), size, (unsigned long long)paddr, dir);
2608         return 0;
2609 }
2610
2611 static dma_addr_t intel_map_page(struct device *dev, struct page *page,
2612                                  unsigned long offset, size_t size,
2613                                  enum dma_data_direction dir,
2614                                  struct dma_attrs *attrs)
2615 {
2616         return __intel_map_single(dev, page_to_phys(page) + offset, size,
2617                                   dir, to_pci_dev(dev)->dma_mask);
2618 }
2619
2620 static void flush_unmaps(void)
2621 {
2622         int i, j;
2623
2624         timer_on = 0;
2625
2626         /* just flush them all */
2627         for (i = 0; i < g_num_of_iommus; i++) {
2628                 struct intel_iommu *iommu = g_iommus[i];
2629                 if (!iommu)
2630                         continue;
2631
2632                 if (!deferred_flush[i].next)
2633                         continue;
2634
2635                 iommu->flush.flush_iotlb(iommu, 0, 0, 0,
2636                                          DMA_TLB_GLOBAL_FLUSH);
2637                 for (j = 0; j < deferred_flush[i].next; j++) {
2638                         unsigned long mask;
2639                         struct iova *iova = deferred_flush[i].iova[j];
2640
2641                         mask = (iova->pfn_hi - iova->pfn_lo + 1) << PAGE_SHIFT;
2642                         mask = ilog2(mask >> VTD_PAGE_SHIFT);
2643                         iommu_flush_dev_iotlb(deferred_flush[i].domain[j],
2644                                         iova->pfn_lo << PAGE_SHIFT, mask);
2645                         __free_iova(&deferred_flush[i].domain[j]->iovad, iova);
2646                 }
2647                 deferred_flush[i].next = 0;
2648         }
2649
2650         list_size = 0;
2651 }
2652
2653 static void flush_unmaps_timeout(unsigned long data)
2654 {
2655         unsigned long flags;
2656
2657         spin_lock_irqsave(&async_umap_flush_lock, flags);
2658         flush_unmaps();
2659         spin_unlock_irqrestore(&async_umap_flush_lock, flags);
2660 }
2661
2662 static void add_unmap(struct dmar_domain *dom, struct iova *iova)
2663 {
2664         unsigned long flags;
2665         int next, iommu_id;
2666         struct intel_iommu *iommu;
2667
2668         spin_lock_irqsave(&async_umap_flush_lock, flags);
2669         if (list_size == HIGH_WATER_MARK)
2670                 flush_unmaps();
2671
2672         iommu = domain_get_iommu(dom);
2673         iommu_id = iommu->seq_id;
2674
2675         next = deferred_flush[iommu_id].next;
2676         deferred_flush[iommu_id].domain[next] = dom;
2677         deferred_flush[iommu_id].iova[next] = iova;
2678         deferred_flush[iommu_id].next++;
2679
2680         if (!timer_on) {
2681                 mod_timer(&unmap_timer, jiffies + msecs_to_jiffies(10));
2682                 timer_on = 1;
2683         }
2684         list_size++;
2685         spin_unlock_irqrestore(&async_umap_flush_lock, flags);
2686 }
2687
2688 static void intel_unmap_page(struct device *dev, dma_addr_t dev_addr,
2689                              size_t size, enum dma_data_direction dir,
2690                              struct dma_attrs *attrs)
2691 {
2692         struct pci_dev *pdev = to_pci_dev(dev);
2693         struct dmar_domain *domain;
2694         unsigned long start_pfn, last_pfn;
2695         struct iova *iova;
2696         struct intel_iommu *iommu;
2697
2698         if (iommu_no_mapping(dev))
2699                 return;
2700
2701         domain = find_domain(pdev);
2702         BUG_ON(!domain);
2703
2704         iommu = domain_get_iommu(domain);
2705
2706         iova = find_iova(&domain->iovad, IOVA_PFN(dev_addr));
2707         if (WARN_ONCE(!iova, "Driver unmaps unmatched page at PFN %llx\n",
2708                       (unsigned long long)dev_addr))
2709                 return;
2710
2711         start_pfn = mm_to_dma_pfn(iova->pfn_lo);
2712         last_pfn = mm_to_dma_pfn(iova->pfn_hi + 1) - 1;
2713
2714         pr_debug("Device %s unmapping: pfn %lx-%lx\n",
2715                  pci_name(pdev), start_pfn, last_pfn);
2716
2717         /*  clear the whole page */
2718         dma_pte_clear_range(domain, start_pfn, last_pfn);
2719
2720         /* free page tables */
2721         dma_pte_free_pagetable(domain, start_pfn, last_pfn);
2722
2723         if (intel_iommu_strict) {
2724                 iommu_flush_iotlb_psi(iommu, domain->id, start_pfn,
2725                                       last_pfn - start_pfn + 1);
2726                 /* free iova */
2727                 __free_iova(&domain->iovad, iova);
2728         } else {
2729                 add_unmap(domain, iova);
2730                 /*
2731                  * queue up the release of the unmap to save the 1/6th of the
2732                  * cpu used up by the iotlb flush operation...
2733                  */
2734         }
2735 }
2736
2737 static void intel_unmap_single(struct device *dev, dma_addr_t dev_addr, size_t size,
2738                                int dir)
2739 {
2740         intel_unmap_page(dev, dev_addr, size, dir, NULL);
2741 }
2742
2743 static void *intel_alloc_coherent(struct device *hwdev, size_t size,
2744                                   dma_addr_t *dma_handle, gfp_t flags)
2745 {
2746         void *vaddr;
2747         int order;
2748
2749         size = PAGE_ALIGN(size);
2750         order = get_order(size);
2751         flags &= ~(GFP_DMA | GFP_DMA32);
2752
2753         vaddr = (void *)__get_free_pages(flags, order);
2754         if (!vaddr)
2755                 return NULL;
2756         memset(vaddr, 0, size);
2757
2758         *dma_handle = __intel_map_single(hwdev, virt_to_bus(vaddr), size,
2759                                          DMA_BIDIRECTIONAL,
2760                                          hwdev->coherent_dma_mask);
2761         if (*dma_handle)
2762                 return vaddr;
2763         free_pages((unsigned long)vaddr, order);
2764         return NULL;
2765 }
2766
2767 static void intel_free_coherent(struct device *hwdev, size_t size, void *vaddr,
2768                                 dma_addr_t dma_handle)
2769 {
2770         int order;
2771
2772         size = PAGE_ALIGN(size);
2773         order = get_order(size);
2774
2775         intel_unmap_single(hwdev, dma_handle, size, DMA_BIDIRECTIONAL);
2776         free_pages((unsigned long)vaddr, order);
2777 }
2778
2779 static void intel_unmap_sg(struct device *hwdev, struct scatterlist *sglist,
2780                            int nelems, enum dma_data_direction dir,
2781                            struct dma_attrs *attrs)
2782 {
2783         struct pci_dev *pdev = to_pci_dev(hwdev);
2784         struct dmar_domain *domain;
2785         unsigned long start_pfn, last_pfn;
2786         struct iova *iova;
2787         struct intel_iommu *iommu;
2788
2789         if (iommu_no_mapping(hwdev))
2790                 return;
2791
2792         domain = find_domain(pdev);
2793         BUG_ON(!domain);
2794
2795         iommu = domain_get_iommu(domain);
2796
2797         iova = find_iova(&domain->iovad, IOVA_PFN(sglist[0].dma_address));
2798         if (WARN_ONCE(!iova, "Driver unmaps unmatched sglist at PFN %llx\n",
2799                       (unsigned long long)sglist[0].dma_address))
2800                 return;
2801
2802         start_pfn = mm_to_dma_pfn(iova->pfn_lo);
2803         last_pfn = mm_to_dma_pfn(iova->pfn_hi + 1) - 1;
2804
2805         /*  clear the whole page */
2806         dma_pte_clear_range(domain, start_pfn, last_pfn);
2807
2808         /* free page tables */
2809         dma_pte_free_pagetable(domain, start_pfn, last_pfn);
2810
2811         iommu_flush_iotlb_psi(iommu, domain->id, start_pfn,
2812                               (last_pfn - start_pfn + 1));
2813
2814         /* free iova */
2815         __free_iova(&domain->iovad, iova);
2816 }
2817
2818 static int intel_nontranslate_map_sg(struct device *hddev,
2819         struct scatterlist *sglist, int nelems, int dir)
2820 {
2821         int i;
2822         struct scatterlist *sg;
2823
2824         for_each_sg(sglist, sg, nelems, i) {
2825                 BUG_ON(!sg_page(sg));
2826                 sg->dma_address = page_to_phys(sg_page(sg)) + sg->offset;
2827                 sg->dma_length = sg->length;
2828         }
2829         return nelems;
2830 }
2831
2832 static int intel_map_sg(struct device *hwdev, struct scatterlist *sglist, int nelems,
2833                         enum dma_data_direction dir, struct dma_attrs *attrs)
2834 {
2835         int i;
2836         struct pci_dev *pdev = to_pci_dev(hwdev);
2837         struct dmar_domain *domain;
2838         size_t size = 0;
2839         int prot = 0;
2840         size_t offset_pfn = 0;
2841         struct iova *iova = NULL;
2842         int ret;
2843         struct scatterlist *sg;
2844         unsigned long start_vpfn;
2845         struct intel_iommu *iommu;
2846
2847         BUG_ON(dir == DMA_NONE);
2848         if (iommu_no_mapping(hwdev))
2849                 return intel_nontranslate_map_sg(hwdev, sglist, nelems, dir);
2850
2851         domain = get_valid_domain_for_dev(pdev);
2852         if (!domain)
2853                 return 0;
2854
2855         iommu = domain_get_iommu(domain);
2856
2857         for_each_sg(sglist, sg, nelems, i)
2858                 size += aligned_nrpages(sg->offset, sg->length);
2859
2860         iova = intel_alloc_iova(hwdev, domain, dma_to_mm_pfn(size),
2861                                 pdev->dma_mask);
2862         if (!iova) {
2863                 sglist->dma_length = 0;
2864                 return 0;
2865         }
2866
2867         /*
2868          * Check if DMAR supports zero-length reads on write only
2869          * mappings..
2870          */
2871         if (dir == DMA_TO_DEVICE || dir == DMA_BIDIRECTIONAL || \
2872                         !cap_zlr(iommu->cap))
2873                 prot |= DMA_PTE_READ;
2874         if (dir == DMA_FROM_DEVICE || dir == DMA_BIDIRECTIONAL)
2875                 prot |= DMA_PTE_WRITE;
2876
2877         start_vpfn = mm_to_dma_pfn(iova->pfn_lo);
2878
2879         ret = domain_sg_mapping(domain, start_vpfn, sglist, size, prot);
2880         if (unlikely(ret)) {
2881                 /*  clear the page */
2882                 dma_pte_clear_range(domain, start_vpfn,
2883                                     start_vpfn + size - 1);
2884                 /* free page tables */
2885                 dma_pte_free_pagetable(domain, start_vpfn,
2886                                        start_vpfn + size - 1);
2887                 /* free iova */
2888                 __free_iova(&domain->iovad, iova);
2889                 return 0;
2890         }
2891
2892         /* it's a non-present to present mapping. Only flush if caching mode */
2893         if (cap_caching_mode(iommu->cap))
2894                 iommu_flush_iotlb_psi(iommu, 0, start_vpfn, offset_pfn);
2895         else
2896                 iommu_flush_write_buffer(iommu);
2897
2898         return nelems;
2899 }
2900
2901 static int intel_mapping_error(struct device *dev, dma_addr_t dma_addr)
2902 {
2903         return !dma_addr;
2904 }
2905
2906 struct dma_map_ops intel_dma_ops = {
2907         .alloc_coherent = intel_alloc_coherent,
2908         .free_coherent = intel_free_coherent,
2909         .map_sg = intel_map_sg,
2910         .unmap_sg = intel_unmap_sg,
2911         .map_page = intel_map_page,
2912         .unmap_page = intel_unmap_page,
2913         .mapping_error = intel_mapping_error,
2914 };
2915
2916 static inline int iommu_domain_cache_init(void)
2917 {
2918         int ret = 0;
2919
2920         iommu_domain_cache = kmem_cache_create("iommu_domain",
2921                                          sizeof(struct dmar_domain),
2922                                          0,
2923                                          SLAB_HWCACHE_ALIGN,
2924
2925                                          NULL);
2926         if (!iommu_domain_cache) {
2927                 printk(KERN_ERR "Couldn't create iommu_domain cache\n");
2928                 ret = -ENOMEM;
2929         }
2930
2931         return ret;
2932 }
2933
2934 static inline int iommu_devinfo_cache_init(void)
2935 {
2936         int ret = 0;
2937
2938         iommu_devinfo_cache = kmem_cache_create("iommu_devinfo",
2939                                          sizeof(struct device_domain_info),
2940                                          0,
2941                                          SLAB_HWCACHE_ALIGN,
2942                                          NULL);
2943         if (!iommu_devinfo_cache) {
2944                 printk(KERN_ERR "Couldn't create devinfo cache\n");
2945                 ret = -ENOMEM;
2946         }
2947
2948         return ret;
2949 }
2950
2951 static inline int iommu_iova_cache_init(void)
2952 {
2953         int ret = 0;
2954
2955         iommu_iova_cache = kmem_cache_create("iommu_iova",
2956                                          sizeof(struct iova),
2957                                          0,
2958                                          SLAB_HWCACHE_ALIGN,
2959                                          NULL);
2960         if (!iommu_iova_cache) {
2961                 printk(KERN_ERR "Couldn't create iova cache\n");
2962                 ret = -ENOMEM;
2963         }
2964
2965         return ret;
2966 }
2967
2968 static int __init iommu_init_mempool(void)
2969 {
2970         int ret;
2971         ret = iommu_iova_cache_init();
2972         if (ret)
2973                 return ret;
2974
2975         ret = iommu_domain_cache_init();
2976         if (ret)
2977                 goto domain_error;
2978
2979         ret = iommu_devinfo_cache_init();
2980         if (!ret)
2981                 return ret;
2982
2983         kmem_cache_destroy(iommu_domain_cache);
2984 domain_error:
2985         kmem_cache_destroy(iommu_iova_cache);
2986
2987         return -ENOMEM;
2988 }
2989
2990 static void __init iommu_exit_mempool(void)
2991 {
2992         kmem_cache_destroy(iommu_devinfo_cache);
2993         kmem_cache_destroy(iommu_domain_cache);
2994         kmem_cache_destroy(iommu_iova_cache);
2995
2996 }
2997
2998 static void __init init_no_remapping_devices(void)
2999 {
3000         struct dmar_drhd_unit *drhd;
3001
3002         for_each_drhd_unit(drhd) {
3003                 if (!drhd->include_all) {
3004                         int i;
3005                         for (i = 0; i < drhd->devices_cnt; i++)
3006                                 if (drhd->devices[i] != NULL)
3007                                         break;
3008                         /* ignore DMAR unit if no pci devices exist */
3009                         if (i == drhd->devices_cnt)
3010                                 drhd->ignored = 1;
3011                 }
3012         }
3013
3014         if (dmar_map_gfx)
3015                 return;
3016
3017         for_each_drhd_unit(drhd) {
3018                 int i;
3019                 if (drhd->ignored || drhd->include_all)
3020                         continue;
3021
3022                 for (i = 0; i < drhd->devices_cnt; i++)
3023                         if (drhd->devices[i] &&
3024                                 !IS_GFX_DEVICE(drhd->devices[i]))
3025                                 break;
3026
3027                 if (i < drhd->devices_cnt)
3028                         continue;
3029
3030                 /* bypass IOMMU if it is just for gfx devices */
3031                 drhd->ignored = 1;
3032                 for (i = 0; i < drhd->devices_cnt; i++) {
3033                         if (!drhd->devices[i])
3034                                 continue;
3035                         drhd->devices[i]->dev.archdata.iommu = DUMMY_DEVICE_DOMAIN_INFO;
3036                 }
3037         }
3038 }
3039
3040 #ifdef CONFIG_SUSPEND
3041 static int init_iommu_hw(void)
3042 {
3043         struct dmar_drhd_unit *drhd;
3044         struct intel_iommu *iommu = NULL;
3045
3046         for_each_active_iommu(iommu, drhd)
3047                 if (iommu->qi)
3048                         dmar_reenable_qi(iommu);
3049
3050         for_each_active_iommu(iommu, drhd) {
3051                 iommu_flush_write_buffer(iommu);
3052
3053                 iommu_set_root_entry(iommu);
3054
3055                 iommu->flush.flush_context(iommu, 0, 0, 0,
3056                                            DMA_CCMD_GLOBAL_INVL);
3057                 iommu->flush.flush_iotlb(iommu, 0, 0, 0,
3058                                          DMA_TLB_GLOBAL_FLUSH);
3059                 iommu_disable_protect_mem_regions(iommu);
3060                 iommu_enable_translation(iommu);
3061         }
3062
3063         return 0;
3064 }
3065
3066 static void iommu_flush_all(void)
3067 {
3068         struct dmar_drhd_unit *drhd;
3069         struct intel_iommu *iommu;
3070
3071         for_each_active_iommu(iommu, drhd) {
3072                 iommu->flush.flush_context(iommu, 0, 0, 0,
3073                                            DMA_CCMD_GLOBAL_INVL);
3074                 iommu->flush.flush_iotlb(iommu, 0, 0, 0,
3075                                          DMA_TLB_GLOBAL_FLUSH);
3076         }
3077 }
3078
3079 static int iommu_suspend(struct sys_device *dev, pm_message_t state)
3080 {
3081         struct dmar_drhd_unit *drhd;
3082         struct intel_iommu *iommu = NULL;
3083         unsigned long flag;
3084
3085         for_each_active_iommu(iommu, drhd) {
3086                 iommu->iommu_state = kzalloc(sizeof(u32) * MAX_SR_DMAR_REGS,
3087                                                  GFP_ATOMIC);
3088                 if (!iommu->iommu_state)
3089                         goto nomem;
3090         }
3091
3092         iommu_flush_all();
3093
3094         for_each_active_iommu(iommu, drhd) {
3095                 iommu_disable_translation(iommu);
3096
3097                 spin_lock_irqsave(&iommu->register_lock, flag);
3098
3099                 iommu->iommu_state[SR_DMAR_FECTL_REG] =
3100                         readl(iommu->reg + DMAR_FECTL_REG);
3101                 iommu->iommu_state[SR_DMAR_FEDATA_REG] =
3102                         readl(iommu->reg + DMAR_FEDATA_REG);
3103                 iommu->iommu_state[SR_DMAR_FEADDR_REG] =
3104                         readl(iommu->reg + DMAR_FEADDR_REG);
3105                 iommu->iommu_state[SR_DMAR_FEUADDR_REG] =
3106                         readl(iommu->reg + DMAR_FEUADDR_REG);
3107
3108                 spin_unlock_irqrestore(&iommu->register_lock, flag);
3109         }
3110         return 0;
3111
3112 nomem:
3113         for_each_active_iommu(iommu, drhd)
3114                 kfree(iommu->iommu_state);
3115
3116         return -ENOMEM;
3117 }
3118
3119 static int iommu_resume(struct sys_device *dev)
3120 {
3121         struct dmar_drhd_unit *drhd;
3122         struct intel_iommu *iommu = NULL;
3123         unsigned long flag;
3124
3125         if (init_iommu_hw()) {
3126                 WARN(1, "IOMMU setup failed, DMAR can not resume!\n");
3127                 return -EIO;
3128         }
3129
3130         for_each_active_iommu(iommu, drhd) {
3131
3132                 spin_lock_irqsave(&iommu->register_lock, flag);
3133
3134                 writel(iommu->iommu_state[SR_DMAR_FECTL_REG],
3135                         iommu->reg + DMAR_FECTL_REG);
3136                 writel(iommu->iommu_state[SR_DMAR_FEDATA_REG],
3137                         iommu->reg + DMAR_FEDATA_REG);
3138                 writel(iommu->iommu_state[SR_DMAR_FEADDR_REG],
3139                         iommu->reg + DMAR_FEADDR_REG);
3140                 writel(iommu->iommu_state[SR_DMAR_FEUADDR_REG],
3141                         iommu->reg + DMAR_FEUADDR_REG);
3142
3143                 spin_unlock_irqrestore(&iommu->register_lock, flag);
3144         }
3145
3146         for_each_active_iommu(iommu, drhd)
3147                 kfree(iommu->iommu_state);
3148
3149         return 0;
3150 }
3151
3152 static struct sysdev_class iommu_sysclass = {
3153         .name           = "iommu",
3154         .resume         = iommu_resume,
3155         .suspend        = iommu_suspend,
3156 };
3157
3158 static struct sys_device device_iommu = {
3159         .cls    = &iommu_sysclass,
3160 };
3161
3162 static int __init init_iommu_sysfs(void)
3163 {
3164         int error;
3165
3166         error = sysdev_class_register(&iommu_sysclass);
3167         if (error)
3168                 return error;
3169
3170         error = sysdev_register(&device_iommu);
3171         if (error)
3172                 sysdev_class_unregister(&iommu_sysclass);
3173
3174         return error;
3175 }
3176
3177 #else
3178 static int __init init_iommu_sysfs(void)
3179 {
3180         return 0;
3181 }
3182 #endif  /* CONFIG_PM */
3183
3184 int __init intel_iommu_init(void)
3185 {
3186         int ret = 0;
3187         int force_on = 0;
3188
3189         /* VT-d is required for a TXT/tboot launch, so enforce that */
3190         force_on = tboot_force_iommu();
3191
3192         if (dmar_table_init()) {
3193                 if (force_on)
3194                         panic("tboot: Failed to initialize DMAR table\n");
3195                 return  -ENODEV;
3196         }
3197
3198         if (dmar_dev_scope_init()) {
3199                 if (force_on)
3200                         panic("tboot: Failed to initialize DMAR device scope\n");
3201                 return  -ENODEV;
3202         }
3203
3204         /*
3205          * Check the need for DMA-remapping initialization now.
3206          * Above initialization will also be used by Interrupt-remapping.
3207          */
3208         if (no_iommu || (swiotlb && !iommu_pass_through) || dmar_disabled)
3209                 return -ENODEV;
3210
3211         iommu_init_mempool();
3212         dmar_init_reserved_ranges();
3213
3214         init_no_remapping_devices();
3215
3216         ret = init_dmars();
3217         if (ret) {
3218                 if (force_on)
3219                         panic("tboot: Failed to initialize DMARs\n");
3220                 printk(KERN_ERR "IOMMU: dmar init failed\n");
3221                 put_iova_domain(&reserved_iova_list);
3222                 iommu_exit_mempool();
3223                 return ret;
3224         }
3225         printk(KERN_INFO
3226         "PCI-DMA: Intel(R) Virtualization Technology for Directed I/O\n");
3227
3228         init_timer(&unmap_timer);
3229         force_iommu = 1;
3230
3231         if (!iommu_pass_through) {
3232                 printk(KERN_INFO
3233                        "Multi-level page-table translation for DMAR.\n");
3234                 dma_ops = &intel_dma_ops;
3235         } else
3236                 printk(KERN_INFO
3237                        "DMAR: Pass through translation for DMAR.\n");
3238
3239         init_iommu_sysfs();
3240
3241         register_iommu(&intel_iommu_ops);
3242
3243         return 0;
3244 }
3245
3246 static void iommu_detach_dependent_devices(struct intel_iommu *iommu,
3247                                            struct pci_dev *pdev)
3248 {
3249         struct pci_dev *tmp, *parent;
3250
3251         if (!iommu || !pdev)
3252                 return;
3253
3254         /* dependent device detach */
3255         tmp = pci_find_upstream_pcie_bridge(pdev);
3256         /* Secondary interface's bus number and devfn 0 */
3257         if (tmp) {
3258                 parent = pdev->bus->self;
3259                 while (parent != tmp) {
3260                         iommu_detach_dev(iommu, parent->bus->number,
3261                                          parent->devfn);
3262                         parent = parent->bus->self;
3263                 }
3264                 if (tmp->is_pcie) /* this is a PCIE-to-PCI bridge */
3265                         iommu_detach_dev(iommu,
3266                                 tmp->subordinate->number, 0);
3267                 else /* this is a legacy PCI bridge */
3268                         iommu_detach_dev(iommu, tmp->bus->number,
3269                                          tmp->devfn);
3270         }
3271 }
3272
3273 static void domain_remove_one_dev_info(struct dmar_domain *domain,
3274                                           struct pci_dev *pdev)
3275 {
3276         struct device_domain_info *info;
3277         struct intel_iommu *iommu;
3278         unsigned long flags;
3279         int found = 0;
3280         struct list_head *entry, *tmp;
3281
3282         iommu = device_to_iommu(pci_domain_nr(pdev->bus), pdev->bus->number,
3283                                 pdev->devfn);
3284         if (!iommu)
3285                 return;
3286
3287         spin_lock_irqsave(&device_domain_lock, flags);
3288         list_for_each_safe(entry, tmp, &domain->devices) {
3289                 info = list_entry(entry, struct device_domain_info, link);
3290                 /* No need to compare PCI domain; it has to be the same */
3291                 if (info->bus == pdev->bus->number &&
3292                     info->devfn == pdev->devfn) {
3293                         list_del(&info->link);
3294                         list_del(&info->global);
3295                         if (info->dev)
3296                                 info->dev->dev.archdata.iommu = NULL;
3297                         spin_unlock_irqrestore(&device_domain_lock, flags);
3298
3299                         iommu_disable_dev_iotlb(info);
3300                         iommu_detach_dev(iommu, info->bus, info->devfn);
3301                         iommu_detach_dependent_devices(iommu, pdev);
3302                         free_devinfo_mem(info);
3303
3304                         spin_lock_irqsave(&device_domain_lock, flags);
3305
3306                         if (found)
3307                                 break;
3308                         else
3309                                 continue;
3310                 }
3311
3312                 /* if there is no other devices under the same iommu
3313                  * owned by this domain, clear this iommu in iommu_bmp
3314                  * update iommu count and coherency
3315                  */
3316                 if (iommu == device_to_iommu(info->segment, info->bus,
3317                                             info->devfn))
3318                         found = 1;
3319         }
3320
3321         if (found == 0) {
3322                 unsigned long tmp_flags;
3323                 spin_lock_irqsave(&domain->iommu_lock, tmp_flags);
3324                 clear_bit(iommu->seq_id, &domain->iommu_bmp);
3325                 domain->iommu_count--;
3326                 domain_update_iommu_cap(domain);
3327                 spin_unlock_irqrestore(&domain->iommu_lock, tmp_flags);
3328         }
3329
3330         spin_unlock_irqrestore(&device_domain_lock, flags);
3331 }
3332
3333 static void vm_domain_remove_all_dev_info(struct dmar_domain *domain)
3334 {
3335         struct device_domain_info *info;
3336         struct intel_iommu *iommu;
3337         unsigned long flags1, flags2;