wl1271: RefClk configuration
[linux-2.6.git] / drivers / net / wireless / wl12xx / wl1271_boot.c
1 /*
2  * This file is part of wl1271
3  *
4  * Copyright (C) 2008-2009 Nokia Corporation
5  *
6  * Contact: Luciano Coelho <luciano.coelho@nokia.com>
7  *
8  * This program is free software; you can redistribute it and/or
9  * modify it under the terms of the GNU General Public License
10  * version 2 as published by the Free Software Foundation.
11  *
12  * This program is distributed in the hope that it will be useful, but
13  * WITHOUT ANY WARRANTY; without even the implied warranty of
14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
15  * General Public License for more details.
16  *
17  * You should have received a copy of the GNU General Public License
18  * along with this program; if not, write to the Free Software
19  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
20  * 02110-1301 USA
21  *
22  */
23
24 #include <linux/gpio.h>
25
26 #include "wl1271_acx.h"
27 #include "wl1271_reg.h"
28 #include "wl1271_boot.h"
29 #include "wl1271_spi.h"
30 #include "wl1271_event.h"
31
32 static struct wl1271_partition_set part_table[PART_TABLE_LEN] = {
33         [PART_DOWN] = {
34                 .mem = {
35                         .start = 0x00000000,
36                         .size  = 0x000177c0
37                 },
38                 .reg = {
39                         .start = REGISTERS_BASE,
40                         .size  = 0x00008800
41                 },
42                 .mem2 = {
43                         .start = 0x00000000,
44                         .size  = 0x00000000
45                 },
46                 .mem3 = {
47                         .start = 0x00000000,
48                         .size  = 0x00000000
49                 },
50         },
51
52         [PART_WORK] = {
53                 .mem = {
54                         .start = 0x00040000,
55                         .size  = 0x00014fc0
56                 },
57                 .reg = {
58                         .start = REGISTERS_BASE,
59                         .size  = 0x0000a000
60                 },
61                 .mem2 = {
62                         .start = 0x003004f8,
63                         .size  = 0x00000004
64                 },
65                 .mem3 = {
66                         .start = 0x00040404,
67                         .size  = 0x00000000
68                 },
69         },
70
71         [PART_DRPW] = {
72                 .mem = {
73                         .start = 0x00040000,
74                         .size  = 0x00014fc0
75                 },
76                 .reg = {
77                         .start = DRPW_BASE,
78                         .size  = 0x00006000
79                 },
80                 .mem2 = {
81                         .start = 0x00000000,
82                         .size  = 0x00000000
83                 },
84                 .mem3 = {
85                         .start = 0x00000000,
86                         .size  = 0x00000000
87                 }
88         }
89 };
90
91 static void wl1271_boot_set_ecpu_ctrl(struct wl1271 *wl, u32 flag)
92 {
93         u32 cpu_ctrl;
94
95         /* 10.5.0 run the firmware (I) */
96         cpu_ctrl = wl1271_reg_read32(wl, ACX_REG_ECPU_CONTROL);
97
98         /* 10.5.1 run the firmware (II) */
99         cpu_ctrl |= flag;
100         wl1271_reg_write32(wl, ACX_REG_ECPU_CONTROL, cpu_ctrl);
101 }
102
103 static void wl1271_boot_fw_version(struct wl1271 *wl)
104 {
105         struct wl1271_static_data static_data;
106
107         wl1271_spi_mem_read(wl, wl->cmd_box_addr,
108                             &static_data, sizeof(static_data));
109
110         strncpy(wl->chip.fw_ver, static_data.fw_version,
111                 sizeof(wl->chip.fw_ver));
112
113         /* make sure the string is NULL-terminated */
114         wl->chip.fw_ver[sizeof(wl->chip.fw_ver) - 1] = '\0';
115 }
116
117 static int wl1271_boot_upload_firmware_chunk(struct wl1271 *wl, void *buf,
118                                              size_t fw_data_len, u32 dest)
119 {
120         struct wl1271_partition_set partition;
121         int addr, chunk_num, partition_limit;
122         u8 *p, *chunk;
123
124         /* whal_FwCtrl_LoadFwImageSm() */
125
126         wl1271_debug(DEBUG_BOOT, "starting firmware upload");
127
128         wl1271_debug(DEBUG_BOOT, "fw_data_len %zd chunk_size %d",
129                      fw_data_len, CHUNK_SIZE);
130
131         if ((fw_data_len % 4) != 0) {
132                 wl1271_error("firmware length not multiple of four");
133                 return -EIO;
134         }
135
136         chunk = kmalloc(CHUNK_SIZE, GFP_KERNEL);
137         if (!buf) {
138                 wl1271_error("allocation for firmware upload chunk failed");
139                 return -ENOMEM;
140         }
141
142         memcpy(&partition, &part_table[PART_DOWN], sizeof(partition));
143         partition.mem.start = dest;
144         wl1271_set_partition(wl, &partition);
145
146         /* 10.1 set partition limit and chunk num */
147         chunk_num = 0;
148         partition_limit = part_table[PART_DOWN].mem.size;
149
150         while (chunk_num < fw_data_len / CHUNK_SIZE) {
151                 /* 10.2 update partition, if needed */
152                 addr = dest + (chunk_num + 2) * CHUNK_SIZE;
153                 if (addr > partition_limit) {
154                         addr = dest + chunk_num * CHUNK_SIZE;
155                         partition_limit = chunk_num * CHUNK_SIZE +
156                                 part_table[PART_DOWN].mem.size;
157                         partition.mem.start = addr;
158                         wl1271_set_partition(wl, &partition);
159                 }
160
161                 /* 10.3 upload the chunk */
162                 addr = dest + chunk_num * CHUNK_SIZE;
163                 p = buf + chunk_num * CHUNK_SIZE;
164                 memcpy(chunk, p, CHUNK_SIZE);
165                 wl1271_debug(DEBUG_BOOT, "uploading fw chunk 0x%p to 0x%x",
166                              p, addr);
167                 wl1271_spi_mem_write(wl, addr, chunk, CHUNK_SIZE);
168
169                 chunk_num++;
170         }
171
172         /* 10.4 upload the last chunk */
173         addr = dest + chunk_num * CHUNK_SIZE;
174         p = buf + chunk_num * CHUNK_SIZE;
175         memcpy(chunk, p, fw_data_len % CHUNK_SIZE);
176         wl1271_debug(DEBUG_BOOT, "uploading fw last chunk (%zd B) 0x%p to 0x%x",
177                      fw_data_len % CHUNK_SIZE, p, addr);
178         wl1271_spi_mem_write(wl, addr, chunk, fw_data_len % CHUNK_SIZE);
179
180         kfree(chunk);
181         return 0;
182 }
183
184 static int wl1271_boot_upload_firmware(struct wl1271 *wl)
185 {
186         u32 chunks, addr, len;
187         u8 *fw;
188
189         fw = wl->fw;
190         chunks = be32_to_cpup((u32 *) fw);
191         fw += sizeof(u32);
192
193         wl1271_debug(DEBUG_BOOT, "firmware chunks to be uploaded: %u", chunks);
194
195         while (chunks--) {
196                 addr = be32_to_cpup((u32 *) fw);
197                 fw += sizeof(u32);
198                 len = be32_to_cpup((u32 *) fw);
199                 fw += sizeof(u32);
200
201                 if (len > 300000) {
202                         wl1271_info("firmware chunk too long: %u", len);
203                         return -EINVAL;
204                 }
205                 wl1271_debug(DEBUG_BOOT, "chunk %d addr 0x%x len %u",
206                              chunks, addr, len);
207                 wl1271_boot_upload_firmware_chunk(wl, fw, len, addr);
208                 fw += len;
209         }
210
211         return 0;
212 }
213
214 static int wl1271_boot_upload_nvs(struct wl1271 *wl)
215 {
216         size_t nvs_len, burst_len;
217         int i;
218         u32 dest_addr, val;
219         u8 *nvs_ptr, *nvs, *nvs_aligned;
220
221         nvs = wl->nvs;
222         if (nvs == NULL)
223                 return -ENODEV;
224
225         nvs_ptr = nvs;
226
227         nvs_len = wl->nvs_len;
228
229         /* Update the device MAC address into the nvs */
230         nvs[11] = wl->mac_addr[0];
231         nvs[10] = wl->mac_addr[1];
232         nvs[6] = wl->mac_addr[2];
233         nvs[5] = wl->mac_addr[3];
234         nvs[4] = wl->mac_addr[4];
235         nvs[3] = wl->mac_addr[5];
236
237         /*
238          * Layout before the actual NVS tables:
239          * 1 byte : burst length.
240          * 2 bytes: destination address.
241          * n bytes: data to burst copy.
242          *
243          * This is ended by a 0 length, then the NVS tables.
244          */
245
246         /* FIXME: Do we need to check here whether the LSB is 1? */
247         while (nvs_ptr[0]) {
248                 burst_len = nvs_ptr[0];
249                 dest_addr = (nvs_ptr[1] & 0xfe) | ((u32)(nvs_ptr[2] << 8));
250
251                 /* FIXME: Due to our new wl1271_translate_reg_addr function,
252                    we need to add the REGISTER_BASE to the destination */
253                 dest_addr += REGISTERS_BASE;
254
255                 /* We move our pointer to the data */
256                 nvs_ptr += 3;
257
258                 for (i = 0; i < burst_len; i++) {
259                         val = (nvs_ptr[0] | (nvs_ptr[1] << 8)
260                                | (nvs_ptr[2] << 16) | (nvs_ptr[3] << 24));
261
262                         wl1271_debug(DEBUG_BOOT,
263                                      "nvs burst write 0x%x: 0x%x",
264                                      dest_addr, val);
265                         wl1271_reg_write32(wl, dest_addr, val);
266
267                         nvs_ptr += 4;
268                         dest_addr += 4;
269                 }
270         }
271
272         /*
273          * We've reached the first zero length, the first NVS table
274          * is 7 bytes further.
275          */
276         nvs_ptr += 7;
277         nvs_len -= nvs_ptr - nvs;
278         nvs_len = ALIGN(nvs_len, 4);
279
280         /* FIXME: The driver sets the partition here, but this is not needed,
281            since it sets to the same one as currently in use */
282         /* Now we must set the partition correctly */
283         wl1271_set_partition(wl, &part_table[PART_WORK]);
284
285         /* Copy the NVS tables to a new block to ensure alignment */
286         nvs_aligned = kmemdup(nvs_ptr, nvs_len, GFP_KERNEL);
287
288         /* And finally we upload the NVS tables */
289         /* FIXME: In wl1271, we upload everything at once.
290            No endianness handling needed here?! The ref driver doesn't do
291            anything about it at this point */
292         wl1271_spi_mem_write(wl, CMD_MBOX_ADDRESS, nvs_aligned, nvs_len);
293
294         kfree(nvs_aligned);
295         return 0;
296 }
297
298 static void wl1271_boot_enable_interrupts(struct wl1271 *wl)
299 {
300         enable_irq(wl->irq);
301         wl1271_reg_write32(wl, ACX_REG_INTERRUPT_MASK,
302                            WL1271_ACX_INTR_ALL & ~(WL1271_INTR_MASK));
303         wl1271_reg_write32(wl, HI_CFG, HI_CFG_DEF_VAL);
304 }
305
306 static int wl1271_boot_soft_reset(struct wl1271 *wl)
307 {
308         unsigned long timeout;
309         u32 boot_data;
310
311         /* perform soft reset */
312         wl1271_reg_write32(wl, ACX_REG_SLV_SOFT_RESET, ACX_SLV_SOFT_RESET_BIT);
313
314         /* SOFT_RESET is self clearing */
315         timeout = jiffies + usecs_to_jiffies(SOFT_RESET_MAX_TIME);
316         while (1) {
317                 boot_data = wl1271_reg_read32(wl, ACX_REG_SLV_SOFT_RESET);
318                 wl1271_debug(DEBUG_BOOT, "soft reset bootdata 0x%x", boot_data);
319                 if ((boot_data & ACX_SLV_SOFT_RESET_BIT) == 0)
320                         break;
321
322                 if (time_after(jiffies, timeout)) {
323                         /* 1.2 check pWhalBus->uSelfClearTime if the
324                          * timeout was reached */
325                         wl1271_error("soft reset timeout");
326                         return -1;
327                 }
328
329                 udelay(SOFT_RESET_STALL_TIME);
330         }
331
332         /* disable Rx/Tx */
333         wl1271_reg_write32(wl, ENABLE, 0x0);
334
335         /* disable auto calibration on start*/
336         wl1271_reg_write32(wl, SPARE_A2, 0xffff);
337
338         return 0;
339 }
340
341 static int wl1271_boot_run_firmware(struct wl1271 *wl)
342 {
343         int loop, ret;
344         u32 chip_id, interrupt;
345
346         wl1271_boot_set_ecpu_ctrl(wl, ECPU_CONTROL_HALT);
347
348         chip_id = wl1271_reg_read32(wl, CHIP_ID_B);
349
350         wl1271_debug(DEBUG_BOOT, "chip id after firmware boot: 0x%x", chip_id);
351
352         if (chip_id != wl->chip.id) {
353                 wl1271_error("chip id doesn't match after firmware boot");
354                 return -EIO;
355         }
356
357         /* wait for init to complete */
358         loop = 0;
359         while (loop++ < INIT_LOOP) {
360                 udelay(INIT_LOOP_DELAY);
361                 interrupt = wl1271_reg_read32(wl, ACX_REG_INTERRUPT_NO_CLEAR);
362
363                 if (interrupt == 0xffffffff) {
364                         wl1271_error("error reading hardware complete "
365                                      "init indication");
366                         return -EIO;
367                 }
368                 /* check that ACX_INTR_INIT_COMPLETE is enabled */
369                 else if (interrupt & WL1271_ACX_INTR_INIT_COMPLETE) {
370                         wl1271_reg_write32(wl, ACX_REG_INTERRUPT_ACK,
371                                            WL1271_ACX_INTR_INIT_COMPLETE);
372                         break;
373                 }
374         }
375
376         if (loop >= INIT_LOOP) {
377                 wl1271_error("timeout waiting for the hardware to "
378                              "complete initialization");
379                 return -EIO;
380         }
381
382         /* get hardware config command mail box */
383         wl->cmd_box_addr = wl1271_reg_read32(wl, REG_COMMAND_MAILBOX_PTR);
384
385         /* get hardware config event mail box */
386         wl->event_box_addr = wl1271_reg_read32(wl, REG_EVENT_MAILBOX_PTR);
387
388         /* set the working partition to its "running" mode offset */
389         wl1271_set_partition(wl, &part_table[PART_WORK]);
390
391         wl1271_debug(DEBUG_MAILBOX, "cmd_box_addr 0x%x event_box_addr 0x%x",
392                      wl->cmd_box_addr, wl->event_box_addr);
393
394         wl1271_boot_fw_version(wl);
395
396         /*
397          * in case of full asynchronous mode the firmware event must be
398          * ready to receive event from the command mailbox
399          */
400
401         /* enable gpio interrupts */
402         wl1271_boot_enable_interrupts(wl);
403
404         /* unmask required mbox events  */
405         wl->event_mask = BSS_LOSE_EVENT_ID |
406                 SCAN_COMPLETE_EVENT_ID;
407
408         ret = wl1271_event_unmask(wl);
409         if (ret < 0) {
410                 wl1271_error("EVENT mask setting failed");
411                 return ret;
412         }
413
414         wl1271_event_mbox_config(wl);
415
416         /* firmware startup completed */
417         return 0;
418 }
419
420 static int wl1271_boot_write_irq_polarity(struct wl1271 *wl)
421 {
422         u32 polarity;
423
424         polarity = wl1271_top_reg_read(wl, OCP_REG_POLARITY);
425
426         /* We use HIGH polarity, so unset the LOW bit */
427         polarity &= ~POLARITY_LOW;
428         wl1271_top_reg_write(wl, OCP_REG_POLARITY, polarity);
429
430         return 0;
431 }
432
433 int wl1271_boot(struct wl1271 *wl)
434 {
435         int ret = 0;
436         u32 tmp, clk, pause;
437
438         if (REF_CLOCK == 0 || REF_CLOCK == 2 || REF_CLOCK == 4)
439                 /* ref clk: 19.2/38.4/38.4-XTAL */
440                 clk = 0x3;
441         else if (REF_CLOCK == 1 || REF_CLOCK == 3)
442                 /* ref clk: 26/52 */
443                 clk = 0x5;
444
445         if (REF_CLOCK != 0) {
446                 u16 val;
447                 /* Set clock type */
448                 val = wl1271_top_reg_read(wl, OCP_REG_CLK_TYPE);
449                 val &= FREF_CLK_TYPE_BITS;
450                 val |= CLK_REQ_PRCM;
451                 wl1271_top_reg_write(wl, OCP_REG_CLK_TYPE, val);
452         } else {
453                 u16 val;
454                 /* Set clock polarity */
455                 val = wl1271_top_reg_read(wl, OCP_REG_CLK_POLARITY);
456                 val &= FREF_CLK_POLARITY_BITS;
457                 val |= CLK_REQ_OUTN_SEL;
458                 wl1271_top_reg_write(wl, OCP_REG_CLK_POLARITY, val);
459         }
460
461         wl1271_reg_write32(wl, PLL_PARAMETERS, clk);
462
463         pause = wl1271_reg_read32(wl, PLL_PARAMETERS);
464
465         wl1271_debug(DEBUG_BOOT, "pause1 0x%x", pause);
466
467         pause &= ~(WU_COUNTER_PAUSE_VAL); /* FIXME: This should probably be
468                                            * WU_COUNTER_PAUSE_VAL instead of
469                                            * 0x3ff (magic number ).  How does
470                                            * this work?! */
471         pause |= WU_COUNTER_PAUSE_VAL;
472         wl1271_reg_write32(wl, WU_COUNTER_PAUSE, pause);
473
474         /* Continue the ELP wake up sequence */
475         wl1271_reg_write32(wl, WELP_ARM_COMMAND, WELP_ARM_COMMAND_VAL);
476         udelay(500);
477
478         wl1271_set_partition(wl, &part_table[PART_DRPW]);
479
480         /* Read-modify-write DRPW_SCRATCH_START register (see next state)
481            to be used by DRPw FW. The RTRIM value will be added by the FW
482            before taking DRPw out of reset */
483
484         wl1271_debug(DEBUG_BOOT, "DRPW_SCRATCH_START %08x", DRPW_SCRATCH_START);
485         clk = wl1271_reg_read32(wl, DRPW_SCRATCH_START);
486
487         wl1271_debug(DEBUG_BOOT, "clk2 0x%x", clk);
488
489         /* 2 */
490         clk |= (REF_CLOCK << 1) << 4;
491         wl1271_reg_write32(wl, DRPW_SCRATCH_START, clk);
492
493         wl1271_set_partition(wl, &part_table[PART_WORK]);
494
495         /* Disable interrupts */
496         wl1271_reg_write32(wl, ACX_REG_INTERRUPT_MASK, WL1271_ACX_INTR_ALL);
497
498         ret = wl1271_boot_soft_reset(wl);
499         if (ret < 0)
500                 goto out;
501
502         /* 2. start processing NVS file */
503         ret = wl1271_boot_upload_nvs(wl);
504         if (ret < 0)
505                 goto out;
506
507         /* write firmware's last address (ie. it's length) to
508          * ACX_EEPROMLESS_IND_REG */
509         wl1271_debug(DEBUG_BOOT, "ACX_EEPROMLESS_IND_REG");
510
511         wl1271_reg_write32(wl, ACX_EEPROMLESS_IND_REG, ACX_EEPROMLESS_IND_REG);
512
513         tmp = wl1271_reg_read32(wl, CHIP_ID_B);
514
515         wl1271_debug(DEBUG_BOOT, "chip id 0x%x", tmp);
516
517         /* 6. read the EEPROM parameters */
518         tmp = wl1271_reg_read32(wl, SCR_PAD2);
519
520         ret = wl1271_boot_write_irq_polarity(wl);
521         if (ret < 0)
522                 goto out;
523
524         /* FIXME: Need to check whether this is really what we want */
525         wl1271_reg_write32(wl, ACX_REG_INTERRUPT_MASK,
526                            WL1271_ACX_ALL_EVENTS_VECTOR);
527
528         /* WL1271: The reference driver skips steps 7 to 10 (jumps directly
529          * to upload_fw) */
530
531         ret = wl1271_boot_upload_firmware(wl);
532         if (ret < 0)
533                 goto out;
534
535         /* 10.5 start firmware */
536         ret = wl1271_boot_run_firmware(wl);
537         if (ret < 0)
538                 goto out;
539
540         /* set the wl1271 default filters */
541         wl->rx_config = WL1271_DEFAULT_RX_CONFIG;
542         wl->rx_filter = WL1271_DEFAULT_RX_FILTER;
543
544         wl1271_event_mbox_config(wl);
545
546 out:
547         return ret;
548 }