wl1271: Mask unneeded events from firmware to conserve power
[linux-2.6.git] / drivers / net / wireless / wl12xx / wl1271_boot.c
1 /*
2  * This file is part of wl1271
3  *
4  * Copyright (C) 2008-2009 Nokia Corporation
5  *
6  * Contact: Luciano Coelho <luciano.coelho@nokia.com>
7  *
8  * This program is free software; you can redistribute it and/or
9  * modify it under the terms of the GNU General Public License
10  * version 2 as published by the Free Software Foundation.
11  *
12  * This program is distributed in the hope that it will be useful, but
13  * WITHOUT ANY WARRANTY; without even the implied warranty of
14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
15  * General Public License for more details.
16  *
17  * You should have received a copy of the GNU General Public License
18  * along with this program; if not, write to the Free Software
19  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
20  * 02110-1301 USA
21  *
22  */
23
24 #include <linux/gpio.h>
25
26 #include "wl1271_acx.h"
27 #include "wl1271_reg.h"
28 #include "wl1271_boot.h"
29 #include "wl1271_spi.h"
30 #include "wl1271_event.h"
31
32 static struct wl1271_partition_set part_table[PART_TABLE_LEN] = {
33         [PART_DOWN] = {
34                 .mem = {
35                         .start = 0x00000000,
36                         .size  = 0x000177c0
37                 },
38                 .reg = {
39                         .start = REGISTERS_BASE,
40                         .size  = 0x00008800
41                 },
42         },
43
44         [PART_WORK] = {
45                 .mem = {
46                         .start = 0x00040000,
47                         .size  = 0x00014fc0
48                 },
49                 .reg = {
50                         .start = REGISTERS_BASE,
51                         .size  = 0x0000b000
52                 },
53         },
54
55         [PART_DRPW] = {
56                 .mem = {
57                         .start = 0x00040000,
58                         .size  = 0x00014fc0
59                 },
60                 .reg = {
61                         .start = DRPW_BASE,
62                         .size  = 0x00006000
63                 }
64         }
65 };
66
67 static void wl1271_boot_set_ecpu_ctrl(struct wl1271 *wl, u32 flag)
68 {
69         u32 cpu_ctrl;
70
71         /* 10.5.0 run the firmware (I) */
72         cpu_ctrl = wl1271_reg_read32(wl, ACX_REG_ECPU_CONTROL);
73
74         /* 10.5.1 run the firmware (II) */
75         cpu_ctrl |= flag;
76         wl1271_reg_write32(wl, ACX_REG_ECPU_CONTROL, cpu_ctrl);
77 }
78
79 static void wl1271_boot_fw_version(struct wl1271 *wl)
80 {
81         struct wl1271_static_data static_data;
82
83         wl1271_spi_mem_read(wl, wl->cmd_box_addr,
84                             &static_data, sizeof(static_data));
85
86         strncpy(wl->chip.fw_ver, static_data.fw_version,
87                 sizeof(wl->chip.fw_ver));
88
89         /* make sure the string is NULL-terminated */
90         wl->chip.fw_ver[sizeof(wl->chip.fw_ver) - 1] = '\0';
91 }
92
93 static int wl1271_boot_upload_firmware_chunk(struct wl1271 *wl, void *buf,
94                                              size_t fw_data_len, u32 dest)
95 {
96         int addr, chunk_num, partition_limit;
97         u8 *p, *chunk;
98
99         /* whal_FwCtrl_LoadFwImageSm() */
100
101         wl1271_debug(DEBUG_BOOT, "starting firmware upload");
102
103         wl1271_debug(DEBUG_BOOT, "fw_data_len %zd chunk_size %d",
104                      fw_data_len, CHUNK_SIZE);
105
106         if ((fw_data_len % 4) != 0) {
107                 wl1271_error("firmware length not multiple of four");
108                 return -EIO;
109         }
110
111         chunk = kmalloc(CHUNK_SIZE, GFP_KERNEL);
112         if (!buf) {
113                 wl1271_error("allocation for firmware upload chunk failed");
114                 return -ENOMEM;
115         }
116
117         wl1271_set_partition(wl, dest,
118                              part_table[PART_DOWN].mem.size,
119                              part_table[PART_DOWN].reg.start,
120                              part_table[PART_DOWN].reg.size);
121
122         /* 10.1 set partition limit and chunk num */
123         chunk_num = 0;
124         partition_limit = part_table[PART_DOWN].mem.size;
125
126         while (chunk_num < fw_data_len / CHUNK_SIZE) {
127                 /* 10.2 update partition, if needed */
128                 addr = dest + (chunk_num + 2) * CHUNK_SIZE;
129                 if (addr > partition_limit) {
130                         addr = dest + chunk_num * CHUNK_SIZE;
131                         partition_limit = chunk_num * CHUNK_SIZE +
132                                 part_table[PART_DOWN].mem.size;
133
134                         /* FIXME: Over 80 chars! */
135                         wl1271_set_partition(wl,
136                                              addr,
137                                              part_table[PART_DOWN].mem.size,
138                                              part_table[PART_DOWN].reg.start,
139                                              part_table[PART_DOWN].reg.size);
140                 }
141
142                 /* 10.3 upload the chunk */
143                 addr = dest + chunk_num * CHUNK_SIZE;
144                 p = buf + chunk_num * CHUNK_SIZE;
145                 memcpy(chunk, p, CHUNK_SIZE);
146                 wl1271_debug(DEBUG_BOOT, "uploading fw chunk 0x%p to 0x%x",
147                              p, addr);
148                 wl1271_spi_mem_write(wl, addr, chunk, CHUNK_SIZE);
149
150                 chunk_num++;
151         }
152
153         /* 10.4 upload the last chunk */
154         addr = dest + chunk_num * CHUNK_SIZE;
155         p = buf + chunk_num * CHUNK_SIZE;
156         memcpy(chunk, p, fw_data_len % CHUNK_SIZE);
157         wl1271_debug(DEBUG_BOOT, "uploading fw last chunk (%zd B) 0x%p to 0x%x",
158                      fw_data_len % CHUNK_SIZE, p, addr);
159         wl1271_spi_mem_write(wl, addr, chunk, fw_data_len % CHUNK_SIZE);
160
161         kfree(chunk);
162         return 0;
163 }
164
165 static int wl1271_boot_upload_firmware(struct wl1271 *wl)
166 {
167         u32 chunks, addr, len;
168         u8 *fw;
169
170         fw = wl->fw;
171         chunks = be32_to_cpup((u32 *) fw);
172         fw += sizeof(u32);
173
174         wl1271_debug(DEBUG_BOOT, "firmware chunks to be uploaded: %u", chunks);
175
176         while (chunks--) {
177                 addr = be32_to_cpup((u32 *) fw);
178                 fw += sizeof(u32);
179                 len = be32_to_cpup((u32 *) fw);
180                 fw += sizeof(u32);
181
182                 if (len > 300000) {
183                         wl1271_info("firmware chunk too long: %u", len);
184                         return -EINVAL;
185                 }
186                 wl1271_debug(DEBUG_BOOT, "chunk %d addr 0x%x len %u",
187                              chunks, addr, len);
188                 wl1271_boot_upload_firmware_chunk(wl, fw, len, addr);
189                 fw += len;
190         }
191
192         return 0;
193 }
194
195 static int wl1271_boot_upload_nvs(struct wl1271 *wl)
196 {
197         size_t nvs_len, burst_len;
198         int i;
199         u32 dest_addr, val;
200         u8 *nvs_ptr, *nvs, *nvs_aligned;
201
202         nvs = wl->nvs;
203         if (nvs == NULL)
204                 return -ENODEV;
205
206         nvs_ptr = nvs;
207
208         nvs_len = wl->nvs_len;
209
210         /* Update the device MAC address into the nvs */
211         nvs[11] = wl->mac_addr[0];
212         nvs[10] = wl->mac_addr[1];
213         nvs[6] = wl->mac_addr[2];
214         nvs[5] = wl->mac_addr[3];
215         nvs[4] = wl->mac_addr[4];
216         nvs[3] = wl->mac_addr[5];
217
218         /*
219          * Layout before the actual NVS tables:
220          * 1 byte : burst length.
221          * 2 bytes: destination address.
222          * n bytes: data to burst copy.
223          *
224          * This is ended by a 0 length, then the NVS tables.
225          */
226
227         /* FIXME: Do we need to check here whether the LSB is 1? */
228         while (nvs_ptr[0]) {
229                 burst_len = nvs_ptr[0];
230                 dest_addr = (nvs_ptr[1] & 0xfe) | ((u32)(nvs_ptr[2] << 8));
231
232                 /* FIXME: Due to our new wl1271_translate_reg_addr function,
233                    we need to add the REGISTER_BASE to the destination */
234                 dest_addr += REGISTERS_BASE;
235
236                 /* We move our pointer to the data */
237                 nvs_ptr += 3;
238
239                 for (i = 0; i < burst_len; i++) {
240                         val = (nvs_ptr[0] | (nvs_ptr[1] << 8)
241                                | (nvs_ptr[2] << 16) | (nvs_ptr[3] << 24));
242
243                         wl1271_debug(DEBUG_BOOT,
244                                      "nvs burst write 0x%x: 0x%x",
245                                      dest_addr, val);
246                         wl1271_reg_write32(wl, dest_addr, val);
247
248                         nvs_ptr += 4;
249                         dest_addr += 4;
250                 }
251         }
252
253         /*
254          * We've reached the first zero length, the first NVS table
255          * is 7 bytes further.
256          */
257         nvs_ptr += 7;
258         nvs_len -= nvs_ptr - nvs;
259         nvs_len = ALIGN(nvs_len, 4);
260
261         /* FIXME: The driver sets the partition here, but this is not needed,
262            since it sets to the same one as currently in use */
263         /* Now we must set the partition correctly */
264         wl1271_set_partition(wl,
265                              part_table[PART_WORK].mem.start,
266                              part_table[PART_WORK].mem.size,
267                              part_table[PART_WORK].reg.start,
268                              part_table[PART_WORK].reg.size);
269
270         /* Copy the NVS tables to a new block to ensure alignment */
271         nvs_aligned = kmemdup(nvs_ptr, nvs_len, GFP_KERNEL);
272
273         /* And finally we upload the NVS tables */
274         /* FIXME: In wl1271, we upload everything at once.
275            No endianness handling needed here?! The ref driver doesn't do
276            anything about it at this point */
277         wl1271_spi_mem_write(wl, CMD_MBOX_ADDRESS, nvs_aligned, nvs_len);
278
279         kfree(nvs_aligned);
280         return 0;
281 }
282
283 static void wl1271_boot_enable_interrupts(struct wl1271 *wl)
284 {
285         enable_irq(wl->irq);
286         wl1271_reg_write32(wl, ACX_REG_INTERRUPT_MASK,
287                            WL1271_ACX_INTR_ALL & ~(WL1271_INTR_MASK));
288         wl1271_reg_write32(wl, HI_CFG, HI_CFG_DEF_VAL);
289 }
290
291 static int wl1271_boot_soft_reset(struct wl1271 *wl)
292 {
293         unsigned long timeout;
294         u32 boot_data;
295
296         /* perform soft reset */
297         wl1271_reg_write32(wl, ACX_REG_SLV_SOFT_RESET, ACX_SLV_SOFT_RESET_BIT);
298
299         /* SOFT_RESET is self clearing */
300         timeout = jiffies + usecs_to_jiffies(SOFT_RESET_MAX_TIME);
301         while (1) {
302                 boot_data = wl1271_reg_read32(wl, ACX_REG_SLV_SOFT_RESET);
303                 wl1271_debug(DEBUG_BOOT, "soft reset bootdata 0x%x", boot_data);
304                 if ((boot_data & ACX_SLV_SOFT_RESET_BIT) == 0)
305                         break;
306
307                 if (time_after(jiffies, timeout)) {
308                         /* 1.2 check pWhalBus->uSelfClearTime if the
309                          * timeout was reached */
310                         wl1271_error("soft reset timeout");
311                         return -1;
312                 }
313
314                 udelay(SOFT_RESET_STALL_TIME);
315         }
316
317         /* disable Rx/Tx */
318         wl1271_reg_write32(wl, ENABLE, 0x0);
319
320         /* disable auto calibration on start*/
321         wl1271_reg_write32(wl, SPARE_A2, 0xffff);
322
323         return 0;
324 }
325
326 static int wl1271_boot_run_firmware(struct wl1271 *wl)
327 {
328         int loop, ret;
329         u32 chip_id, interrupt;
330
331         wl1271_boot_set_ecpu_ctrl(wl, ECPU_CONTROL_HALT);
332
333         chip_id = wl1271_reg_read32(wl, CHIP_ID_B);
334
335         wl1271_debug(DEBUG_BOOT, "chip id after firmware boot: 0x%x", chip_id);
336
337         if (chip_id != wl->chip.id) {
338                 wl1271_error("chip id doesn't match after firmware boot");
339                 return -EIO;
340         }
341
342         /* wait for init to complete */
343         loop = 0;
344         while (loop++ < INIT_LOOP) {
345                 udelay(INIT_LOOP_DELAY);
346                 interrupt = wl1271_reg_read32(wl, ACX_REG_INTERRUPT_NO_CLEAR);
347
348                 if (interrupt == 0xffffffff) {
349                         wl1271_error("error reading hardware complete "
350                                      "init indication");
351                         return -EIO;
352                 }
353                 /* check that ACX_INTR_INIT_COMPLETE is enabled */
354                 else if (interrupt & WL1271_ACX_INTR_INIT_COMPLETE) {
355                         wl1271_reg_write32(wl, ACX_REG_INTERRUPT_ACK,
356                                            WL1271_ACX_INTR_INIT_COMPLETE);
357                         break;
358                 }
359         }
360
361         if (loop >= INIT_LOOP) {
362                 wl1271_error("timeout waiting for the hardware to "
363                              "complete initialization");
364                 return -EIO;
365         }
366
367         /* get hardware config command mail box */
368         wl->cmd_box_addr = wl1271_reg_read32(wl, REG_COMMAND_MAILBOX_PTR);
369
370         /* get hardware config event mail box */
371         wl->event_box_addr = wl1271_reg_read32(wl, REG_EVENT_MAILBOX_PTR);
372
373         /* set the working partition to its "running" mode offset */
374         wl1271_set_partition(wl,
375                              part_table[PART_WORK].mem.start,
376                              part_table[PART_WORK].mem.size,
377                              part_table[PART_WORK].reg.start,
378                              part_table[PART_WORK].reg.size);
379
380         wl1271_debug(DEBUG_MAILBOX, "cmd_box_addr 0x%x event_box_addr 0x%x",
381                      wl->cmd_box_addr, wl->event_box_addr);
382
383         wl1271_boot_fw_version(wl);
384
385         /*
386          * in case of full asynchronous mode the firmware event must be
387          * ready to receive event from the command mailbox
388          */
389
390         /* enable gpio interrupts */
391         wl1271_boot_enable_interrupts(wl);
392
393         /* unmask required mbox events  */
394         wl->event_mask = BSS_LOSE_EVENT_ID |
395                 SCAN_COMPLETE_EVENT_ID;
396
397         ret = wl1271_event_unmask(wl);
398         if (ret < 0) {
399                 wl1271_error("EVENT mask setting failed");
400                 return ret;
401         }
402
403         wl1271_event_mbox_config(wl);
404
405         /* firmware startup completed */
406         return 0;
407 }
408
409 static int wl1271_boot_write_irq_polarity(struct wl1271 *wl)
410 {
411         u32 polarity, status, i;
412
413         wl1271_reg_write32(wl, OCP_POR_CTR, OCP_REG_POLARITY);
414         wl1271_reg_write32(wl, OCP_CMD, OCP_CMD_READ);
415
416         /* Wait until the command is complete (ie. bit 18 is set) */
417         for (i = 0; i < OCP_CMD_LOOP; i++) {
418                 polarity = wl1271_reg_read32(wl, OCP_DATA_READ);
419                 if (polarity & OCP_READY_MASK)
420                         break;
421         }
422         if (i == OCP_CMD_LOOP) {
423                 wl1271_error("OCP command timeout!");
424                 return -EIO;
425         }
426
427         status = polarity & OCP_STATUS_MASK;
428         if (status != OCP_STATUS_OK) {
429                 wl1271_error("OCP command failed (%d)", status);
430                 return -EIO;
431         }
432
433         /* We use HIGH polarity, so unset the LOW bit */
434         polarity &= ~POLARITY_LOW;
435
436         wl1271_reg_write32(wl, OCP_POR_CTR, OCP_REG_POLARITY);
437         wl1271_reg_write32(wl, OCP_DATA_WRITE, polarity);
438         wl1271_reg_write32(wl, OCP_CMD, OCP_CMD_WRITE);
439
440         return 0;
441 }
442
443 int wl1271_boot(struct wl1271 *wl)
444 {
445         int ret = 0;
446         u32 tmp, clk, pause;
447
448         if (REF_CLOCK == 0 || REF_CLOCK == 2)
449                 /* ref clk: 19.2/38.4 */
450                 clk = 0x3;
451         else if (REF_CLOCK == 1 || REF_CLOCK == 3)
452                 /* ref clk: 26/52 */
453                 clk = 0x5;
454
455         wl1271_reg_write32(wl, PLL_PARAMETERS, clk);
456
457         pause = wl1271_reg_read32(wl, PLL_PARAMETERS);
458
459         wl1271_debug(DEBUG_BOOT, "pause1 0x%x", pause);
460
461         pause &= ~(WU_COUNTER_PAUSE_VAL); /* FIXME: This should probably be
462                                            * WU_COUNTER_PAUSE_VAL instead of
463                                            * 0x3ff (magic number ).  How does
464                                            * this work?! */
465         pause |= WU_COUNTER_PAUSE_VAL;
466         wl1271_reg_write32(wl, WU_COUNTER_PAUSE, pause);
467
468         /* Continue the ELP wake up sequence */
469         wl1271_reg_write32(wl, WELP_ARM_COMMAND, WELP_ARM_COMMAND_VAL);
470         udelay(500);
471
472         wl1271_set_partition(wl,
473                              part_table[PART_DRPW].mem.start,
474                              part_table[PART_DRPW].mem.size,
475                              part_table[PART_DRPW].reg.start,
476                              part_table[PART_DRPW].reg.size);
477
478         /* Read-modify-write DRPW_SCRATCH_START register (see next state)
479            to be used by DRPw FW. The RTRIM value will be added by the FW
480            before taking DRPw out of reset */
481
482         wl1271_debug(DEBUG_BOOT, "DRPW_SCRATCH_START %08x", DRPW_SCRATCH_START);
483         clk = wl1271_reg_read32(wl, DRPW_SCRATCH_START);
484
485         wl1271_debug(DEBUG_BOOT, "clk2 0x%x", clk);
486
487         /* 2 */
488         clk |= (REF_CLOCK << 1) << 4;
489         wl1271_reg_write32(wl, DRPW_SCRATCH_START, clk);
490
491         wl1271_set_partition(wl,
492                              part_table[PART_WORK].mem.start,
493                              part_table[PART_WORK].mem.size,
494                              part_table[PART_WORK].reg.start,
495                              part_table[PART_WORK].reg.size);
496
497         /* Disable interrupts */
498         wl1271_reg_write32(wl, ACX_REG_INTERRUPT_MASK, WL1271_ACX_INTR_ALL);
499
500         ret = wl1271_boot_soft_reset(wl);
501         if (ret < 0)
502                 goto out;
503
504         /* 2. start processing NVS file */
505         ret = wl1271_boot_upload_nvs(wl);
506         if (ret < 0)
507                 goto out;
508
509         /* write firmware's last address (ie. it's length) to
510          * ACX_EEPROMLESS_IND_REG */
511         wl1271_debug(DEBUG_BOOT, "ACX_EEPROMLESS_IND_REG");
512
513         wl1271_reg_write32(wl, ACX_EEPROMLESS_IND_REG, ACX_EEPROMLESS_IND_REG);
514
515         tmp = wl1271_reg_read32(wl, CHIP_ID_B);
516
517         wl1271_debug(DEBUG_BOOT, "chip id 0x%x", tmp);
518
519         /* 6. read the EEPROM parameters */
520         tmp = wl1271_reg_read32(wl, SCR_PAD2);
521
522         ret = wl1271_boot_write_irq_polarity(wl);
523         if (ret < 0)
524                 goto out;
525
526         /* FIXME: Need to check whether this is really what we want */
527         wl1271_reg_write32(wl, ACX_REG_INTERRUPT_MASK,
528                            WL1271_ACX_ALL_EVENTS_VECTOR);
529
530         /* WL1271: The reference driver skips steps 7 to 10 (jumps directly
531          * to upload_fw) */
532
533         ret = wl1271_boot_upload_firmware(wl);
534         if (ret < 0)
535                 goto out;
536
537         /* 10.5 start firmware */
538         ret = wl1271_boot_run_firmware(wl);
539         if (ret < 0)
540                 goto out;
541
542         /* set the wl1271 default filters */
543         wl->rx_config = WL1271_DEFAULT_RX_CONFIG;
544         wl->rx_filter = WL1271_DEFAULT_RX_FILTER;
545
546         wl1271_event_mbox_config(wl);
547
548 out:
549         return ret;
550 }