iwlwifi/iwl3945: remove data_retry_limit
[linux-2.6.git] / drivers / net / wireless / iwlwifi / iwl-3945.c
1 /******************************************************************************
2  *
3  * Copyright(c) 2003 - 2009 Intel Corporation. All rights reserved.
4  *
5  * This program is free software; you can redistribute it and/or modify it
6  * under the terms of version 2 of the GNU General Public License as
7  * published by the Free Software Foundation.
8  *
9  * This program is distributed in the hope that it will be useful, but WITHOUT
10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
12  * more details.
13  *
14  * You should have received a copy of the GNU General Public License along with
15  * this program; if not, write to the Free Software Foundation, Inc.,
16  * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
17  *
18  * The full GNU General Public License is included in this distribution in the
19  * file called LICENSE.
20  *
21  * Contact Information:
22  *  Intel Linux Wireless <ilw@linux.intel.com>
23  * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
24  *
25  *****************************************************************************/
26
27 #include <linux/kernel.h>
28 #include <linux/module.h>
29 #include <linux/init.h>
30 #include <linux/pci.h>
31 #include <linux/dma-mapping.h>
32 #include <linux/delay.h>
33 #include <linux/skbuff.h>
34 #include <linux/netdevice.h>
35 #include <linux/wireless.h>
36 #include <linux/firmware.h>
37 #include <linux/etherdevice.h>
38 #include <asm/unaligned.h>
39 #include <net/mac80211.h>
40
41 #include "iwl-fh.h"
42 #include "iwl-3945-fh.h"
43 #include "iwl-commands.h"
44 #include "iwl-sta.h"
45 #include "iwl-3945.h"
46 #include "iwl-eeprom.h"
47 #include "iwl-helpers.h"
48 #include "iwl-core.h"
49 #include "iwl-led.h"
50 #include "iwl-3945-led.h"
51
52 #define IWL_DECLARE_RATE_INFO(r, ip, in, rp, rn, pp, np)    \
53         [IWL_RATE_##r##M_INDEX] = { IWL_RATE_##r##M_PLCP,   \
54                                     IWL_RATE_##r##M_IEEE,   \
55                                     IWL_RATE_##ip##M_INDEX, \
56                                     IWL_RATE_##in##M_INDEX, \
57                                     IWL_RATE_##rp##M_INDEX, \
58                                     IWL_RATE_##rn##M_INDEX, \
59                                     IWL_RATE_##pp##M_INDEX, \
60                                     IWL_RATE_##np##M_INDEX, \
61                                     IWL_RATE_##r##M_INDEX_TABLE, \
62                                     IWL_RATE_##ip##M_INDEX_TABLE }
63
64 /*
65  * Parameter order:
66  *   rate, prev rate, next rate, prev tgg rate, next tgg rate
67  *
68  * If there isn't a valid next or previous rate then INV is used which
69  * maps to IWL_RATE_INVALID
70  *
71  */
72 const struct iwl3945_rate_info iwl3945_rates[IWL_RATE_COUNT_3945] = {
73         IWL_DECLARE_RATE_INFO(1, INV, 2, INV, 2, INV, 2),    /*  1mbps */
74         IWL_DECLARE_RATE_INFO(2, 1, 5, 1, 5, 1, 5),          /*  2mbps */
75         IWL_DECLARE_RATE_INFO(5, 2, 6, 2, 11, 2, 11),        /*5.5mbps */
76         IWL_DECLARE_RATE_INFO(11, 9, 12, 5, 12, 5, 18),      /* 11mbps */
77         IWL_DECLARE_RATE_INFO(6, 5, 9, 5, 11, 5, 11),        /*  6mbps */
78         IWL_DECLARE_RATE_INFO(9, 6, 11, 5, 11, 5, 11),       /*  9mbps */
79         IWL_DECLARE_RATE_INFO(12, 11, 18, 11, 18, 11, 18),   /* 12mbps */
80         IWL_DECLARE_RATE_INFO(18, 12, 24, 12, 24, 11, 24),   /* 18mbps */
81         IWL_DECLARE_RATE_INFO(24, 18, 36, 18, 36, 18, 36),   /* 24mbps */
82         IWL_DECLARE_RATE_INFO(36, 24, 48, 24, 48, 24, 48),   /* 36mbps */
83         IWL_DECLARE_RATE_INFO(48, 36, 54, 36, 54, 36, 54),   /* 48mbps */
84         IWL_DECLARE_RATE_INFO(54, 48, INV, 48, INV, 48, INV),/* 54mbps */
85 };
86
87 /* 1 = enable the iwl3945_disable_events() function */
88 #define IWL_EVT_DISABLE (0)
89 #define IWL_EVT_DISABLE_SIZE (1532/32)
90
91 /**
92  * iwl3945_disable_events - Disable selected events in uCode event log
93  *
94  * Disable an event by writing "1"s into "disable"
95  *   bitmap in SRAM.  Bit position corresponds to Event # (id/type).
96  *   Default values of 0 enable uCode events to be logged.
97  * Use for only special debugging.  This function is just a placeholder as-is,
98  *   you'll need to provide the special bits! ...
99  *   ... and set IWL_EVT_DISABLE to 1. */
100 void iwl3945_disable_events(struct iwl_priv *priv)
101 {
102         int i;
103         u32 base;               /* SRAM address of event log header */
104         u32 disable_ptr;        /* SRAM address of event-disable bitmap array */
105         u32 array_size;         /* # of u32 entries in array */
106         u32 evt_disable[IWL_EVT_DISABLE_SIZE] = {
107                 0x00000000,     /*   31 -    0  Event id numbers */
108                 0x00000000,     /*   63 -   32 */
109                 0x00000000,     /*   95 -   64 */
110                 0x00000000,     /*  127 -   96 */
111                 0x00000000,     /*  159 -  128 */
112                 0x00000000,     /*  191 -  160 */
113                 0x00000000,     /*  223 -  192 */
114                 0x00000000,     /*  255 -  224 */
115                 0x00000000,     /*  287 -  256 */
116                 0x00000000,     /*  319 -  288 */
117                 0x00000000,     /*  351 -  320 */
118                 0x00000000,     /*  383 -  352 */
119                 0x00000000,     /*  415 -  384 */
120                 0x00000000,     /*  447 -  416 */
121                 0x00000000,     /*  479 -  448 */
122                 0x00000000,     /*  511 -  480 */
123                 0x00000000,     /*  543 -  512 */
124                 0x00000000,     /*  575 -  544 */
125                 0x00000000,     /*  607 -  576 */
126                 0x00000000,     /*  639 -  608 */
127                 0x00000000,     /*  671 -  640 */
128                 0x00000000,     /*  703 -  672 */
129                 0x00000000,     /*  735 -  704 */
130                 0x00000000,     /*  767 -  736 */
131                 0x00000000,     /*  799 -  768 */
132                 0x00000000,     /*  831 -  800 */
133                 0x00000000,     /*  863 -  832 */
134                 0x00000000,     /*  895 -  864 */
135                 0x00000000,     /*  927 -  896 */
136                 0x00000000,     /*  959 -  928 */
137                 0x00000000,     /*  991 -  960 */
138                 0x00000000,     /* 1023 -  992 */
139                 0x00000000,     /* 1055 - 1024 */
140                 0x00000000,     /* 1087 - 1056 */
141                 0x00000000,     /* 1119 - 1088 */
142                 0x00000000,     /* 1151 - 1120 */
143                 0x00000000,     /* 1183 - 1152 */
144                 0x00000000,     /* 1215 - 1184 */
145                 0x00000000,     /* 1247 - 1216 */
146                 0x00000000,     /* 1279 - 1248 */
147                 0x00000000,     /* 1311 - 1280 */
148                 0x00000000,     /* 1343 - 1312 */
149                 0x00000000,     /* 1375 - 1344 */
150                 0x00000000,     /* 1407 - 1376 */
151                 0x00000000,     /* 1439 - 1408 */
152                 0x00000000,     /* 1471 - 1440 */
153                 0x00000000,     /* 1503 - 1472 */
154         };
155
156         base = le32_to_cpu(priv->card_alive.log_event_table_ptr);
157         if (!iwl3945_hw_valid_rtc_data_addr(base)) {
158                 IWL_ERR(priv, "Invalid event log pointer 0x%08X\n", base);
159                 return;
160         }
161
162         disable_ptr = iwl_read_targ_mem(priv, base + (4 * sizeof(u32)));
163         array_size = iwl_read_targ_mem(priv, base + (5 * sizeof(u32)));
164
165         if (IWL_EVT_DISABLE && (array_size == IWL_EVT_DISABLE_SIZE)) {
166                 IWL_DEBUG_INFO(priv, "Disabling selected uCode log events at 0x%x\n",
167                                disable_ptr);
168                 for (i = 0; i < IWL_EVT_DISABLE_SIZE; i++)
169                         iwl_write_targ_mem(priv,
170                                            disable_ptr + (i * sizeof(u32)),
171                                            evt_disable[i]);
172
173         } else {
174                 IWL_DEBUG_INFO(priv, "Selected uCode log events may be disabled\n");
175                 IWL_DEBUG_INFO(priv, "  by writing \"1\"s into disable bitmap\n");
176                 IWL_DEBUG_INFO(priv, "  in SRAM at 0x%x, size %d u32s\n",
177                                disable_ptr, array_size);
178         }
179
180 }
181
182 static int iwl3945_hwrate_to_plcp_idx(u8 plcp)
183 {
184         int idx;
185
186         for (idx = 0; idx < IWL_RATE_COUNT; idx++)
187                 if (iwl3945_rates[idx].plcp == plcp)
188                         return idx;
189         return -1;
190 }
191
192 #ifdef CONFIG_IWLWIFI_DEBUG
193 #define TX_STATUS_ENTRY(x) case TX_STATUS_FAIL_ ## x: return #x
194
195 static const char *iwl3945_get_tx_fail_reason(u32 status)
196 {
197         switch (status & TX_STATUS_MSK) {
198         case TX_STATUS_SUCCESS:
199                 return "SUCCESS";
200                 TX_STATUS_ENTRY(SHORT_LIMIT);
201                 TX_STATUS_ENTRY(LONG_LIMIT);
202                 TX_STATUS_ENTRY(FIFO_UNDERRUN);
203                 TX_STATUS_ENTRY(MGMNT_ABORT);
204                 TX_STATUS_ENTRY(NEXT_FRAG);
205                 TX_STATUS_ENTRY(LIFE_EXPIRE);
206                 TX_STATUS_ENTRY(DEST_PS);
207                 TX_STATUS_ENTRY(ABORTED);
208                 TX_STATUS_ENTRY(BT_RETRY);
209                 TX_STATUS_ENTRY(STA_INVALID);
210                 TX_STATUS_ENTRY(FRAG_DROPPED);
211                 TX_STATUS_ENTRY(TID_DISABLE);
212                 TX_STATUS_ENTRY(FRAME_FLUSHED);
213                 TX_STATUS_ENTRY(INSUFFICIENT_CF_POLL);
214                 TX_STATUS_ENTRY(TX_LOCKED);
215                 TX_STATUS_ENTRY(NO_BEACON_ON_RADAR);
216         }
217
218         return "UNKNOWN";
219 }
220 #else
221 static inline const char *iwl3945_get_tx_fail_reason(u32 status)
222 {
223         return "";
224 }
225 #endif
226
227 /*
228  * get ieee prev rate from rate scale table.
229  * for A and B mode we need to overright prev
230  * value
231  */
232 int iwl3945_rs_next_rate(struct iwl_priv *priv, int rate)
233 {
234         int next_rate = iwl3945_get_prev_ieee_rate(rate);
235
236         switch (priv->band) {
237         case IEEE80211_BAND_5GHZ:
238                 if (rate == IWL_RATE_12M_INDEX)
239                         next_rate = IWL_RATE_9M_INDEX;
240                 else if (rate == IWL_RATE_6M_INDEX)
241                         next_rate = IWL_RATE_6M_INDEX;
242                 break;
243         case IEEE80211_BAND_2GHZ:
244                 if (!(priv->sta_supp_rates & IWL_OFDM_RATES_MASK) &&
245                     iwl_is_associated(priv)) {
246                         if (rate == IWL_RATE_11M_INDEX)
247                                 next_rate = IWL_RATE_5M_INDEX;
248                 }
249                 break;
250
251         default:
252                 break;
253         }
254
255         return next_rate;
256 }
257
258
259 /**
260  * iwl3945_tx_queue_reclaim - Reclaim Tx queue entries already Tx'd
261  *
262  * When FW advances 'R' index, all entries between old and new 'R' index
263  * need to be reclaimed. As result, some free space forms. If there is
264  * enough free space (> low mark), wake the stack that feeds us.
265  */
266 static void iwl3945_tx_queue_reclaim(struct iwl_priv *priv,
267                                      int txq_id, int index)
268 {
269         struct iwl_tx_queue *txq = &priv->txq[txq_id];
270         struct iwl_queue *q = &txq->q;
271         struct iwl_tx_info *tx_info;
272
273         BUG_ON(txq_id == IWL_CMD_QUEUE_NUM);
274
275         for (index = iwl_queue_inc_wrap(index, q->n_bd); q->read_ptr != index;
276                 q->read_ptr = iwl_queue_inc_wrap(q->read_ptr, q->n_bd)) {
277
278                 tx_info = &txq->txb[txq->q.read_ptr];
279                 ieee80211_tx_status_irqsafe(priv->hw, tx_info->skb[0]);
280                 tx_info->skb[0] = NULL;
281                 priv->cfg->ops->lib->txq_free_tfd(priv, txq);
282         }
283
284         if (iwl_queue_space(q) > q->low_mark && (txq_id >= 0) &&
285                         (txq_id != IWL_CMD_QUEUE_NUM) &&
286                         priv->mac80211_registered)
287                 iwl_wake_queue(priv, txq_id);
288 }
289
290 /**
291  * iwl3945_rx_reply_tx - Handle Tx response
292  */
293 static void iwl3945_rx_reply_tx(struct iwl_priv *priv,
294                             struct iwl_rx_mem_buffer *rxb)
295 {
296         struct iwl_rx_packet *pkt = (void *)rxb->skb->data;
297         u16 sequence = le16_to_cpu(pkt->hdr.sequence);
298         int txq_id = SEQ_TO_QUEUE(sequence);
299         int index = SEQ_TO_INDEX(sequence);
300         struct iwl_tx_queue *txq = &priv->txq[txq_id];
301         struct ieee80211_tx_info *info;
302         struct iwl3945_tx_resp *tx_resp = (void *)&pkt->u.raw[0];
303         u32  status = le32_to_cpu(tx_resp->status);
304         int rate_idx;
305         int fail;
306
307         if ((index >= txq->q.n_bd) || (iwl_queue_used(&txq->q, index) == 0)) {
308                 IWL_ERR(priv, "Read index for DMA queue txq_id (%d) index %d "
309                           "is out of range [0-%d] %d %d\n", txq_id,
310                           index, txq->q.n_bd, txq->q.write_ptr,
311                           txq->q.read_ptr);
312                 return;
313         }
314
315         info = IEEE80211_SKB_CB(txq->txb[txq->q.read_ptr].skb[0]);
316         ieee80211_tx_info_clear_status(info);
317
318         /* Fill the MRR chain with some info about on-chip retransmissions */
319         rate_idx = iwl3945_hwrate_to_plcp_idx(tx_resp->rate);
320         if (info->band == IEEE80211_BAND_5GHZ)
321                 rate_idx -= IWL_FIRST_OFDM_RATE;
322
323         fail = tx_resp->failure_frame;
324
325         info->status.rates[0].idx = rate_idx;
326         info->status.rates[0].count = fail + 1; /* add final attempt */
327
328         /* tx_status->rts_retry_count = tx_resp->failure_rts; */
329         info->flags |= ((status & TX_STATUS_MSK) == TX_STATUS_SUCCESS) ?
330                                 IEEE80211_TX_STAT_ACK : 0;
331
332         IWL_DEBUG_TX(priv, "Tx queue %d Status %s (0x%08x) plcp rate %d retries %d\n",
333                         txq_id, iwl3945_get_tx_fail_reason(status), status,
334                         tx_resp->rate, tx_resp->failure_frame);
335
336         IWL_DEBUG_TX_REPLY(priv, "Tx queue reclaim %d\n", index);
337         iwl3945_tx_queue_reclaim(priv, txq_id, index);
338
339         if (iwl_check_bits(status, TX_ABORT_REQUIRED_MSK))
340                 IWL_ERR(priv, "TODO:  Implement Tx ABORT REQUIRED!!!\n");
341 }
342
343
344
345 /*****************************************************************************
346  *
347  * Intel PRO/Wireless 3945ABG/BG Network Connection
348  *
349  *  RX handler implementations
350  *
351  *****************************************************************************/
352
353 void iwl3945_hw_rx_statistics(struct iwl_priv *priv,
354                 struct iwl_rx_mem_buffer *rxb)
355 {
356         struct iwl_rx_packet *pkt = (void *)rxb->skb->data;
357         IWL_DEBUG_RX(priv, "Statistics notification received (%d vs %d).\n",
358                      (int)sizeof(struct iwl3945_notif_statistics),
359                      le32_to_cpu(pkt->len_n_flags) & FH_RSCSR_FRAME_SIZE_MSK);
360
361         memcpy(&priv->statistics_39, pkt->u.raw, sizeof(priv->statistics_39));
362
363         iwl_leds_background(priv);
364 }
365
366 /******************************************************************************
367  *
368  * Misc. internal state and helper functions
369  *
370  ******************************************************************************/
371 #ifdef CONFIG_IWLWIFI_DEBUG
372
373 /**
374  * iwl3945_report_frame - dump frame to syslog during debug sessions
375  *
376  * You may hack this function to show different aspects of received frames,
377  * including selective frame dumps.
378  * group100 parameter selects whether to show 1 out of 100 good frames.
379  */
380 static void _iwl3945_dbg_report_frame(struct iwl_priv *priv,
381                       struct iwl_rx_packet *pkt,
382                       struct ieee80211_hdr *header, int group100)
383 {
384         u32 to_us;
385         u32 print_summary = 0;
386         u32 print_dump = 0;     /* set to 1 to dump all frames' contents */
387         u32 hundred = 0;
388         u32 dataframe = 0;
389         __le16 fc;
390         u16 seq_ctl;
391         u16 channel;
392         u16 phy_flags;
393         u16 length;
394         u16 status;
395         u16 bcn_tmr;
396         u32 tsf_low;
397         u64 tsf;
398         u8 rssi;
399         u8 agc;
400         u16 sig_avg;
401         u16 noise_diff;
402         struct iwl3945_rx_frame_stats *rx_stats = IWL_RX_STATS(pkt);
403         struct iwl3945_rx_frame_hdr *rx_hdr = IWL_RX_HDR(pkt);
404         struct iwl3945_rx_frame_end *rx_end = IWL_RX_END(pkt);
405         u8 *data = IWL_RX_DATA(pkt);
406
407         /* MAC header */
408         fc = header->frame_control;
409         seq_ctl = le16_to_cpu(header->seq_ctrl);
410
411         /* metadata */
412         channel = le16_to_cpu(rx_hdr->channel);
413         phy_flags = le16_to_cpu(rx_hdr->phy_flags);
414         length = le16_to_cpu(rx_hdr->len);
415
416         /* end-of-frame status and timestamp */
417         status = le32_to_cpu(rx_end->status);
418         bcn_tmr = le32_to_cpu(rx_end->beacon_timestamp);
419         tsf_low = le64_to_cpu(rx_end->timestamp) & 0x0ffffffff;
420         tsf = le64_to_cpu(rx_end->timestamp);
421
422         /* signal statistics */
423         rssi = rx_stats->rssi;
424         agc = rx_stats->agc;
425         sig_avg = le16_to_cpu(rx_stats->sig_avg);
426         noise_diff = le16_to_cpu(rx_stats->noise_diff);
427
428         to_us = !compare_ether_addr(header->addr1, priv->mac_addr);
429
430         /* if data frame is to us and all is good,
431          *   (optionally) print summary for only 1 out of every 100 */
432         if (to_us && (fc & ~cpu_to_le16(IEEE80211_FCTL_PROTECTED)) ==
433             cpu_to_le16(IEEE80211_FCTL_FROMDS | IEEE80211_FTYPE_DATA)) {
434                 dataframe = 1;
435                 if (!group100)
436                         print_summary = 1;      /* print each frame */
437                 else if (priv->framecnt_to_us < 100) {
438                         priv->framecnt_to_us++;
439                         print_summary = 0;
440                 } else {
441                         priv->framecnt_to_us = 0;
442                         print_summary = 1;
443                         hundred = 1;
444                 }
445         } else {
446                 /* print summary for all other frames */
447                 print_summary = 1;
448         }
449
450         if (print_summary) {
451                 char *title;
452                 int rate;
453
454                 if (hundred)
455                         title = "100Frames";
456                 else if (ieee80211_has_retry(fc))
457                         title = "Retry";
458                 else if (ieee80211_is_assoc_resp(fc))
459                         title = "AscRsp";
460                 else if (ieee80211_is_reassoc_resp(fc))
461                         title = "RasRsp";
462                 else if (ieee80211_is_probe_resp(fc)) {
463                         title = "PrbRsp";
464                         print_dump = 1; /* dump frame contents */
465                 } else if (ieee80211_is_beacon(fc)) {
466                         title = "Beacon";
467                         print_dump = 1; /* dump frame contents */
468                 } else if (ieee80211_is_atim(fc))
469                         title = "ATIM";
470                 else if (ieee80211_is_auth(fc))
471                         title = "Auth";
472                 else if (ieee80211_is_deauth(fc))
473                         title = "DeAuth";
474                 else if (ieee80211_is_disassoc(fc))
475                         title = "DisAssoc";
476                 else
477                         title = "Frame";
478
479                 rate = iwl3945_hwrate_to_plcp_idx(rx_hdr->rate);
480                 if (rate == -1)
481                         rate = 0;
482                 else
483                         rate = iwl3945_rates[rate].ieee / 2;
484
485                 /* print frame summary.
486                  * MAC addresses show just the last byte (for brevity),
487                  *    but you can hack it to show more, if you'd like to. */
488                 if (dataframe)
489                         IWL_DEBUG_RX(priv, "%s: mhd=0x%04x, dst=0x%02x, "
490                                      "len=%u, rssi=%d, chnl=%d, rate=%d, \n",
491                                      title, le16_to_cpu(fc), header->addr1[5],
492                                      length, rssi, channel, rate);
493                 else {
494                         /* src/dst addresses assume managed mode */
495                         IWL_DEBUG_RX(priv, "%s: 0x%04x, dst=0x%02x, "
496                                      "src=0x%02x, rssi=%u, tim=%lu usec, "
497                                      "phy=0x%02x, chnl=%d\n",
498                                      title, le16_to_cpu(fc), header->addr1[5],
499                                      header->addr3[5], rssi,
500                                      tsf_low - priv->scan_start_tsf,
501                                      phy_flags, channel);
502                 }
503         }
504         if (print_dump)
505                 iwl_print_hex_dump(priv, IWL_DL_RX, data, length);
506 }
507
508 static void iwl3945_dbg_report_frame(struct iwl_priv *priv,
509                       struct iwl_rx_packet *pkt,
510                       struct ieee80211_hdr *header, int group100)
511 {
512         if (iwl_get_debug_level(priv) & IWL_DL_RX)
513                 _iwl3945_dbg_report_frame(priv, pkt, header, group100);
514 }
515
516 #else
517 static inline void iwl3945_dbg_report_frame(struct iwl_priv *priv,
518                       struct iwl_rx_packet *pkt,
519                       struct ieee80211_hdr *header, int group100)
520 {
521 }
522 #endif
523
524 /* This is necessary only for a number of statistics, see the caller. */
525 static int iwl3945_is_network_packet(struct iwl_priv *priv,
526                 struct ieee80211_hdr *header)
527 {
528         /* Filter incoming packets to determine if they are targeted toward
529          * this network, discarding packets coming from ourselves */
530         switch (priv->iw_mode) {
531         case NL80211_IFTYPE_ADHOC: /* Header: Dest. | Source    | BSSID */
532                 /* packets to our IBSS update information */
533                 return !compare_ether_addr(header->addr3, priv->bssid);
534         case NL80211_IFTYPE_STATION: /* Header: Dest. | AP{BSSID} | Source */
535                 /* packets to our IBSS update information */
536                 return !compare_ether_addr(header->addr2, priv->bssid);
537         default:
538                 return 1;
539         }
540 }
541
542 static void iwl3945_pass_packet_to_mac80211(struct iwl_priv *priv,
543                                    struct iwl_rx_mem_buffer *rxb,
544                                    struct ieee80211_rx_status *stats)
545 {
546         struct iwl_rx_packet *pkt = (struct iwl_rx_packet *)rxb->skb->data;
547         struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)IWL_RX_DATA(pkt);
548         struct iwl3945_rx_frame_hdr *rx_hdr = IWL_RX_HDR(pkt);
549         struct iwl3945_rx_frame_end *rx_end = IWL_RX_END(pkt);
550         short len = le16_to_cpu(rx_hdr->len);
551
552         /* We received data from the HW, so stop the watchdog */
553         if (unlikely((len + IWL39_RX_FRAME_SIZE) > skb_tailroom(rxb->skb))) {
554                 IWL_DEBUG_DROP(priv, "Corruption detected!\n");
555                 return;
556         }
557
558         /* We only process data packets if the interface is open */
559         if (unlikely(!priv->is_open)) {
560                 IWL_DEBUG_DROP_LIMIT(priv,
561                         "Dropping packet while interface is not open.\n");
562                 return;
563         }
564
565         skb_reserve(rxb->skb, (void *)rx_hdr->payload - (void *)pkt);
566         /* Set the size of the skb to the size of the frame */
567         skb_put(rxb->skb, le16_to_cpu(rx_hdr->len));
568
569         if (!iwl3945_mod_params.sw_crypto)
570                 iwl_set_decrypted_flag(priv,
571                                        (struct ieee80211_hdr *)rxb->skb->data,
572                                        le32_to_cpu(rx_end->status), stats);
573
574         iwl_update_stats(priv, false, hdr->frame_control, len);
575
576         memcpy(IEEE80211_SKB_RXCB(rxb->skb), stats, sizeof(*stats));
577         ieee80211_rx_irqsafe(priv->hw, rxb->skb);
578         rxb->skb = NULL;
579 }
580
581 #define IWL_DELAY_NEXT_SCAN_AFTER_ASSOC (HZ*6)
582
583 static void iwl3945_rx_reply_rx(struct iwl_priv *priv,
584                                 struct iwl_rx_mem_buffer *rxb)
585 {
586         struct ieee80211_hdr *header;
587         struct ieee80211_rx_status rx_status;
588         struct iwl_rx_packet *pkt = (void *)rxb->skb->data;
589         struct iwl3945_rx_frame_stats *rx_stats = IWL_RX_STATS(pkt);
590         struct iwl3945_rx_frame_hdr *rx_hdr = IWL_RX_HDR(pkt);
591         struct iwl3945_rx_frame_end *rx_end = IWL_RX_END(pkt);
592         int snr;
593         u16 rx_stats_sig_avg = le16_to_cpu(rx_stats->sig_avg);
594         u16 rx_stats_noise_diff = le16_to_cpu(rx_stats->noise_diff);
595         u8 network_packet;
596
597         rx_status.flag = 0;
598         rx_status.mactime = le64_to_cpu(rx_end->timestamp);
599         rx_status.freq =
600                 ieee80211_channel_to_frequency(le16_to_cpu(rx_hdr->channel));
601         rx_status.band = (rx_hdr->phy_flags & RX_RES_PHY_FLAGS_BAND_24_MSK) ?
602                                 IEEE80211_BAND_2GHZ : IEEE80211_BAND_5GHZ;
603
604         rx_status.rate_idx = iwl3945_hwrate_to_plcp_idx(rx_hdr->rate);
605         if (rx_status.band == IEEE80211_BAND_5GHZ)
606                 rx_status.rate_idx -= IWL_FIRST_OFDM_RATE;
607
608         rx_status.antenna = (le16_to_cpu(rx_hdr->phy_flags) &
609                                         RX_RES_PHY_FLAGS_ANTENNA_MSK) >> 4;
610
611         /* set the preamble flag if appropriate */
612         if (rx_hdr->phy_flags & RX_RES_PHY_FLAGS_SHORT_PREAMBLE_MSK)
613                 rx_status.flag |= RX_FLAG_SHORTPRE;
614
615         if ((unlikely(rx_stats->phy_count > 20))) {
616                 IWL_DEBUG_DROP(priv, "dsp size out of range [0,20]: %d/n",
617                                 rx_stats->phy_count);
618                 return;
619         }
620
621         if (!(rx_end->status & RX_RES_STATUS_NO_CRC32_ERROR)
622             || !(rx_end->status & RX_RES_STATUS_NO_RXE_OVERFLOW)) {
623                 IWL_DEBUG_RX(priv, "Bad CRC or FIFO: 0x%08X.\n", rx_end->status);
624                 return;
625         }
626
627
628
629         /* Convert 3945's rssi indicator to dBm */
630         rx_status.signal = rx_stats->rssi - IWL39_RSSI_OFFSET;
631
632         /* Set default noise value to -127 */
633         if (priv->last_rx_noise == 0)
634                 priv->last_rx_noise = IWL_NOISE_MEAS_NOT_AVAILABLE;
635
636         /* 3945 provides noise info for OFDM frames only.
637          * sig_avg and noise_diff are measured by the 3945's digital signal
638          *   processor (DSP), and indicate linear levels of signal level and
639          *   distortion/noise within the packet preamble after
640          *   automatic gain control (AGC).  sig_avg should stay fairly
641          *   constant if the radio's AGC is working well.
642          * Since these values are linear (not dB or dBm), linear
643          *   signal-to-noise ratio (SNR) is (sig_avg / noise_diff).
644          * Convert linear SNR to dB SNR, then subtract that from rssi dBm
645          *   to obtain noise level in dBm.
646          * Calculate rx_status.signal (quality indicator in %) based on SNR. */
647         if (rx_stats_noise_diff) {
648                 snr = rx_stats_sig_avg / rx_stats_noise_diff;
649                 rx_status.noise = rx_status.signal -
650                                         iwl3945_calc_db_from_ratio(snr);
651                 rx_status.qual = iwl3945_calc_sig_qual(rx_status.signal,
652                                                          rx_status.noise);
653
654         /* If noise info not available, calculate signal quality indicator (%)
655          *   using just the dBm signal level. */
656         } else {
657                 rx_status.noise = priv->last_rx_noise;
658                 rx_status.qual = iwl3945_calc_sig_qual(rx_status.signal, 0);
659         }
660
661
662         IWL_DEBUG_STATS(priv, "Rssi %d noise %d qual %d sig_avg %d noise_diff %d\n",
663                         rx_status.signal, rx_status.noise, rx_status.qual,
664                         rx_stats_sig_avg, rx_stats_noise_diff);
665
666         header = (struct ieee80211_hdr *)IWL_RX_DATA(pkt);
667
668         network_packet = iwl3945_is_network_packet(priv, header);
669
670         IWL_DEBUG_STATS_LIMIT(priv, "[%c] %d RSSI:%d Signal:%u, Noise:%u, Rate:%u\n",
671                               network_packet ? '*' : ' ',
672                               le16_to_cpu(rx_hdr->channel),
673                               rx_status.signal, rx_status.signal,
674                               rx_status.noise, rx_status.rate_idx);
675
676         /* Set "1" to report good data frames in groups of 100 */
677         iwl3945_dbg_report_frame(priv, pkt, header, 1);
678         iwl_dbg_log_rx_data_frame(priv, le16_to_cpu(rx_hdr->len), header);
679
680         if (network_packet) {
681                 priv->last_beacon_time = le32_to_cpu(rx_end->beacon_timestamp);
682                 priv->last_tsf = le64_to_cpu(rx_end->timestamp);
683                 priv->last_rx_rssi = rx_status.signal;
684                 priv->last_rx_noise = rx_status.noise;
685         }
686
687         iwl3945_pass_packet_to_mac80211(priv, rxb, &rx_status);
688 }
689
690 int iwl3945_hw_txq_attach_buf_to_tfd(struct iwl_priv *priv,
691                                      struct iwl_tx_queue *txq,
692                                      dma_addr_t addr, u16 len, u8 reset, u8 pad)
693 {
694         int count;
695         struct iwl_queue *q;
696         struct iwl3945_tfd *tfd, *tfd_tmp;
697
698         q = &txq->q;
699         tfd_tmp = (struct iwl3945_tfd *)txq->tfds;
700         tfd = &tfd_tmp[q->write_ptr];
701
702         if (reset)
703                 memset(tfd, 0, sizeof(*tfd));
704
705         count = TFD_CTL_COUNT_GET(le32_to_cpu(tfd->control_flags));
706
707         if ((count >= NUM_TFD_CHUNKS) || (count < 0)) {
708                 IWL_ERR(priv, "Error can not send more than %d chunks\n",
709                           NUM_TFD_CHUNKS);
710                 return -EINVAL;
711         }
712
713         tfd->tbs[count].addr = cpu_to_le32(addr);
714         tfd->tbs[count].len = cpu_to_le32(len);
715
716         count++;
717
718         tfd->control_flags = cpu_to_le32(TFD_CTL_COUNT_SET(count) |
719                                          TFD_CTL_PAD_SET(pad));
720
721         return 0;
722 }
723
724 /**
725  * iwl3945_hw_txq_free_tfd - Free one TFD, those at index [txq->q.read_ptr]
726  *
727  * Does NOT advance any indexes
728  */
729 void iwl3945_hw_txq_free_tfd(struct iwl_priv *priv, struct iwl_tx_queue *txq)
730 {
731         struct iwl3945_tfd *tfd_tmp = (struct iwl3945_tfd *)txq->tfds;
732         int index = txq->q.read_ptr;
733         struct iwl3945_tfd *tfd = &tfd_tmp[index];
734         struct pci_dev *dev = priv->pci_dev;
735         int i;
736         int counter;
737
738         /* sanity check */
739         counter = TFD_CTL_COUNT_GET(le32_to_cpu(tfd->control_flags));
740         if (counter > NUM_TFD_CHUNKS) {
741                 IWL_ERR(priv, "Too many chunks: %i\n", counter);
742                 /* @todo issue fatal error, it is quite serious situation */
743                 return;
744         }
745
746         /* Unmap tx_cmd */
747         if (counter)
748                 pci_unmap_single(dev,
749                                 pci_unmap_addr(&txq->meta[index], mapping),
750                                 pci_unmap_len(&txq->meta[index], len),
751                                 PCI_DMA_TODEVICE);
752
753         /* unmap chunks if any */
754
755         for (i = 1; i < counter; i++) {
756                 pci_unmap_single(dev, le32_to_cpu(tfd->tbs[i].addr),
757                          le32_to_cpu(tfd->tbs[i].len), PCI_DMA_TODEVICE);
758                 if (txq->txb[txq->q.read_ptr].skb[0]) {
759                         struct sk_buff *skb = txq->txb[txq->q.read_ptr].skb[0];
760                         if (txq->txb[txq->q.read_ptr].skb[0]) {
761                                 /* Can be called from interrupt context */
762                                 dev_kfree_skb_any(skb);
763                                 txq->txb[txq->q.read_ptr].skb[0] = NULL;
764                         }
765                 }
766         }
767         return ;
768 }
769
770 /**
771  * iwl3945_hw_build_tx_cmd_rate - Add rate portion to TX_CMD:
772  *
773 */
774 void iwl3945_hw_build_tx_cmd_rate(struct iwl_priv *priv,
775                                   struct iwl_device_cmd *cmd,
776                                   struct ieee80211_tx_info *info,
777                                   struct ieee80211_hdr *hdr,
778                                   int sta_id, int tx_id)
779 {
780         u16 hw_value = ieee80211_get_tx_rate(priv->hw, info)->hw_value;
781         u16 rate_index = min(hw_value & 0xffff, IWL_RATE_COUNT - 1);
782         u16 rate_mask;
783         int rate;
784         u8 rts_retry_limit;
785         u8 data_retry_limit;
786         __le32 tx_flags;
787         __le16 fc = hdr->frame_control;
788         struct iwl3945_tx_cmd *tx_cmd = (struct iwl3945_tx_cmd *)cmd->cmd.payload;
789
790         rate = iwl3945_rates[rate_index].plcp;
791         tx_flags = tx_cmd->tx_flags;
792
793         /* We need to figure out how to get the sta->supp_rates while
794          * in this running context */
795         rate_mask = IWL_RATES_MASK;
796
797         if (tx_id >= IWL_CMD_QUEUE_NUM)
798                 rts_retry_limit = 3;
799         else
800                 rts_retry_limit = 7;
801
802         if (ieee80211_is_probe_resp(fc)) {
803                 data_retry_limit = 3;
804                 if (data_retry_limit < rts_retry_limit)
805                         rts_retry_limit = data_retry_limit;
806         } else
807                 data_retry_limit = IWL_DEFAULT_TX_RETRY;
808
809         if (ieee80211_is_mgmt(fc)) {
810                 switch (fc & cpu_to_le16(IEEE80211_FCTL_STYPE)) {
811                 case cpu_to_le16(IEEE80211_STYPE_AUTH):
812                 case cpu_to_le16(IEEE80211_STYPE_DEAUTH):
813                 case cpu_to_le16(IEEE80211_STYPE_ASSOC_REQ):
814                 case cpu_to_le16(IEEE80211_STYPE_REASSOC_REQ):
815                         if (tx_flags & TX_CMD_FLG_RTS_MSK) {
816                                 tx_flags &= ~TX_CMD_FLG_RTS_MSK;
817                                 tx_flags |= TX_CMD_FLG_CTS_MSK;
818                         }
819                         break;
820                 default:
821                         break;
822                 }
823         }
824
825         tx_cmd->rts_retry_limit = rts_retry_limit;
826         tx_cmd->data_retry_limit = data_retry_limit;
827         tx_cmd->rate = rate;
828         tx_cmd->tx_flags = tx_flags;
829
830         /* OFDM */
831         tx_cmd->supp_rates[0] =
832            ((rate_mask & IWL_OFDM_RATES_MASK) >> IWL_FIRST_OFDM_RATE) & 0xFF;
833
834         /* CCK */
835         tx_cmd->supp_rates[1] = (rate_mask & 0xF);
836
837         IWL_DEBUG_RATE(priv, "Tx sta id: %d, rate: %d (plcp), flags: 0x%4X "
838                        "cck/ofdm mask: 0x%x/0x%x\n", sta_id,
839                        tx_cmd->rate, le32_to_cpu(tx_cmd->tx_flags),
840                        tx_cmd->supp_rates[1], tx_cmd->supp_rates[0]);
841 }
842
843 u8 iwl3945_sync_sta(struct iwl_priv *priv, int sta_id, u16 tx_rate, u8 flags)
844 {
845         unsigned long flags_spin;
846         struct iwl_station_entry *station;
847
848         if (sta_id == IWL_INVALID_STATION)
849                 return IWL_INVALID_STATION;
850
851         spin_lock_irqsave(&priv->sta_lock, flags_spin);
852         station = &priv->stations[sta_id];
853
854         station->sta.sta.modify_mask = STA_MODIFY_TX_RATE_MSK;
855         station->sta.rate_n_flags = cpu_to_le16(tx_rate);
856         station->sta.mode = STA_CONTROL_MODIFY_MSK;
857
858         spin_unlock_irqrestore(&priv->sta_lock, flags_spin);
859
860         iwl_send_add_sta(priv, &station->sta, flags);
861         IWL_DEBUG_RATE(priv, "SCALE sync station %d to rate %d\n",
862                         sta_id, tx_rate);
863         return sta_id;
864 }
865
866 static int iwl3945_set_pwr_src(struct iwl_priv *priv, enum iwl_pwr_src src)
867 {
868         if (src == IWL_PWR_SRC_VAUX) {
869                 if (pci_pme_capable(priv->pci_dev, PCI_D3cold)) {
870                         iwl_set_bits_mask_prph(priv, APMG_PS_CTRL_REG,
871                                         APMG_PS_CTRL_VAL_PWR_SRC_VAUX,
872                                         ~APMG_PS_CTRL_MSK_PWR_SRC);
873
874                         iwl_poll_bit(priv, CSR_GPIO_IN,
875                                      CSR_GPIO_IN_VAL_VAUX_PWR_SRC,
876                                      CSR_GPIO_IN_BIT_AUX_POWER, 5000);
877                 }
878         } else {
879                 iwl_set_bits_mask_prph(priv, APMG_PS_CTRL_REG,
880                                 APMG_PS_CTRL_VAL_PWR_SRC_VMAIN,
881                                 ~APMG_PS_CTRL_MSK_PWR_SRC);
882
883                 iwl_poll_bit(priv, CSR_GPIO_IN, CSR_GPIO_IN_VAL_VMAIN_PWR_SRC,
884                              CSR_GPIO_IN_BIT_AUX_POWER, 5000);  /* uS */
885         }
886
887         return 0;
888 }
889
890 static int iwl3945_rx_init(struct iwl_priv *priv, struct iwl_rx_queue *rxq)
891 {
892         iwl_write_direct32(priv, FH39_RCSR_RBD_BASE(0), rxq->dma_addr);
893         iwl_write_direct32(priv, FH39_RCSR_RPTR_ADDR(0), rxq->rb_stts_dma);
894         iwl_write_direct32(priv, FH39_RCSR_WPTR(0), 0);
895         iwl_write_direct32(priv, FH39_RCSR_CONFIG(0),
896                 FH39_RCSR_RX_CONFIG_REG_VAL_DMA_CHNL_EN_ENABLE |
897                 FH39_RCSR_RX_CONFIG_REG_VAL_RDRBD_EN_ENABLE |
898                 FH39_RCSR_RX_CONFIG_REG_BIT_WR_STTS_EN |
899                 FH39_RCSR_RX_CONFIG_REG_VAL_MAX_FRAG_SIZE_128 |
900                 (RX_QUEUE_SIZE_LOG << FH39_RCSR_RX_CONFIG_REG_POS_RBDC_SIZE) |
901                 FH39_RCSR_RX_CONFIG_REG_VAL_IRQ_DEST_INT_HOST |
902                 (1 << FH39_RCSR_RX_CONFIG_REG_POS_IRQ_RBTH) |
903                 FH39_RCSR_RX_CONFIG_REG_VAL_MSG_MODE_FH);
904
905         /* fake read to flush all prev I/O */
906         iwl_read_direct32(priv, FH39_RSSR_CTRL);
907
908         return 0;
909 }
910
911 static int iwl3945_tx_reset(struct iwl_priv *priv)
912 {
913
914         /* bypass mode */
915         iwl_write_prph(priv, ALM_SCD_MODE_REG, 0x2);
916
917         /* RA 0 is active */
918         iwl_write_prph(priv, ALM_SCD_ARASTAT_REG, 0x01);
919
920         /* all 6 fifo are active */
921         iwl_write_prph(priv, ALM_SCD_TXFACT_REG, 0x3f);
922
923         iwl_write_prph(priv, ALM_SCD_SBYP_MODE_1_REG, 0x010000);
924         iwl_write_prph(priv, ALM_SCD_SBYP_MODE_2_REG, 0x030002);
925         iwl_write_prph(priv, ALM_SCD_TXF4MF_REG, 0x000004);
926         iwl_write_prph(priv, ALM_SCD_TXF5MF_REG, 0x000005);
927
928         iwl_write_direct32(priv, FH39_TSSR_CBB_BASE,
929                              priv->shared_phys);
930
931         iwl_write_direct32(priv, FH39_TSSR_MSG_CONFIG,
932                 FH39_TSSR_TX_MSG_CONFIG_REG_VAL_SNOOP_RD_TXPD_ON |
933                 FH39_TSSR_TX_MSG_CONFIG_REG_VAL_ORDER_RD_TXPD_ON |
934                 FH39_TSSR_TX_MSG_CONFIG_REG_VAL_MAX_FRAG_SIZE_128B |
935                 FH39_TSSR_TX_MSG_CONFIG_REG_VAL_SNOOP_RD_TFD_ON |
936                 FH39_TSSR_TX_MSG_CONFIG_REG_VAL_ORDER_RD_CBB_ON |
937                 FH39_TSSR_TX_MSG_CONFIG_REG_VAL_ORDER_RSP_WAIT_TH |
938                 FH39_TSSR_TX_MSG_CONFIG_REG_VAL_RSP_WAIT_TH);
939
940
941         return 0;
942 }
943
944 /**
945  * iwl3945_txq_ctx_reset - Reset TX queue context
946  *
947  * Destroys all DMA structures and initialize them again
948  */
949 static int iwl3945_txq_ctx_reset(struct iwl_priv *priv)
950 {
951         int rc;
952         int txq_id, slots_num;
953
954         iwl3945_hw_txq_ctx_free(priv);
955
956         /* allocate tx queue structure */
957         rc = iwl_alloc_txq_mem(priv);
958         if (rc)
959                 return rc;
960
961         /* Tx CMD queue */
962         rc = iwl3945_tx_reset(priv);
963         if (rc)
964                 goto error;
965
966         /* Tx queue(s) */
967         for (txq_id = 0; txq_id < priv->hw_params.max_txq_num; txq_id++) {
968                 slots_num = (txq_id == IWL_CMD_QUEUE_NUM) ?
969                                 TFD_CMD_SLOTS : TFD_TX_CMD_SLOTS;
970                 rc = iwl_tx_queue_init(priv, &priv->txq[txq_id], slots_num,
971                                        txq_id);
972                 if (rc) {
973                         IWL_ERR(priv, "Tx %d queue init failed\n", txq_id);
974                         goto error;
975                 }
976         }
977
978         return rc;
979
980  error:
981         iwl3945_hw_txq_ctx_free(priv);
982         return rc;
983 }
984
985 /*
986  * Start up NIC's basic functionality after it has been reset
987  * (e.g. after platform boot, or shutdown via iwl3945_apm_stop())
988  * NOTE:  This does not load uCode nor start the embedded processor
989  */
990 static int iwl3945_apm_init(struct iwl_priv *priv)
991 {
992         int ret;
993
994         /* Configure chip clock phase-lock-loop */
995         iwl_set_bit(priv, CSR_ANA_PLL_CFG, CSR39_ANA_PLL_CFG_VAL);
996
997         /*
998          * Disable L0S exit timer (platform NMI Work/Around)
999          * (does this do anything on 3945, or just 4965 and beyond?)
1000          */
1001         iwl_set_bit(priv, CSR_GIO_CHICKEN_BITS,
1002                           CSR_GIO_CHICKEN_BITS_REG_BIT_DIS_L0S_EXIT_TIMER);
1003
1004         /* Disable L0s without affecting L1; don't wait for ICH (L0s bug W/A) */
1005         iwl_set_bit(priv, CSR_GIO_CHICKEN_BITS,
1006                           CSR_GIO_CHICKEN_BITS_REG_BIT_L1A_NO_L0S_RX);
1007
1008         /* Set FH wait threshold to maximum (HW error during stress W/A) */
1009         iwl_set_bit(priv, CSR_DBG_HPET_MEM_REG, CSR_DBG_HPET_MEM_REG_VAL);
1010
1011         /*
1012          * Set "initialization complete" bit to move adapter from
1013          * D0U* --> D0A* (powered-up active) state.
1014          */
1015         iwl_set_bit(priv, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
1016
1017         /*
1018          * Wait for clock stabilization; once stabilized, access to
1019          * device-internal resources is supported, e.g. iwl_write_prph()
1020          * and accesses to uCode SRAM.
1021          */
1022         ret = iwl_poll_bit(priv, CSR_GP_CNTRL,
1023                         CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
1024                         CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY, 25000);
1025         if (ret < 0) {
1026                 IWL_DEBUG_INFO(priv, "Failed to init the card\n");
1027                 goto out;
1028         }
1029
1030         /* Enable DMA and BSM clocks, wait for them to stabilize */
1031         iwl_write_prph(priv, APMG_CLK_CTRL_REG, APMG_CLK_VAL_DMA_CLK_RQT |
1032                                                 APMG_CLK_VAL_BSM_CLK_RQT);
1033         udelay(20);
1034
1035         /* Clear APMG (NIC's internal power management) interrupts */
1036         iwl_write_prph(priv, APMG_RTC_INT_MSK_REG, 0x0);
1037         iwl_write_prph(priv, APMG_RTC_INT_STT_REG, 0xFFFFFFFF);
1038
1039         /* Reset radio chip */
1040         iwl_set_bits_prph(priv, APMG_PS_CTRL_REG, APMG_PS_CTRL_VAL_RESET_REQ);
1041         udelay(5);
1042         iwl_clear_bits_prph(priv, APMG_PS_CTRL_REG, APMG_PS_CTRL_VAL_RESET_REQ);
1043
1044         /* Disable L1-Active */
1045         iwl_set_bits_prph(priv, APMG_PCIDEV_STT_REG,
1046                           APMG_PCIDEV_STT_VAL_L1_ACT_DIS);
1047
1048 out:
1049         return ret;
1050 }
1051
1052 static void iwl3945_nic_config(struct iwl_priv *priv)
1053 {
1054         struct iwl3945_eeprom *eeprom = (struct iwl3945_eeprom *)priv->eeprom;
1055         unsigned long flags;
1056         u8 rev_id = 0;
1057
1058         spin_lock_irqsave(&priv->lock, flags);
1059
1060         /* Determine HW type */
1061         pci_read_config_byte(priv->pci_dev, PCI_REVISION_ID, &rev_id);
1062
1063         IWL_DEBUG_INFO(priv, "HW Revision ID = 0x%X\n", rev_id);
1064
1065         if (rev_id & PCI_CFG_REV_ID_BIT_RTP)
1066                 IWL_DEBUG_INFO(priv, "RTP type \n");
1067         else if (rev_id & PCI_CFG_REV_ID_BIT_BASIC_SKU) {
1068                 IWL_DEBUG_INFO(priv, "3945 RADIO-MB type\n");
1069                 iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
1070                             CSR39_HW_IF_CONFIG_REG_BIT_3945_MB);
1071         } else {
1072                 IWL_DEBUG_INFO(priv, "3945 RADIO-MM type\n");
1073                 iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
1074                             CSR39_HW_IF_CONFIG_REG_BIT_3945_MM);
1075         }
1076
1077         if (EEPROM_SKU_CAP_OP_MODE_MRC == eeprom->sku_cap) {
1078                 IWL_DEBUG_INFO(priv, "SKU OP mode is mrc\n");
1079                 iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
1080                             CSR39_HW_IF_CONFIG_REG_BIT_SKU_MRC);
1081         } else
1082                 IWL_DEBUG_INFO(priv, "SKU OP mode is basic\n");
1083
1084         if ((eeprom->board_revision & 0xF0) == 0xD0) {
1085                 IWL_DEBUG_INFO(priv, "3945ABG revision is 0x%X\n",
1086                                eeprom->board_revision);
1087                 iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
1088                             CSR39_HW_IF_CONFIG_REG_BIT_BOARD_TYPE);
1089         } else {
1090                 IWL_DEBUG_INFO(priv, "3945ABG revision is 0x%X\n",
1091                                eeprom->board_revision);
1092                 iwl_clear_bit(priv, CSR_HW_IF_CONFIG_REG,
1093                               CSR39_HW_IF_CONFIG_REG_BIT_BOARD_TYPE);
1094         }
1095
1096         if (eeprom->almgor_m_version <= 1) {
1097                 iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
1098                             CSR39_HW_IF_CONFIG_REG_BITS_SILICON_TYPE_A);
1099                 IWL_DEBUG_INFO(priv, "Card M type A version is 0x%X\n",
1100                                eeprom->almgor_m_version);
1101         } else {
1102                 IWL_DEBUG_INFO(priv, "Card M type B version is 0x%X\n",
1103                                eeprom->almgor_m_version);
1104                 iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
1105                             CSR39_HW_IF_CONFIG_REG_BITS_SILICON_TYPE_B);
1106         }
1107         spin_unlock_irqrestore(&priv->lock, flags);
1108
1109         if (eeprom->sku_cap & EEPROM_SKU_CAP_SW_RF_KILL_ENABLE)
1110                 IWL_DEBUG_RF_KILL(priv, "SW RF KILL supported in EEPROM.\n");
1111
1112         if (eeprom->sku_cap & EEPROM_SKU_CAP_HW_RF_KILL_ENABLE)
1113                 IWL_DEBUG_RF_KILL(priv, "HW RF KILL supported in EEPROM.\n");
1114 }
1115
1116 int iwl3945_hw_nic_init(struct iwl_priv *priv)
1117 {
1118         int rc;
1119         unsigned long flags;
1120         struct iwl_rx_queue *rxq = &priv->rxq;
1121
1122         spin_lock_irqsave(&priv->lock, flags);
1123         priv->cfg->ops->lib->apm_ops.init(priv);
1124         spin_unlock_irqrestore(&priv->lock, flags);
1125
1126         rc = priv->cfg->ops->lib->apm_ops.set_pwr_src(priv, IWL_PWR_SRC_VMAIN);
1127         if (rc)
1128                 return rc;
1129
1130         priv->cfg->ops->lib->apm_ops.config(priv);
1131
1132         /* Allocate the RX queue, or reset if it is already allocated */
1133         if (!rxq->bd) {
1134                 rc = iwl_rx_queue_alloc(priv);
1135                 if (rc) {
1136                         IWL_ERR(priv, "Unable to initialize Rx queue\n");
1137                         return -ENOMEM;
1138                 }
1139         } else
1140                 iwl3945_rx_queue_reset(priv, rxq);
1141
1142         iwl3945_rx_replenish(priv);
1143
1144         iwl3945_rx_init(priv, rxq);
1145
1146
1147         /* Look at using this instead:
1148         rxq->need_update = 1;
1149         iwl_rx_queue_update_write_ptr(priv, rxq);
1150         */
1151
1152         iwl_write_direct32(priv, FH39_RCSR_WPTR(0), rxq->write & ~7);
1153
1154         rc = iwl3945_txq_ctx_reset(priv);
1155         if (rc)
1156                 return rc;
1157
1158         set_bit(STATUS_INIT, &priv->status);
1159
1160         return 0;
1161 }
1162
1163 /**
1164  * iwl3945_hw_txq_ctx_free - Free TXQ Context
1165  *
1166  * Destroy all TX DMA queues and structures
1167  */
1168 void iwl3945_hw_txq_ctx_free(struct iwl_priv *priv)
1169 {
1170         int txq_id;
1171
1172         /* Tx queues */
1173         if (priv->txq)
1174                 for (txq_id = 0; txq_id < priv->hw_params.max_txq_num;
1175                      txq_id++)
1176                         if (txq_id == IWL_CMD_QUEUE_NUM)
1177                                 iwl_cmd_queue_free(priv);
1178                         else
1179                                 iwl_tx_queue_free(priv, txq_id);
1180
1181         /* free tx queue structure */
1182         iwl_free_txq_mem(priv);
1183 }
1184
1185 void iwl3945_hw_txq_ctx_stop(struct iwl_priv *priv)
1186 {
1187         int txq_id;
1188
1189         /* stop SCD */
1190         iwl_write_prph(priv, ALM_SCD_MODE_REG, 0);
1191
1192         /* reset TFD queues */
1193         for (txq_id = 0; txq_id < priv->hw_params.max_txq_num; txq_id++) {
1194                 iwl_write_direct32(priv, FH39_TCSR_CONFIG(txq_id), 0x0);
1195                 iwl_poll_direct_bit(priv, FH39_TSSR_TX_STATUS,
1196                                 FH39_TSSR_TX_STATUS_REG_MSK_CHNL_IDLE(txq_id),
1197                                 1000);
1198         }
1199
1200         iwl3945_hw_txq_ctx_free(priv);
1201 }
1202
1203 /**
1204  * iwl3945_hw_reg_adjust_power_by_temp
1205  * return index delta into power gain settings table
1206 */
1207 static int iwl3945_hw_reg_adjust_power_by_temp(int new_reading, int old_reading)
1208 {
1209         return (new_reading - old_reading) * (-11) / 100;
1210 }
1211
1212 /**
1213  * iwl3945_hw_reg_temp_out_of_range - Keep temperature in sane range
1214  */
1215 static inline int iwl3945_hw_reg_temp_out_of_range(int temperature)
1216 {
1217         return ((temperature < -260) || (temperature > 25)) ? 1 : 0;
1218 }
1219
1220 int iwl3945_hw_get_temperature(struct iwl_priv *priv)
1221 {
1222         return iwl_read32(priv, CSR_UCODE_DRV_GP2);
1223 }
1224
1225 /**
1226  * iwl3945_hw_reg_txpower_get_temperature
1227  * get the current temperature by reading from NIC
1228 */
1229 static int iwl3945_hw_reg_txpower_get_temperature(struct iwl_priv *priv)
1230 {
1231         struct iwl3945_eeprom *eeprom = (struct iwl3945_eeprom *)priv->eeprom;
1232         int temperature;
1233
1234         temperature = iwl3945_hw_get_temperature(priv);
1235
1236         /* driver's okay range is -260 to +25.
1237          *   human readable okay range is 0 to +285 */
1238         IWL_DEBUG_INFO(priv, "Temperature: %d\n", temperature + IWL_TEMP_CONVERT);
1239
1240         /* handle insane temp reading */
1241         if (iwl3945_hw_reg_temp_out_of_range(temperature)) {
1242                 IWL_ERR(priv, "Error bad temperature value  %d\n", temperature);
1243
1244                 /* if really really hot(?),
1245                  *   substitute the 3rd band/group's temp measured at factory */
1246                 if (priv->last_temperature > 100)
1247                         temperature = eeprom->groups[2].temperature;
1248                 else /* else use most recent "sane" value from driver */
1249                         temperature = priv->last_temperature;
1250         }
1251
1252         return temperature;     /* raw, not "human readable" */
1253 }
1254
1255 /* Adjust Txpower only if temperature variance is greater than threshold.
1256  *
1257  * Both are lower than older versions' 9 degrees */
1258 #define IWL_TEMPERATURE_LIMIT_TIMER   6
1259
1260 /**
1261  * is_temp_calib_needed - determines if new calibration is needed
1262  *
1263  * records new temperature in tx_mgr->temperature.
1264  * replaces tx_mgr->last_temperature *only* if calib needed
1265  *    (assumes caller will actually do the calibration!). */
1266 static int is_temp_calib_needed(struct iwl_priv *priv)
1267 {
1268         int temp_diff;
1269
1270         priv->temperature = iwl3945_hw_reg_txpower_get_temperature(priv);
1271         temp_diff = priv->temperature - priv->last_temperature;
1272
1273         /* get absolute value */
1274         if (temp_diff < 0) {
1275                 IWL_DEBUG_POWER(priv, "Getting cooler, delta %d,\n", temp_diff);
1276                 temp_diff = -temp_diff;
1277         } else if (temp_diff == 0)
1278                 IWL_DEBUG_POWER(priv, "Same temp,\n");
1279         else
1280                 IWL_DEBUG_POWER(priv, "Getting warmer, delta %d,\n", temp_diff);
1281
1282         /* if we don't need calibration, *don't* update last_temperature */
1283         if (temp_diff < IWL_TEMPERATURE_LIMIT_TIMER) {
1284                 IWL_DEBUG_POWER(priv, "Timed thermal calib not needed\n");
1285                 return 0;
1286         }
1287
1288         IWL_DEBUG_POWER(priv, "Timed thermal calib needed\n");
1289
1290         /* assume that caller will actually do calib ...
1291          *   update the "last temperature" value */
1292         priv->last_temperature = priv->temperature;
1293         return 1;
1294 }
1295
1296 #define IWL_MAX_GAIN_ENTRIES 78
1297 #define IWL_CCK_FROM_OFDM_POWER_DIFF  -5
1298 #define IWL_CCK_FROM_OFDM_INDEX_DIFF (10)
1299
1300 /* radio and DSP power table, each step is 1/2 dB.
1301  * 1st number is for RF analog gain, 2nd number is for DSP pre-DAC gain. */
1302 static struct iwl3945_tx_power power_gain_table[2][IWL_MAX_GAIN_ENTRIES] = {
1303         {
1304          {251, 127},            /* 2.4 GHz, highest power */
1305          {251, 127},
1306          {251, 127},
1307          {251, 127},
1308          {251, 125},
1309          {251, 110},
1310          {251, 105},
1311          {251, 98},
1312          {187, 125},
1313          {187, 115},
1314          {187, 108},
1315          {187, 99},
1316          {243, 119},
1317          {243, 111},
1318          {243, 105},
1319          {243, 97},
1320          {243, 92},
1321          {211, 106},
1322          {211, 100},
1323          {179, 120},
1324          {179, 113},
1325          {179, 107},
1326          {147, 125},
1327          {147, 119},
1328          {147, 112},
1329          {147, 106},
1330          {147, 101},
1331          {147, 97},
1332          {147, 91},
1333          {115, 107},
1334          {235, 121},
1335          {235, 115},
1336          {235, 109},
1337          {203, 127},
1338          {203, 121},
1339          {203, 115},
1340          {203, 108},
1341          {203, 102},
1342          {203, 96},
1343          {203, 92},
1344          {171, 110},
1345          {171, 104},
1346          {171, 98},
1347          {139, 116},
1348          {227, 125},
1349          {227, 119},
1350          {227, 113},
1351          {227, 107},
1352          {227, 101},
1353          {227, 96},
1354          {195, 113},
1355          {195, 106},
1356          {195, 102},
1357          {195, 95},
1358          {163, 113},
1359          {163, 106},
1360          {163, 102},
1361          {163, 95},
1362          {131, 113},
1363          {131, 106},
1364          {131, 102},
1365          {131, 95},
1366          {99, 113},
1367          {99, 106},
1368          {99, 102},
1369          {99, 95},
1370          {67, 113},
1371          {67, 106},
1372          {67, 102},
1373          {67, 95},
1374          {35, 113},
1375          {35, 106},
1376          {35, 102},
1377          {35, 95},
1378          {3, 113},
1379          {3, 106},
1380          {3, 102},
1381          {3, 95} },             /* 2.4 GHz, lowest power */
1382         {
1383          {251, 127},            /* 5.x GHz, highest power */
1384          {251, 120},
1385          {251, 114},
1386          {219, 119},
1387          {219, 101},
1388          {187, 113},
1389          {187, 102},
1390          {155, 114},
1391          {155, 103},
1392          {123, 117},
1393          {123, 107},
1394          {123, 99},
1395          {123, 92},
1396          {91, 108},
1397          {59, 125},
1398          {59, 118},
1399          {59, 109},
1400          {59, 102},
1401          {59, 96},
1402          {59, 90},
1403          {27, 104},
1404          {27, 98},
1405          {27, 92},
1406          {115, 118},
1407          {115, 111},
1408          {115, 104},
1409          {83, 126},
1410          {83, 121},
1411          {83, 113},
1412          {83, 105},
1413          {83, 99},
1414          {51, 118},
1415          {51, 111},
1416          {51, 104},
1417          {51, 98},
1418          {19, 116},
1419          {19, 109},
1420          {19, 102},
1421          {19, 98},
1422          {19, 93},
1423          {171, 113},
1424          {171, 107},
1425          {171, 99},
1426          {139, 120},
1427          {139, 113},
1428          {139, 107},
1429          {139, 99},
1430          {107, 120},
1431          {107, 113},
1432          {107, 107},
1433          {107, 99},
1434          {75, 120},
1435          {75, 113},
1436          {75, 107},
1437          {75, 99},
1438          {43, 120},
1439          {43, 113},
1440          {43, 107},
1441          {43, 99},
1442          {11, 120},
1443          {11, 113},
1444          {11, 107},
1445          {11, 99},
1446          {131, 107},
1447          {131, 99},
1448          {99, 120},
1449          {99, 113},
1450          {99, 107},
1451          {99, 99},
1452          {67, 120},
1453          {67, 113},
1454          {67, 107},
1455          {67, 99},
1456          {35, 120},
1457          {35, 113},
1458          {35, 107},
1459          {35, 99},
1460          {3, 120} }             /* 5.x GHz, lowest power */
1461 };
1462
1463 static inline u8 iwl3945_hw_reg_fix_power_index(int index)
1464 {
1465         if (index < 0)
1466                 return 0;
1467         if (index >= IWL_MAX_GAIN_ENTRIES)
1468                 return IWL_MAX_GAIN_ENTRIES - 1;
1469         return (u8) index;
1470 }
1471
1472 /* Kick off thermal recalibration check every 60 seconds */
1473 #define REG_RECALIB_PERIOD (60)
1474
1475 /**
1476  * iwl3945_hw_reg_set_scan_power - Set Tx power for scan probe requests
1477  *
1478  * Set (in our channel info database) the direct scan Tx power for 1 Mbit (CCK)
1479  * or 6 Mbit (OFDM) rates.
1480  */
1481 static void iwl3945_hw_reg_set_scan_power(struct iwl_priv *priv, u32 scan_tbl_index,
1482                                s32 rate_index, const s8 *clip_pwrs,
1483                                struct iwl_channel_info *ch_info,
1484                                int band_index)
1485 {
1486         struct iwl3945_scan_power_info *scan_power_info;
1487         s8 power;
1488         u8 power_index;
1489
1490         scan_power_info = &ch_info->scan_pwr_info[scan_tbl_index];
1491
1492         /* use this channel group's 6Mbit clipping/saturation pwr,
1493          *   but cap at regulatory scan power restriction (set during init
1494          *   based on eeprom channel data) for this channel.  */
1495         power = min(ch_info->scan_power, clip_pwrs[IWL_RATE_6M_INDEX_TABLE]);
1496
1497         /* further limit to user's max power preference.
1498          * FIXME:  Other spectrum management power limitations do not
1499          *   seem to apply?? */
1500         power = min(power, priv->tx_power_user_lmt);
1501         scan_power_info->requested_power = power;
1502
1503         /* find difference between new scan *power* and current "normal"
1504          *   Tx *power* for 6Mb.  Use this difference (x2) to adjust the
1505          *   current "normal" temperature-compensated Tx power *index* for
1506          *   this rate (1Mb or 6Mb) to yield new temp-compensated scan power
1507          *   *index*. */
1508         power_index = ch_info->power_info[rate_index].power_table_index
1509             - (power - ch_info->power_info
1510                [IWL_RATE_6M_INDEX_TABLE].requested_power) * 2;
1511
1512         /* store reference index that we use when adjusting *all* scan
1513          *   powers.  So we can accommodate user (all channel) or spectrum
1514          *   management (single channel) power changes "between" temperature
1515          *   feedback compensation procedures.
1516          * don't force fit this reference index into gain table; it may be a
1517          *   negative number.  This will help avoid errors when we're at
1518          *   the lower bounds (highest gains, for warmest temperatures)
1519          *   of the table. */
1520
1521         /* don't exceed table bounds for "real" setting */
1522         power_index = iwl3945_hw_reg_fix_power_index(power_index);
1523
1524         scan_power_info->power_table_index = power_index;
1525         scan_power_info->tpc.tx_gain =
1526             power_gain_table[band_index][power_index].tx_gain;
1527         scan_power_info->tpc.dsp_atten =
1528             power_gain_table[band_index][power_index].dsp_atten;
1529 }
1530
1531 /**
1532  * iwl3945_send_tx_power - fill in Tx Power command with gain settings
1533  *
1534  * Configures power settings for all rates for the current channel,
1535  * using values from channel info struct, and send to NIC
1536  */
1537 static int iwl3945_send_tx_power(struct iwl_priv *priv)
1538 {
1539         int rate_idx, i;
1540         const struct iwl_channel_info *ch_info = NULL;
1541         struct iwl3945_txpowertable_cmd txpower = {
1542                 .channel = priv->active_rxon.channel,
1543         };
1544
1545         txpower.band = (priv->band == IEEE80211_BAND_5GHZ) ? 0 : 1;
1546         ch_info = iwl_get_channel_info(priv,
1547                                        priv->band,
1548                                        le16_to_cpu(priv->active_rxon.channel));
1549         if (!ch_info) {
1550                 IWL_ERR(priv,
1551                         "Failed to get channel info for channel %d [%d]\n",
1552                         le16_to_cpu(priv->active_rxon.channel), priv->band);
1553                 return -EINVAL;
1554         }
1555
1556         if (!is_channel_valid(ch_info)) {
1557                 IWL_DEBUG_POWER(priv, "Not calling TX_PWR_TABLE_CMD on "
1558                                 "non-Tx channel.\n");
1559                 return 0;
1560         }
1561
1562         /* fill cmd with power settings for all rates for current channel */
1563         /* Fill OFDM rate */
1564         for (rate_idx = IWL_FIRST_OFDM_RATE, i = 0;
1565              rate_idx <= IWL39_LAST_OFDM_RATE; rate_idx++, i++) {
1566
1567                 txpower.power[i].tpc = ch_info->power_info[i].tpc;
1568                 txpower.power[i].rate = iwl3945_rates[rate_idx].plcp;
1569
1570                 IWL_DEBUG_POWER(priv, "ch %d:%d rf %d dsp %3d rate code 0x%02x\n",
1571                                 le16_to_cpu(txpower.channel),
1572                                 txpower.band,
1573                                 txpower.power[i].tpc.tx_gain,
1574                                 txpower.power[i].tpc.dsp_atten,
1575                                 txpower.power[i].rate);
1576         }
1577         /* Fill CCK rates */
1578         for (rate_idx = IWL_FIRST_CCK_RATE;
1579              rate_idx <= IWL_LAST_CCK_RATE; rate_idx++, i++) {
1580                 txpower.power[i].tpc = ch_info->power_info[i].tpc;
1581                 txpower.power[i].rate = iwl3945_rates[rate_idx].plcp;
1582
1583                 IWL_DEBUG_POWER(priv, "ch %d:%d rf %d dsp %3d rate code 0x%02x\n",
1584                                 le16_to_cpu(txpower.channel),
1585                                 txpower.band,
1586                                 txpower.power[i].tpc.tx_gain,
1587                                 txpower.power[i].tpc.dsp_atten,
1588                                 txpower.power[i].rate);
1589         }
1590
1591         return iwl_send_cmd_pdu(priv, REPLY_TX_PWR_TABLE_CMD,
1592                                 sizeof(struct iwl3945_txpowertable_cmd),
1593                                 &txpower);
1594
1595 }
1596
1597 /**
1598  * iwl3945_hw_reg_set_new_power - Configures power tables at new levels
1599  * @ch_info: Channel to update.  Uses power_info.requested_power.
1600  *
1601  * Replace requested_power and base_power_index ch_info fields for
1602  * one channel.
1603  *
1604  * Called if user or spectrum management changes power preferences.
1605  * Takes into account h/w and modulation limitations (clip power).
1606  *
1607  * This does *not* send anything to NIC, just sets up ch_info for one channel.
1608  *
1609  * NOTE: reg_compensate_for_temperature_dif() *must* be run after this to
1610  *       properly fill out the scan powers, and actual h/w gain settings,
1611  *       and send changes to NIC
1612  */
1613 static int iwl3945_hw_reg_set_new_power(struct iwl_priv *priv,
1614                              struct iwl_channel_info *ch_info)
1615 {
1616         struct iwl3945_channel_power_info *power_info;
1617         int power_changed = 0;
1618         int i;
1619         const s8 *clip_pwrs;
1620         int power;
1621
1622         /* Get this chnlgrp's rate-to-max/clip-powers table */
1623         clip_pwrs = priv->clip39_groups[ch_info->group_index].clip_powers;
1624
1625         /* Get this channel's rate-to-current-power settings table */
1626         power_info = ch_info->power_info;
1627
1628         /* update OFDM Txpower settings */
1629         for (i = IWL_RATE_6M_INDEX_TABLE; i <= IWL_RATE_54M_INDEX_TABLE;
1630              i++, ++power_info) {
1631                 int delta_idx;
1632
1633                 /* limit new power to be no more than h/w capability */
1634                 power = min(ch_info->curr_txpow, clip_pwrs[i]);
1635                 if (power == power_info->requested_power)
1636                         continue;
1637
1638                 /* find difference between old and new requested powers,
1639                  *    update base (non-temp-compensated) power index */
1640                 delta_idx = (power - power_info->requested_power) * 2;
1641                 power_info->base_power_index -= delta_idx;
1642
1643                 /* save new requested power value */
1644                 power_info->requested_power = power;
1645
1646                 power_changed = 1;
1647         }
1648
1649         /* update CCK Txpower settings, based on OFDM 12M setting ...
1650          *    ... all CCK power settings for a given channel are the *same*. */
1651         if (power_changed) {
1652                 power =
1653                     ch_info->power_info[IWL_RATE_12M_INDEX_TABLE].
1654                     requested_power + IWL_CCK_FROM_OFDM_POWER_DIFF;
1655
1656                 /* do all CCK rates' iwl3945_channel_power_info structures */
1657                 for (i = IWL_RATE_1M_INDEX_TABLE; i <= IWL_RATE_11M_INDEX_TABLE; i++) {
1658                         power_info->requested_power = power;
1659                         power_info->base_power_index =
1660                             ch_info->power_info[IWL_RATE_12M_INDEX_TABLE].
1661                             base_power_index + IWL_CCK_FROM_OFDM_INDEX_DIFF;
1662                         ++power_info;
1663                 }
1664         }
1665
1666         return 0;
1667 }
1668
1669 /**
1670  * iwl3945_hw_reg_get_ch_txpower_limit - returns new power limit for channel
1671  *
1672  * NOTE: Returned power limit may be less (but not more) than requested,
1673  *       based strictly on regulatory (eeprom and spectrum mgt) limitations
1674  *       (no consideration for h/w clipping limitations).
1675  */
1676 static int iwl3945_hw_reg_get_ch_txpower_limit(struct iwl_channel_info *ch_info)
1677 {
1678         s8 max_power;
1679
1680 #if 0
1681         /* if we're using TGd limits, use lower of TGd or EEPROM */
1682         if (ch_info->tgd_data.max_power != 0)
1683                 max_power = min(ch_info->tgd_data.max_power,
1684                                 ch_info->eeprom.max_power_avg);
1685
1686         /* else just use EEPROM limits */
1687         else
1688 #endif
1689                 max_power = ch_info->eeprom.max_power_avg;
1690
1691         return min(max_power, ch_info->max_power_avg);
1692 }
1693
1694 /**
1695  * iwl3945_hw_reg_comp_txpower_temp - Compensate for temperature
1696  *
1697  * Compensate txpower settings of *all* channels for temperature.
1698  * This only accounts for the difference between current temperature
1699  *   and the factory calibration temperatures, and bases the new settings
1700  *   on the channel's base_power_index.
1701  *
1702  * If RxOn is "associated", this sends the new Txpower to NIC!
1703  */
1704 static int iwl3945_hw_reg_comp_txpower_temp(struct iwl_priv *priv)
1705 {
1706         struct iwl_channel_info *ch_info = NULL;
1707         struct iwl3945_eeprom *eeprom = (struct iwl3945_eeprom *)priv->eeprom;
1708         int delta_index;
1709         const s8 *clip_pwrs; /* array of h/w max power levels for each rate */
1710         u8 a_band;
1711         u8 rate_index;
1712         u8 scan_tbl_index;
1713         u8 i;
1714         int ref_temp;
1715         int temperature = priv->temperature;
1716
1717         /* set up new Tx power info for each and every channel, 2.4 and 5.x */
1718         for (i = 0; i < priv->channel_count; i++) {
1719                 ch_info = &priv->channel_info[i];
1720                 a_band = is_channel_a_band(ch_info);
1721
1722                 /* Get this chnlgrp's factory calibration temperature */
1723                 ref_temp = (s16)eeprom->groups[ch_info->group_index].
1724                     temperature;
1725
1726                 /* get power index adjustment based on current and factory
1727                  * temps */
1728                 delta_index = iwl3945_hw_reg_adjust_power_by_temp(temperature,
1729                                                               ref_temp);
1730
1731                 /* set tx power value for all rates, OFDM and CCK */
1732                 for (rate_index = 0; rate_index < IWL_RATE_COUNT;
1733                      rate_index++) {
1734                         int power_idx =
1735                             ch_info->power_info[rate_index].base_power_index;
1736
1737                         /* temperature compensate */
1738                         power_idx += delta_index;
1739
1740                         /* stay within table range */
1741                         power_idx = iwl3945_hw_reg_fix_power_index(power_idx);
1742                         ch_info->power_info[rate_index].
1743                             power_table_index = (u8) power_idx;
1744                         ch_info->power_info[rate_index].tpc =
1745                             power_gain_table[a_band][power_idx];
1746                 }
1747
1748                 /* Get this chnlgrp's rate-to-max/clip-powers table */
1749                 clip_pwrs = priv->clip39_groups[ch_info->group_index].clip_powers;
1750
1751                 /* set scan tx power, 1Mbit for CCK, 6Mbit for OFDM */
1752                 for (scan_tbl_index = 0;
1753                      scan_tbl_index < IWL_NUM_SCAN_RATES; scan_tbl_index++) {
1754                         s32 actual_index = (scan_tbl_index == 0) ?
1755                             IWL_RATE_1M_INDEX_TABLE : IWL_RATE_6M_INDEX_TABLE;
1756                         iwl3945_hw_reg_set_scan_power(priv, scan_tbl_index,
1757                                            actual_index, clip_pwrs,
1758                                            ch_info, a_band);
1759                 }
1760         }
1761
1762         /* send Txpower command for current channel to ucode */
1763         return priv->cfg->ops->lib->send_tx_power(priv);
1764 }
1765
1766 int iwl3945_hw_reg_set_txpower(struct iwl_priv *priv, s8 power)
1767 {
1768         struct iwl_channel_info *ch_info;
1769         s8 max_power;
1770         u8 a_band;
1771         u8 i;
1772
1773         if (priv->tx_power_user_lmt == power) {
1774                 IWL_DEBUG_POWER(priv, "Requested Tx power same as current "
1775                                 "limit: %ddBm.\n", power);
1776                 return 0;
1777         }
1778
1779         IWL_DEBUG_POWER(priv, "Setting upper limit clamp to %ddBm.\n", power);
1780         priv->tx_power_user_lmt = power;
1781
1782         /* set up new Tx powers for each and every channel, 2.4 and 5.x */
1783
1784         for (i = 0; i < priv->channel_count; i++) {
1785                 ch_info = &priv->channel_info[i];
1786                 a_band = is_channel_a_band(ch_info);
1787
1788                 /* find minimum power of all user and regulatory constraints
1789                  *    (does not consider h/w clipping limitations) */
1790                 max_power = iwl3945_hw_reg_get_ch_txpower_limit(ch_info);
1791                 max_power = min(power, max_power);
1792                 if (max_power != ch_info->curr_txpow) {
1793                         ch_info->curr_txpow = max_power;
1794
1795                         /* this considers the h/w clipping limitations */
1796                         iwl3945_hw_reg_set_new_power(priv, ch_info);
1797                 }
1798         }
1799
1800         /* update txpower settings for all channels,
1801          *   send to NIC if associated. */
1802         is_temp_calib_needed(priv);
1803         iwl3945_hw_reg_comp_txpower_temp(priv);
1804
1805         return 0;
1806 }
1807
1808 static int iwl3945_send_rxon_assoc(struct iwl_priv *priv)
1809 {
1810         int rc = 0;
1811         struct iwl_rx_packet *res = NULL;
1812         struct iwl3945_rxon_assoc_cmd rxon_assoc;
1813         struct iwl_host_cmd cmd = {
1814                 .id = REPLY_RXON_ASSOC,
1815                 .len = sizeof(rxon_assoc),
1816                 .flags = CMD_WANT_SKB,
1817                 .data = &rxon_assoc,
1818         };
1819         const struct iwl_rxon_cmd *rxon1 = &priv->staging_rxon;
1820         const struct iwl_rxon_cmd *rxon2 = &priv->active_rxon;
1821
1822         if ((rxon1->flags == rxon2->flags) &&
1823             (rxon1->filter_flags == rxon2->filter_flags) &&
1824             (rxon1->cck_basic_rates == rxon2->cck_basic_rates) &&
1825             (rxon1->ofdm_basic_rates == rxon2->ofdm_basic_rates)) {
1826                 IWL_DEBUG_INFO(priv, "Using current RXON_ASSOC.  Not resending.\n");
1827                 return 0;
1828         }
1829
1830         rxon_assoc.flags = priv->staging_rxon.flags;
1831         rxon_assoc.filter_flags = priv->staging_rxon.filter_flags;
1832         rxon_assoc.ofdm_basic_rates = priv->staging_rxon.ofdm_basic_rates;
1833         rxon_assoc.cck_basic_rates = priv->staging_rxon.cck_basic_rates;
1834         rxon_assoc.reserved = 0;
1835
1836         rc = iwl_send_cmd_sync(priv, &cmd);
1837         if (rc)
1838                 return rc;
1839
1840         res = (struct iwl_rx_packet *)cmd.reply_skb->data;
1841         if (res->hdr.flags & IWL_CMD_FAILED_MSK) {
1842                 IWL_ERR(priv, "Bad return from REPLY_RXON_ASSOC command\n");
1843                 rc = -EIO;
1844         }
1845
1846         priv->alloc_rxb_skb--;
1847         dev_kfree_skb_any(cmd.reply_skb);
1848
1849         return rc;
1850 }
1851
1852 /**
1853  * iwl3945_commit_rxon - commit staging_rxon to hardware
1854  *
1855  * The RXON command in staging_rxon is committed to the hardware and
1856  * the active_rxon structure is updated with the new data.  This
1857  * function correctly transitions out of the RXON_ASSOC_MSK state if
1858  * a HW tune is required based on the RXON structure changes.
1859  */
1860 static int iwl3945_commit_rxon(struct iwl_priv *priv)
1861 {
1862         /* cast away the const for active_rxon in this function */
1863         struct iwl3945_rxon_cmd *active_rxon = (void *)&priv->active_rxon;
1864         struct iwl3945_rxon_cmd *staging_rxon = (void *)&priv->staging_rxon;
1865         int rc = 0;
1866         bool new_assoc =
1867                 !!(priv->staging_rxon.filter_flags & RXON_FILTER_ASSOC_MSK);
1868
1869         if (!iwl_is_alive(priv))
1870                 return -1;
1871
1872         /* always get timestamp with Rx frame */
1873         staging_rxon->flags |= RXON_FLG_TSF2HOST_MSK;
1874
1875         /* select antenna */
1876         staging_rxon->flags &=
1877             ~(RXON_FLG_DIS_DIV_MSK | RXON_FLG_ANT_SEL_MSK);
1878         staging_rxon->flags |= iwl3945_get_antenna_flags(priv);
1879
1880         rc = iwl_check_rxon_cmd(priv);
1881         if (rc) {
1882                 IWL_ERR(priv, "Invalid RXON configuration.  Not committing.\n");
1883                 return -EINVAL;
1884         }
1885
1886         /* If we don't need to send a full RXON, we can use
1887          * iwl3945_rxon_assoc_cmd which is used to reconfigure filter
1888          * and other flags for the current radio configuration. */
1889         if (!iwl_full_rxon_required(priv)) {
1890                 rc = iwl_send_rxon_assoc(priv);
1891                 if (rc) {
1892                         IWL_ERR(priv, "Error setting RXON_ASSOC "
1893                                   "configuration (%d).\n", rc);
1894                         return rc;
1895                 }
1896
1897                 memcpy(active_rxon, staging_rxon, sizeof(*active_rxon));
1898
1899                 return 0;
1900         }
1901
1902         /* If we are currently associated and the new config requires
1903          * an RXON_ASSOC and the new config wants the associated mask enabled,
1904          * we must clear the associated from the active configuration
1905          * before we apply the new config */
1906         if (iwl_is_associated(priv) && new_assoc) {
1907                 IWL_DEBUG_INFO(priv, "Toggling associated bit on current RXON\n");
1908                 active_rxon->filter_flags &= ~RXON_FILTER_ASSOC_MSK;
1909
1910                 /*
1911                  * reserved4 and 5 could have been filled by the iwlcore code.
1912                  * Let's clear them before pushing to the 3945.
1913                  */
1914                 active_rxon->reserved4 = 0;
1915                 active_rxon->reserved5 = 0;
1916                 rc = iwl_send_cmd_pdu(priv, REPLY_RXON,
1917                                       sizeof(struct iwl3945_rxon_cmd),
1918                                       &priv->active_rxon);
1919
1920                 /* If the mask clearing failed then we set
1921                  * active_rxon back to what it was previously */
1922                 if (rc) {
1923                         active_rxon->filter_flags |= RXON_FILTER_ASSOC_MSK;
1924                         IWL_ERR(priv, "Error clearing ASSOC_MSK on current "
1925                                   "configuration (%d).\n", rc);
1926                         return rc;
1927                 }
1928         }
1929
1930         IWL_DEBUG_INFO(priv, "Sending RXON\n"
1931                        "* with%s RXON_FILTER_ASSOC_MSK\n"
1932                        "* channel = %d\n"
1933                        "* bssid = %pM\n",
1934                        (new_assoc ? "" : "out"),
1935                        le16_to_cpu(staging_rxon->channel),
1936                        staging_rxon->bssid_addr);
1937
1938         /*
1939          * reserved4 and 5 could have been filled by the iwlcore code.
1940          * Let's clear them before pushing to the 3945.
1941          */
1942         staging_rxon->reserved4 = 0;
1943         staging_rxon->reserved5 = 0;
1944
1945         iwl_set_rxon_hwcrypto(priv, !iwl3945_mod_params.sw_crypto);
1946
1947         /* Apply the new configuration */
1948         rc = iwl_send_cmd_pdu(priv, REPLY_RXON,
1949                               sizeof(struct iwl3945_rxon_cmd),
1950                               staging_rxon);
1951         if (rc) {
1952                 IWL_ERR(priv, "Error setting new configuration (%d).\n", rc);
1953                 return rc;
1954         }
1955
1956         memcpy(active_rxon, staging_rxon, sizeof(*active_rxon));
1957
1958         iwl_clear_stations_table(priv);
1959
1960         /* If we issue a new RXON command which required a tune then we must
1961          * send a new TXPOWER command or we won't be able to Tx any frames */
1962         rc = priv->cfg->ops->lib->send_tx_power(priv);
1963         if (rc) {
1964                 IWL_ERR(priv, "Error setting Tx power (%d).\n", rc);
1965                 return rc;
1966         }
1967
1968         /* Add the broadcast address so we can send broadcast frames */
1969         if (iwl_add_station(priv, iwl_bcast_addr, false, CMD_SYNC, NULL) ==
1970             IWL_INVALID_STATION) {
1971                 IWL_ERR(priv, "Error adding BROADCAST address for transmit.\n");
1972                 return -EIO;
1973         }
1974
1975         /* If we have set the ASSOC_MSK and we are in BSS mode then
1976          * add the IWL_AP_ID to the station rate table */
1977         if (iwl_is_associated(priv) &&
1978             (priv->iw_mode == NL80211_IFTYPE_STATION))
1979                 if (iwl_add_station(priv, priv->active_rxon.bssid_addr,
1980                                 true, CMD_SYNC, NULL) == IWL_INVALID_STATION) {
1981                         IWL_ERR(priv, "Error adding AP address for transmit\n");
1982                         return -EIO;
1983                 }
1984
1985         /* Init the hardware's rate fallback order based on the band */
1986         rc = iwl3945_init_hw_rate_table(priv);
1987         if (rc) {
1988                 IWL_ERR(priv, "Error setting HW rate table: %02X\n", rc);
1989                 return -EIO;
1990         }
1991
1992         return 0;
1993 }
1994
1995 /* will add 3945 channel switch cmd handling later */
1996 int iwl3945_hw_channel_switch(struct iwl_priv *priv, u16 channel)
1997 {
1998         return 0;
1999 }
2000
2001 /**
2002  * iwl3945_reg_txpower_periodic -  called when time to check our temperature.
2003  *
2004  * -- reset periodic timer
2005  * -- see if temp has changed enough to warrant re-calibration ... if so:
2006  *     -- correct coeffs for temp (can reset temp timer)
2007  *     -- save this temp as "last",
2008  *     -- send new set of gain settings to NIC
2009  * NOTE:  This should continue working, even when we're not associated,
2010  *   so we can keep our internal table of scan powers current. */
2011 void iwl3945_reg_txpower_periodic(struct iwl_priv *priv)
2012 {
2013         /* This will kick in the "brute force"
2014          * iwl3945_hw_reg_comp_txpower_temp() below */
2015         if (!is_temp_calib_needed(priv))
2016                 goto reschedule;
2017
2018         /* Set up a new set of temp-adjusted TxPowers, send to NIC.
2019          * This is based *only* on current temperature,
2020          * ignoring any previous power measurements */
2021         iwl3945_hw_reg_comp_txpower_temp(priv);
2022
2023  reschedule:
2024         queue_delayed_work(priv->workqueue,
2025                            &priv->thermal_periodic, REG_RECALIB_PERIOD * HZ);
2026 }
2027
2028 static void iwl3945_bg_reg_txpower_periodic(struct work_struct *work)
2029 {
2030         struct iwl_priv *priv = container_of(work, struct iwl_priv,
2031                                              thermal_periodic.work);
2032
2033         if (test_bit(STATUS_EXIT_PENDING, &priv->status))
2034                 return;
2035
2036         mutex_lock(&priv->mutex);
2037         iwl3945_reg_txpower_periodic(priv);
2038         mutex_unlock(&priv->mutex);
2039 }
2040
2041 /**
2042  * iwl3945_hw_reg_get_ch_grp_index - find the channel-group index (0-4)
2043  *                                 for the channel.
2044  *
2045  * This function is used when initializing channel-info structs.
2046  *
2047  * NOTE: These channel groups do *NOT* match the bands above!
2048  *       These channel groups are based on factory-tested channels;
2049  *       on A-band, EEPROM's "group frequency" entries represent the top
2050  *       channel in each group 1-4.  Group 5 All B/G channels are in group 0.
2051  */
2052 static u16 iwl3945_hw_reg_get_ch_grp_index(struct iwl_priv *priv,
2053                                        const struct iwl_channel_info *ch_info)
2054 {
2055         struct iwl3945_eeprom *eeprom = (struct iwl3945_eeprom *)priv->eeprom;
2056         struct iwl3945_eeprom_txpower_group *ch_grp = &eeprom->groups[0];
2057         u8 group;
2058         u16 group_index = 0;    /* based on factory calib frequencies */
2059         u8 grp_channel;
2060
2061         /* Find the group index for the channel ... don't use index 1(?) */
2062         if (is_channel_a_band(ch_info)) {
2063                 for (group = 1; group < 5; group++) {
2064                         grp_channel = ch_grp[group].group_channel;
2065                         if (ch_info->channel <= grp_channel) {
2066                                 group_index = group;
2067                                 break;
2068                         }
2069                 }
2070                 /* group 4 has a few channels *above* its factory cal freq */
2071                 if (group == 5)
2072                         group_index = 4;
2073         } else
2074                 group_index = 0;        /* 2.4 GHz, group 0 */
2075
2076         IWL_DEBUG_POWER(priv, "Chnl %d mapped to grp %d\n", ch_info->channel,
2077                         group_index);
2078         return group_index;
2079 }
2080
2081 /**
2082  * iwl3945_hw_reg_get_matched_power_index - Interpolate to get nominal index
2083  *
2084  * Interpolate to get nominal (i.e. at factory calibration temperature) index
2085  *   into radio/DSP gain settings table for requested power.
2086  */
2087 static int iwl3945_hw_reg_get_matched_power_index(struct iwl_priv *priv,
2088                                        s8 requested_power,
2089                                        s32 setting_index, s32 *new_index)
2090 {
2091         const struct iwl3945_eeprom_txpower_group *chnl_grp = NULL;
2092         struct iwl3945_eeprom *eeprom = (struct iwl3945_eeprom *)priv->eeprom;
2093         s32 index0, index1;
2094         s32 power = 2 * requested_power;
2095         s32 i;
2096         const struct iwl3945_eeprom_txpower_sample *samples;
2097         s32 gains0, gains1;
2098         s32 res;
2099         s32 denominator;
2100
2101         chnl_grp = &eeprom->groups[setting_index];
2102         samples = chnl_grp->samples;
2103         for (i = 0; i < 5; i++) {
2104                 if (power == samples[i].power) {
2105                         *new_index = samples[i].gain_index;
2106                         return 0;
2107                 }
2108         }
2109
2110         if (power > samples[1].power) {
2111                 index0 = 0;
2112                 index1 = 1;
2113         } else if (power > samples[2].power) {
2114                 index0 = 1;
2115                 index1 = 2;
2116         } else if (power > samples[3].power) {
2117                 index0 = 2;
2118                 index1 = 3;
2119         } else {
2120                 index0 = 3;
2121                 index1 = 4;
2122         }
2123
2124         denominator = (s32) samples[index1].power - (s32) samples[index0].power;
2125         if (denominator == 0)
2126                 return -EINVAL;
2127         gains0 = (s32) samples[index0].gain_index * (1 << 19);
2128         gains1 = (s32) samples[index1].gain_index * (1 << 19);
2129         res = gains0 + (gains1 - gains0) *
2130             ((s32) power - (s32) samples[index0].power) / denominator +
2131             (1 << 18);
2132         *new_index = res >> 19;
2133         return 0;
2134 }
2135
2136 static void iwl3945_hw_reg_init_channel_groups(struct iwl_priv *priv)
2137 {
2138         u32 i;
2139         s32 rate_index;
2140         struct iwl3945_eeprom *eeprom = (struct iwl3945_eeprom *)priv->eeprom;
2141         const struct iwl3945_eeprom_txpower_group *group;
2142
2143         IWL_DEBUG_POWER(priv, "Initializing factory calib info from EEPROM\n");
2144
2145         for (i = 0; i < IWL_NUM_TX_CALIB_GROUPS; i++) {
2146                 s8 *clip_pwrs;  /* table of power levels for each rate */
2147                 s8 satur_pwr;   /* saturation power for each chnl group */
2148                 group = &eeprom->groups[i];
2149
2150                 /* sanity check on factory saturation power value */
2151                 if (group->saturation_power < 40) {
2152                         IWL_WARN(priv, "Error: saturation power is %d, "
2153                                     "less than minimum expected 40\n",
2154                                     group->saturation_power);
2155                         return;
2156                 }
2157
2158                 /*
2159                  * Derive requested power levels for each rate, based on
2160                  *   hardware capabilities (saturation power for band).
2161                  * Basic value is 3dB down from saturation, with further
2162                  *   power reductions for highest 3 data rates.  These
2163                  *   backoffs provide headroom for high rate modulation
2164                  *   power peaks, without too much distortion (clipping).
2165                  */
2166                 /* we'll fill in this array with h/w max power levels */
2167                 clip_pwrs = (s8 *) priv->clip39_groups[i].clip_powers;
2168
2169                 /* divide factory saturation power by 2 to find -3dB level */
2170                 satur_pwr = (s8) (group->saturation_power >> 1);
2171
2172                 /* fill in channel group's nominal powers for each rate */
2173                 for (rate_index = 0;
2174                      rate_index < IWL_RATE_COUNT; rate_index++, clip_pwrs++) {
2175                         switch (rate_index) {
2176                         case IWL_RATE_36M_INDEX_TABLE:
2177                                 if (i == 0)     /* B/G */
2178                                         *clip_pwrs = satur_pwr;
2179                                 else    /* A */
2180                                         *clip_pwrs = satur_pwr - 5;
2181                                 break;
2182                         case IWL_RATE_48M_INDEX_TABLE:
2183                                 if (i == 0)
2184                                         *clip_pwrs = satur_pwr - 7;
2185                                 else
2186                                         *clip_pwrs = satur_pwr - 10;
2187                                 break;
2188                         case IWL_RATE_54M_INDEX_TABLE:
2189                                 if (i == 0)
2190                                         *clip_pwrs = satur_pwr - 9;
2191                                 else
2192                                         *clip_pwrs = satur_pwr - 12;
2193                                 break;
2194                         default:
2195                                 *clip_pwrs = satur_pwr;
2196                                 break;
2197                         }
2198                 }
2199         }
2200 }
2201
2202 /**
2203  * iwl3945_txpower_set_from_eeprom - Set channel power info based on EEPROM
2204  *
2205  * Second pass (during init) to set up priv->channel_info
2206  *
2207  * Set up Tx-power settings in our channel info database for each VALID
2208  * (for this geo/SKU) channel, at all Tx data rates, based on eeprom values
2209  * and current temperature.
2210  *
2211  * Since this is based on current temperature (at init time), these values may
2212  * not be valid for very long, but it gives us a starting/default point,
2213  * and allows us to active (i.e. using Tx) scan.
2214  *
2215  * This does *not* write values to NIC, just sets up our internal table.
2216  */
2217 int iwl3945_txpower_set_from_eeprom(struct iwl_priv *priv)
2218 {
2219         struct iwl_channel_info *ch_info = NULL;
2220         struct iwl3945_channel_power_info *pwr_info;
2221         struct iwl3945_eeprom *eeprom = (struct iwl3945_eeprom *)priv->eeprom;
2222         int delta_index;
2223         u8 rate_index;
2224         u8 scan_tbl_index;
2225         const s8 *clip_pwrs;    /* array of power levels for each rate */
2226         u8 gain, dsp_atten;
2227         s8 power;
2228         u8 pwr_index, base_pwr_index, a_band;
2229         u8 i;
2230         int temperature;
2231
2232         /* save temperature reference,
2233          *   so we can determine next time to calibrate */
2234         temperature = iwl3945_hw_reg_txpower_get_temperature(priv);
2235         priv->last_temperature = temperature;
2236
2237         iwl3945_hw_reg_init_channel_groups(priv);
2238
2239         /* initialize Tx power info for each and every channel, 2.4 and 5.x */
2240         for (i = 0, ch_info = priv->channel_info; i < priv->channel_count;
2241              i++, ch_info++) {
2242                 a_band = is_channel_a_band(ch_info);
2243                 if (!is_channel_valid(ch_info))
2244                         continue;
2245
2246                 /* find this channel's channel group (*not* "band") index */
2247                 ch_info->group_index =
2248                         iwl3945_hw_reg_get_ch_grp_index(priv, ch_info);
2249
2250                 /* Get this chnlgrp's rate->max/clip-powers table */
2251                 clip_pwrs = priv->clip39_groups[ch_info->group_index].clip_powers;
2252
2253                 /* calculate power index *adjustment* value according to
2254                  *  diff between current temperature and factory temperature */
2255                 delta_index = iwl3945_hw_reg_adjust_power_by_temp(temperature,
2256                                 eeprom->groups[ch_info->group_index].
2257                                 temperature);
2258
2259                 IWL_DEBUG_POWER(priv, "Delta index for channel %d: %d [%d]\n",
2260                                 ch_info->channel, delta_index, temperature +
2261                                 IWL_TEMP_CONVERT);
2262
2263                 /* set tx power value for all OFDM rates */
2264                 for (rate_index = 0; rate_index < IWL_OFDM_RATES;
2265                      rate_index++) {
2266                         s32 uninitialized_var(power_idx);
2267                         int rc;
2268
2269                         /* use channel group's clip-power table,
2270                          *   but don't exceed channel's max power */
2271                         s8 pwr = min(ch_info->max_power_avg,
2272                                      clip_pwrs[rate_index]);
2273
2274                         pwr_info = &ch_info->power_info[rate_index];
2275
2276                         /* get base (i.e. at factory-measured temperature)
2277                          *    power table index for this rate's power */
2278                         rc = iwl3945_hw_reg_get_matched_power_index(priv, pwr,
2279                                                          ch_info->group_index,
2280                                                          &power_idx);
2281                         if (rc) {
2282                                 IWL_ERR(priv, "Invalid power index\n");
2283                                 return rc;
2284                         }
2285                         pwr_info->base_power_index = (u8) power_idx;
2286
2287                         /* temperature compensate */
2288                         power_idx += delta_index;
2289
2290                         /* stay within range of gain table */
2291                         power_idx = iwl3945_hw_reg_fix_power_index(power_idx);
2292
2293                         /* fill 1 OFDM rate's iwl3945_channel_power_info struct */
2294                         pwr_info->requested_power = pwr;
2295                         pwr_info->power_table_index = (u8) power_idx;
2296                         pwr_info->tpc.tx_gain =
2297                             power_gain_table[a_band][power_idx].tx_gain;
2298                         pwr_info->tpc.dsp_atten =
2299                             power_gain_table[a_band][power_idx].dsp_atten;
2300                 }
2301
2302                 /* set tx power for CCK rates, based on OFDM 12 Mbit settings*/
2303                 pwr_info = &ch_info->power_info[IWL_RATE_12M_INDEX_TABLE];
2304                 power = pwr_info->requested_power +
2305                         IWL_CCK_FROM_OFDM_POWER_DIFF;
2306                 pwr_index = pwr_info->power_table_index +
2307                         IWL_CCK_FROM_OFDM_INDEX_DIFF;
2308                 base_pwr_index = pwr_info->base_power_index +
2309                         IWL_CCK_FROM_OFDM_INDEX_DIFF;
2310
2311                 /* stay within table range */
2312                 pwr_index = iwl3945_hw_reg_fix_power_index(pwr_index);
2313                 gain = power_gain_table[a_band][pwr_index].tx_gain;
2314                 dsp_atten = power_gain_table[a_band][pwr_index].dsp_atten;
2315
2316                 /* fill each CCK rate's iwl3945_channel_power_info structure
2317                  * NOTE:  All CCK-rate Txpwrs are the same for a given chnl!
2318                  * NOTE:  CCK rates start at end of OFDM rates! */
2319                 for (rate_index = 0;
2320                      rate_index < IWL_CCK_RATES; rate_index++) {
2321                         pwr_info = &ch_info->power_info[rate_index+IWL_OFDM_RATES];
2322                         pwr_info->requested_power = power;
2323                         pwr_info->power_table_index = pwr_index;
2324                         pwr_info->base_power_index = base_pwr_index;
2325                         pwr_info->tpc.tx_gain = gain;
2326                         pwr_info->tpc.dsp_atten = dsp_atten;
2327                 }
2328
2329                 /* set scan tx power, 1Mbit for CCK, 6Mbit for OFDM */
2330                 for (scan_tbl_index = 0;
2331                      scan_tbl_index < IWL_NUM_SCAN_RATES; scan_tbl_index++) {
2332                         s32 actual_index = (scan_tbl_index == 0) ?
2333                                 IWL_RATE_1M_INDEX_TABLE : IWL_RATE_6M_INDEX_TABLE;
2334                         iwl3945_hw_reg_set_scan_power(priv, scan_tbl_index,
2335                                 actual_index, clip_pwrs, ch_info, a_band);
2336                 }
2337         }
2338
2339         return 0;
2340 }
2341
2342 int iwl3945_hw_rxq_stop(struct iwl_priv *priv)
2343 {
2344         int rc;
2345
2346         iwl_write_direct32(priv, FH39_RCSR_CONFIG(0), 0);
2347         rc = iwl_poll_direct_bit(priv, FH39_RSSR_STATUS,
2348                         FH39_RSSR_CHNL0_RX_STATUS_CHNL_IDLE, 1000);
2349         if (rc < 0)
2350                 IWL_ERR(priv, "Can't stop Rx DMA.\n");
2351
2352         return 0;
2353 }
2354
2355 int iwl3945_hw_tx_queue_init(struct iwl_priv *priv, struct iwl_tx_queue *txq)
2356 {
2357         int txq_id = txq->q.id;
2358
2359         struct iwl3945_shared *shared_data = priv->shared_virt;
2360
2361         shared_data->tx_base_ptr[txq_id] = cpu_to_le32((u32)txq->q.dma_addr);
2362
2363         iwl_write_direct32(priv, FH39_CBCC_CTRL(txq_id), 0);
2364         iwl_write_direct32(priv, FH39_CBCC_BASE(txq_id), 0);
2365
2366         iwl_write_direct32(priv, FH39_TCSR_CONFIG(txq_id),
2367                 FH39_TCSR_TX_CONFIG_REG_VAL_CIRQ_RTC_NOINT |
2368                 FH39_TCSR_TX_CONFIG_REG_VAL_MSG_MODE_TXF |
2369                 FH39_TCSR_TX_CONFIG_REG_VAL_CIRQ_HOST_IFTFD |
2370                 FH39_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_ENABLE_VAL |
2371                 FH39_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE);
2372
2373         /* fake read to flush all prev. writes */
2374         iwl_read32(priv, FH39_TSSR_CBB_BASE);
2375
2376         return 0;
2377 }
2378
2379 /*
2380  * HCMD utils
2381  */
2382 static u16 iwl3945_get_hcmd_size(u8 cmd_id, u16 len)
2383 {
2384         switch (cmd_id) {
2385         case REPLY_RXON:
2386                 return sizeof(struct iwl3945_rxon_cmd);
2387         case POWER_TABLE_CMD:
2388                 return sizeof(struct iwl3945_powertable_cmd);
2389         default:
2390                 return len;
2391         }
2392 }
2393
2394
2395 static u16 iwl3945_build_addsta_hcmd(const struct iwl_addsta_cmd *cmd, u8 *data)
2396 {
2397         struct iwl3945_addsta_cmd *addsta = (struct iwl3945_addsta_cmd *)data;
2398         addsta->mode = cmd->mode;
2399         memcpy(&addsta->sta, &cmd->sta, sizeof(struct sta_id_modify));
2400         memcpy(&addsta->key, &cmd->key, sizeof(struct iwl4965_keyinfo));
2401         addsta->station_flags = cmd->station_flags;
2402         addsta->station_flags_msk = cmd->station_flags_msk;
2403         addsta->tid_disable_tx = cpu_to_le16(0);
2404         addsta->rate_n_flags = cmd->rate_n_flags;
2405         addsta->add_immediate_ba_tid = cmd->add_immediate_ba_tid;
2406         addsta->remove_immediate_ba_tid = cmd->remove_immediate_ba_tid;
2407         addsta->add_immediate_ba_ssn = cmd->add_immediate_ba_ssn;
2408
2409         return (u16)sizeof(struct iwl3945_addsta_cmd);
2410 }
2411
2412
2413 /**
2414  * iwl3945_init_hw_rate_table - Initialize the hardware rate fallback table
2415  */
2416 int iwl3945_init_hw_rate_table(struct iwl_priv *priv)
2417 {
2418         int rc, i, index, prev_index;
2419         struct iwl3945_rate_scaling_cmd rate_cmd = {
2420                 .reserved = {0, 0, 0},
2421         };
2422         struct iwl3945_rate_scaling_info *table = rate_cmd.table;
2423
2424         for (i = 0; i < ARRAY_SIZE(iwl3945_rates); i++) {
2425                 index = iwl3945_rates[i].table_rs_index;
2426
2427                 table[index].rate_n_flags =
2428                         iwl3945_hw_set_rate_n_flags(iwl3945_rates[i].plcp, 0);
2429                 table[index].try_cnt = priv->retry_rate;
2430                 prev_index = iwl3945_get_prev_ieee_rate(i);
2431                 table[index].next_rate_index =
2432                                 iwl3945_rates[prev_index].table_rs_index;
2433         }
2434
2435         switch (priv->band) {
2436         case IEEE80211_BAND_5GHZ:
2437                 IWL_DEBUG_RATE(priv, "Select A mode rate scale\n");
2438                 /* If one of the following CCK rates is used,
2439                  * have it fall back to the 6M OFDM rate */
2440                 for (i = IWL_RATE_1M_INDEX_TABLE;
2441                         i <= IWL_RATE_11M_INDEX_TABLE; i++)
2442                         table[i].next_rate_index =
2443                           iwl3945_rates[IWL_FIRST_OFDM_RATE].table_rs_index;
2444
2445                 /* Don't fall back to CCK rates */
2446                 table[IWL_RATE_12M_INDEX_TABLE].next_rate_index =
2447                                                 IWL_RATE_9M_INDEX_TABLE;
2448
2449                 /* Don't drop out of OFDM rates */
2450                 table[IWL_RATE_6M_INDEX_TABLE].next_rate_index =
2451                     iwl3945_rates[IWL_FIRST_OFDM_RATE].table_rs_index;
2452                 break;
2453
2454         case IEEE80211_BAND_2GHZ:
2455                 IWL_DEBUG_RATE(priv, "Select B/G mode rate scale\n");
2456                 /* If an OFDM rate is used, have it fall back to the
2457                  * 1M CCK rates */
2458
2459                 if (!(priv->sta_supp_rates & IWL_OFDM_RATES_MASK) &&
2460                     iwl_is_associated(priv)) {
2461
2462                         index = IWL_FIRST_CCK_RATE;
2463                         for (i = IWL_RATE_6M_INDEX_TABLE;
2464                              i <= IWL_RATE_54M_INDEX_TABLE; i++)
2465                                 table[i].next_rate_index =
2466                                         iwl3945_rates[index].table_rs_index;
2467
2468                         index = IWL_RATE_11M_INDEX_TABLE;
2469                         /* CCK shouldn't fall back to OFDM... */
2470                         table[index].next_rate_index = IWL_RATE_5M_INDEX_TABLE;
2471                 }
2472                 break;
2473
2474         default:
2475                 WARN_ON(1);
2476                 break;
2477         }
2478
2479         /* Update the rate scaling for control frame Tx */
2480         rate_cmd.table_id = 0;
2481         rc = iwl_send_cmd_pdu(priv, REPLY_RATE_SCALE, sizeof(rate_cmd),
2482                               &rate_cmd);
2483         if (rc)
2484                 return rc;
2485
2486         /* Update the rate scaling for data frame Tx */
2487         rate_cmd.table_id = 1;
2488         return iwl_send_cmd_pdu(priv, REPLY_RATE_SCALE, sizeof(rate_cmd),
2489                                 &rate_cmd);
2490 }
2491
2492 /* Called when initializing driver */
2493 int iwl3945_hw_set_hw_params(struct iwl_priv *priv)
2494 {
2495         memset((void *)&priv->hw_params, 0,
2496                sizeof(struct iwl_hw_params));
2497
2498         priv->shared_virt =
2499             pci_alloc_consistent(priv->pci_dev,
2500                                  sizeof(struct iwl3945_shared),
2501                                  &priv->shared_phys);
2502
2503         if (!priv->shared_virt) {
2504                 IWL_ERR(priv, "failed to allocate pci memory\n");
2505                 mutex_unlock(&priv->mutex);
2506                 return -ENOMEM;
2507         }
2508
2509         /* Assign number of Usable TX queues */
2510         priv->hw_params.max_txq_num = priv->cfg->num_of_queues;
2511
2512         priv->hw_params.tfd_size = sizeof(struct iwl3945_tfd);
2513         priv->hw_params.rx_buf_size = IWL_RX_BUF_SIZE_3K;
2514         priv->hw_params.max_pkt_size = 2342;
2515         priv->hw_params.max_rxq_size = RX_QUEUE_SIZE;
2516         priv->hw_params.max_rxq_log = RX_QUEUE_SIZE_LOG;
2517         priv->hw_params.max_stations = IWL3945_STATION_COUNT;
2518         priv->hw_params.bcast_sta_id = IWL3945_BROADCAST_ID;
2519
2520         priv->hw_params.rx_wrt_ptr_reg = FH39_RSCSR_CHNL0_WPTR;
2521         priv->hw_params.max_beacon_itrvl = IWL39_MAX_UCODE_BEACON_INTERVAL;
2522
2523         return 0;
2524 }
2525
2526 unsigned int iwl3945_hw_get_beacon_cmd(struct iwl_priv *priv,
2527                           struct iwl3945_frame *frame, u8 rate)
2528 {
2529         struct iwl3945_tx_beacon_cmd *tx_beacon_cmd;
2530         unsigned int frame_size;
2531
2532         tx_beacon_cmd = (struct iwl3945_tx_beacon_cmd *)&frame->u;
2533         memset(tx_beacon_cmd, 0, sizeof(*tx_beacon_cmd));
2534
2535         tx_beacon_cmd->tx.sta_id = priv->hw_params.bcast_sta_id;
2536         tx_beacon_cmd->tx.stop_time.life_time = TX_CMD_LIFE_TIME_INFINITE;
2537
2538         frame_size = iwl3945_fill_beacon_frame(priv,
2539                                 tx_beacon_cmd->frame,
2540                                 sizeof(frame->u) - sizeof(*tx_beacon_cmd));
2541
2542         BUG_ON(frame_size > MAX_MPDU_SIZE);
2543         tx_beacon_cmd->tx.len = cpu_to_le16((u16)frame_size);
2544
2545         tx_beacon_cmd->tx.rate = rate;
2546         tx_beacon_cmd->tx.tx_flags = (TX_CMD_FLG_SEQ_CTL_MSK |
2547                                       TX_CMD_FLG_TSF_MSK);
2548
2549         /* supp_rates[0] == OFDM start at IWL_FIRST_OFDM_RATE*/
2550         tx_beacon_cmd->tx.supp_rates[0] =
2551                 (IWL_OFDM_BASIC_RATES_MASK >> IWL_FIRST_OFDM_RATE) & 0xFF;
2552
2553         tx_beacon_cmd->tx.supp_rates[1] =
2554                 (IWL_CCK_BASIC_RATES_MASK & 0xF);
2555
2556         return sizeof(struct iwl3945_tx_beacon_cmd) + frame_size;
2557 }
2558
2559 void iwl3945_hw_rx_handler_setup(struct iwl_priv *priv)
2560 {
2561         priv->rx_handlers[REPLY_TX] = iwl3945_rx_reply_tx;
2562         priv->rx_handlers[REPLY_3945_RX] = iwl3945_rx_reply_rx;
2563 }
2564
2565 void iwl3945_hw_setup_deferred_work(struct iwl_priv *priv)
2566 {
2567         INIT_DELAYED_WORK(&priv->thermal_periodic,
2568                           iwl3945_bg_reg_txpower_periodic);
2569 }
2570
2571 void iwl3945_hw_cancel_deferred_work(struct iwl_priv *priv)
2572 {
2573         cancel_delayed_work(&priv->thermal_periodic);
2574 }
2575
2576 /* check contents of special bootstrap uCode SRAM */
2577 static int iwl3945_verify_bsm(struct iwl_priv *priv)
2578  {
2579         __le32 *image = priv->ucode_boot.v_addr;
2580         u32 len = priv->ucode_boot.len;
2581         u32 reg;
2582         u32 val;
2583
2584         IWL_DEBUG_INFO(priv, "Begin verify bsm\n");
2585
2586         /* verify BSM SRAM contents */
2587         val = iwl_read_prph(priv, BSM_WR_DWCOUNT_REG);
2588         for (reg = BSM_SRAM_LOWER_BOUND;
2589              reg < BSM_SRAM_LOWER_BOUND + len;
2590              reg += sizeof(u32), image++) {
2591                 val = iwl_read_prph(priv, reg);
2592                 if (val != le32_to_cpu(*image)) {
2593                         IWL_ERR(priv, "BSM uCode verification failed at "
2594                                   "addr 0x%08X+%u (of %u), is 0x%x, s/b 0x%x\n",
2595                                   BSM_SRAM_LOWER_BOUND,
2596                                   reg - BSM_SRAM_LOWER_BOUND, len,
2597                                   val, le32_to_cpu(*image));
2598                         return -EIO;
2599                 }
2600         }
2601
2602         IWL_DEBUG_INFO(priv, "BSM bootstrap uCode image OK\n");
2603
2604         return 0;
2605 }
2606
2607
2608 /******************************************************************************
2609  *
2610  * EEPROM related functions
2611  *
2612  ******************************************************************************/
2613
2614 /*
2615  * Clear the OWNER_MSK, to establish driver (instead of uCode running on
2616  * embedded controller) as EEPROM reader; each read is a series of pulses
2617  * to/from the EEPROM chip, not a single event, so even reads could conflict
2618  * if they weren't arbitrated by some ownership mechanism.  Here, the driver
2619  * simply claims ownership, which should be safe when this function is called
2620  * (i.e. before loading uCode!).
2621  */
2622 static int iwl3945_eeprom_acquire_semaphore(struct iwl_priv *priv)
2623 {
2624         _iwl_clear_bit(priv, CSR_EEPROM_GP, CSR_EEPROM_GP_IF_OWNER_MSK);
2625         return 0;
2626 }
2627
2628
2629 static void iwl3945_eeprom_release_semaphore(struct iwl_priv *priv)
2630 {
2631         return;
2632 }
2633
2634  /**
2635   * iwl3945_load_bsm - Load bootstrap instructions
2636   *
2637   * BSM operation:
2638   *
2639   * The Bootstrap State Machine (BSM) stores a short bootstrap uCode program
2640   * in special SRAM that does not power down during RFKILL.  When powering back
2641   * up after power-saving sleeps (or during initial uCode load), the BSM loads
2642   * the bootstrap program into the on-board processor, and starts it.
2643   *
2644   * The bootstrap program loads (via DMA) instructions and data for a new
2645   * program from host DRAM locations indicated by the host driver in the
2646   * BSM_DRAM_* registers.  Once the new program is loaded, it starts
2647   * automatically.
2648   *
2649   * When initializing the NIC, the host driver points the BSM to the
2650   * "initialize" uCode image.  This uCode sets up some internal data, then
2651   * notifies host via "initialize alive" that it is complete.
2652   *
2653   * The host then replaces the BSM_DRAM_* pointer values to point to the
2654   * normal runtime uCode instructions and a backup uCode data cache buffer
2655   * (filled initially with starting data values for the on-board processor),
2656   * then triggers the "initialize" uCode to load and launch the runtime uCode,
2657   * which begins normal operation.
2658   *
2659   * When doing a power-save shutdown, runtime uCode saves data SRAM into
2660   * the backup data cache in DRAM before SRAM is powered down.
2661   *
2662   * When powering back up, the BSM loads the bootstrap program.  This reloads
2663   * the runtime uCode instructions and the backup data cache into SRAM,
2664   * and re-launches the runtime uCode from where it left off.
2665   */
2666 static int iwl3945_load_bsm(struct iwl_priv *priv)
2667 {
2668         __le32 *image = priv->ucode_boot.v_addr;
2669         u32 len = priv->ucode_boot.len;
2670         dma_addr_t pinst;
2671         dma_addr_t pdata;
2672         u32 inst_len;
2673         u32 data_len;
2674         int rc;
2675         int i;
2676         u32 done;
2677         u32 reg_offset;
2678
2679         IWL_DEBUG_INFO(priv, "Begin load bsm\n");
2680
2681         /* make sure bootstrap program is no larger than BSM's SRAM size */
2682         if (len > IWL39_MAX_BSM_SIZE)
2683                 return -EINVAL;
2684
2685         /* Tell bootstrap uCode where to find the "Initialize" uCode
2686         *   in host DRAM ... host DRAM physical address bits 31:0 for 3945.
2687         * NOTE:  iwl3945_initialize_alive_start() will replace these values,
2688         *        after the "initialize" uCode has run, to point to
2689         *        runtime/protocol instructions and backup data cache. */
2690         pinst = priv->ucode_init.p_addr;
2691         pdata = priv->ucode_init_data.p_addr;
2692         inst_len = priv->ucode_init.len;
2693         data_len = priv->ucode_init_data.len;
2694
2695         iwl_write_prph(priv, BSM_DRAM_INST_PTR_REG, pinst);
2696         iwl_write_prph(priv, BSM_DRAM_DATA_PTR_REG, pdata);
2697         iwl_write_prph(priv, BSM_DRAM_INST_BYTECOUNT_REG, inst_len);
2698         iwl_write_prph(priv, BSM_DRAM_DATA_BYTECOUNT_REG, data_len);
2699
2700         /* Fill BSM memory with bootstrap instructions */
2701         for (reg_offset = BSM_SRAM_LOWER_BOUND;
2702              reg_offset < BSM_SRAM_LOWER_BOUND + len;
2703              reg_offset += sizeof(u32), image++)
2704                 _iwl_write_prph(priv, reg_offset,
2705                                           le32_to_cpu(*image));
2706
2707         rc = iwl3945_verify_bsm(priv);
2708         if (rc)
2709                 return rc;
2710
2711         /* Tell BSM to copy from BSM SRAM into instruction SRAM, when asked */
2712         iwl_write_prph(priv, BSM_WR_MEM_SRC_REG, 0x0);
2713         iwl_write_prph(priv, BSM_WR_MEM_DST_REG,
2714                                  IWL39_RTC_INST_LOWER_BOUND);
2715         iwl_write_prph(priv, BSM_WR_DWCOUNT_REG, len / sizeof(u32));
2716
2717         /* Load bootstrap code into instruction SRAM now,
2718          *   to prepare to load "initialize" uCode */
2719         iwl_write_prph(priv, BSM_WR_CTRL_REG,
2720                 BSM_WR_CTRL_REG_BIT_START);
2721
2722         /* Wait for load of bootstrap uCode to finish */
2723         for (i = 0; i < 100; i++) {
2724                 done = iwl_read_prph(priv, BSM_WR_CTRL_REG);
2725                 if (!(done & BSM_WR_CTRL_REG_BIT_START))
2726                         break;
2727                 udelay(10);
2728         }
2729         if (i < 100)
2730                 IWL_DEBUG_INFO(priv, "BSM write complete, poll %d iterations\n", i);
2731         else {
2732                 IWL_ERR(priv, "BSM write did not complete!\n");
2733                 return -EIO;
2734         }
2735
2736         /* Enable future boot loads whenever power management unit triggers it
2737          *   (e.g. when powering back up after power-save shutdown) */
2738         iwl_write_prph(priv, BSM_WR_CTRL_REG,
2739                 BSM_WR_CTRL_REG_BIT_START_EN);
2740
2741         return 0;
2742 }
2743
2744 #define IWL3945_UCODE_GET(item)                                         \
2745 static u32 iwl3945_ucode_get_##item(const struct iwl_ucode_header *ucode,\
2746                                     u32 api_ver)                        \
2747 {                                                                       \
2748         return le32_to_cpu(ucode->u.v1.item);                           \
2749 }
2750
2751 static u32 iwl3945_ucode_get_header_size(u32 api_ver)
2752 {
2753         return UCODE_HEADER_SIZE(1);
2754 }
2755 static u32 iwl3945_ucode_get_build(const struct iwl_ucode_header *ucode,
2756                                    u32 api_ver)
2757 {
2758         return 0;
2759 }
2760 static u8 *iwl3945_ucode_get_data(const struct iwl_ucode_header *ucode,
2761                                   u32 api_ver)
2762 {
2763         return (u8 *) ucode->u.v1.data;
2764 }
2765
2766 IWL3945_UCODE_GET(inst_size);
2767 IWL3945_UCODE_GET(data_size);
2768 IWL3945_UCODE_GET(init_size);
2769 IWL3945_UCODE_GET(init_data_size);
2770 IWL3945_UCODE_GET(boot_size);
2771
2772 static struct iwl_hcmd_ops iwl3945_hcmd = {
2773         .rxon_assoc = iwl3945_send_rxon_assoc,
2774         .commit_rxon = iwl3945_commit_rxon,
2775 };
2776
2777 static struct iwl_ucode_ops iwl3945_ucode = {
2778         .get_header_size = iwl3945_ucode_get_header_size,
2779         .get_build = iwl3945_ucode_get_build,
2780         .get_inst_size = iwl3945_ucode_get_inst_size,
2781         .get_data_size = iwl3945_ucode_get_data_size,
2782         .get_init_size = iwl3945_ucode_get_init_size,
2783         .get_init_data_size = iwl3945_ucode_get_init_data_size,
2784         .get_boot_size = iwl3945_ucode_get_boot_size,
2785         .get_data = iwl3945_ucode_get_data,
2786 };
2787
2788 static struct iwl_lib_ops iwl3945_lib = {
2789         .txq_attach_buf_to_tfd = iwl3945_hw_txq_attach_buf_to_tfd,
2790         .txq_free_tfd = iwl3945_hw_txq_free_tfd,
2791         .txq_init = iwl3945_hw_tx_queue_init,
2792         .load_ucode = iwl3945_load_bsm,
2793         .dump_nic_event_log = iwl3945_dump_nic_event_log,
2794         .dump_nic_error_log = iwl3945_dump_nic_error_log,
2795         .apm_ops = {
2796                 .init = iwl3945_apm_init,
2797                 .stop = iwl_apm_stop,
2798                 .config = iwl3945_nic_config,
2799                 .set_pwr_src = iwl3945_set_pwr_src,
2800         },
2801         .eeprom_ops = {
2802                 .regulatory_bands = {
2803                         EEPROM_REGULATORY_BAND_1_CHANNELS,
2804                         EEPROM_REGULATORY_BAND_2_CHANNELS,
2805                         EEPROM_REGULATORY_BAND_3_CHANNELS,
2806                         EEPROM_REGULATORY_BAND_4_CHANNELS,
2807                         EEPROM_REGULATORY_BAND_5_CHANNELS,
2808                         EEPROM_REGULATORY_BAND_NO_HT40,
2809                         EEPROM_REGULATORY_BAND_NO_HT40,
2810                 },
2811                 .verify_signature  = iwlcore_eeprom_verify_signature,
2812                 .acquire_semaphore = iwl3945_eeprom_acquire_semaphore,
2813                 .release_semaphore = iwl3945_eeprom_release_semaphore,
2814                 .query_addr = iwlcore_eeprom_query_addr,
2815         },
2816         .send_tx_power  = iwl3945_send_tx_power,
2817         .is_valid_rtc_data_addr = iwl3945_hw_valid_rtc_data_addr,
2818         .post_associate = iwl3945_post_associate,
2819         .isr = iwl_isr_legacy,
2820         .config_ap = iwl3945_config_ap,
2821 };
2822
2823 static struct iwl_hcmd_utils_ops iwl3945_hcmd_utils = {
2824         .get_hcmd_size = iwl3945_get_hcmd_size,
2825         .build_addsta_hcmd = iwl3945_build_addsta_hcmd,
2826         .rts_tx_cmd_flag = iwlcore_rts_tx_cmd_flag,
2827 };
2828
2829 static struct iwl_ops iwl3945_ops = {
2830         .ucode = &iwl3945_ucode,
2831         .lib = &iwl3945_lib,
2832         .hcmd = &iwl3945_hcmd,
2833         .utils = &iwl3945_hcmd_utils,
2834         .led = &iwl3945_led_ops,
2835 };
2836
2837 static struct iwl_cfg iwl3945_bg_cfg = {
2838         .name = "3945BG",
2839         .fw_name_pre = IWL3945_FW_PRE,
2840         .ucode_api_max = IWL3945_UCODE_API_MAX,
2841         .ucode_api_min = IWL3945_UCODE_API_MIN,
2842         .sku = IWL_SKU_G,
2843         .eeprom_size = IWL3945_EEPROM_IMG_SIZE,
2844         .eeprom_ver = EEPROM_3945_EEPROM_VERSION,
2845         .ops = &iwl3945_ops,
2846         .num_of_queues = IWL39_NUM_QUEUES,
2847         .mod_params = &iwl3945_mod_params,
2848         .use_isr_legacy = true,
2849         .ht_greenfield_support = false,
2850         .led_compensation = 64,
2851 };
2852
2853 static struct iwl_cfg iwl3945_abg_cfg = {
2854         .name = "3945ABG",
2855         .fw_name_pre = IWL3945_FW_PRE,
2856         .ucode_api_max = IWL3945_UCODE_API_MAX,
2857         .ucode_api_min = IWL3945_UCODE_API_MIN,
2858         .sku = IWL_SKU_A|IWL_SKU_G,
2859         .eeprom_size = IWL3945_EEPROM_IMG_SIZE,
2860         .eeprom_ver = EEPROM_3945_EEPROM_VERSION,
2861         .ops = &iwl3945_ops,
2862         .num_of_queues = IWL39_NUM_QUEUES,
2863         .mod_params = &iwl3945_mod_params,
2864         .use_isr_legacy = true,
2865         .ht_greenfield_support = false,
2866         .led_compensation = 64,
2867 };
2868
2869 struct pci_device_id iwl3945_hw_card_ids[] = {
2870         {IWL_PCI_DEVICE(0x4222, 0x1005, iwl3945_bg_cfg)},
2871         {IWL_PCI_DEVICE(0x4222, 0x1034, iwl3945_bg_cfg)},
2872         {IWL_PCI_DEVICE(0x4222, 0x1044, iwl3945_bg_cfg)},
2873         {IWL_PCI_DEVICE(0x4227, 0x1014, iwl3945_bg_cfg)},
2874         {IWL_PCI_DEVICE(0x4222, PCI_ANY_ID, iwl3945_abg_cfg)},
2875         {IWL_PCI_DEVICE(0x4227, PCI_ANY_ID, iwl3945_abg_cfg)},
2876         {0}
2877 };
2878
2879 MODULE_DEVICE_TABLE(pci, iwl3945_hw_card_ids);