4e15a8e20d0900008e6c8fb269247c4651778910
[linux-2.6.git] / drivers / net / wireless / iwlwifi / iwl-3945.c
1 /******************************************************************************
2  *
3  * Copyright(c) 2003 - 2009 Intel Corporation. All rights reserved.
4  *
5  * This program is free software; you can redistribute it and/or modify it
6  * under the terms of version 2 of the GNU General Public License as
7  * published by the Free Software Foundation.
8  *
9  * This program is distributed in the hope that it will be useful, but WITHOUT
10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
12  * more details.
13  *
14  * You should have received a copy of the GNU General Public License along with
15  * this program; if not, write to the Free Software Foundation, Inc.,
16  * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
17  *
18  * The full GNU General Public License is included in this distribution in the
19  * file called LICENSE.
20  *
21  * Contact Information:
22  *  Intel Linux Wireless <ilw@linux.intel.com>
23  * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
24  *
25  *****************************************************************************/
26
27 #include <linux/kernel.h>
28 #include <linux/module.h>
29 #include <linux/init.h>
30 #include <linux/pci.h>
31 #include <linux/dma-mapping.h>
32 #include <linux/delay.h>
33 #include <linux/skbuff.h>
34 #include <linux/netdevice.h>
35 #include <linux/wireless.h>
36 #include <linux/firmware.h>
37 #include <linux/etherdevice.h>
38 #include <asm/unaligned.h>
39 #include <net/mac80211.h>
40
41 #include "iwl-fh.h"
42 #include "iwl-3945-fh.h"
43 #include "iwl-commands.h"
44 #include "iwl-sta.h"
45 #include "iwl-3945.h"
46 #include "iwl-eeprom.h"
47 #include "iwl-helpers.h"
48 #include "iwl-core.h"
49 #include "iwl-led.h"
50 #include "iwl-3945-led.h"
51
52 #define IWL_DECLARE_RATE_INFO(r, ip, in, rp, rn, pp, np)    \
53         [IWL_RATE_##r##M_INDEX] = { IWL_RATE_##r##M_PLCP,   \
54                                     IWL_RATE_##r##M_IEEE,   \
55                                     IWL_RATE_##ip##M_INDEX, \
56                                     IWL_RATE_##in##M_INDEX, \
57                                     IWL_RATE_##rp##M_INDEX, \
58                                     IWL_RATE_##rn##M_INDEX, \
59                                     IWL_RATE_##pp##M_INDEX, \
60                                     IWL_RATE_##np##M_INDEX, \
61                                     IWL_RATE_##r##M_INDEX_TABLE, \
62                                     IWL_RATE_##ip##M_INDEX_TABLE }
63
64 /*
65  * Parameter order:
66  *   rate, prev rate, next rate, prev tgg rate, next tgg rate
67  *
68  * If there isn't a valid next or previous rate then INV is used which
69  * maps to IWL_RATE_INVALID
70  *
71  */
72 const struct iwl3945_rate_info iwl3945_rates[IWL_RATE_COUNT_3945] = {
73         IWL_DECLARE_RATE_INFO(1, INV, 2, INV, 2, INV, 2),    /*  1mbps */
74         IWL_DECLARE_RATE_INFO(2, 1, 5, 1, 5, 1, 5),          /*  2mbps */
75         IWL_DECLARE_RATE_INFO(5, 2, 6, 2, 11, 2, 11),        /*5.5mbps */
76         IWL_DECLARE_RATE_INFO(11, 9, 12, 5, 12, 5, 18),      /* 11mbps */
77         IWL_DECLARE_RATE_INFO(6, 5, 9, 5, 11, 5, 11),        /*  6mbps */
78         IWL_DECLARE_RATE_INFO(9, 6, 11, 5, 11, 5, 11),       /*  9mbps */
79         IWL_DECLARE_RATE_INFO(12, 11, 18, 11, 18, 11, 18),   /* 12mbps */
80         IWL_DECLARE_RATE_INFO(18, 12, 24, 12, 24, 11, 24),   /* 18mbps */
81         IWL_DECLARE_RATE_INFO(24, 18, 36, 18, 36, 18, 36),   /* 24mbps */
82         IWL_DECLARE_RATE_INFO(36, 24, 48, 24, 48, 24, 48),   /* 36mbps */
83         IWL_DECLARE_RATE_INFO(48, 36, 54, 36, 54, 36, 54),   /* 48mbps */
84         IWL_DECLARE_RATE_INFO(54, 48, INV, 48, INV, 48, INV),/* 54mbps */
85 };
86
87 /* 1 = enable the iwl3945_disable_events() function */
88 #define IWL_EVT_DISABLE (0)
89 #define IWL_EVT_DISABLE_SIZE (1532/32)
90
91 /**
92  * iwl3945_disable_events - Disable selected events in uCode event log
93  *
94  * Disable an event by writing "1"s into "disable"
95  *   bitmap in SRAM.  Bit position corresponds to Event # (id/type).
96  *   Default values of 0 enable uCode events to be logged.
97  * Use for only special debugging.  This function is just a placeholder as-is,
98  *   you'll need to provide the special bits! ...
99  *   ... and set IWL_EVT_DISABLE to 1. */
100 void iwl3945_disable_events(struct iwl_priv *priv)
101 {
102         int i;
103         u32 base;               /* SRAM address of event log header */
104         u32 disable_ptr;        /* SRAM address of event-disable bitmap array */
105         u32 array_size;         /* # of u32 entries in array */
106         u32 evt_disable[IWL_EVT_DISABLE_SIZE] = {
107                 0x00000000,     /*   31 -    0  Event id numbers */
108                 0x00000000,     /*   63 -   32 */
109                 0x00000000,     /*   95 -   64 */
110                 0x00000000,     /*  127 -   96 */
111                 0x00000000,     /*  159 -  128 */
112                 0x00000000,     /*  191 -  160 */
113                 0x00000000,     /*  223 -  192 */
114                 0x00000000,     /*  255 -  224 */
115                 0x00000000,     /*  287 -  256 */
116                 0x00000000,     /*  319 -  288 */
117                 0x00000000,     /*  351 -  320 */
118                 0x00000000,     /*  383 -  352 */
119                 0x00000000,     /*  415 -  384 */
120                 0x00000000,     /*  447 -  416 */
121                 0x00000000,     /*  479 -  448 */
122                 0x00000000,     /*  511 -  480 */
123                 0x00000000,     /*  543 -  512 */
124                 0x00000000,     /*  575 -  544 */
125                 0x00000000,     /*  607 -  576 */
126                 0x00000000,     /*  639 -  608 */
127                 0x00000000,     /*  671 -  640 */
128                 0x00000000,     /*  703 -  672 */
129                 0x00000000,     /*  735 -  704 */
130                 0x00000000,     /*  767 -  736 */
131                 0x00000000,     /*  799 -  768 */
132                 0x00000000,     /*  831 -  800 */
133                 0x00000000,     /*  863 -  832 */
134                 0x00000000,     /*  895 -  864 */
135                 0x00000000,     /*  927 -  896 */
136                 0x00000000,     /*  959 -  928 */
137                 0x00000000,     /*  991 -  960 */
138                 0x00000000,     /* 1023 -  992 */
139                 0x00000000,     /* 1055 - 1024 */
140                 0x00000000,     /* 1087 - 1056 */
141                 0x00000000,     /* 1119 - 1088 */
142                 0x00000000,     /* 1151 - 1120 */
143                 0x00000000,     /* 1183 - 1152 */
144                 0x00000000,     /* 1215 - 1184 */
145                 0x00000000,     /* 1247 - 1216 */
146                 0x00000000,     /* 1279 - 1248 */
147                 0x00000000,     /* 1311 - 1280 */
148                 0x00000000,     /* 1343 - 1312 */
149                 0x00000000,     /* 1375 - 1344 */
150                 0x00000000,     /* 1407 - 1376 */
151                 0x00000000,     /* 1439 - 1408 */
152                 0x00000000,     /* 1471 - 1440 */
153                 0x00000000,     /* 1503 - 1472 */
154         };
155
156         base = le32_to_cpu(priv->card_alive.log_event_table_ptr);
157         if (!iwl3945_hw_valid_rtc_data_addr(base)) {
158                 IWL_ERR(priv, "Invalid event log pointer 0x%08X\n", base);
159                 return;
160         }
161
162         disable_ptr = iwl_read_targ_mem(priv, base + (4 * sizeof(u32)));
163         array_size = iwl_read_targ_mem(priv, base + (5 * sizeof(u32)));
164
165         if (IWL_EVT_DISABLE && (array_size == IWL_EVT_DISABLE_SIZE)) {
166                 IWL_DEBUG_INFO(priv, "Disabling selected uCode log events at 0x%x\n",
167                                disable_ptr);
168                 for (i = 0; i < IWL_EVT_DISABLE_SIZE; i++)
169                         iwl_write_targ_mem(priv,
170                                            disable_ptr + (i * sizeof(u32)),
171                                            evt_disable[i]);
172
173         } else {
174                 IWL_DEBUG_INFO(priv, "Selected uCode log events may be disabled\n");
175                 IWL_DEBUG_INFO(priv, "  by writing \"1\"s into disable bitmap\n");
176                 IWL_DEBUG_INFO(priv, "  in SRAM at 0x%x, size %d u32s\n",
177                                disable_ptr, array_size);
178         }
179
180 }
181
182 static int iwl3945_hwrate_to_plcp_idx(u8 plcp)
183 {
184         int idx;
185
186         for (idx = 0; idx < IWL_RATE_COUNT; idx++)
187                 if (iwl3945_rates[idx].plcp == plcp)
188                         return idx;
189         return -1;
190 }
191
192 #ifdef CONFIG_IWLWIFI_DEBUG
193 #define TX_STATUS_ENTRY(x) case TX_STATUS_FAIL_ ## x: return #x
194
195 static const char *iwl3945_get_tx_fail_reason(u32 status)
196 {
197         switch (status & TX_STATUS_MSK) {
198         case TX_STATUS_SUCCESS:
199                 return "SUCCESS";
200                 TX_STATUS_ENTRY(SHORT_LIMIT);
201                 TX_STATUS_ENTRY(LONG_LIMIT);
202                 TX_STATUS_ENTRY(FIFO_UNDERRUN);
203                 TX_STATUS_ENTRY(MGMNT_ABORT);
204                 TX_STATUS_ENTRY(NEXT_FRAG);
205                 TX_STATUS_ENTRY(LIFE_EXPIRE);
206                 TX_STATUS_ENTRY(DEST_PS);
207                 TX_STATUS_ENTRY(ABORTED);
208                 TX_STATUS_ENTRY(BT_RETRY);
209                 TX_STATUS_ENTRY(STA_INVALID);
210                 TX_STATUS_ENTRY(FRAG_DROPPED);
211                 TX_STATUS_ENTRY(TID_DISABLE);
212                 TX_STATUS_ENTRY(FRAME_FLUSHED);
213                 TX_STATUS_ENTRY(INSUFFICIENT_CF_POLL);
214                 TX_STATUS_ENTRY(TX_LOCKED);
215                 TX_STATUS_ENTRY(NO_BEACON_ON_RADAR);
216         }
217
218         return "UNKNOWN";
219 }
220 #else
221 static inline const char *iwl3945_get_tx_fail_reason(u32 status)
222 {
223         return "";
224 }
225 #endif
226
227 /*
228  * get ieee prev rate from rate scale table.
229  * for A and B mode we need to overright prev
230  * value
231  */
232 int iwl3945_rs_next_rate(struct iwl_priv *priv, int rate)
233 {
234         int next_rate = iwl3945_get_prev_ieee_rate(rate);
235
236         switch (priv->band) {
237         case IEEE80211_BAND_5GHZ:
238                 if (rate == IWL_RATE_12M_INDEX)
239                         next_rate = IWL_RATE_9M_INDEX;
240                 else if (rate == IWL_RATE_6M_INDEX)
241                         next_rate = IWL_RATE_6M_INDEX;
242                 break;
243         case IEEE80211_BAND_2GHZ:
244                 if (!(priv->sta_supp_rates & IWL_OFDM_RATES_MASK) &&
245                     iwl_is_associated(priv)) {
246                         if (rate == IWL_RATE_11M_INDEX)
247                                 next_rate = IWL_RATE_5M_INDEX;
248                 }
249                 break;
250
251         default:
252                 break;
253         }
254
255         return next_rate;
256 }
257
258
259 /**
260  * iwl3945_tx_queue_reclaim - Reclaim Tx queue entries already Tx'd
261  *
262  * When FW advances 'R' index, all entries between old and new 'R' index
263  * need to be reclaimed. As result, some free space forms. If there is
264  * enough free space (> low mark), wake the stack that feeds us.
265  */
266 static void iwl3945_tx_queue_reclaim(struct iwl_priv *priv,
267                                      int txq_id, int index)
268 {
269         struct iwl_tx_queue *txq = &priv->txq[txq_id];
270         struct iwl_queue *q = &txq->q;
271         struct iwl_tx_info *tx_info;
272
273         BUG_ON(txq_id == IWL_CMD_QUEUE_NUM);
274
275         for (index = iwl_queue_inc_wrap(index, q->n_bd); q->read_ptr != index;
276                 q->read_ptr = iwl_queue_inc_wrap(q->read_ptr, q->n_bd)) {
277
278                 tx_info = &txq->txb[txq->q.read_ptr];
279                 ieee80211_tx_status_irqsafe(priv->hw, tx_info->skb[0]);
280                 tx_info->skb[0] = NULL;
281                 priv->cfg->ops->lib->txq_free_tfd(priv, txq);
282         }
283
284         if (iwl_queue_space(q) > q->low_mark && (txq_id >= 0) &&
285                         (txq_id != IWL_CMD_QUEUE_NUM) &&
286                         priv->mac80211_registered)
287                 iwl_wake_queue(priv, txq_id);
288 }
289
290 /**
291  * iwl3945_rx_reply_tx - Handle Tx response
292  */
293 static void iwl3945_rx_reply_tx(struct iwl_priv *priv,
294                             struct iwl_rx_mem_buffer *rxb)
295 {
296         struct iwl_rx_packet *pkt = (void *)rxb->skb->data;
297         u16 sequence = le16_to_cpu(pkt->hdr.sequence);
298         int txq_id = SEQ_TO_QUEUE(sequence);
299         int index = SEQ_TO_INDEX(sequence);
300         struct iwl_tx_queue *txq = &priv->txq[txq_id];
301         struct ieee80211_tx_info *info;
302         struct iwl3945_tx_resp *tx_resp = (void *)&pkt->u.raw[0];
303         u32  status = le32_to_cpu(tx_resp->status);
304         int rate_idx;
305         int fail;
306
307         if ((index >= txq->q.n_bd) || (iwl_queue_used(&txq->q, index) == 0)) {
308                 IWL_ERR(priv, "Read index for DMA queue txq_id (%d) index %d "
309                           "is out of range [0-%d] %d %d\n", txq_id,
310                           index, txq->q.n_bd, txq->q.write_ptr,
311                           txq->q.read_ptr);
312                 return;
313         }
314
315         info = IEEE80211_SKB_CB(txq->txb[txq->q.read_ptr].skb[0]);
316         ieee80211_tx_info_clear_status(info);
317
318         /* Fill the MRR chain with some info about on-chip retransmissions */
319         rate_idx = iwl3945_hwrate_to_plcp_idx(tx_resp->rate);
320         if (info->band == IEEE80211_BAND_5GHZ)
321                 rate_idx -= IWL_FIRST_OFDM_RATE;
322
323         fail = tx_resp->failure_frame;
324
325         info->status.rates[0].idx = rate_idx;
326         info->status.rates[0].count = fail + 1; /* add final attempt */
327
328         /* tx_status->rts_retry_count = tx_resp->failure_rts; */
329         info->flags |= ((status & TX_STATUS_MSK) == TX_STATUS_SUCCESS) ?
330                                 IEEE80211_TX_STAT_ACK : 0;
331
332         IWL_DEBUG_TX(priv, "Tx queue %d Status %s (0x%08x) plcp rate %d retries %d\n",
333                         txq_id, iwl3945_get_tx_fail_reason(status), status,
334                         tx_resp->rate, tx_resp->failure_frame);
335
336         IWL_DEBUG_TX_REPLY(priv, "Tx queue reclaim %d\n", index);
337         iwl3945_tx_queue_reclaim(priv, txq_id, index);
338
339         if (iwl_check_bits(status, TX_ABORT_REQUIRED_MSK))
340                 IWL_ERR(priv, "TODO:  Implement Tx ABORT REQUIRED!!!\n");
341 }
342
343
344
345 /*****************************************************************************
346  *
347  * Intel PRO/Wireless 3945ABG/BG Network Connection
348  *
349  *  RX handler implementations
350  *
351  *****************************************************************************/
352
353 void iwl3945_hw_rx_statistics(struct iwl_priv *priv,
354                 struct iwl_rx_mem_buffer *rxb)
355 {
356         struct iwl_rx_packet *pkt = (void *)rxb->skb->data;
357         IWL_DEBUG_RX(priv, "Statistics notification received (%d vs %d).\n",
358                      (int)sizeof(struct iwl3945_notif_statistics),
359                      le32_to_cpu(pkt->len_n_flags) & FH_RSCSR_FRAME_SIZE_MSK);
360
361         memcpy(&priv->statistics_39, pkt->u.raw, sizeof(priv->statistics_39));
362
363         iwl_leds_background(priv);
364
365         priv->last_statistics_time = jiffies;
366 }
367
368 /******************************************************************************
369  *
370  * Misc. internal state and helper functions
371  *
372  ******************************************************************************/
373 #ifdef CONFIG_IWLWIFI_DEBUG
374
375 /**
376  * iwl3945_report_frame - dump frame to syslog during debug sessions
377  *
378  * You may hack this function to show different aspects of received frames,
379  * including selective frame dumps.
380  * group100 parameter selects whether to show 1 out of 100 good frames.
381  */
382 static void _iwl3945_dbg_report_frame(struct iwl_priv *priv,
383                       struct iwl_rx_packet *pkt,
384                       struct ieee80211_hdr *header, int group100)
385 {
386         u32 to_us;
387         u32 print_summary = 0;
388         u32 print_dump = 0;     /* set to 1 to dump all frames' contents */
389         u32 hundred = 0;
390         u32 dataframe = 0;
391         __le16 fc;
392         u16 seq_ctl;
393         u16 channel;
394         u16 phy_flags;
395         u16 length;
396         u16 status;
397         u16 bcn_tmr;
398         u32 tsf_low;
399         u64 tsf;
400         u8 rssi;
401         u8 agc;
402         u16 sig_avg;
403         u16 noise_diff;
404         struct iwl3945_rx_frame_stats *rx_stats = IWL_RX_STATS(pkt);
405         struct iwl3945_rx_frame_hdr *rx_hdr = IWL_RX_HDR(pkt);
406         struct iwl3945_rx_frame_end *rx_end = IWL_RX_END(pkt);
407         u8 *data = IWL_RX_DATA(pkt);
408
409         /* MAC header */
410         fc = header->frame_control;
411         seq_ctl = le16_to_cpu(header->seq_ctrl);
412
413         /* metadata */
414         channel = le16_to_cpu(rx_hdr->channel);
415         phy_flags = le16_to_cpu(rx_hdr->phy_flags);
416         length = le16_to_cpu(rx_hdr->len);
417
418         /* end-of-frame status and timestamp */
419         status = le32_to_cpu(rx_end->status);
420         bcn_tmr = le32_to_cpu(rx_end->beacon_timestamp);
421         tsf_low = le64_to_cpu(rx_end->timestamp) & 0x0ffffffff;
422         tsf = le64_to_cpu(rx_end->timestamp);
423
424         /* signal statistics */
425         rssi = rx_stats->rssi;
426         agc = rx_stats->agc;
427         sig_avg = le16_to_cpu(rx_stats->sig_avg);
428         noise_diff = le16_to_cpu(rx_stats->noise_diff);
429
430         to_us = !compare_ether_addr(header->addr1, priv->mac_addr);
431
432         /* if data frame is to us and all is good,
433          *   (optionally) print summary for only 1 out of every 100 */
434         if (to_us && (fc & ~cpu_to_le16(IEEE80211_FCTL_PROTECTED)) ==
435             cpu_to_le16(IEEE80211_FCTL_FROMDS | IEEE80211_FTYPE_DATA)) {
436                 dataframe = 1;
437                 if (!group100)
438                         print_summary = 1;      /* print each frame */
439                 else if (priv->framecnt_to_us < 100) {
440                         priv->framecnt_to_us++;
441                         print_summary = 0;
442                 } else {
443                         priv->framecnt_to_us = 0;
444                         print_summary = 1;
445                         hundred = 1;
446                 }
447         } else {
448                 /* print summary for all other frames */
449                 print_summary = 1;
450         }
451
452         if (print_summary) {
453                 char *title;
454                 int rate;
455
456                 if (hundred)
457                         title = "100Frames";
458                 else if (ieee80211_has_retry(fc))
459                         title = "Retry";
460                 else if (ieee80211_is_assoc_resp(fc))
461                         title = "AscRsp";
462                 else if (ieee80211_is_reassoc_resp(fc))
463                         title = "RasRsp";
464                 else if (ieee80211_is_probe_resp(fc)) {
465                         title = "PrbRsp";
466                         print_dump = 1; /* dump frame contents */
467                 } else if (ieee80211_is_beacon(fc)) {
468                         title = "Beacon";
469                         print_dump = 1; /* dump frame contents */
470                 } else if (ieee80211_is_atim(fc))
471                         title = "ATIM";
472                 else if (ieee80211_is_auth(fc))
473                         title = "Auth";
474                 else if (ieee80211_is_deauth(fc))
475                         title = "DeAuth";
476                 else if (ieee80211_is_disassoc(fc))
477                         title = "DisAssoc";
478                 else
479                         title = "Frame";
480
481                 rate = iwl3945_hwrate_to_plcp_idx(rx_hdr->rate);
482                 if (rate == -1)
483                         rate = 0;
484                 else
485                         rate = iwl3945_rates[rate].ieee / 2;
486
487                 /* print frame summary.
488                  * MAC addresses show just the last byte (for brevity),
489                  *    but you can hack it to show more, if you'd like to. */
490                 if (dataframe)
491                         IWL_DEBUG_RX(priv, "%s: mhd=0x%04x, dst=0x%02x, "
492                                      "len=%u, rssi=%d, chnl=%d, rate=%d, \n",
493                                      title, le16_to_cpu(fc), header->addr1[5],
494                                      length, rssi, channel, rate);
495                 else {
496                         /* src/dst addresses assume managed mode */
497                         IWL_DEBUG_RX(priv, "%s: 0x%04x, dst=0x%02x, "
498                                      "src=0x%02x, rssi=%u, tim=%lu usec, "
499                                      "phy=0x%02x, chnl=%d\n",
500                                      title, le16_to_cpu(fc), header->addr1[5],
501                                      header->addr3[5], rssi,
502                                      tsf_low - priv->scan_start_tsf,
503                                      phy_flags, channel);
504                 }
505         }
506         if (print_dump)
507                 iwl_print_hex_dump(priv, IWL_DL_RX, data, length);
508 }
509
510 static void iwl3945_dbg_report_frame(struct iwl_priv *priv,
511                       struct iwl_rx_packet *pkt,
512                       struct ieee80211_hdr *header, int group100)
513 {
514         if (iwl_get_debug_level(priv) & IWL_DL_RX)
515                 _iwl3945_dbg_report_frame(priv, pkt, header, group100);
516 }
517
518 #else
519 static inline void iwl3945_dbg_report_frame(struct iwl_priv *priv,
520                       struct iwl_rx_packet *pkt,
521                       struct ieee80211_hdr *header, int group100)
522 {
523 }
524 #endif
525
526 /* This is necessary only for a number of statistics, see the caller. */
527 static int iwl3945_is_network_packet(struct iwl_priv *priv,
528                 struct ieee80211_hdr *header)
529 {
530         /* Filter incoming packets to determine if they are targeted toward
531          * this network, discarding packets coming from ourselves */
532         switch (priv->iw_mode) {
533         case NL80211_IFTYPE_ADHOC: /* Header: Dest. | Source    | BSSID */
534                 /* packets to our IBSS update information */
535                 return !compare_ether_addr(header->addr3, priv->bssid);
536         case NL80211_IFTYPE_STATION: /* Header: Dest. | AP{BSSID} | Source */
537                 /* packets to our IBSS update information */
538                 return !compare_ether_addr(header->addr2, priv->bssid);
539         default:
540                 return 1;
541         }
542 }
543
544 static void iwl3945_pass_packet_to_mac80211(struct iwl_priv *priv,
545                                    struct iwl_rx_mem_buffer *rxb,
546                                    struct ieee80211_rx_status *stats)
547 {
548         struct iwl_rx_packet *pkt = (struct iwl_rx_packet *)rxb->skb->data;
549         struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)IWL_RX_DATA(pkt);
550         struct iwl3945_rx_frame_hdr *rx_hdr = IWL_RX_HDR(pkt);
551         struct iwl3945_rx_frame_end *rx_end = IWL_RX_END(pkt);
552         short len = le16_to_cpu(rx_hdr->len);
553
554         /* We received data from the HW, so stop the watchdog */
555         if (unlikely((len + IWL39_RX_FRAME_SIZE) > skb_tailroom(rxb->skb))) {
556                 IWL_DEBUG_DROP(priv, "Corruption detected!\n");
557                 return;
558         }
559
560         /* We only process data packets if the interface is open */
561         if (unlikely(!priv->is_open)) {
562                 IWL_DEBUG_DROP_LIMIT(priv,
563                         "Dropping packet while interface is not open.\n");
564                 return;
565         }
566
567         skb_reserve(rxb->skb, (void *)rx_hdr->payload - (void *)pkt);
568         /* Set the size of the skb to the size of the frame */
569         skb_put(rxb->skb, le16_to_cpu(rx_hdr->len));
570
571         if (!iwl3945_mod_params.sw_crypto)
572                 iwl_set_decrypted_flag(priv,
573                                        (struct ieee80211_hdr *)rxb->skb->data,
574                                        le32_to_cpu(rx_end->status), stats);
575
576         iwl_update_stats(priv, false, hdr->frame_control, len);
577
578         memcpy(IEEE80211_SKB_RXCB(rxb->skb), stats, sizeof(*stats));
579         ieee80211_rx_irqsafe(priv->hw, rxb->skb);
580         rxb->skb = NULL;
581 }
582
583 #define IWL_DELAY_NEXT_SCAN_AFTER_ASSOC (HZ*6)
584
585 static void iwl3945_rx_reply_rx(struct iwl_priv *priv,
586                                 struct iwl_rx_mem_buffer *rxb)
587 {
588         struct ieee80211_hdr *header;
589         struct ieee80211_rx_status rx_status;
590         struct iwl_rx_packet *pkt = (void *)rxb->skb->data;
591         struct iwl3945_rx_frame_stats *rx_stats = IWL_RX_STATS(pkt);
592         struct iwl3945_rx_frame_hdr *rx_hdr = IWL_RX_HDR(pkt);
593         struct iwl3945_rx_frame_end *rx_end = IWL_RX_END(pkt);
594         int snr;
595         u16 rx_stats_sig_avg = le16_to_cpu(rx_stats->sig_avg);
596         u16 rx_stats_noise_diff = le16_to_cpu(rx_stats->noise_diff);
597         u8 network_packet;
598
599         rx_status.flag = 0;
600         rx_status.mactime = le64_to_cpu(rx_end->timestamp);
601         rx_status.freq =
602                 ieee80211_channel_to_frequency(le16_to_cpu(rx_hdr->channel));
603         rx_status.band = (rx_hdr->phy_flags & RX_RES_PHY_FLAGS_BAND_24_MSK) ?
604                                 IEEE80211_BAND_2GHZ : IEEE80211_BAND_5GHZ;
605
606         rx_status.rate_idx = iwl3945_hwrate_to_plcp_idx(rx_hdr->rate);
607         if (rx_status.band == IEEE80211_BAND_5GHZ)
608                 rx_status.rate_idx -= IWL_FIRST_OFDM_RATE;
609
610         rx_status.antenna = (le16_to_cpu(rx_hdr->phy_flags) &
611                                         RX_RES_PHY_FLAGS_ANTENNA_MSK) >> 4;
612
613         /* set the preamble flag if appropriate */
614         if (rx_hdr->phy_flags & RX_RES_PHY_FLAGS_SHORT_PREAMBLE_MSK)
615                 rx_status.flag |= RX_FLAG_SHORTPRE;
616
617         if ((unlikely(rx_stats->phy_count > 20))) {
618                 IWL_DEBUG_DROP(priv, "dsp size out of range [0,20]: %d/n",
619                                 rx_stats->phy_count);
620                 return;
621         }
622
623         if (!(rx_end->status & RX_RES_STATUS_NO_CRC32_ERROR)
624             || !(rx_end->status & RX_RES_STATUS_NO_RXE_OVERFLOW)) {
625                 IWL_DEBUG_RX(priv, "Bad CRC or FIFO: 0x%08X.\n", rx_end->status);
626                 return;
627         }
628
629
630
631         /* Convert 3945's rssi indicator to dBm */
632         rx_status.signal = rx_stats->rssi - IWL39_RSSI_OFFSET;
633
634         /* Set default noise value to -127 */
635         if (priv->last_rx_noise == 0)
636                 priv->last_rx_noise = IWL_NOISE_MEAS_NOT_AVAILABLE;
637
638         /* 3945 provides noise info for OFDM frames only.
639          * sig_avg and noise_diff are measured by the 3945's digital signal
640          *   processor (DSP), and indicate linear levels of signal level and
641          *   distortion/noise within the packet preamble after
642          *   automatic gain control (AGC).  sig_avg should stay fairly
643          *   constant if the radio's AGC is working well.
644          * Since these values are linear (not dB or dBm), linear
645          *   signal-to-noise ratio (SNR) is (sig_avg / noise_diff).
646          * Convert linear SNR to dB SNR, then subtract that from rssi dBm
647          *   to obtain noise level in dBm.
648          * Calculate rx_status.signal (quality indicator in %) based on SNR. */
649         if (rx_stats_noise_diff) {
650                 snr = rx_stats_sig_avg / rx_stats_noise_diff;
651                 rx_status.noise = rx_status.signal -
652                                         iwl3945_calc_db_from_ratio(snr);
653                 rx_status.qual = iwl3945_calc_sig_qual(rx_status.signal,
654                                                          rx_status.noise);
655
656         /* If noise info not available, calculate signal quality indicator (%)
657          *   using just the dBm signal level. */
658         } else {
659                 rx_status.noise = priv->last_rx_noise;
660                 rx_status.qual = iwl3945_calc_sig_qual(rx_status.signal, 0);
661         }
662
663
664         IWL_DEBUG_STATS(priv, "Rssi %d noise %d qual %d sig_avg %d noise_diff %d\n",
665                         rx_status.signal, rx_status.noise, rx_status.qual,
666                         rx_stats_sig_avg, rx_stats_noise_diff);
667
668         header = (struct ieee80211_hdr *)IWL_RX_DATA(pkt);
669
670         network_packet = iwl3945_is_network_packet(priv, header);
671
672         IWL_DEBUG_STATS_LIMIT(priv, "[%c] %d RSSI:%d Signal:%u, Noise:%u, Rate:%u\n",
673                               network_packet ? '*' : ' ',
674                               le16_to_cpu(rx_hdr->channel),
675                               rx_status.signal, rx_status.signal,
676                               rx_status.noise, rx_status.rate_idx);
677
678         /* Set "1" to report good data frames in groups of 100 */
679         iwl3945_dbg_report_frame(priv, pkt, header, 1);
680         iwl_dbg_log_rx_data_frame(priv, le16_to_cpu(rx_hdr->len), header);
681
682         if (network_packet) {
683                 priv->last_beacon_time = le32_to_cpu(rx_end->beacon_timestamp);
684                 priv->last_tsf = le64_to_cpu(rx_end->timestamp);
685                 priv->last_rx_rssi = rx_status.signal;
686                 priv->last_rx_noise = rx_status.noise;
687         }
688
689         iwl3945_pass_packet_to_mac80211(priv, rxb, &rx_status);
690 }
691
692 int iwl3945_hw_txq_attach_buf_to_tfd(struct iwl_priv *priv,
693                                      struct iwl_tx_queue *txq,
694                                      dma_addr_t addr, u16 len, u8 reset, u8 pad)
695 {
696         int count;
697         struct iwl_queue *q;
698         struct iwl3945_tfd *tfd, *tfd_tmp;
699
700         q = &txq->q;
701         tfd_tmp = (struct iwl3945_tfd *)txq->tfds;
702         tfd = &tfd_tmp[q->write_ptr];
703
704         if (reset)
705                 memset(tfd, 0, sizeof(*tfd));
706
707         count = TFD_CTL_COUNT_GET(le32_to_cpu(tfd->control_flags));
708
709         if ((count >= NUM_TFD_CHUNKS) || (count < 0)) {
710                 IWL_ERR(priv, "Error can not send more than %d chunks\n",
711                           NUM_TFD_CHUNKS);
712                 return -EINVAL;
713         }
714
715         tfd->tbs[count].addr = cpu_to_le32(addr);
716         tfd->tbs[count].len = cpu_to_le32(len);
717
718         count++;
719
720         tfd->control_flags = cpu_to_le32(TFD_CTL_COUNT_SET(count) |
721                                          TFD_CTL_PAD_SET(pad));
722
723         return 0;
724 }
725
726 /**
727  * iwl3945_hw_txq_free_tfd - Free one TFD, those at index [txq->q.read_ptr]
728  *
729  * Does NOT advance any indexes
730  */
731 void iwl3945_hw_txq_free_tfd(struct iwl_priv *priv, struct iwl_tx_queue *txq)
732 {
733         struct iwl3945_tfd *tfd_tmp = (struct iwl3945_tfd *)txq->tfds;
734         int index = txq->q.read_ptr;
735         struct iwl3945_tfd *tfd = &tfd_tmp[index];
736         struct pci_dev *dev = priv->pci_dev;
737         int i;
738         int counter;
739
740         /* sanity check */
741         counter = TFD_CTL_COUNT_GET(le32_to_cpu(tfd->control_flags));
742         if (counter > NUM_TFD_CHUNKS) {
743                 IWL_ERR(priv, "Too many chunks: %i\n", counter);
744                 /* @todo issue fatal error, it is quite serious situation */
745                 return;
746         }
747
748         /* Unmap tx_cmd */
749         if (counter)
750                 pci_unmap_single(dev,
751                                 pci_unmap_addr(&txq->meta[index], mapping),
752                                 pci_unmap_len(&txq->meta[index], len),
753                                 PCI_DMA_TODEVICE);
754
755         /* unmap chunks if any */
756
757         for (i = 1; i < counter; i++) {
758                 pci_unmap_single(dev, le32_to_cpu(tfd->tbs[i].addr),
759                          le32_to_cpu(tfd->tbs[i].len), PCI_DMA_TODEVICE);
760                 if (txq->txb[txq->q.read_ptr].skb[0]) {
761                         struct sk_buff *skb = txq->txb[txq->q.read_ptr].skb[0];
762                         if (txq->txb[txq->q.read_ptr].skb[0]) {
763                                 /* Can be called from interrupt context */
764                                 dev_kfree_skb_any(skb);
765                                 txq->txb[txq->q.read_ptr].skb[0] = NULL;
766                         }
767                 }
768         }
769         return ;
770 }
771
772 /**
773  * iwl3945_hw_build_tx_cmd_rate - Add rate portion to TX_CMD:
774  *
775 */
776 void iwl3945_hw_build_tx_cmd_rate(struct iwl_priv *priv,
777                                   struct iwl_device_cmd *cmd,
778                                   struct ieee80211_tx_info *info,
779                                   struct ieee80211_hdr *hdr,
780                                   int sta_id, int tx_id)
781 {
782         u16 hw_value = ieee80211_get_tx_rate(priv->hw, info)->hw_value;
783         u16 rate_index = min(hw_value & 0xffff, IWL_RATE_COUNT - 1);
784         u16 rate_mask;
785         int rate;
786         u8 rts_retry_limit;
787         u8 data_retry_limit;
788         __le32 tx_flags;
789         __le16 fc = hdr->frame_control;
790         struct iwl3945_tx_cmd *tx = (struct iwl3945_tx_cmd *)cmd->cmd.payload;
791
792         rate = iwl3945_rates[rate_index].plcp;
793         tx_flags = tx->tx_flags;
794
795         /* We need to figure out how to get the sta->supp_rates while
796          * in this running context */
797         rate_mask = IWL_RATES_MASK;
798
799         if (tx_id >= IWL_CMD_QUEUE_NUM)
800                 rts_retry_limit = 3;
801         else
802                 rts_retry_limit = 7;
803
804         if (ieee80211_is_probe_resp(fc)) {
805                 data_retry_limit = 3;
806                 if (data_retry_limit < rts_retry_limit)
807                         rts_retry_limit = data_retry_limit;
808         } else
809                 data_retry_limit = IWL_DEFAULT_TX_RETRY;
810
811         if (priv->data_retry_limit != -1)
812                 data_retry_limit = priv->data_retry_limit;
813
814         if (ieee80211_is_mgmt(fc)) {
815                 switch (fc & cpu_to_le16(IEEE80211_FCTL_STYPE)) {
816                 case cpu_to_le16(IEEE80211_STYPE_AUTH):
817                 case cpu_to_le16(IEEE80211_STYPE_DEAUTH):
818                 case cpu_to_le16(IEEE80211_STYPE_ASSOC_REQ):
819                 case cpu_to_le16(IEEE80211_STYPE_REASSOC_REQ):
820                         if (tx_flags & TX_CMD_FLG_RTS_MSK) {
821                                 tx_flags &= ~TX_CMD_FLG_RTS_MSK;
822                                 tx_flags |= TX_CMD_FLG_CTS_MSK;
823                         }
824                         break;
825                 default:
826                         break;
827                 }
828         }
829
830         tx->rts_retry_limit = rts_retry_limit;
831         tx->data_retry_limit = data_retry_limit;
832         tx->rate = rate;
833         tx->tx_flags = tx_flags;
834
835         /* OFDM */
836         tx->supp_rates[0] =
837            ((rate_mask & IWL_OFDM_RATES_MASK) >> IWL_FIRST_OFDM_RATE) & 0xFF;
838
839         /* CCK */
840         tx->supp_rates[1] = (rate_mask & 0xF);
841
842         IWL_DEBUG_RATE(priv, "Tx sta id: %d, rate: %d (plcp), flags: 0x%4X "
843                        "cck/ofdm mask: 0x%x/0x%x\n", sta_id,
844                        tx->rate, le32_to_cpu(tx->tx_flags),
845                        tx->supp_rates[1], tx->supp_rates[0]);
846 }
847
848 u8 iwl3945_sync_sta(struct iwl_priv *priv, int sta_id, u16 tx_rate, u8 flags)
849 {
850         unsigned long flags_spin;
851         struct iwl_station_entry *station;
852
853         if (sta_id == IWL_INVALID_STATION)
854                 return IWL_INVALID_STATION;
855
856         spin_lock_irqsave(&priv->sta_lock, flags_spin);
857         station = &priv->stations[sta_id];
858
859         station->sta.sta.modify_mask = STA_MODIFY_TX_RATE_MSK;
860         station->sta.rate_n_flags = cpu_to_le16(tx_rate);
861         station->sta.mode = STA_CONTROL_MODIFY_MSK;
862
863         spin_unlock_irqrestore(&priv->sta_lock, flags_spin);
864
865         iwl_send_add_sta(priv, &station->sta, flags);
866         IWL_DEBUG_RATE(priv, "SCALE sync station %d to rate %d\n",
867                         sta_id, tx_rate);
868         return sta_id;
869 }
870
871 static int iwl3945_set_pwr_src(struct iwl_priv *priv, enum iwl_pwr_src src)
872 {
873         if (src == IWL_PWR_SRC_VAUX) {
874                 if (pci_pme_capable(priv->pci_dev, PCI_D3cold)) {
875                         iwl_set_bits_mask_prph(priv, APMG_PS_CTRL_REG,
876                                         APMG_PS_CTRL_VAL_PWR_SRC_VAUX,
877                                         ~APMG_PS_CTRL_MSK_PWR_SRC);
878
879                         iwl_poll_bit(priv, CSR_GPIO_IN,
880                                      CSR_GPIO_IN_VAL_VAUX_PWR_SRC,
881                                      CSR_GPIO_IN_BIT_AUX_POWER, 5000);
882                 }
883         } else {
884                 iwl_set_bits_mask_prph(priv, APMG_PS_CTRL_REG,
885                                 APMG_PS_CTRL_VAL_PWR_SRC_VMAIN,
886                                 ~APMG_PS_CTRL_MSK_PWR_SRC);
887
888                 iwl_poll_bit(priv, CSR_GPIO_IN, CSR_GPIO_IN_VAL_VMAIN_PWR_SRC,
889                              CSR_GPIO_IN_BIT_AUX_POWER, 5000);  /* uS */
890         }
891
892         return 0;
893 }
894
895 static int iwl3945_rx_init(struct iwl_priv *priv, struct iwl_rx_queue *rxq)
896 {
897         iwl_write_direct32(priv, FH39_RCSR_RBD_BASE(0), rxq->dma_addr);
898         iwl_write_direct32(priv, FH39_RCSR_RPTR_ADDR(0), rxq->rb_stts_dma);
899         iwl_write_direct32(priv, FH39_RCSR_WPTR(0), 0);
900         iwl_write_direct32(priv, FH39_RCSR_CONFIG(0),
901                 FH39_RCSR_RX_CONFIG_REG_VAL_DMA_CHNL_EN_ENABLE |
902                 FH39_RCSR_RX_CONFIG_REG_VAL_RDRBD_EN_ENABLE |
903                 FH39_RCSR_RX_CONFIG_REG_BIT_WR_STTS_EN |
904                 FH39_RCSR_RX_CONFIG_REG_VAL_MAX_FRAG_SIZE_128 |
905                 (RX_QUEUE_SIZE_LOG << FH39_RCSR_RX_CONFIG_REG_POS_RBDC_SIZE) |
906                 FH39_RCSR_RX_CONFIG_REG_VAL_IRQ_DEST_INT_HOST |
907                 (1 << FH39_RCSR_RX_CONFIG_REG_POS_IRQ_RBTH) |
908                 FH39_RCSR_RX_CONFIG_REG_VAL_MSG_MODE_FH);
909
910         /* fake read to flush all prev I/O */
911         iwl_read_direct32(priv, FH39_RSSR_CTRL);
912
913         return 0;
914 }
915
916 static int iwl3945_tx_reset(struct iwl_priv *priv)
917 {
918
919         /* bypass mode */
920         iwl_write_prph(priv, ALM_SCD_MODE_REG, 0x2);
921
922         /* RA 0 is active */
923         iwl_write_prph(priv, ALM_SCD_ARASTAT_REG, 0x01);
924
925         /* all 6 fifo are active */
926         iwl_write_prph(priv, ALM_SCD_TXFACT_REG, 0x3f);
927
928         iwl_write_prph(priv, ALM_SCD_SBYP_MODE_1_REG, 0x010000);
929         iwl_write_prph(priv, ALM_SCD_SBYP_MODE_2_REG, 0x030002);
930         iwl_write_prph(priv, ALM_SCD_TXF4MF_REG, 0x000004);
931         iwl_write_prph(priv, ALM_SCD_TXF5MF_REG, 0x000005);
932
933         iwl_write_direct32(priv, FH39_TSSR_CBB_BASE,
934                              priv->shared_phys);
935
936         iwl_write_direct32(priv, FH39_TSSR_MSG_CONFIG,
937                 FH39_TSSR_TX_MSG_CONFIG_REG_VAL_SNOOP_RD_TXPD_ON |
938                 FH39_TSSR_TX_MSG_CONFIG_REG_VAL_ORDER_RD_TXPD_ON |
939                 FH39_TSSR_TX_MSG_CONFIG_REG_VAL_MAX_FRAG_SIZE_128B |
940                 FH39_TSSR_TX_MSG_CONFIG_REG_VAL_SNOOP_RD_TFD_ON |
941                 FH39_TSSR_TX_MSG_CONFIG_REG_VAL_ORDER_RD_CBB_ON |
942                 FH39_TSSR_TX_MSG_CONFIG_REG_VAL_ORDER_RSP_WAIT_TH |
943                 FH39_TSSR_TX_MSG_CONFIG_REG_VAL_RSP_WAIT_TH);
944
945
946         return 0;
947 }
948
949 /**
950  * iwl3945_txq_ctx_reset - Reset TX queue context
951  *
952  * Destroys all DMA structures and initialize them again
953  */
954 static int iwl3945_txq_ctx_reset(struct iwl_priv *priv)
955 {
956         int rc;
957         int txq_id, slots_num;
958
959         iwl3945_hw_txq_ctx_free(priv);
960
961         /* Tx CMD queue */
962         rc = iwl3945_tx_reset(priv);
963         if (rc)
964                 goto error;
965
966         /* Tx queue(s) */
967         for (txq_id = 0; txq_id < priv->hw_params.max_txq_num; txq_id++) {
968                 slots_num = (txq_id == IWL_CMD_QUEUE_NUM) ?
969                                 TFD_CMD_SLOTS : TFD_TX_CMD_SLOTS;
970                 rc = iwl_tx_queue_init(priv, &priv->txq[txq_id], slots_num,
971                                        txq_id);
972                 if (rc) {
973                         IWL_ERR(priv, "Tx %d queue init failed\n", txq_id);
974                         goto error;
975                 }
976         }
977
978         return rc;
979
980  error:
981         iwl3945_hw_txq_ctx_free(priv);
982         return rc;
983 }
984
985 /*
986  * Start up NIC's basic functionality after it has been reset
987  * (e.g. after platform boot, or shutdown via iwl3945_apm_stop())
988  * NOTE:  This does not load uCode nor start the embedded processor
989  */
990 static int iwl3945_apm_init(struct iwl_priv *priv)
991 {
992         int ret;
993
994         /* Configure chip clock phase-lock-loop */
995         iwl_set_bit(priv, CSR_ANA_PLL_CFG, CSR39_ANA_PLL_CFG_VAL);
996
997         /*
998          * Disable L0S exit timer (platform NMI Work/Around)
999          * (does this do anything on 3945, or just 4965 and beyond?)
1000          */
1001         iwl_set_bit(priv, CSR_GIO_CHICKEN_BITS,
1002                           CSR_GIO_CHICKEN_BITS_REG_BIT_DIS_L0S_EXIT_TIMER);
1003
1004         /* Disable L0s without affecting L1; don't wait for ICH (L0s bug W/A) */
1005         iwl_set_bit(priv, CSR_GIO_CHICKEN_BITS,
1006                           CSR_GIO_CHICKEN_BITS_REG_BIT_L1A_NO_L0S_RX);
1007
1008         /* Set FH wait threshold to maximum (HW error during stress W/A) */
1009         iwl_set_bit(priv, CSR_DBG_HPET_MEM_REG, CSR_DBG_HPET_MEM_REG_VAL);
1010
1011         /*
1012          * Set "initialization complete" bit to move adapter from
1013          * D0U* --> D0A* (powered-up active) state.
1014          */
1015         iwl_set_bit(priv, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
1016
1017         /*
1018          * Wait for clock stabilization; once stabilized, access to
1019          * device-internal resources is supported, e.g. iwl_write_prph()
1020          * and accesses to uCode SRAM.
1021          */
1022         ret = iwl_poll_bit(priv, CSR_GP_CNTRL,
1023                         CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
1024                         CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY, 25000);
1025         if (ret < 0) {
1026                 IWL_DEBUG_INFO(priv, "Failed to init the card\n");
1027                 goto out;
1028         }
1029
1030         /* Enable DMA and BSM clocks, wait for them to stabilize */
1031         iwl_write_prph(priv, APMG_CLK_CTRL_REG, APMG_CLK_VAL_DMA_CLK_RQT |
1032                                                 APMG_CLK_VAL_BSM_CLK_RQT);
1033         udelay(20);
1034
1035         /* Clear APMG (NIC's internal power management) interrupts */
1036         iwl_write_prph(priv, APMG_RTC_INT_MSK_REG, 0x0);
1037         iwl_write_prph(priv, APMG_RTC_INT_STT_REG, 0xFFFFFFFF);
1038
1039         /* Reset radio chip */
1040         iwl_set_bits_prph(priv, APMG_PS_CTRL_REG, APMG_PS_CTRL_VAL_RESET_REQ);
1041         udelay(5);
1042         iwl_clear_bits_prph(priv, APMG_PS_CTRL_REG, APMG_PS_CTRL_VAL_RESET_REQ);
1043
1044         /* Disable L1-Active */
1045         iwl_set_bits_prph(priv, APMG_PCIDEV_STT_REG,
1046                           APMG_PCIDEV_STT_VAL_L1_ACT_DIS);
1047
1048 out:
1049         return ret;
1050 }
1051
1052 static void iwl3945_nic_config(struct iwl_priv *priv)
1053 {
1054         struct iwl3945_eeprom *eeprom = (struct iwl3945_eeprom *)priv->eeprom;
1055         unsigned long flags;
1056         u8 rev_id = 0;
1057
1058         spin_lock_irqsave(&priv->lock, flags);
1059
1060         /* Determine HW type */
1061         pci_read_config_byte(priv->pci_dev, PCI_REVISION_ID, &rev_id);
1062
1063         IWL_DEBUG_INFO(priv, "HW Revision ID = 0x%X\n", rev_id);
1064
1065         if (rev_id & PCI_CFG_REV_ID_BIT_RTP)
1066                 IWL_DEBUG_INFO(priv, "RTP type \n");
1067         else if (rev_id & PCI_CFG_REV_ID_BIT_BASIC_SKU) {
1068                 IWL_DEBUG_INFO(priv, "3945 RADIO-MB type\n");
1069                 iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
1070                             CSR39_HW_IF_CONFIG_REG_BIT_3945_MB);
1071         } else {
1072                 IWL_DEBUG_INFO(priv, "3945 RADIO-MM type\n");
1073                 iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
1074                             CSR39_HW_IF_CONFIG_REG_BIT_3945_MM);
1075         }
1076
1077         if (EEPROM_SKU_CAP_OP_MODE_MRC == eeprom->sku_cap) {
1078                 IWL_DEBUG_INFO(priv, "SKU OP mode is mrc\n");
1079                 iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
1080                             CSR39_HW_IF_CONFIG_REG_BIT_SKU_MRC);
1081         } else
1082                 IWL_DEBUG_INFO(priv, "SKU OP mode is basic\n");
1083
1084         if ((eeprom->board_revision & 0xF0) == 0xD0) {
1085                 IWL_DEBUG_INFO(priv, "3945ABG revision is 0x%X\n",
1086                                eeprom->board_revision);
1087                 iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
1088                             CSR39_HW_IF_CONFIG_REG_BIT_BOARD_TYPE);
1089         } else {
1090                 IWL_DEBUG_INFO(priv, "3945ABG revision is 0x%X\n",
1091                                eeprom->board_revision);
1092                 iwl_clear_bit(priv, CSR_HW_IF_CONFIG_REG,
1093                               CSR39_HW_IF_CONFIG_REG_BIT_BOARD_TYPE);
1094         }
1095
1096         if (eeprom->almgor_m_version <= 1) {
1097                 iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
1098                             CSR39_HW_IF_CONFIG_REG_BITS_SILICON_TYPE_A);
1099                 IWL_DEBUG_INFO(priv, "Card M type A version is 0x%X\n",
1100                                eeprom->almgor_m_version);
1101         } else {
1102                 IWL_DEBUG_INFO(priv, "Card M type B version is 0x%X\n",
1103                                eeprom->almgor_m_version);
1104                 iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
1105                             CSR39_HW_IF_CONFIG_REG_BITS_SILICON_TYPE_B);
1106         }
1107         spin_unlock_irqrestore(&priv->lock, flags);
1108
1109         if (eeprom->sku_cap & EEPROM_SKU_CAP_SW_RF_KILL_ENABLE)
1110                 IWL_DEBUG_RF_KILL(priv, "SW RF KILL supported in EEPROM.\n");
1111
1112         if (eeprom->sku_cap & EEPROM_SKU_CAP_HW_RF_KILL_ENABLE)
1113                 IWL_DEBUG_RF_KILL(priv, "HW RF KILL supported in EEPROM.\n");
1114 }
1115
1116 int iwl3945_hw_nic_init(struct iwl_priv *priv)
1117 {
1118         int rc;
1119         unsigned long flags;
1120         struct iwl_rx_queue *rxq = &priv->rxq;
1121
1122         spin_lock_irqsave(&priv->lock, flags);
1123         priv->cfg->ops->lib->apm_ops.init(priv);
1124         spin_unlock_irqrestore(&priv->lock, flags);
1125
1126         rc = priv->cfg->ops->lib->apm_ops.set_pwr_src(priv, IWL_PWR_SRC_VMAIN);
1127         if (rc)
1128                 return rc;
1129
1130         priv->cfg->ops->lib->apm_ops.config(priv);
1131
1132         /* Allocate the RX queue, or reset if it is already allocated */
1133         if (!rxq->bd) {
1134                 rc = iwl_rx_queue_alloc(priv);
1135                 if (rc) {
1136                         IWL_ERR(priv, "Unable to initialize Rx queue\n");
1137                         return -ENOMEM;
1138                 }
1139         } else
1140                 iwl3945_rx_queue_reset(priv, rxq);
1141
1142         iwl3945_rx_replenish(priv);
1143
1144         iwl3945_rx_init(priv, rxq);
1145
1146
1147         /* Look at using this instead:
1148         rxq->need_update = 1;
1149         iwl_rx_queue_update_write_ptr(priv, rxq);
1150         */
1151
1152         iwl_write_direct32(priv, FH39_RCSR_WPTR(0), rxq->write & ~7);
1153
1154         rc = iwl3945_txq_ctx_reset(priv);
1155         if (rc)
1156                 return rc;
1157
1158         set_bit(STATUS_INIT, &priv->status);
1159
1160         return 0;
1161 }
1162
1163 /**
1164  * iwl3945_hw_txq_ctx_free - Free TXQ Context
1165  *
1166  * Destroy all TX DMA queues and structures
1167  */
1168 void iwl3945_hw_txq_ctx_free(struct iwl_priv *priv)
1169 {
1170         int txq_id;
1171
1172         /* Tx queues */
1173         for (txq_id = 0; txq_id < priv->hw_params.max_txq_num; txq_id++)
1174                 if (txq_id == IWL_CMD_QUEUE_NUM)
1175                         iwl_cmd_queue_free(priv);
1176                 else
1177                         iwl_tx_queue_free(priv, txq_id);
1178
1179 }
1180
1181 void iwl3945_hw_txq_ctx_stop(struct iwl_priv *priv)
1182 {
1183         int txq_id;
1184
1185         /* stop SCD */
1186         iwl_write_prph(priv, ALM_SCD_MODE_REG, 0);
1187
1188         /* reset TFD queues */
1189         for (txq_id = 0; txq_id < priv->hw_params.max_txq_num; txq_id++) {
1190                 iwl_write_direct32(priv, FH39_TCSR_CONFIG(txq_id), 0x0);
1191                 iwl_poll_direct_bit(priv, FH39_TSSR_TX_STATUS,
1192                                 FH39_TSSR_TX_STATUS_REG_MSK_CHNL_IDLE(txq_id),
1193                                 1000);
1194         }
1195
1196         iwl3945_hw_txq_ctx_free(priv);
1197 }
1198
1199 /**
1200  * iwl3945_hw_reg_adjust_power_by_temp
1201  * return index delta into power gain settings table
1202 */
1203 static int iwl3945_hw_reg_adjust_power_by_temp(int new_reading, int old_reading)
1204 {
1205         return (new_reading - old_reading) * (-11) / 100;
1206 }
1207
1208 /**
1209  * iwl3945_hw_reg_temp_out_of_range - Keep temperature in sane range
1210  */
1211 static inline int iwl3945_hw_reg_temp_out_of_range(int temperature)
1212 {
1213         return ((temperature < -260) || (temperature > 25)) ? 1 : 0;
1214 }
1215
1216 int iwl3945_hw_get_temperature(struct iwl_priv *priv)
1217 {
1218         return iwl_read32(priv, CSR_UCODE_DRV_GP2);
1219 }
1220
1221 /**
1222  * iwl3945_hw_reg_txpower_get_temperature
1223  * get the current temperature by reading from NIC
1224 */
1225 static int iwl3945_hw_reg_txpower_get_temperature(struct iwl_priv *priv)
1226 {
1227         struct iwl3945_eeprom *eeprom = (struct iwl3945_eeprom *)priv->eeprom;
1228         int temperature;
1229
1230         temperature = iwl3945_hw_get_temperature(priv);
1231
1232         /* driver's okay range is -260 to +25.
1233          *   human readable okay range is 0 to +285 */
1234         IWL_DEBUG_INFO(priv, "Temperature: %d\n", temperature + IWL_TEMP_CONVERT);
1235
1236         /* handle insane temp reading */
1237         if (iwl3945_hw_reg_temp_out_of_range(temperature)) {
1238                 IWL_ERR(priv, "Error bad temperature value  %d\n", temperature);
1239
1240                 /* if really really hot(?),
1241                  *   substitute the 3rd band/group's temp measured at factory */
1242                 if (priv->last_temperature > 100)
1243                         temperature = eeprom->groups[2].temperature;
1244                 else /* else use most recent "sane" value from driver */
1245                         temperature = priv->last_temperature;
1246         }
1247
1248         return temperature;     /* raw, not "human readable" */
1249 }
1250
1251 /* Adjust Txpower only if temperature variance is greater than threshold.
1252  *
1253  * Both are lower than older versions' 9 degrees */
1254 #define IWL_TEMPERATURE_LIMIT_TIMER   6
1255
1256 /**
1257  * is_temp_calib_needed - determines if new calibration is needed
1258  *
1259  * records new temperature in tx_mgr->temperature.
1260  * replaces tx_mgr->last_temperature *only* if calib needed
1261  *    (assumes caller will actually do the calibration!). */
1262 static int is_temp_calib_needed(struct iwl_priv *priv)
1263 {
1264         int temp_diff;
1265
1266         priv->temperature = iwl3945_hw_reg_txpower_get_temperature(priv);
1267         temp_diff = priv->temperature - priv->last_temperature;
1268
1269         /* get absolute value */
1270         if (temp_diff < 0) {
1271                 IWL_DEBUG_POWER(priv, "Getting cooler, delta %d,\n", temp_diff);
1272                 temp_diff = -temp_diff;
1273         } else if (temp_diff == 0)
1274                 IWL_DEBUG_POWER(priv, "Same temp,\n");
1275         else
1276                 IWL_DEBUG_POWER(priv, "Getting warmer, delta %d,\n", temp_diff);
1277
1278         /* if we don't need calibration, *don't* update last_temperature */
1279         if (temp_diff < IWL_TEMPERATURE_LIMIT_TIMER) {
1280                 IWL_DEBUG_POWER(priv, "Timed thermal calib not needed\n");
1281                 return 0;
1282         }
1283
1284         IWL_DEBUG_POWER(priv, "Timed thermal calib needed\n");
1285
1286         /* assume that caller will actually do calib ...
1287          *   update the "last temperature" value */
1288         priv->last_temperature = priv->temperature;
1289         return 1;
1290 }
1291
1292 #define IWL_MAX_GAIN_ENTRIES 78
1293 #define IWL_CCK_FROM_OFDM_POWER_DIFF  -5
1294 #define IWL_CCK_FROM_OFDM_INDEX_DIFF (10)
1295
1296 /* radio and DSP power table, each step is 1/2 dB.
1297  * 1st number is for RF analog gain, 2nd number is for DSP pre-DAC gain. */
1298 static struct iwl3945_tx_power power_gain_table[2][IWL_MAX_GAIN_ENTRIES] = {
1299         {
1300          {251, 127},            /* 2.4 GHz, highest power */
1301          {251, 127},
1302          {251, 127},
1303          {251, 127},
1304          {251, 125},
1305          {251, 110},
1306          {251, 105},
1307          {251, 98},
1308          {187, 125},
1309          {187, 115},
1310          {187, 108},
1311          {187, 99},
1312          {243, 119},
1313          {243, 111},
1314          {243, 105},
1315          {243, 97},
1316          {243, 92},
1317          {211, 106},
1318          {211, 100},
1319          {179, 120},
1320          {179, 113},
1321          {179, 107},
1322          {147, 125},
1323          {147, 119},
1324          {147, 112},
1325          {147, 106},
1326          {147, 101},
1327          {147, 97},
1328          {147, 91},
1329          {115, 107},
1330          {235, 121},
1331          {235, 115},
1332          {235, 109},
1333          {203, 127},
1334          {203, 121},
1335          {203, 115},
1336          {203, 108},
1337          {203, 102},
1338          {203, 96},
1339          {203, 92},
1340          {171, 110},
1341          {171, 104},
1342          {171, 98},
1343          {139, 116},
1344          {227, 125},
1345          {227, 119},
1346          {227, 113},
1347          {227, 107},
1348          {227, 101},
1349          {227, 96},
1350          {195, 113},
1351          {195, 106},
1352          {195, 102},
1353          {195, 95},
1354          {163, 113},
1355          {163, 106},
1356          {163, 102},
1357          {163, 95},
1358          {131, 113},
1359          {131, 106},
1360          {131, 102},
1361          {131, 95},
1362          {99, 113},
1363          {99, 106},
1364          {99, 102},
1365          {99, 95},
1366          {67, 113},
1367          {67, 106},
1368          {67, 102},
1369          {67, 95},
1370          {35, 113},
1371          {35, 106},
1372          {35, 102},
1373          {35, 95},
1374          {3, 113},
1375          {3, 106},
1376          {3, 102},
1377          {3, 95} },             /* 2.4 GHz, lowest power */
1378         {
1379          {251, 127},            /* 5.x GHz, highest power */
1380          {251, 120},
1381          {251, 114},
1382          {219, 119},
1383          {219, 101},
1384          {187, 113},
1385          {187, 102},
1386          {155, 114},
1387          {155, 103},
1388          {123, 117},
1389          {123, 107},
1390          {123, 99},
1391          {123, 92},
1392          {91, 108},
1393          {59, 125},
1394          {59, 118},
1395          {59, 109},
1396          {59, 102},
1397          {59, 96},
1398          {59, 90},
1399          {27, 104},
1400          {27, 98},
1401          {27, 92},
1402          {115, 118},
1403          {115, 111},
1404          {115, 104},
1405          {83, 126},
1406          {83, 121},
1407          {83, 113},
1408          {83, 105},
1409          {83, 99},
1410          {51, 118},
1411          {51, 111},
1412          {51, 104},
1413          {51, 98},
1414          {19, 116},
1415          {19, 109},
1416          {19, 102},
1417          {19, 98},
1418          {19, 93},
1419          {171, 113},
1420          {171, 107},
1421          {171, 99},
1422          {139, 120},
1423          {139, 113},
1424          {139, 107},
1425          {139, 99},
1426          {107, 120},
1427          {107, 113},
1428          {107, 107},
1429          {107, 99},
1430          {75, 120},
1431          {75, 113},
1432          {75, 107},
1433          {75, 99},
1434          {43, 120},
1435          {43, 113},
1436          {43, 107},
1437          {43, 99},
1438          {11, 120},
1439          {11, 113},
1440          {11, 107},
1441          {11, 99},
1442          {131, 107},
1443          {131, 99},
1444          {99, 120},
1445          {99, 113},
1446          {99, 107},
1447          {99, 99},
1448          {67, 120},
1449          {67, 113},
1450          {67, 107},
1451          {67, 99},
1452          {35, 120},
1453          {35, 113},
1454          {35, 107},
1455          {35, 99},
1456          {3, 120} }             /* 5.x GHz, lowest power */
1457 };
1458
1459 static inline u8 iwl3945_hw_reg_fix_power_index(int index)
1460 {
1461         if (index < 0)
1462                 return 0;
1463         if (index >= IWL_MAX_GAIN_ENTRIES)
1464                 return IWL_MAX_GAIN_ENTRIES - 1;
1465         return (u8) index;
1466 }
1467
1468 /* Kick off thermal recalibration check every 60 seconds */
1469 #define REG_RECALIB_PERIOD (60)
1470
1471 /**
1472  * iwl3945_hw_reg_set_scan_power - Set Tx power for scan probe requests
1473  *
1474  * Set (in our channel info database) the direct scan Tx power for 1 Mbit (CCK)
1475  * or 6 Mbit (OFDM) rates.
1476  */
1477 static void iwl3945_hw_reg_set_scan_power(struct iwl_priv *priv, u32 scan_tbl_index,
1478                                s32 rate_index, const s8 *clip_pwrs,
1479                                struct iwl_channel_info *ch_info,
1480                                int band_index)
1481 {
1482         struct iwl3945_scan_power_info *scan_power_info;
1483         s8 power;
1484         u8 power_index;
1485
1486         scan_power_info = &ch_info->scan_pwr_info[scan_tbl_index];
1487
1488         /* use this channel group's 6Mbit clipping/saturation pwr,
1489          *   but cap at regulatory scan power restriction (set during init
1490          *   based on eeprom channel data) for this channel.  */
1491         power = min(ch_info->scan_power, clip_pwrs[IWL_RATE_6M_INDEX_TABLE]);
1492
1493         /* further limit to user's max power preference.
1494          * FIXME:  Other spectrum management power limitations do not
1495          *   seem to apply?? */
1496         power = min(power, priv->tx_power_user_lmt);
1497         scan_power_info->requested_power = power;
1498
1499         /* find difference between new scan *power* and current "normal"
1500          *   Tx *power* for 6Mb.  Use this difference (x2) to adjust the
1501          *   current "normal" temperature-compensated Tx power *index* for
1502          *   this rate (1Mb or 6Mb) to yield new temp-compensated scan power
1503          *   *index*. */
1504         power_index = ch_info->power_info[rate_index].power_table_index
1505             - (power - ch_info->power_info
1506                [IWL_RATE_6M_INDEX_TABLE].requested_power) * 2;
1507
1508         /* store reference index that we use when adjusting *all* scan
1509          *   powers.  So we can accommodate user (all channel) or spectrum
1510          *   management (single channel) power changes "between" temperature
1511          *   feedback compensation procedures.
1512          * don't force fit this reference index into gain table; it may be a
1513          *   negative number.  This will help avoid errors when we're at
1514          *   the lower bounds (highest gains, for warmest temperatures)
1515          *   of the table. */
1516
1517         /* don't exceed table bounds for "real" setting */
1518         power_index = iwl3945_hw_reg_fix_power_index(power_index);
1519
1520         scan_power_info->power_table_index = power_index;
1521         scan_power_info->tpc.tx_gain =
1522             power_gain_table[band_index][power_index].tx_gain;
1523         scan_power_info->tpc.dsp_atten =
1524             power_gain_table[band_index][power_index].dsp_atten;
1525 }
1526
1527 /**
1528  * iwl3945_send_tx_power - fill in Tx Power command with gain settings
1529  *
1530  * Configures power settings for all rates for the current channel,
1531  * using values from channel info struct, and send to NIC
1532  */
1533 static int iwl3945_send_tx_power(struct iwl_priv *priv)
1534 {
1535         int rate_idx, i;
1536         const struct iwl_channel_info *ch_info = NULL;
1537         struct iwl3945_txpowertable_cmd txpower = {
1538                 .channel = priv->active_rxon.channel,
1539         };
1540
1541         txpower.band = (priv->band == IEEE80211_BAND_5GHZ) ? 0 : 1;
1542         ch_info = iwl_get_channel_info(priv,
1543                                        priv->band,
1544                                        le16_to_cpu(priv->active_rxon.channel));
1545         if (!ch_info) {
1546                 IWL_ERR(priv,
1547                         "Failed to get channel info for channel %d [%d]\n",
1548                         le16_to_cpu(priv->active_rxon.channel), priv->band);
1549                 return -EINVAL;
1550         }
1551
1552         if (!is_channel_valid(ch_info)) {
1553                 IWL_DEBUG_POWER(priv, "Not calling TX_PWR_TABLE_CMD on "
1554                                 "non-Tx channel.\n");
1555                 return 0;
1556         }
1557
1558         /* fill cmd with power settings for all rates for current channel */
1559         /* Fill OFDM rate */
1560         for (rate_idx = IWL_FIRST_OFDM_RATE, i = 0;
1561              rate_idx <= IWL39_LAST_OFDM_RATE; rate_idx++, i++) {
1562
1563                 txpower.power[i].tpc = ch_info->power_info[i].tpc;
1564                 txpower.power[i].rate = iwl3945_rates[rate_idx].plcp;
1565
1566                 IWL_DEBUG_POWER(priv, "ch %d:%d rf %d dsp %3d rate code 0x%02x\n",
1567                                 le16_to_cpu(txpower.channel),
1568                                 txpower.band,
1569                                 txpower.power[i].tpc.tx_gain,
1570                                 txpower.power[i].tpc.dsp_atten,
1571                                 txpower.power[i].rate);
1572         }
1573         /* Fill CCK rates */
1574         for (rate_idx = IWL_FIRST_CCK_RATE;
1575              rate_idx <= IWL_LAST_CCK_RATE; rate_idx++, i++) {
1576                 txpower.power[i].tpc = ch_info->power_info[i].tpc;
1577                 txpower.power[i].rate = iwl3945_rates[rate_idx].plcp;
1578
1579                 IWL_DEBUG_POWER(priv, "ch %d:%d rf %d dsp %3d rate code 0x%02x\n",
1580                                 le16_to_cpu(txpower.channel),
1581                                 txpower.band,
1582                                 txpower.power[i].tpc.tx_gain,
1583                                 txpower.power[i].tpc.dsp_atten,
1584                                 txpower.power[i].rate);
1585         }
1586
1587         return iwl_send_cmd_pdu(priv, REPLY_TX_PWR_TABLE_CMD,
1588                                 sizeof(struct iwl3945_txpowertable_cmd),
1589                                 &txpower);
1590
1591 }
1592
1593 /**
1594  * iwl3945_hw_reg_set_new_power - Configures power tables at new levels
1595  * @ch_info: Channel to update.  Uses power_info.requested_power.
1596  *
1597  * Replace requested_power and base_power_index ch_info fields for
1598  * one channel.
1599  *
1600  * Called if user or spectrum management changes power preferences.
1601  * Takes into account h/w and modulation limitations (clip power).
1602  *
1603  * This does *not* send anything to NIC, just sets up ch_info for one channel.
1604  *
1605  * NOTE: reg_compensate_for_temperature_dif() *must* be run after this to
1606  *       properly fill out the scan powers, and actual h/w gain settings,
1607  *       and send changes to NIC
1608  */
1609 static int iwl3945_hw_reg_set_new_power(struct iwl_priv *priv,
1610                              struct iwl_channel_info *ch_info)
1611 {
1612         struct iwl3945_channel_power_info *power_info;
1613         int power_changed = 0;
1614         int i;
1615         const s8 *clip_pwrs;
1616         int power;
1617
1618         /* Get this chnlgrp's rate-to-max/clip-powers table */
1619         clip_pwrs = priv->clip39_groups[ch_info->group_index].clip_powers;
1620
1621         /* Get this channel's rate-to-current-power settings table */
1622         power_info = ch_info->power_info;
1623
1624         /* update OFDM Txpower settings */
1625         for (i = IWL_RATE_6M_INDEX_TABLE; i <= IWL_RATE_54M_INDEX_TABLE;
1626              i++, ++power_info) {
1627                 int delta_idx;
1628
1629                 /* limit new power to be no more than h/w capability */
1630                 power = min(ch_info->curr_txpow, clip_pwrs[i]);
1631                 if (power == power_info->requested_power)
1632                         continue;
1633
1634                 /* find difference between old and new requested powers,
1635                  *    update base (non-temp-compensated) power index */
1636                 delta_idx = (power - power_info->requested_power) * 2;
1637                 power_info->base_power_index -= delta_idx;
1638
1639                 /* save new requested power value */
1640                 power_info->requested_power = power;
1641
1642                 power_changed = 1;
1643         }
1644
1645         /* update CCK Txpower settings, based on OFDM 12M setting ...
1646          *    ... all CCK power settings for a given channel are the *same*. */
1647         if (power_changed) {
1648                 power =
1649                     ch_info->power_info[IWL_RATE_12M_INDEX_TABLE].
1650                     requested_power + IWL_CCK_FROM_OFDM_POWER_DIFF;
1651
1652                 /* do all CCK rates' iwl3945_channel_power_info structures */
1653                 for (i = IWL_RATE_1M_INDEX_TABLE; i <= IWL_RATE_11M_INDEX_TABLE; i++) {
1654                         power_info->requested_power = power;
1655                         power_info->base_power_index =
1656                             ch_info->power_info[IWL_RATE_12M_INDEX_TABLE].
1657                             base_power_index + IWL_CCK_FROM_OFDM_INDEX_DIFF;
1658                         ++power_info;
1659                 }
1660         }
1661
1662         return 0;
1663 }
1664
1665 /**
1666  * iwl3945_hw_reg_get_ch_txpower_limit - returns new power limit for channel
1667  *
1668  * NOTE: Returned power limit may be less (but not more) than requested,
1669  *       based strictly on regulatory (eeprom and spectrum mgt) limitations
1670  *       (no consideration for h/w clipping limitations).
1671  */
1672 static int iwl3945_hw_reg_get_ch_txpower_limit(struct iwl_channel_info *ch_info)
1673 {
1674         s8 max_power;
1675
1676 #if 0
1677         /* if we're using TGd limits, use lower of TGd or EEPROM */
1678         if (ch_info->tgd_data.max_power != 0)
1679                 max_power = min(ch_info->tgd_data.max_power,
1680                                 ch_info->eeprom.max_power_avg);
1681
1682         /* else just use EEPROM limits */
1683         else
1684 #endif
1685                 max_power = ch_info->eeprom.max_power_avg;
1686
1687         return min(max_power, ch_info->max_power_avg);
1688 }
1689
1690 /**
1691  * iwl3945_hw_reg_comp_txpower_temp - Compensate for temperature
1692  *
1693  * Compensate txpower settings of *all* channels for temperature.
1694  * This only accounts for the difference between current temperature
1695  *   and the factory calibration temperatures, and bases the new settings
1696  *   on the channel's base_power_index.
1697  *
1698  * If RxOn is "associated", this sends the new Txpower to NIC!
1699  */
1700 static int iwl3945_hw_reg_comp_txpower_temp(struct iwl_priv *priv)
1701 {
1702         struct iwl_channel_info *ch_info = NULL;
1703         struct iwl3945_eeprom *eeprom = (struct iwl3945_eeprom *)priv->eeprom;
1704         int delta_index;
1705         const s8 *clip_pwrs; /* array of h/w max power levels for each rate */
1706         u8 a_band;
1707         u8 rate_index;
1708         u8 scan_tbl_index;
1709         u8 i;
1710         int ref_temp;
1711         int temperature = priv->temperature;
1712
1713         /* set up new Tx power info for each and every channel, 2.4 and 5.x */
1714         for (i = 0; i < priv->channel_count; i++) {
1715                 ch_info = &priv->channel_info[i];
1716                 a_band = is_channel_a_band(ch_info);
1717
1718                 /* Get this chnlgrp's factory calibration temperature */
1719                 ref_temp = (s16)eeprom->groups[ch_info->group_index].
1720                     temperature;
1721
1722                 /* get power index adjustment based on current and factory
1723                  * temps */
1724                 delta_index = iwl3945_hw_reg_adjust_power_by_temp(temperature,
1725                                                               ref_temp);
1726
1727                 /* set tx power value for all rates, OFDM and CCK */
1728                 for (rate_index = 0; rate_index < IWL_RATE_COUNT;
1729                      rate_index++) {
1730                         int power_idx =
1731                             ch_info->power_info[rate_index].base_power_index;
1732
1733                         /* temperature compensate */
1734                         power_idx += delta_index;
1735
1736                         /* stay within table range */
1737                         power_idx = iwl3945_hw_reg_fix_power_index(power_idx);
1738                         ch_info->power_info[rate_index].
1739                             power_table_index = (u8) power_idx;
1740                         ch_info->power_info[rate_index].tpc =
1741                             power_gain_table[a_band][power_idx];
1742                 }
1743
1744                 /* Get this chnlgrp's rate-to-max/clip-powers table */
1745                 clip_pwrs = priv->clip39_groups[ch_info->group_index].clip_powers;
1746
1747                 /* set scan tx power, 1Mbit for CCK, 6Mbit for OFDM */
1748                 for (scan_tbl_index = 0;
1749                      scan_tbl_index < IWL_NUM_SCAN_RATES; scan_tbl_index++) {
1750                         s32 actual_index = (scan_tbl_index == 0) ?
1751                             IWL_RATE_1M_INDEX_TABLE : IWL_RATE_6M_INDEX_TABLE;
1752                         iwl3945_hw_reg_set_scan_power(priv, scan_tbl_index,
1753                                            actual_index, clip_pwrs,
1754                                            ch_info, a_band);
1755                 }
1756         }
1757
1758         /* send Txpower command for current channel to ucode */
1759         return priv->cfg->ops->lib->send_tx_power(priv);
1760 }
1761
1762 int iwl3945_hw_reg_set_txpower(struct iwl_priv *priv, s8 power)
1763 {
1764         struct iwl_channel_info *ch_info;
1765         s8 max_power;
1766         u8 a_band;
1767         u8 i;
1768
1769         if (priv->tx_power_user_lmt == power) {
1770                 IWL_DEBUG_POWER(priv, "Requested Tx power same as current "
1771                                 "limit: %ddBm.\n", power);
1772                 return 0;
1773         }
1774
1775         IWL_DEBUG_POWER(priv, "Setting upper limit clamp to %ddBm.\n", power);
1776         priv->tx_power_user_lmt = power;
1777
1778         /* set up new Tx powers for each and every channel, 2.4 and 5.x */
1779
1780         for (i = 0; i < priv->channel_count; i++) {
1781                 ch_info = &priv->channel_info[i];
1782                 a_band = is_channel_a_band(ch_info);
1783
1784                 /* find minimum power of all user and regulatory constraints
1785                  *    (does not consider h/w clipping limitations) */
1786                 max_power = iwl3945_hw_reg_get_ch_txpower_limit(ch_info);
1787                 max_power = min(power, max_power);
1788                 if (max_power != ch_info->curr_txpow) {
1789                         ch_info->curr_txpow = max_power;
1790
1791                         /* this considers the h/w clipping limitations */
1792                         iwl3945_hw_reg_set_new_power(priv, ch_info);
1793                 }
1794         }
1795
1796         /* update txpower settings for all channels,
1797          *   send to NIC if associated. */
1798         is_temp_calib_needed(priv);
1799         iwl3945_hw_reg_comp_txpower_temp(priv);
1800
1801         return 0;
1802 }
1803
1804 static int iwl3945_send_rxon_assoc(struct iwl_priv *priv)
1805 {
1806         int rc = 0;
1807         struct iwl_rx_packet *res = NULL;
1808         struct iwl3945_rxon_assoc_cmd rxon_assoc;
1809         struct iwl_host_cmd cmd = {
1810                 .id = REPLY_RXON_ASSOC,
1811                 .len = sizeof(rxon_assoc),
1812                 .flags = CMD_WANT_SKB,
1813                 .data = &rxon_assoc,
1814         };
1815         const struct iwl_rxon_cmd *rxon1 = &priv->staging_rxon;
1816         const struct iwl_rxon_cmd *rxon2 = &priv->active_rxon;
1817
1818         if ((rxon1->flags == rxon2->flags) &&
1819             (rxon1->filter_flags == rxon2->filter_flags) &&
1820             (rxon1->cck_basic_rates == rxon2->cck_basic_rates) &&
1821             (rxon1->ofdm_basic_rates == rxon2->ofdm_basic_rates)) {
1822                 IWL_DEBUG_INFO(priv, "Using current RXON_ASSOC.  Not resending.\n");
1823                 return 0;
1824         }
1825
1826         rxon_assoc.flags = priv->staging_rxon.flags;
1827         rxon_assoc.filter_flags = priv->staging_rxon.filter_flags;
1828         rxon_assoc.ofdm_basic_rates = priv->staging_rxon.ofdm_basic_rates;
1829         rxon_assoc.cck_basic_rates = priv->staging_rxon.cck_basic_rates;
1830         rxon_assoc.reserved = 0;
1831
1832         rc = iwl_send_cmd_sync(priv, &cmd);
1833         if (rc)
1834                 return rc;
1835
1836         res = (struct iwl_rx_packet *)cmd.reply_skb->data;
1837         if (res->hdr.flags & IWL_CMD_FAILED_MSK) {
1838                 IWL_ERR(priv, "Bad return from REPLY_RXON_ASSOC command\n");
1839                 rc = -EIO;
1840         }
1841
1842         priv->alloc_rxb_skb--;
1843         dev_kfree_skb_any(cmd.reply_skb);
1844
1845         return rc;
1846 }
1847
1848 /**
1849  * iwl3945_commit_rxon - commit staging_rxon to hardware
1850  *
1851  * The RXON command in staging_rxon is committed to the hardware and
1852  * the active_rxon structure is updated with the new data.  This
1853  * function correctly transitions out of the RXON_ASSOC_MSK state if
1854  * a HW tune is required based on the RXON structure changes.
1855  */
1856 static int iwl3945_commit_rxon(struct iwl_priv *priv)
1857 {
1858         /* cast away the const for active_rxon in this function */
1859         struct iwl3945_rxon_cmd *active_rxon = (void *)&priv->active_rxon;
1860         struct iwl3945_rxon_cmd *staging_rxon = (void *)&priv->staging_rxon;
1861         int rc = 0;
1862         bool new_assoc =
1863                 !!(priv->staging_rxon.filter_flags & RXON_FILTER_ASSOC_MSK);
1864
1865         if (!iwl_is_alive(priv))
1866                 return -1;
1867
1868         /* always get timestamp with Rx frame */
1869         staging_rxon->flags |= RXON_FLG_TSF2HOST_MSK;
1870
1871         /* select antenna */
1872         staging_rxon->flags &=
1873             ~(RXON_FLG_DIS_DIV_MSK | RXON_FLG_ANT_SEL_MSK);
1874         staging_rxon->flags |= iwl3945_get_antenna_flags(priv);
1875
1876         rc = iwl_check_rxon_cmd(priv);
1877         if (rc) {
1878                 IWL_ERR(priv, "Invalid RXON configuration.  Not committing.\n");
1879                 return -EINVAL;
1880         }
1881
1882         /* If we don't need to send a full RXON, we can use
1883          * iwl3945_rxon_assoc_cmd which is used to reconfigure filter
1884          * and other flags for the current radio configuration. */
1885         if (!iwl_full_rxon_required(priv)) {
1886                 rc = iwl_send_rxon_assoc(priv);
1887                 if (rc) {
1888                         IWL_ERR(priv, "Error setting RXON_ASSOC "
1889                                   "configuration (%d).\n", rc);
1890                         return rc;
1891                 }
1892
1893                 memcpy(active_rxon, staging_rxon, sizeof(*active_rxon));
1894
1895                 return 0;
1896         }
1897
1898         /* If we are currently associated and the new config requires
1899          * an RXON_ASSOC and the new config wants the associated mask enabled,
1900          * we must clear the associated from the active configuration
1901          * before we apply the new config */
1902         if (iwl_is_associated(priv) && new_assoc) {
1903                 IWL_DEBUG_INFO(priv, "Toggling associated bit on current RXON\n");
1904                 active_rxon->filter_flags &= ~RXON_FILTER_ASSOC_MSK;
1905
1906                 /*
1907                  * reserved4 and 5 could have been filled by the iwlcore code.
1908                  * Let's clear them before pushing to the 3945.
1909                  */
1910                 active_rxon->reserved4 = 0;
1911                 active_rxon->reserved5 = 0;
1912                 rc = iwl_send_cmd_pdu(priv, REPLY_RXON,
1913                                       sizeof(struct iwl3945_rxon_cmd),
1914                                       &priv->active_rxon);
1915
1916                 /* If the mask clearing failed then we set
1917                  * active_rxon back to what it was previously */
1918                 if (rc) {
1919                         active_rxon->filter_flags |= RXON_FILTER_ASSOC_MSK;
1920                         IWL_ERR(priv, "Error clearing ASSOC_MSK on current "
1921                                   "configuration (%d).\n", rc);
1922                         return rc;
1923                 }
1924         }
1925
1926         IWL_DEBUG_INFO(priv, "Sending RXON\n"
1927                        "* with%s RXON_FILTER_ASSOC_MSK\n"
1928                        "* channel = %d\n"
1929                        "* bssid = %pM\n",
1930                        (new_assoc ? "" : "out"),
1931                        le16_to_cpu(staging_rxon->channel),
1932                        staging_rxon->bssid_addr);
1933
1934         /*
1935          * reserved4 and 5 could have been filled by the iwlcore code.
1936          * Let's clear them before pushing to the 3945.
1937          */
1938         staging_rxon->reserved4 = 0;
1939         staging_rxon->reserved5 = 0;
1940
1941         iwl_set_rxon_hwcrypto(priv, !iwl3945_mod_params.sw_crypto);
1942
1943         /* Apply the new configuration */
1944         rc = iwl_send_cmd_pdu(priv, REPLY_RXON,
1945                               sizeof(struct iwl3945_rxon_cmd),
1946                               staging_rxon);
1947         if (rc) {
1948                 IWL_ERR(priv, "Error setting new configuration (%d).\n", rc);
1949                 return rc;
1950         }
1951
1952         memcpy(active_rxon, staging_rxon, sizeof(*active_rxon));
1953
1954         iwl_clear_stations_table(priv);
1955
1956         /* If we issue a new RXON command which required a tune then we must
1957          * send a new TXPOWER command or we won't be able to Tx any frames */
1958         rc = priv->cfg->ops->lib->send_tx_power(priv);
1959         if (rc) {
1960                 IWL_ERR(priv, "Error setting Tx power (%d).\n", rc);
1961                 return rc;
1962         }
1963
1964         /* Add the broadcast address so we can send broadcast frames */
1965         if (iwl_add_station(priv, iwl_bcast_addr, false, CMD_SYNC, NULL) ==
1966             IWL_INVALID_STATION) {
1967                 IWL_ERR(priv, "Error adding BROADCAST address for transmit.\n");
1968                 return -EIO;
1969         }
1970
1971         /* If we have set the ASSOC_MSK and we are in BSS mode then
1972          * add the IWL_AP_ID to the station rate table */
1973         if (iwl_is_associated(priv) &&
1974             (priv->iw_mode == NL80211_IFTYPE_STATION))
1975                 if (iwl_add_station(priv, priv->active_rxon.bssid_addr,
1976                                 true, CMD_SYNC, NULL) == IWL_INVALID_STATION) {
1977                         IWL_ERR(priv, "Error adding AP address for transmit\n");
1978                         return -EIO;
1979                 }
1980
1981         /* Init the hardware's rate fallback order based on the band */
1982         rc = iwl3945_init_hw_rate_table(priv);
1983         if (rc) {
1984                 IWL_ERR(priv, "Error setting HW rate table: %02X\n", rc);
1985                 return -EIO;
1986         }
1987
1988         return 0;
1989 }
1990
1991 /* will add 3945 channel switch cmd handling later */
1992 int iwl3945_hw_channel_switch(struct iwl_priv *priv, u16 channel)
1993 {
1994         return 0;
1995 }
1996
1997 /**
1998  * iwl3945_reg_txpower_periodic -  called when time to check our temperature.
1999  *
2000  * -- reset periodic timer
2001  * -- see if temp has changed enough to warrant re-calibration ... if so:
2002  *     -- correct coeffs for temp (can reset temp timer)
2003  *     -- save this temp as "last",
2004  *     -- send new set of gain settings to NIC
2005  * NOTE:  This should continue working, even when we're not associated,
2006  *   so we can keep our internal table of scan powers current. */
2007 void iwl3945_reg_txpower_periodic(struct iwl_priv *priv)
2008 {
2009         /* This will kick in the "brute force"
2010          * iwl3945_hw_reg_comp_txpower_temp() below */
2011         if (!is_temp_calib_needed(priv))
2012                 goto reschedule;
2013
2014         /* Set up a new set of temp-adjusted TxPowers, send to NIC.
2015          * This is based *only* on current temperature,
2016          * ignoring any previous power measurements */
2017         iwl3945_hw_reg_comp_txpower_temp(priv);
2018
2019  reschedule:
2020         queue_delayed_work(priv->workqueue,
2021                            &priv->thermal_periodic, REG_RECALIB_PERIOD * HZ);
2022 }
2023
2024 static void iwl3945_bg_reg_txpower_periodic(struct work_struct *work)
2025 {
2026         struct iwl_priv *priv = container_of(work, struct iwl_priv,
2027                                              thermal_periodic.work);
2028
2029         if (test_bit(STATUS_EXIT_PENDING, &priv->status))
2030                 return;
2031
2032         mutex_lock(&priv->mutex);
2033         iwl3945_reg_txpower_periodic(priv);
2034         mutex_unlock(&priv->mutex);
2035 }
2036
2037 /**
2038  * iwl3945_hw_reg_get_ch_grp_index - find the channel-group index (0-4)
2039  *                                 for the channel.
2040  *
2041  * This function is used when initializing channel-info structs.
2042  *
2043  * NOTE: These channel groups do *NOT* match the bands above!
2044  *       These channel groups are based on factory-tested channels;
2045  *       on A-band, EEPROM's "group frequency" entries represent the top
2046  *       channel in each group 1-4.  Group 5 All B/G channels are in group 0.
2047  */
2048 static u16 iwl3945_hw_reg_get_ch_grp_index(struct iwl_priv *priv,
2049                                        const struct iwl_channel_info *ch_info)
2050 {
2051         struct iwl3945_eeprom *eeprom = (struct iwl3945_eeprom *)priv->eeprom;
2052         struct iwl3945_eeprom_txpower_group *ch_grp = &eeprom->groups[0];
2053         u8 group;
2054         u16 group_index = 0;    /* based on factory calib frequencies */
2055         u8 grp_channel;
2056
2057         /* Find the group index for the channel ... don't use index 1(?) */
2058         if (is_channel_a_band(ch_info)) {
2059                 for (group = 1; group < 5; group++) {
2060                         grp_channel = ch_grp[group].group_channel;
2061                         if (ch_info->channel <= grp_channel) {
2062                                 group_index = group;
2063                                 break;
2064                         }
2065                 }
2066                 /* group 4 has a few channels *above* its factory cal freq */
2067                 if (group == 5)
2068                         group_index = 4;
2069         } else
2070                 group_index = 0;        /* 2.4 GHz, group 0 */
2071
2072         IWL_DEBUG_POWER(priv, "Chnl %d mapped to grp %d\n", ch_info->channel,
2073                         group_index);
2074         return group_index;
2075 }
2076
2077 /**
2078  * iwl3945_hw_reg_get_matched_power_index - Interpolate to get nominal index
2079  *
2080  * Interpolate to get nominal (i.e. at factory calibration temperature) index
2081  *   into radio/DSP gain settings table for requested power.
2082  */
2083 static int iwl3945_hw_reg_get_matched_power_index(struct iwl_priv *priv,
2084                                        s8 requested_power,
2085                                        s32 setting_index, s32 *new_index)
2086 {
2087         const struct iwl3945_eeprom_txpower_group *chnl_grp = NULL;
2088         struct iwl3945_eeprom *eeprom = (struct iwl3945_eeprom *)priv->eeprom;
2089         s32 index0, index1;
2090         s32 power = 2 * requested_power;
2091         s32 i;
2092         const struct iwl3945_eeprom_txpower_sample *samples;
2093         s32 gains0, gains1;
2094         s32 res;
2095         s32 denominator;
2096
2097         chnl_grp = &eeprom->groups[setting_index];
2098         samples = chnl_grp->samples;
2099         for (i = 0; i < 5; i++) {
2100                 if (power == samples[i].power) {
2101                         *new_index = samples[i].gain_index;
2102                         return 0;
2103                 }
2104         }
2105
2106         if (power > samples[1].power) {
2107                 index0 = 0;
2108                 index1 = 1;
2109         } else if (power > samples[2].power) {
2110                 index0 = 1;
2111                 index1 = 2;
2112         } else if (power > samples[3].power) {
2113                 index0 = 2;
2114                 index1 = 3;
2115         } else {
2116                 index0 = 3;
2117                 index1 = 4;
2118         }
2119
2120         denominator = (s32) samples[index1].power - (s32) samples[index0].power;
2121         if (denominator == 0)
2122                 return -EINVAL;
2123         gains0 = (s32) samples[index0].gain_index * (1 << 19);
2124         gains1 = (s32) samples[index1].gain_index * (1 << 19);
2125         res = gains0 + (gains1 - gains0) *
2126             ((s32) power - (s32) samples[index0].power) / denominator +
2127             (1 << 18);
2128         *new_index = res >> 19;
2129         return 0;
2130 }
2131
2132 static void iwl3945_hw_reg_init_channel_groups(struct iwl_priv *priv)
2133 {
2134         u32 i;
2135         s32 rate_index;
2136         struct iwl3945_eeprom *eeprom = (struct iwl3945_eeprom *)priv->eeprom;
2137         const struct iwl3945_eeprom_txpower_group *group;
2138
2139         IWL_DEBUG_POWER(priv, "Initializing factory calib info from EEPROM\n");
2140
2141         for (i = 0; i < IWL_NUM_TX_CALIB_GROUPS; i++) {
2142                 s8 *clip_pwrs;  /* table of power levels for each rate */
2143                 s8 satur_pwr;   /* saturation power for each chnl group */
2144                 group = &eeprom->groups[i];
2145
2146                 /* sanity check on factory saturation power value */
2147                 if (group->saturation_power < 40) {
2148                         IWL_WARN(priv, "Error: saturation power is %d, "
2149                                     "less than minimum expected 40\n",
2150                                     group->saturation_power);
2151                         return;
2152                 }
2153
2154                 /*
2155                  * Derive requested power levels for each rate, based on
2156                  *   hardware capabilities (saturation power for band).
2157                  * Basic value is 3dB down from saturation, with further
2158                  *   power reductions for highest 3 data rates.  These
2159                  *   backoffs provide headroom for high rate modulation
2160                  *   power peaks, without too much distortion (clipping).
2161                  */
2162                 /* we'll fill in this array with h/w max power levels */
2163                 clip_pwrs = (s8 *) priv->clip39_groups[i].clip_powers;
2164
2165                 /* divide factory saturation power by 2 to find -3dB level */
2166                 satur_pwr = (s8) (group->saturation_power >> 1);
2167
2168                 /* fill in channel group's nominal powers for each rate */
2169                 for (rate_index = 0;
2170                      rate_index < IWL_RATE_COUNT; rate_index++, clip_pwrs++) {
2171                         switch (rate_index) {
2172                         case IWL_RATE_36M_INDEX_TABLE:
2173                                 if (i == 0)     /* B/G */
2174                                         *clip_pwrs = satur_pwr;
2175                                 else    /* A */
2176                                         *clip_pwrs = satur_pwr - 5;
2177                                 break;
2178                         case IWL_RATE_48M_INDEX_TABLE:
2179                                 if (i == 0)
2180                                         *clip_pwrs = satur_pwr - 7;
2181                                 else
2182                                         *clip_pwrs = satur_pwr - 10;
2183                                 break;
2184                         case IWL_RATE_54M_INDEX_TABLE:
2185                                 if (i == 0)
2186                                         *clip_pwrs = satur_pwr - 9;
2187                                 else
2188                                         *clip_pwrs = satur_pwr - 12;
2189                                 break;
2190                         default:
2191                                 *clip_pwrs = satur_pwr;
2192                                 break;
2193                         }
2194                 }
2195         }
2196 }
2197
2198 /**
2199  * iwl3945_txpower_set_from_eeprom - Set channel power info based on EEPROM
2200  *
2201  * Second pass (during init) to set up priv->channel_info
2202  *
2203  * Set up Tx-power settings in our channel info database for each VALID
2204  * (for this geo/SKU) channel, at all Tx data rates, based on eeprom values
2205  * and current temperature.
2206  *
2207  * Since this is based on current temperature (at init time), these values may
2208  * not be valid for very long, but it gives us a starting/default point,
2209  * and allows us to active (i.e. using Tx) scan.
2210  *
2211  * This does *not* write values to NIC, just sets up our internal table.
2212  */
2213 int iwl3945_txpower_set_from_eeprom(struct iwl_priv *priv)
2214 {
2215         struct iwl_channel_info *ch_info = NULL;
2216         struct iwl3945_channel_power_info *pwr_info;
2217         struct iwl3945_eeprom *eeprom = (struct iwl3945_eeprom *)priv->eeprom;
2218         int delta_index;
2219         u8 rate_index;
2220         u8 scan_tbl_index;
2221         const s8 *clip_pwrs;    /* array of power levels for each rate */
2222         u8 gain, dsp_atten;
2223         s8 power;
2224         u8 pwr_index, base_pwr_index, a_band;
2225         u8 i;
2226         int temperature;
2227
2228         /* save temperature reference,
2229          *   so we can determine next time to calibrate */
2230         temperature = iwl3945_hw_reg_txpower_get_temperature(priv);
2231         priv->last_temperature = temperature;
2232
2233         iwl3945_hw_reg_init_channel_groups(priv);
2234
2235         /* initialize Tx power info for each and every channel, 2.4 and 5.x */
2236         for (i = 0, ch_info = priv->channel_info; i < priv->channel_count;
2237              i++, ch_info++) {
2238                 a_band = is_channel_a_band(ch_info);
2239                 if (!is_channel_valid(ch_info))
2240                         continue;
2241
2242                 /* find this channel's channel group (*not* "band") index */
2243                 ch_info->group_index =
2244                         iwl3945_hw_reg_get_ch_grp_index(priv, ch_info);
2245
2246                 /* Get this chnlgrp's rate->max/clip-powers table */
2247                 clip_pwrs = priv->clip39_groups[ch_info->group_index].clip_powers;
2248
2249                 /* calculate power index *adjustment* value according to
2250                  *  diff between current temperature and factory temperature */
2251                 delta_index = iwl3945_hw_reg_adjust_power_by_temp(temperature,
2252                                 eeprom->groups[ch_info->group_index].
2253                                 temperature);
2254
2255                 IWL_DEBUG_POWER(priv, "Delta index for channel %d: %d [%d]\n",
2256                                 ch_info->channel, delta_index, temperature +
2257                                 IWL_TEMP_CONVERT);
2258
2259                 /* set tx power value for all OFDM rates */
2260                 for (rate_index = 0; rate_index < IWL_OFDM_RATES;
2261                      rate_index++) {
2262                         s32 uninitialized_var(power_idx);
2263                         int rc;
2264
2265                         /* use channel group's clip-power table,
2266                          *   but don't exceed channel's max power */
2267                         s8 pwr = min(ch_info->max_power_avg,
2268                                      clip_pwrs[rate_index]);
2269
2270                         pwr_info = &ch_info->power_info[rate_index];
2271
2272                         /* get base (i.e. at factory-measured temperature)
2273                          *    power table index for this rate's power */
2274                         rc = iwl3945_hw_reg_get_matched_power_index(priv, pwr,
2275                                                          ch_info->group_index,
2276                                                          &power_idx);
2277                         if (rc) {
2278                                 IWL_ERR(priv, "Invalid power index\n");
2279                                 return rc;
2280                         }
2281                         pwr_info->base_power_index = (u8) power_idx;
2282
2283                         /* temperature compensate */
2284                         power_idx += delta_index;
2285
2286                         /* stay within range of gain table */
2287                         power_idx = iwl3945_hw_reg_fix_power_index(power_idx);
2288
2289                         /* fill 1 OFDM rate's iwl3945_channel_power_info struct */
2290                         pwr_info->requested_power = pwr;
2291                         pwr_info->power_table_index = (u8) power_idx;
2292                         pwr_info->tpc.tx_gain =
2293                             power_gain_table[a_band][power_idx].tx_gain;
2294                         pwr_info->tpc.dsp_atten =
2295                             power_gain_table[a_band][power_idx].dsp_atten;
2296                 }
2297
2298                 /* set tx power for CCK rates, based on OFDM 12 Mbit settings*/
2299                 pwr_info = &ch_info->power_info[IWL_RATE_12M_INDEX_TABLE];
2300                 power = pwr_info->requested_power +
2301                         IWL_CCK_FROM_OFDM_POWER_DIFF;
2302                 pwr_index = pwr_info->power_table_index +
2303                         IWL_CCK_FROM_OFDM_INDEX_DIFF;
2304                 base_pwr_index = pwr_info->base_power_index +
2305                         IWL_CCK_FROM_OFDM_INDEX_DIFF;
2306
2307                 /* stay within table range */
2308                 pwr_index = iwl3945_hw_reg_fix_power_index(pwr_index);
2309                 gain = power_gain_table[a_band][pwr_index].tx_gain;
2310                 dsp_atten = power_gain_table[a_band][pwr_index].dsp_atten;
2311
2312                 /* fill each CCK rate's iwl3945_channel_power_info structure
2313                  * NOTE:  All CCK-rate Txpwrs are the same for a given chnl!
2314                  * NOTE:  CCK rates start at end of OFDM rates! */
2315                 for (rate_index = 0;
2316                      rate_index < IWL_CCK_RATES; rate_index++) {
2317                         pwr_info = &ch_info->power_info[rate_index+IWL_OFDM_RATES];
2318                         pwr_info->requested_power = power;
2319                         pwr_info->power_table_index = pwr_index;
2320                         pwr_info->base_power_index = base_pwr_index;
2321                         pwr_info->tpc.tx_gain = gain;
2322                         pwr_info->tpc.dsp_atten = dsp_atten;
2323                 }
2324
2325                 /* set scan tx power, 1Mbit for CCK, 6Mbit for OFDM */
2326                 for (scan_tbl_index = 0;
2327                      scan_tbl_index < IWL_NUM_SCAN_RATES; scan_tbl_index++) {
2328                         s32 actual_index = (scan_tbl_index == 0) ?
2329                                 IWL_RATE_1M_INDEX_TABLE : IWL_RATE_6M_INDEX_TABLE;
2330                         iwl3945_hw_reg_set_scan_power(priv, scan_tbl_index,
2331                                 actual_index, clip_pwrs, ch_info, a_band);
2332                 }
2333         }
2334
2335         return 0;
2336 }
2337
2338 int iwl3945_hw_rxq_stop(struct iwl_priv *priv)
2339 {
2340         int rc;
2341
2342         iwl_write_direct32(priv, FH39_RCSR_CONFIG(0), 0);
2343         rc = iwl_poll_direct_bit(priv, FH39_RSSR_STATUS,
2344                         FH39_RSSR_CHNL0_RX_STATUS_CHNL_IDLE, 1000);
2345         if (rc < 0)
2346                 IWL_ERR(priv, "Can't stop Rx DMA.\n");
2347
2348         return 0;
2349 }
2350
2351 int iwl3945_hw_tx_queue_init(struct iwl_priv *priv, struct iwl_tx_queue *txq)
2352 {
2353         int txq_id = txq->q.id;
2354
2355         struct iwl3945_shared *shared_data = priv->shared_virt;
2356
2357         shared_data->tx_base_ptr[txq_id] = cpu_to_le32((u32)txq->q.dma_addr);
2358
2359         iwl_write_direct32(priv, FH39_CBCC_CTRL(txq_id), 0);
2360         iwl_write_direct32(priv, FH39_CBCC_BASE(txq_id), 0);
2361
2362         iwl_write_direct32(priv, FH39_TCSR_CONFIG(txq_id),
2363                 FH39_TCSR_TX_CONFIG_REG_VAL_CIRQ_RTC_NOINT |
2364                 FH39_TCSR_TX_CONFIG_REG_VAL_MSG_MODE_TXF |
2365                 FH39_TCSR_TX_CONFIG_REG_VAL_CIRQ_HOST_IFTFD |
2366                 FH39_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_ENABLE_VAL |
2367                 FH39_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE);
2368
2369         /* fake read to flush all prev. writes */
2370         iwl_read32(priv, FH39_TSSR_CBB_BASE);
2371
2372         return 0;
2373 }
2374
2375 /*
2376  * HCMD utils
2377  */
2378 static u16 iwl3945_get_hcmd_size(u8 cmd_id, u16 len)
2379 {
2380         switch (cmd_id) {
2381         case REPLY_RXON:
2382                 return sizeof(struct iwl3945_rxon_cmd);
2383         case POWER_TABLE_CMD:
2384                 return sizeof(struct iwl3945_powertable_cmd);
2385         default:
2386                 return len;
2387         }
2388 }
2389
2390
2391 static u16 iwl3945_build_addsta_hcmd(const struct iwl_addsta_cmd *cmd, u8 *data)
2392 {
2393         struct iwl3945_addsta_cmd *addsta = (struct iwl3945_addsta_cmd *)data;
2394         addsta->mode = cmd->mode;
2395         memcpy(&addsta->sta, &cmd->sta, sizeof(struct sta_id_modify));
2396         memcpy(&addsta->key, &cmd->key, sizeof(struct iwl4965_keyinfo));
2397         addsta->station_flags = cmd->station_flags;
2398         addsta->station_flags_msk = cmd->station_flags_msk;
2399         addsta->tid_disable_tx = cpu_to_le16(0);
2400         addsta->rate_n_flags = cmd->rate_n_flags;
2401         addsta->add_immediate_ba_tid = cmd->add_immediate_ba_tid;
2402         addsta->remove_immediate_ba_tid = cmd->remove_immediate_ba_tid;
2403         addsta->add_immediate_ba_ssn = cmd->add_immediate_ba_ssn;
2404
2405         return (u16)sizeof(struct iwl3945_addsta_cmd);
2406 }
2407
2408
2409 /**
2410  * iwl3945_init_hw_rate_table - Initialize the hardware rate fallback table
2411  */
2412 int iwl3945_init_hw_rate_table(struct iwl_priv *priv)
2413 {
2414         int rc, i, index, prev_index;
2415         struct iwl3945_rate_scaling_cmd rate_cmd = {
2416                 .reserved = {0, 0, 0},
2417         };
2418         struct iwl3945_rate_scaling_info *table = rate_cmd.table;
2419
2420         for (i = 0; i < ARRAY_SIZE(iwl3945_rates); i++) {
2421                 index = iwl3945_rates[i].table_rs_index;
2422
2423                 table[index].rate_n_flags =
2424                         iwl3945_hw_set_rate_n_flags(iwl3945_rates[i].plcp, 0);
2425                 table[index].try_cnt = priv->retry_rate;
2426                 prev_index = iwl3945_get_prev_ieee_rate(i);
2427                 table[index].next_rate_index =
2428                                 iwl3945_rates[prev_index].table_rs_index;
2429         }
2430
2431         switch (priv->band) {
2432         case IEEE80211_BAND_5GHZ:
2433                 IWL_DEBUG_RATE(priv, "Select A mode rate scale\n");
2434                 /* If one of the following CCK rates is used,
2435                  * have it fall back to the 6M OFDM rate */
2436                 for (i = IWL_RATE_1M_INDEX_TABLE;
2437                         i <= IWL_RATE_11M_INDEX_TABLE; i++)
2438                         table[i].next_rate_index =
2439                           iwl3945_rates[IWL_FIRST_OFDM_RATE].table_rs_index;
2440
2441                 /* Don't fall back to CCK rates */
2442                 table[IWL_RATE_12M_INDEX_TABLE].next_rate_index =
2443                                                 IWL_RATE_9M_INDEX_TABLE;
2444
2445                 /* Don't drop out of OFDM rates */
2446                 table[IWL_RATE_6M_INDEX_TABLE].next_rate_index =
2447                     iwl3945_rates[IWL_FIRST_OFDM_RATE].table_rs_index;
2448                 break;
2449
2450         case IEEE80211_BAND_2GHZ:
2451                 IWL_DEBUG_RATE(priv, "Select B/G mode rate scale\n");
2452                 /* If an OFDM rate is used, have it fall back to the
2453                  * 1M CCK rates */
2454
2455                 if (!(priv->sta_supp_rates & IWL_OFDM_RATES_MASK) &&
2456                     iwl_is_associated(priv)) {
2457
2458                         index = IWL_FIRST_CCK_RATE;
2459                         for (i = IWL_RATE_6M_INDEX_TABLE;
2460                              i <= IWL_RATE_54M_INDEX_TABLE; i++)
2461                                 table[i].next_rate_index =
2462                                         iwl3945_rates[index].table_rs_index;
2463
2464                         index = IWL_RATE_11M_INDEX_TABLE;
2465                         /* CCK shouldn't fall back to OFDM... */
2466                         table[index].next_rate_index = IWL_RATE_5M_INDEX_TABLE;
2467                 }
2468                 break;
2469
2470         default:
2471                 WARN_ON(1);
2472                 break;
2473         }
2474
2475         /* Update the rate scaling for control frame Tx */
2476         rate_cmd.table_id = 0;
2477         rc = iwl_send_cmd_pdu(priv, REPLY_RATE_SCALE, sizeof(rate_cmd),
2478                               &rate_cmd);
2479         if (rc)
2480                 return rc;
2481
2482         /* Update the rate scaling for data frame Tx */
2483         rate_cmd.table_id = 1;
2484         return iwl_send_cmd_pdu(priv, REPLY_RATE_SCALE, sizeof(rate_cmd),
2485                                 &rate_cmd);
2486 }
2487
2488 /* Called when initializing driver */
2489 int iwl3945_hw_set_hw_params(struct iwl_priv *priv)
2490 {
2491         memset((void *)&priv->hw_params, 0,
2492                sizeof(struct iwl_hw_params));
2493
2494         priv->shared_virt =
2495             pci_alloc_consistent(priv->pci_dev,
2496                                  sizeof(struct iwl3945_shared),
2497                                  &priv->shared_phys);
2498
2499         if (!priv->shared_virt) {
2500                 IWL_ERR(priv, "failed to allocate pci memory\n");
2501                 mutex_unlock(&priv->mutex);
2502                 return -ENOMEM;
2503         }
2504
2505         /* Assign number of Usable TX queues */
2506         priv->hw_params.max_txq_num = IWL39_NUM_QUEUES;
2507
2508         priv->hw_params.tfd_size = sizeof(struct iwl3945_tfd);
2509         priv->hw_params.rx_buf_size = IWL_RX_BUF_SIZE_3K;
2510         priv->hw_params.max_pkt_size = 2342;
2511         priv->hw_params.max_rxq_size = RX_QUEUE_SIZE;
2512         priv->hw_params.max_rxq_log = RX_QUEUE_SIZE_LOG;
2513         priv->hw_params.max_stations = IWL3945_STATION_COUNT;
2514         priv->hw_params.bcast_sta_id = IWL3945_BROADCAST_ID;
2515
2516         priv->hw_params.rx_wrt_ptr_reg = FH39_RSCSR_CHNL0_WPTR;
2517         priv->hw_params.max_beacon_itrvl = IWL39_MAX_UCODE_BEACON_INTERVAL;
2518
2519         return 0;
2520 }
2521
2522 unsigned int iwl3945_hw_get_beacon_cmd(struct iwl_priv *priv,
2523                           struct iwl3945_frame *frame, u8 rate)
2524 {
2525         struct iwl3945_tx_beacon_cmd *tx_beacon_cmd;
2526         unsigned int frame_size;
2527
2528         tx_beacon_cmd = (struct iwl3945_tx_beacon_cmd *)&frame->u;
2529         memset(tx_beacon_cmd, 0, sizeof(*tx_beacon_cmd));
2530
2531         tx_beacon_cmd->tx.sta_id = priv->hw_params.bcast_sta_id;
2532         tx_beacon_cmd->tx.stop_time.life_time = TX_CMD_LIFE_TIME_INFINITE;
2533
2534         frame_size = iwl3945_fill_beacon_frame(priv,
2535                                 tx_beacon_cmd->frame,
2536                                 sizeof(frame->u) - sizeof(*tx_beacon_cmd));
2537
2538         BUG_ON(frame_size > MAX_MPDU_SIZE);
2539         tx_beacon_cmd->tx.len = cpu_to_le16((u16)frame_size);
2540
2541         tx_beacon_cmd->tx.rate = rate;
2542         tx_beacon_cmd->tx.tx_flags = (TX_CMD_FLG_SEQ_CTL_MSK |
2543                                       TX_CMD_FLG_TSF_MSK);
2544
2545         /* supp_rates[0] == OFDM start at IWL_FIRST_OFDM_RATE*/
2546         tx_beacon_cmd->tx.supp_rates[0] =
2547                 (IWL_OFDM_BASIC_RATES_MASK >> IWL_FIRST_OFDM_RATE) & 0xFF;
2548
2549         tx_beacon_cmd->tx.supp_rates[1] =
2550                 (IWL_CCK_BASIC_RATES_MASK & 0xF);
2551
2552         return sizeof(struct iwl3945_tx_beacon_cmd) + frame_size;
2553 }
2554
2555 void iwl3945_hw_rx_handler_setup(struct iwl_priv *priv)
2556 {
2557         priv->rx_handlers[REPLY_TX] = iwl3945_rx_reply_tx;
2558         priv->rx_handlers[REPLY_3945_RX] = iwl3945_rx_reply_rx;
2559 }
2560
2561 void iwl3945_hw_setup_deferred_work(struct iwl_priv *priv)
2562 {
2563         INIT_DELAYED_WORK(&priv->thermal_periodic,
2564                           iwl3945_bg_reg_txpower_periodic);
2565 }
2566
2567 void iwl3945_hw_cancel_deferred_work(struct iwl_priv *priv)
2568 {
2569         cancel_delayed_work(&priv->thermal_periodic);
2570 }
2571
2572 /* check contents of special bootstrap uCode SRAM */
2573 static int iwl3945_verify_bsm(struct iwl_priv *priv)
2574  {
2575         __le32 *image = priv->ucode_boot.v_addr;
2576         u32 len = priv->ucode_boot.len;
2577         u32 reg;
2578         u32 val;
2579
2580         IWL_DEBUG_INFO(priv, "Begin verify bsm\n");
2581
2582         /* verify BSM SRAM contents */
2583         val = iwl_read_prph(priv, BSM_WR_DWCOUNT_REG);
2584         for (reg = BSM_SRAM_LOWER_BOUND;
2585              reg < BSM_SRAM_LOWER_BOUND + len;
2586              reg += sizeof(u32), image++) {
2587                 val = iwl_read_prph(priv, reg);
2588                 if (val != le32_to_cpu(*image)) {
2589                         IWL_ERR(priv, "BSM uCode verification failed at "
2590                                   "addr 0x%08X+%u (of %u), is 0x%x, s/b 0x%x\n",
2591                                   BSM_SRAM_LOWER_BOUND,
2592                                   reg - BSM_SRAM_LOWER_BOUND, len,
2593                                   val, le32_to_cpu(*image));
2594                         return -EIO;
2595                 }
2596         }
2597
2598         IWL_DEBUG_INFO(priv, "BSM bootstrap uCode image OK\n");
2599
2600         return 0;
2601 }
2602
2603
2604 /******************************************************************************
2605  *
2606  * EEPROM related functions
2607  *
2608  ******************************************************************************/
2609
2610 /*
2611  * Clear the OWNER_MSK, to establish driver (instead of uCode running on
2612  * embedded controller) as EEPROM reader; each read is a series of pulses
2613  * to/from the EEPROM chip, not a single event, so even reads could conflict
2614  * if they weren't arbitrated by some ownership mechanism.  Here, the driver
2615  * simply claims ownership, which should be safe when this function is called
2616  * (i.e. before loading uCode!).
2617  */
2618 static int iwl3945_eeprom_acquire_semaphore(struct iwl_priv *priv)
2619 {
2620         _iwl_clear_bit(priv, CSR_EEPROM_GP, CSR_EEPROM_GP_IF_OWNER_MSK);
2621         return 0;
2622 }
2623
2624
2625 static void iwl3945_eeprom_release_semaphore(struct iwl_priv *priv)
2626 {
2627         return;
2628 }
2629
2630  /**
2631   * iwl3945_load_bsm - Load bootstrap instructions
2632   *
2633   * BSM operation:
2634   *
2635   * The Bootstrap State Machine (BSM) stores a short bootstrap uCode program
2636   * in special SRAM that does not power down during RFKILL.  When powering back
2637   * up after power-saving sleeps (or during initial uCode load), the BSM loads
2638   * the bootstrap program into the on-board processor, and starts it.
2639   *
2640   * The bootstrap program loads (via DMA) instructions and data for a new
2641   * program from host DRAM locations indicated by the host driver in the
2642   * BSM_DRAM_* registers.  Once the new program is loaded, it starts
2643   * automatically.
2644   *
2645   * When initializing the NIC, the host driver points the BSM to the
2646   * "initialize" uCode image.  This uCode sets up some internal data, then
2647   * notifies host via "initialize alive" that it is complete.
2648   *
2649   * The host then replaces the BSM_DRAM_* pointer values to point to the
2650   * normal runtime uCode instructions and a backup uCode data cache buffer
2651   * (filled initially with starting data values for the on-board processor),
2652   * then triggers the "initialize" uCode to load and launch the runtime uCode,
2653   * which begins normal operation.
2654   *
2655   * When doing a power-save shutdown, runtime uCode saves data SRAM into
2656   * the backup data cache in DRAM before SRAM is powered down.
2657   *
2658   * When powering back up, the BSM loads the bootstrap program.  This reloads
2659   * the runtime uCode instructions and the backup data cache into SRAM,
2660   * and re-launches the runtime uCode from where it left off.
2661   */
2662 static int iwl3945_load_bsm(struct iwl_priv *priv)
2663 {
2664         __le32 *image = priv->ucode_boot.v_addr;
2665         u32 len = priv->ucode_boot.len;
2666         dma_addr_t pinst;
2667         dma_addr_t pdata;
2668         u32 inst_len;
2669         u32 data_len;
2670         int rc;
2671         int i;
2672         u32 done;
2673         u32 reg_offset;
2674
2675         IWL_DEBUG_INFO(priv, "Begin load bsm\n");
2676
2677         /* make sure bootstrap program is no larger than BSM's SRAM size */
2678         if (len > IWL39_MAX_BSM_SIZE)
2679                 return -EINVAL;
2680
2681         /* Tell bootstrap uCode where to find the "Initialize" uCode
2682         *   in host DRAM ... host DRAM physical address bits 31:0 for 3945.
2683         * NOTE:  iwl3945_initialize_alive_start() will replace these values,
2684         *        after the "initialize" uCode has run, to point to
2685         *        runtime/protocol instructions and backup data cache. */
2686         pinst = priv->ucode_init.p_addr;
2687         pdata = priv->ucode_init_data.p_addr;
2688         inst_len = priv->ucode_init.len;
2689         data_len = priv->ucode_init_data.len;
2690
2691         iwl_write_prph(priv, BSM_DRAM_INST_PTR_REG, pinst);
2692         iwl_write_prph(priv, BSM_DRAM_DATA_PTR_REG, pdata);
2693         iwl_write_prph(priv, BSM_DRAM_INST_BYTECOUNT_REG, inst_len);
2694         iwl_write_prph(priv, BSM_DRAM_DATA_BYTECOUNT_REG, data_len);
2695
2696         /* Fill BSM memory with bootstrap instructions */
2697         for (reg_offset = BSM_SRAM_LOWER_BOUND;
2698              reg_offset < BSM_SRAM_LOWER_BOUND + len;
2699              reg_offset += sizeof(u32), image++)
2700                 _iwl_write_prph(priv, reg_offset,
2701                                           le32_to_cpu(*image));
2702
2703         rc = iwl3945_verify_bsm(priv);
2704         if (rc)
2705                 return rc;
2706
2707         /* Tell BSM to copy from BSM SRAM into instruction SRAM, when asked */
2708         iwl_write_prph(priv, BSM_WR_MEM_SRC_REG, 0x0);
2709         iwl_write_prph(priv, BSM_WR_MEM_DST_REG,
2710                                  IWL39_RTC_INST_LOWER_BOUND);
2711         iwl_write_prph(priv, BSM_WR_DWCOUNT_REG, len / sizeof(u32));
2712
2713         /* Load bootstrap code into instruction SRAM now,
2714          *   to prepare to load "initialize" uCode */
2715         iwl_write_prph(priv, BSM_WR_CTRL_REG,
2716                 BSM_WR_CTRL_REG_BIT_START);
2717
2718         /* Wait for load of bootstrap uCode to finish */
2719         for (i = 0; i < 100; i++) {
2720                 done = iwl_read_prph(priv, BSM_WR_CTRL_REG);
2721                 if (!(done & BSM_WR_CTRL_REG_BIT_START))
2722                         break;
2723                 udelay(10);
2724         }
2725         if (i < 100)
2726                 IWL_DEBUG_INFO(priv, "BSM write complete, poll %d iterations\n", i);
2727         else {
2728                 IWL_ERR(priv, "BSM write did not complete!\n");
2729                 return -EIO;
2730         }
2731
2732         /* Enable future boot loads whenever power management unit triggers it
2733          *   (e.g. when powering back up after power-save shutdown) */
2734         iwl_write_prph(priv, BSM_WR_CTRL_REG,
2735                 BSM_WR_CTRL_REG_BIT_START_EN);
2736
2737         return 0;
2738 }
2739
2740 #define IWL3945_UCODE_GET(item)                                         \
2741 static u32 iwl3945_ucode_get_##item(const struct iwl_ucode_header *ucode,\
2742                                     u32 api_ver)                        \
2743 {                                                                       \
2744         return le32_to_cpu(ucode->u.v1.item);                           \
2745 }
2746
2747 static u32 iwl3945_ucode_get_header_size(u32 api_ver)
2748 {
2749         return UCODE_HEADER_SIZE(1);
2750 }
2751 static u32 iwl3945_ucode_get_build(const struct iwl_ucode_header *ucode,
2752                                    u32 api_ver)
2753 {
2754         return 0;
2755 }
2756 static u8 *iwl3945_ucode_get_data(const struct iwl_ucode_header *ucode,
2757                                   u32 api_ver)
2758 {
2759         return (u8 *) ucode->u.v1.data;
2760 }
2761
2762 IWL3945_UCODE_GET(inst_size);
2763 IWL3945_UCODE_GET(data_size);
2764 IWL3945_UCODE_GET(init_size);
2765 IWL3945_UCODE_GET(init_data_size);
2766 IWL3945_UCODE_GET(boot_size);
2767
2768 static struct iwl_hcmd_ops iwl3945_hcmd = {
2769         .rxon_assoc = iwl3945_send_rxon_assoc,
2770         .commit_rxon = iwl3945_commit_rxon,
2771 };
2772
2773 static struct iwl_ucode_ops iwl3945_ucode = {
2774         .get_header_size = iwl3945_ucode_get_header_size,
2775         .get_build = iwl3945_ucode_get_build,
2776         .get_inst_size = iwl3945_ucode_get_inst_size,
2777         .get_data_size = iwl3945_ucode_get_data_size,
2778         .get_init_size = iwl3945_ucode_get_init_size,
2779         .get_init_data_size = iwl3945_ucode_get_init_data_size,
2780         .get_boot_size = iwl3945_ucode_get_boot_size,
2781         .get_data = iwl3945_ucode_get_data,
2782 };
2783
2784 static struct iwl_lib_ops iwl3945_lib = {
2785         .txq_attach_buf_to_tfd = iwl3945_hw_txq_attach_buf_to_tfd,
2786         .txq_free_tfd = iwl3945_hw_txq_free_tfd,
2787         .txq_init = iwl3945_hw_tx_queue_init,
2788         .load_ucode = iwl3945_load_bsm,
2789         .dump_nic_event_log = iwl3945_dump_nic_event_log,
2790         .dump_nic_error_log = iwl3945_dump_nic_error_log,
2791         .apm_ops = {
2792                 .init = iwl3945_apm_init,
2793                 .stop = iwl_apm_stop,
2794                 .config = iwl3945_nic_config,
2795                 .set_pwr_src = iwl3945_set_pwr_src,
2796         },
2797         .eeprom_ops = {
2798                 .regulatory_bands = {
2799                         EEPROM_REGULATORY_BAND_1_CHANNELS,
2800                         EEPROM_REGULATORY_BAND_2_CHANNELS,
2801                         EEPROM_REGULATORY_BAND_3_CHANNELS,
2802                         EEPROM_REGULATORY_BAND_4_CHANNELS,
2803                         EEPROM_REGULATORY_BAND_5_CHANNELS,
2804                         EEPROM_REGULATORY_BAND_NO_HT40,
2805                         EEPROM_REGULATORY_BAND_NO_HT40,
2806                 },
2807                 .verify_signature  = iwlcore_eeprom_verify_signature,
2808                 .acquire_semaphore = iwl3945_eeprom_acquire_semaphore,
2809                 .release_semaphore = iwl3945_eeprom_release_semaphore,
2810                 .query_addr = iwlcore_eeprom_query_addr,
2811         },
2812         .send_tx_power  = iwl3945_send_tx_power,
2813         .is_valid_rtc_data_addr = iwl3945_hw_valid_rtc_data_addr,
2814         .post_associate = iwl3945_post_associate,
2815         .isr = iwl_isr_legacy,
2816         .config_ap = iwl3945_config_ap,
2817 };
2818
2819 static struct iwl_hcmd_utils_ops iwl3945_hcmd_utils = {
2820         .get_hcmd_size = iwl3945_get_hcmd_size,
2821         .build_addsta_hcmd = iwl3945_build_addsta_hcmd,
2822 };
2823
2824 static struct iwl_ops iwl3945_ops = {
2825         .ucode = &iwl3945_ucode,
2826         .lib = &iwl3945_lib,
2827         .hcmd = &iwl3945_hcmd,
2828         .utils = &iwl3945_hcmd_utils,
2829         .led = &iwl3945_led_ops,
2830 };
2831
2832 static struct iwl_cfg iwl3945_bg_cfg = {
2833         .name = "3945BG",
2834         .fw_name_pre = IWL3945_FW_PRE,
2835         .ucode_api_max = IWL3945_UCODE_API_MAX,
2836         .ucode_api_min = IWL3945_UCODE_API_MIN,
2837         .sku = IWL_SKU_G,
2838         .eeprom_size = IWL3945_EEPROM_IMG_SIZE,
2839         .eeprom_ver = EEPROM_3945_EEPROM_VERSION,
2840         .ops = &iwl3945_ops,
2841         .mod_params = &iwl3945_mod_params,
2842         .use_isr_legacy = true,
2843         .ht_greenfield_support = false,
2844         .led_compensation = 64,
2845 };
2846
2847 static struct iwl_cfg iwl3945_abg_cfg = {
2848         .name = "3945ABG",
2849         .fw_name_pre = IWL3945_FW_PRE,
2850         .ucode_api_max = IWL3945_UCODE_API_MAX,
2851         .ucode_api_min = IWL3945_UCODE_API_MIN,
2852         .sku = IWL_SKU_A|IWL_SKU_G,
2853         .eeprom_size = IWL3945_EEPROM_IMG_SIZE,
2854         .eeprom_ver = EEPROM_3945_EEPROM_VERSION,
2855         .ops = &iwl3945_ops,
2856         .mod_params = &iwl3945_mod_params,
2857         .use_isr_legacy = true,
2858         .ht_greenfield_support = false,
2859         .led_compensation = 64,
2860 };
2861
2862 struct pci_device_id iwl3945_hw_card_ids[] = {
2863         {IWL_PCI_DEVICE(0x4222, 0x1005, iwl3945_bg_cfg)},
2864         {IWL_PCI_DEVICE(0x4222, 0x1034, iwl3945_bg_cfg)},
2865         {IWL_PCI_DEVICE(0x4222, 0x1044, iwl3945_bg_cfg)},
2866         {IWL_PCI_DEVICE(0x4227, 0x1014, iwl3945_bg_cfg)},
2867         {IWL_PCI_DEVICE(0x4222, PCI_ANY_ID, iwl3945_abg_cfg)},
2868         {IWL_PCI_DEVICE(0x4227, PCI_ANY_ID, iwl3945_abg_cfg)},
2869         {0}
2870 };
2871
2872 MODULE_DEVICE_TABLE(pci, iwl3945_hw_card_ids);