Merge branch 'from-linus' into upstream
[linux-2.6.git] / drivers / net / wireless / ipw2200.c
1 /******************************************************************************
2
3   Copyright(c) 2003 - 2006 Intel Corporation. All rights reserved.
4
5   802.11 status code portion of this file from ethereal-0.10.6:
6     Copyright 2000, Axis Communications AB
7     Ethereal - Network traffic analyzer
8     By Gerald Combs <gerald@ethereal.com>
9     Copyright 1998 Gerald Combs
10
11   This program is free software; you can redistribute it and/or modify it
12   under the terms of version 2 of the GNU General Public License as
13   published by the Free Software Foundation.
14
15   This program is distributed in the hope that it will be useful, but WITHOUT
16   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
17   FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
18   more details.
19
20   You should have received a copy of the GNU General Public License along with
21   this program; if not, write to the Free Software Foundation, Inc., 59
22   Temple Place - Suite 330, Boston, MA  02111-1307, USA.
23
24   The full GNU General Public License is included in this distribution in the
25   file called LICENSE.
26
27   Contact Information:
28   James P. Ketrenos <ipw2100-admin@linux.intel.com>
29   Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
30
31 ******************************************************************************/
32
33 #include "ipw2200.h"
34 #include <linux/version.h>
35
36
37 #ifndef KBUILD_EXTMOD
38 #define VK "k"
39 #else
40 #define VK
41 #endif
42
43 #ifdef CONFIG_IPW2200_DEBUG
44 #define VD "d"
45 #else
46 #define VD
47 #endif
48
49 #ifdef CONFIG_IPW2200_MONITOR
50 #define VM "m"
51 #else
52 #define VM
53 #endif
54
55 #ifdef CONFIG_IPW2200_PROMISCUOUS
56 #define VP "p"
57 #else
58 #define VP
59 #endif
60
61 #ifdef CONFIG_IPW2200_RADIOTAP
62 #define VR "r"
63 #else
64 #define VR
65 #endif
66
67 #ifdef CONFIG_IPW2200_QOS
68 #define VQ "q"
69 #else
70 #define VQ
71 #endif
72
73 #define IPW2200_VERSION "1.1.2" VK VD VM VP VR VQ
74 #define DRV_DESCRIPTION "Intel(R) PRO/Wireless 2200/2915 Network Driver"
75 #define DRV_COPYRIGHT   "Copyright(c) 2003-2006 Intel Corporation"
76 #define DRV_VERSION     IPW2200_VERSION
77
78 #define ETH_P_80211_STATS (ETH_P_80211_RAW + 1)
79
80 MODULE_DESCRIPTION(DRV_DESCRIPTION);
81 MODULE_VERSION(DRV_VERSION);
82 MODULE_AUTHOR(DRV_COPYRIGHT);
83 MODULE_LICENSE("GPL");
84
85 static int cmdlog = 0;
86 #ifdef CONFIG_IPW2200_DEBUG
87 static int debug = 0;
88 #endif
89 static int channel = 0;
90 static int mode = 0;
91
92 static u32 ipw_debug_level;
93 static int associate = 1;
94 static int auto_create = 1;
95 static int led = 0;
96 static int disable = 0;
97 static int bt_coexist = 0;
98 static int hwcrypto = 0;
99 static int roaming = 1;
100 static const char ipw_modes[] = {
101         'a', 'b', 'g', '?'
102 };
103 static int antenna = CFG_SYS_ANTENNA_BOTH;
104
105 #ifdef CONFIG_IPW2200_PROMISCUOUS
106 static int rtap_iface = 0;     /* def: 0 -- do not create rtap interface */
107 #endif
108
109
110 #ifdef CONFIG_IPW2200_QOS
111 static int qos_enable = 0;
112 static int qos_burst_enable = 0;
113 static int qos_no_ack_mask = 0;
114 static int burst_duration_CCK = 0;
115 static int burst_duration_OFDM = 0;
116
117 static struct ieee80211_qos_parameters def_qos_parameters_OFDM = {
118         {QOS_TX0_CW_MIN_OFDM, QOS_TX1_CW_MIN_OFDM, QOS_TX2_CW_MIN_OFDM,
119          QOS_TX3_CW_MIN_OFDM},
120         {QOS_TX0_CW_MAX_OFDM, QOS_TX1_CW_MAX_OFDM, QOS_TX2_CW_MAX_OFDM,
121          QOS_TX3_CW_MAX_OFDM},
122         {QOS_TX0_AIFS, QOS_TX1_AIFS, QOS_TX2_AIFS, QOS_TX3_AIFS},
123         {QOS_TX0_ACM, QOS_TX1_ACM, QOS_TX2_ACM, QOS_TX3_ACM},
124         {QOS_TX0_TXOP_LIMIT_OFDM, QOS_TX1_TXOP_LIMIT_OFDM,
125          QOS_TX2_TXOP_LIMIT_OFDM, QOS_TX3_TXOP_LIMIT_OFDM}
126 };
127
128 static struct ieee80211_qos_parameters def_qos_parameters_CCK = {
129         {QOS_TX0_CW_MIN_CCK, QOS_TX1_CW_MIN_CCK, QOS_TX2_CW_MIN_CCK,
130          QOS_TX3_CW_MIN_CCK},
131         {QOS_TX0_CW_MAX_CCK, QOS_TX1_CW_MAX_CCK, QOS_TX2_CW_MAX_CCK,
132          QOS_TX3_CW_MAX_CCK},
133         {QOS_TX0_AIFS, QOS_TX1_AIFS, QOS_TX2_AIFS, QOS_TX3_AIFS},
134         {QOS_TX0_ACM, QOS_TX1_ACM, QOS_TX2_ACM, QOS_TX3_ACM},
135         {QOS_TX0_TXOP_LIMIT_CCK, QOS_TX1_TXOP_LIMIT_CCK, QOS_TX2_TXOP_LIMIT_CCK,
136          QOS_TX3_TXOP_LIMIT_CCK}
137 };
138
139 static struct ieee80211_qos_parameters def_parameters_OFDM = {
140         {DEF_TX0_CW_MIN_OFDM, DEF_TX1_CW_MIN_OFDM, DEF_TX2_CW_MIN_OFDM,
141          DEF_TX3_CW_MIN_OFDM},
142         {DEF_TX0_CW_MAX_OFDM, DEF_TX1_CW_MAX_OFDM, DEF_TX2_CW_MAX_OFDM,
143          DEF_TX3_CW_MAX_OFDM},
144         {DEF_TX0_AIFS, DEF_TX1_AIFS, DEF_TX2_AIFS, DEF_TX3_AIFS},
145         {DEF_TX0_ACM, DEF_TX1_ACM, DEF_TX2_ACM, DEF_TX3_ACM},
146         {DEF_TX0_TXOP_LIMIT_OFDM, DEF_TX1_TXOP_LIMIT_OFDM,
147          DEF_TX2_TXOP_LIMIT_OFDM, DEF_TX3_TXOP_LIMIT_OFDM}
148 };
149
150 static struct ieee80211_qos_parameters def_parameters_CCK = {
151         {DEF_TX0_CW_MIN_CCK, DEF_TX1_CW_MIN_CCK, DEF_TX2_CW_MIN_CCK,
152          DEF_TX3_CW_MIN_CCK},
153         {DEF_TX0_CW_MAX_CCK, DEF_TX1_CW_MAX_CCK, DEF_TX2_CW_MAX_CCK,
154          DEF_TX3_CW_MAX_CCK},
155         {DEF_TX0_AIFS, DEF_TX1_AIFS, DEF_TX2_AIFS, DEF_TX3_AIFS},
156         {DEF_TX0_ACM, DEF_TX1_ACM, DEF_TX2_ACM, DEF_TX3_ACM},
157         {DEF_TX0_TXOP_LIMIT_CCK, DEF_TX1_TXOP_LIMIT_CCK, DEF_TX2_TXOP_LIMIT_CCK,
158          DEF_TX3_TXOP_LIMIT_CCK}
159 };
160
161 static u8 qos_oui[QOS_OUI_LEN] = { 0x00, 0x50, 0xF2 };
162
163 static int from_priority_to_tx_queue[] = {
164         IPW_TX_QUEUE_1, IPW_TX_QUEUE_2, IPW_TX_QUEUE_2, IPW_TX_QUEUE_1,
165         IPW_TX_QUEUE_3, IPW_TX_QUEUE_3, IPW_TX_QUEUE_4, IPW_TX_QUEUE_4
166 };
167
168 static u32 ipw_qos_get_burst_duration(struct ipw_priv *priv);
169
170 static int ipw_send_qos_params_command(struct ipw_priv *priv, struct ieee80211_qos_parameters
171                                        *qos_param);
172 static int ipw_send_qos_info_command(struct ipw_priv *priv, struct ieee80211_qos_information_element
173                                      *qos_param);
174 #endif                          /* CONFIG_IPW2200_QOS */
175
176 static struct iw_statistics *ipw_get_wireless_stats(struct net_device *dev);
177 static void ipw_remove_current_network(struct ipw_priv *priv);
178 static void ipw_rx(struct ipw_priv *priv);
179 static int ipw_queue_tx_reclaim(struct ipw_priv *priv,
180                                 struct clx2_tx_queue *txq, int qindex);
181 static int ipw_queue_reset(struct ipw_priv *priv);
182
183 static int ipw_queue_tx_hcmd(struct ipw_priv *priv, int hcmd, void *buf,
184                              int len, int sync);
185
186 static void ipw_tx_queue_free(struct ipw_priv *);
187
188 static struct ipw_rx_queue *ipw_rx_queue_alloc(struct ipw_priv *);
189 static void ipw_rx_queue_free(struct ipw_priv *, struct ipw_rx_queue *);
190 static void ipw_rx_queue_replenish(void *);
191 static int ipw_up(struct ipw_priv *);
192 static void ipw_bg_up(void *);
193 static void ipw_down(struct ipw_priv *);
194 static void ipw_bg_down(void *);
195 static int ipw_config(struct ipw_priv *);
196 static int init_supported_rates(struct ipw_priv *priv,
197                                 struct ipw_supported_rates *prates);
198 static void ipw_set_hwcrypto_keys(struct ipw_priv *);
199 static void ipw_send_wep_keys(struct ipw_priv *, int);
200
201 static int snprint_line(char *buf, size_t count,
202                         const u8 * data, u32 len, u32 ofs)
203 {
204         int out, i, j, l;
205         char c;
206
207         out = snprintf(buf, count, "%08X", ofs);
208
209         for (l = 0, i = 0; i < 2; i++) {
210                 out += snprintf(buf + out, count - out, " ");
211                 for (j = 0; j < 8 && l < len; j++, l++)
212                         out += snprintf(buf + out, count - out, "%02X ",
213                                         data[(i * 8 + j)]);
214                 for (; j < 8; j++)
215                         out += snprintf(buf + out, count - out, "   ");
216         }
217
218         out += snprintf(buf + out, count - out, " ");
219         for (l = 0, i = 0; i < 2; i++) {
220                 out += snprintf(buf + out, count - out, " ");
221                 for (j = 0; j < 8 && l < len; j++, l++) {
222                         c = data[(i * 8 + j)];
223                         if (!isascii(c) || !isprint(c))
224                                 c = '.';
225
226                         out += snprintf(buf + out, count - out, "%c", c);
227                 }
228
229                 for (; j < 8; j++)
230                         out += snprintf(buf + out, count - out, " ");
231         }
232
233         return out;
234 }
235
236 static void printk_buf(int level, const u8 * data, u32 len)
237 {
238         char line[81];
239         u32 ofs = 0;
240         if (!(ipw_debug_level & level))
241                 return;
242
243         while (len) {
244                 snprint_line(line, sizeof(line), &data[ofs],
245                              min(len, 16U), ofs);
246                 printk(KERN_DEBUG "%s\n", line);
247                 ofs += 16;
248                 len -= min(len, 16U);
249         }
250 }
251
252 static int snprintk_buf(u8 * output, size_t size, const u8 * data, size_t len)
253 {
254         size_t out = size;
255         u32 ofs = 0;
256         int total = 0;
257
258         while (size && len) {
259                 out = snprint_line(output, size, &data[ofs],
260                                    min_t(size_t, len, 16U), ofs);
261
262                 ofs += 16;
263                 output += out;
264                 size -= out;
265                 len -= min_t(size_t, len, 16U);
266                 total += out;
267         }
268         return total;
269 }
270
271 /* alias for 32-bit indirect read (for SRAM/reg above 4K), with debug wrapper */
272 static u32 _ipw_read_reg32(struct ipw_priv *priv, u32 reg);
273 #define ipw_read_reg32(a, b) _ipw_read_reg32(a, b)
274
275 /* alias for 8-bit indirect read (for SRAM/reg above 4K), with debug wrapper */
276 static u8 _ipw_read_reg8(struct ipw_priv *ipw, u32 reg);
277 #define ipw_read_reg8(a, b) _ipw_read_reg8(a, b)
278
279 /* 8-bit indirect write (for SRAM/reg above 4K), with debug wrapper */
280 static void _ipw_write_reg8(struct ipw_priv *priv, u32 reg, u8 value);
281 static inline void ipw_write_reg8(struct ipw_priv *a, u32 b, u8 c)
282 {
283         IPW_DEBUG_IO("%s %d: write_indirect8(0x%08X, 0x%08X)\n", __FILE__,
284                      __LINE__, (u32) (b), (u32) (c));
285         _ipw_write_reg8(a, b, c);
286 }
287
288 /* 16-bit indirect write (for SRAM/reg above 4K), with debug wrapper */
289 static void _ipw_write_reg16(struct ipw_priv *priv, u32 reg, u16 value);
290 static inline void ipw_write_reg16(struct ipw_priv *a, u32 b, u16 c)
291 {
292         IPW_DEBUG_IO("%s %d: write_indirect16(0x%08X, 0x%08X)\n", __FILE__,
293                      __LINE__, (u32) (b), (u32) (c));
294         _ipw_write_reg16(a, b, c);
295 }
296
297 /* 32-bit indirect write (for SRAM/reg above 4K), with debug wrapper */
298 static void _ipw_write_reg32(struct ipw_priv *priv, u32 reg, u32 value);
299 static inline void ipw_write_reg32(struct ipw_priv *a, u32 b, u32 c)
300 {
301         IPW_DEBUG_IO("%s %d: write_indirect32(0x%08X, 0x%08X)\n", __FILE__,
302                      __LINE__, (u32) (b), (u32) (c));
303         _ipw_write_reg32(a, b, c);
304 }
305
306 /* 8-bit direct write (low 4K) */
307 #define _ipw_write8(ipw, ofs, val) writeb((val), (ipw)->hw_base + (ofs))
308
309 /* 8-bit direct write (for low 4K of SRAM/regs), with debug wrapper */
310 #define ipw_write8(ipw, ofs, val) \
311  IPW_DEBUG_IO("%s %d: write_direct8(0x%08X, 0x%08X)\n", __FILE__, __LINE__, (u32)(ofs), (u32)(val)); \
312  _ipw_write8(ipw, ofs, val)
313
314 /* 16-bit direct write (low 4K) */
315 #define _ipw_write16(ipw, ofs, val) writew((val), (ipw)->hw_base + (ofs))
316
317 /* 16-bit direct write (for low 4K of SRAM/regs), with debug wrapper */
318 #define ipw_write16(ipw, ofs, val) \
319  IPW_DEBUG_IO("%s %d: write_direct16(0x%08X, 0x%08X)\n", __FILE__, __LINE__, (u32)(ofs), (u32)(val)); \
320  _ipw_write16(ipw, ofs, val)
321
322 /* 32-bit direct write (low 4K) */
323 #define _ipw_write32(ipw, ofs, val) writel((val), (ipw)->hw_base + (ofs))
324
325 /* 32-bit direct write (for low 4K of SRAM/regs), with debug wrapper */
326 #define ipw_write32(ipw, ofs, val) \
327  IPW_DEBUG_IO("%s %d: write_direct32(0x%08X, 0x%08X)\n", __FILE__, __LINE__, (u32)(ofs), (u32)(val)); \
328  _ipw_write32(ipw, ofs, val)
329
330 /* 8-bit direct read (low 4K) */
331 #define _ipw_read8(ipw, ofs) readb((ipw)->hw_base + (ofs))
332
333 /* 8-bit direct read (low 4K), with debug wrapper */
334 static inline u8 __ipw_read8(char *f, u32 l, struct ipw_priv *ipw, u32 ofs)
335 {
336         IPW_DEBUG_IO("%s %d: read_direct8(0x%08X)\n", f, l, (u32) (ofs));
337         return _ipw_read8(ipw, ofs);
338 }
339
340 /* alias to 8-bit direct read (low 4K of SRAM/regs), with debug wrapper */
341 #define ipw_read8(ipw, ofs) __ipw_read8(__FILE__, __LINE__, ipw, ofs)
342
343 /* 16-bit direct read (low 4K) */
344 #define _ipw_read16(ipw, ofs) readw((ipw)->hw_base + (ofs))
345
346 /* 16-bit direct read (low 4K), with debug wrapper */
347 static inline u16 __ipw_read16(char *f, u32 l, struct ipw_priv *ipw, u32 ofs)
348 {
349         IPW_DEBUG_IO("%s %d: read_direct16(0x%08X)\n", f, l, (u32) (ofs));
350         return _ipw_read16(ipw, ofs);
351 }
352
353 /* alias to 16-bit direct read (low 4K of SRAM/regs), with debug wrapper */
354 #define ipw_read16(ipw, ofs) __ipw_read16(__FILE__, __LINE__, ipw, ofs)
355
356 /* 32-bit direct read (low 4K) */
357 #define _ipw_read32(ipw, ofs) readl((ipw)->hw_base + (ofs))
358
359 /* 32-bit direct read (low 4K), with debug wrapper */
360 static inline u32 __ipw_read32(char *f, u32 l, struct ipw_priv *ipw, u32 ofs)
361 {
362         IPW_DEBUG_IO("%s %d: read_direct32(0x%08X)\n", f, l, (u32) (ofs));
363         return _ipw_read32(ipw, ofs);
364 }
365
366 /* alias to 32-bit direct read (low 4K of SRAM/regs), with debug wrapper */
367 #define ipw_read32(ipw, ofs) __ipw_read32(__FILE__, __LINE__, ipw, ofs)
368
369 /* multi-byte read (above 4K), with debug wrapper */
370 static void _ipw_read_indirect(struct ipw_priv *, u32, u8 *, int);
371 static inline void __ipw_read_indirect(const char *f, int l,
372                                        struct ipw_priv *a, u32 b, u8 * c, int d)
373 {
374         IPW_DEBUG_IO("%s %d: read_indirect(0x%08X) %d bytes\n", f, l, (u32) (b),
375                      d);
376         _ipw_read_indirect(a, b, c, d);
377 }
378
379 /* alias to multi-byte read (SRAM/regs above 4K), with debug wrapper */
380 #define ipw_read_indirect(a, b, c, d) __ipw_read_indirect(__FILE__, __LINE__, a, b, c, d)
381
382 /* alias to multi-byte read (SRAM/regs above 4K), with debug wrapper */
383 static void _ipw_write_indirect(struct ipw_priv *priv, u32 addr, u8 * data,
384                                 int num);
385 #define ipw_write_indirect(a, b, c, d) \
386         IPW_DEBUG_IO("%s %d: write_indirect(0x%08X) %d bytes\n", __FILE__, __LINE__, (u32)(b), d); \
387         _ipw_write_indirect(a, b, c, d)
388
389 /* 32-bit indirect write (above 4K) */
390 static void _ipw_write_reg32(struct ipw_priv *priv, u32 reg, u32 value)
391 {
392         IPW_DEBUG_IO(" %p : reg = 0x%8X : value = 0x%8X\n", priv, reg, value);
393         _ipw_write32(priv, IPW_INDIRECT_ADDR, reg);
394         _ipw_write32(priv, IPW_INDIRECT_DATA, value);
395 }
396
397 /* 8-bit indirect write (above 4K) */
398 static void _ipw_write_reg8(struct ipw_priv *priv, u32 reg, u8 value)
399 {
400         u32 aligned_addr = reg & IPW_INDIRECT_ADDR_MASK;        /* dword align */
401         u32 dif_len = reg - aligned_addr;
402
403         IPW_DEBUG_IO(" reg = 0x%8X : value = 0x%8X\n", reg, value);
404         _ipw_write32(priv, IPW_INDIRECT_ADDR, aligned_addr);
405         _ipw_write8(priv, IPW_INDIRECT_DATA + dif_len, value);
406 }
407
408 /* 16-bit indirect write (above 4K) */
409 static void _ipw_write_reg16(struct ipw_priv *priv, u32 reg, u16 value)
410 {
411         u32 aligned_addr = reg & IPW_INDIRECT_ADDR_MASK;        /* dword align */
412         u32 dif_len = (reg - aligned_addr) & (~0x1ul);
413
414         IPW_DEBUG_IO(" reg = 0x%8X : value = 0x%8X\n", reg, value);
415         _ipw_write32(priv, IPW_INDIRECT_ADDR, aligned_addr);
416         _ipw_write16(priv, IPW_INDIRECT_DATA + dif_len, value);
417 }
418
419 /* 8-bit indirect read (above 4K) */
420 static u8 _ipw_read_reg8(struct ipw_priv *priv, u32 reg)
421 {
422         u32 word;
423         _ipw_write32(priv, IPW_INDIRECT_ADDR, reg & IPW_INDIRECT_ADDR_MASK);
424         IPW_DEBUG_IO(" reg = 0x%8X : \n", reg);
425         word = _ipw_read32(priv, IPW_INDIRECT_DATA);
426         return (word >> ((reg & 0x3) * 8)) & 0xff;
427 }
428
429 /* 32-bit indirect read (above 4K) */
430 static u32 _ipw_read_reg32(struct ipw_priv *priv, u32 reg)
431 {
432         u32 value;
433
434         IPW_DEBUG_IO("%p : reg = 0x%08x\n", priv, reg);
435
436         _ipw_write32(priv, IPW_INDIRECT_ADDR, reg);
437         value = _ipw_read32(priv, IPW_INDIRECT_DATA);
438         IPW_DEBUG_IO(" reg = 0x%4X : value = 0x%4x \n", reg, value);
439         return value;
440 }
441
442 /* General purpose, no alignment requirement, iterative (multi-byte) read, */
443 /*    for area above 1st 4K of SRAM/reg space */
444 static void _ipw_read_indirect(struct ipw_priv *priv, u32 addr, u8 * buf,
445                                int num)
446 {
447         u32 aligned_addr = addr & IPW_INDIRECT_ADDR_MASK;       /* dword align */
448         u32 dif_len = addr - aligned_addr;
449         u32 i;
450
451         IPW_DEBUG_IO("addr = %i, buf = %p, num = %i\n", addr, buf, num);
452
453         if (num <= 0) {
454                 return;
455         }
456
457         /* Read the first dword (or portion) byte by byte */
458         if (unlikely(dif_len)) {
459                 _ipw_write32(priv, IPW_INDIRECT_ADDR, aligned_addr);
460                 /* Start reading at aligned_addr + dif_len */
461                 for (i = dif_len; ((i < 4) && (num > 0)); i++, num--)
462                         *buf++ = _ipw_read8(priv, IPW_INDIRECT_DATA + i);
463                 aligned_addr += 4;
464         }
465
466         /* Read all of the middle dwords as dwords, with auto-increment */
467         _ipw_write32(priv, IPW_AUTOINC_ADDR, aligned_addr);
468         for (; num >= 4; buf += 4, aligned_addr += 4, num -= 4)
469                 *(u32 *) buf = _ipw_read32(priv, IPW_AUTOINC_DATA);
470
471         /* Read the last dword (or portion) byte by byte */
472         if (unlikely(num)) {
473                 _ipw_write32(priv, IPW_INDIRECT_ADDR, aligned_addr);
474                 for (i = 0; num > 0; i++, num--)
475                         *buf++ = ipw_read8(priv, IPW_INDIRECT_DATA + i);
476         }
477 }
478
479 /* General purpose, no alignment requirement, iterative (multi-byte) write, */
480 /*    for area above 1st 4K of SRAM/reg space */
481 static void _ipw_write_indirect(struct ipw_priv *priv, u32 addr, u8 * buf,
482                                 int num)
483 {
484         u32 aligned_addr = addr & IPW_INDIRECT_ADDR_MASK;       /* dword align */
485         u32 dif_len = addr - aligned_addr;
486         u32 i;
487
488         IPW_DEBUG_IO("addr = %i, buf = %p, num = %i\n", addr, buf, num);
489
490         if (num <= 0) {
491                 return;
492         }
493
494         /* Write the first dword (or portion) byte by byte */
495         if (unlikely(dif_len)) {
496                 _ipw_write32(priv, IPW_INDIRECT_ADDR, aligned_addr);
497                 /* Start writing at aligned_addr + dif_len */
498                 for (i = dif_len; ((i < 4) && (num > 0)); i++, num--, buf++)
499                         _ipw_write8(priv, IPW_INDIRECT_DATA + i, *buf);
500                 aligned_addr += 4;
501         }
502
503         /* Write all of the middle dwords as dwords, with auto-increment */
504         _ipw_write32(priv, IPW_AUTOINC_ADDR, aligned_addr);
505         for (; num >= 4; buf += 4, aligned_addr += 4, num -= 4)
506                 _ipw_write32(priv, IPW_AUTOINC_DATA, *(u32 *) buf);
507
508         /* Write the last dword (or portion) byte by byte */
509         if (unlikely(num)) {
510                 _ipw_write32(priv, IPW_INDIRECT_ADDR, aligned_addr);
511                 for (i = 0; num > 0; i++, num--, buf++)
512                         _ipw_write8(priv, IPW_INDIRECT_DATA + i, *buf);
513         }
514 }
515
516 /* General purpose, no alignment requirement, iterative (multi-byte) write, */
517 /*    for 1st 4K of SRAM/regs space */
518 static void ipw_write_direct(struct ipw_priv *priv, u32 addr, void *buf,
519                              int num)
520 {
521         memcpy_toio((priv->hw_base + addr), buf, num);
522 }
523
524 /* Set bit(s) in low 4K of SRAM/regs */
525 static inline void ipw_set_bit(struct ipw_priv *priv, u32 reg, u32 mask)
526 {
527         ipw_write32(priv, reg, ipw_read32(priv, reg) | mask);
528 }
529
530 /* Clear bit(s) in low 4K of SRAM/regs */
531 static inline void ipw_clear_bit(struct ipw_priv *priv, u32 reg, u32 mask)
532 {
533         ipw_write32(priv, reg, ipw_read32(priv, reg) & ~mask);
534 }
535
536 static inline void __ipw_enable_interrupts(struct ipw_priv *priv)
537 {
538         if (priv->status & STATUS_INT_ENABLED)
539                 return;
540         priv->status |= STATUS_INT_ENABLED;
541         ipw_write32(priv, IPW_INTA_MASK_R, IPW_INTA_MASK_ALL);
542 }
543
544 static inline void __ipw_disable_interrupts(struct ipw_priv *priv)
545 {
546         if (!(priv->status & STATUS_INT_ENABLED))
547                 return;
548         priv->status &= ~STATUS_INT_ENABLED;
549         ipw_write32(priv, IPW_INTA_MASK_R, ~IPW_INTA_MASK_ALL);
550 }
551
552 static inline void ipw_enable_interrupts(struct ipw_priv *priv)
553 {
554         unsigned long flags;
555
556         spin_lock_irqsave(&priv->irq_lock, flags);
557         __ipw_enable_interrupts(priv);
558         spin_unlock_irqrestore(&priv->irq_lock, flags);
559 }
560
561 static inline void ipw_disable_interrupts(struct ipw_priv *priv)
562 {
563         unsigned long flags;
564
565         spin_lock_irqsave(&priv->irq_lock, flags);
566         __ipw_disable_interrupts(priv);
567         spin_unlock_irqrestore(&priv->irq_lock, flags);
568 }
569
570 #ifdef CONFIG_IPW2200_DEBUG
571 static char *ipw_error_desc(u32 val)
572 {
573         switch (val) {
574         case IPW_FW_ERROR_OK:
575                 return "ERROR_OK";
576         case IPW_FW_ERROR_FAIL:
577                 return "ERROR_FAIL";
578         case IPW_FW_ERROR_MEMORY_UNDERFLOW:
579                 return "MEMORY_UNDERFLOW";
580         case IPW_FW_ERROR_MEMORY_OVERFLOW:
581                 return "MEMORY_OVERFLOW";
582         case IPW_FW_ERROR_BAD_PARAM:
583                 return "BAD_PARAM";
584         case IPW_FW_ERROR_BAD_CHECKSUM:
585                 return "BAD_CHECKSUM";
586         case IPW_FW_ERROR_NMI_INTERRUPT:
587                 return "NMI_INTERRUPT";
588         case IPW_FW_ERROR_BAD_DATABASE:
589                 return "BAD_DATABASE";
590         case IPW_FW_ERROR_ALLOC_FAIL:
591                 return "ALLOC_FAIL";
592         case IPW_FW_ERROR_DMA_UNDERRUN:
593                 return "DMA_UNDERRUN";
594         case IPW_FW_ERROR_DMA_STATUS:
595                 return "DMA_STATUS";
596         case IPW_FW_ERROR_DINO_ERROR:
597                 return "DINO_ERROR";
598         case IPW_FW_ERROR_EEPROM_ERROR:
599                 return "EEPROM_ERROR";
600         case IPW_FW_ERROR_SYSASSERT:
601                 return "SYSASSERT";
602         case IPW_FW_ERROR_FATAL_ERROR:
603                 return "FATAL_ERROR";
604         default:
605                 return "UNKNOWN_ERROR";
606         }
607 }
608
609 static void ipw_dump_error_log(struct ipw_priv *priv,
610                                struct ipw_fw_error *error)
611 {
612         u32 i;
613
614         if (!error) {
615                 IPW_ERROR("Error allocating and capturing error log.  "
616                           "Nothing to dump.\n");
617                 return;
618         }
619
620         IPW_ERROR("Start IPW Error Log Dump:\n");
621         IPW_ERROR("Status: 0x%08X, Config: %08X\n",
622                   error->status, error->config);
623
624         for (i = 0; i < error->elem_len; i++)
625                 IPW_ERROR("%s %i 0x%08x  0x%08x  0x%08x  0x%08x  0x%08x\n",
626                           ipw_error_desc(error->elem[i].desc),
627                           error->elem[i].time,
628                           error->elem[i].blink1,
629                           error->elem[i].blink2,
630                           error->elem[i].link1,
631                           error->elem[i].link2, error->elem[i].data);
632         for (i = 0; i < error->log_len; i++)
633                 IPW_ERROR("%i\t0x%08x\t%i\n",
634                           error->log[i].time,
635                           error->log[i].data, error->log[i].event);
636 }
637 #endif
638
639 static inline int ipw_is_init(struct ipw_priv *priv)
640 {
641         return (priv->status & STATUS_INIT) ? 1 : 0;
642 }
643
644 static int ipw_get_ordinal(struct ipw_priv *priv, u32 ord, void *val, u32 * len)
645 {
646         u32 addr, field_info, field_len, field_count, total_len;
647
648         IPW_DEBUG_ORD("ordinal = %i\n", ord);
649
650         if (!priv || !val || !len) {
651                 IPW_DEBUG_ORD("Invalid argument\n");
652                 return -EINVAL;
653         }
654
655         /* verify device ordinal tables have been initialized */
656         if (!priv->table0_addr || !priv->table1_addr || !priv->table2_addr) {
657                 IPW_DEBUG_ORD("Access ordinals before initialization\n");
658                 return -EINVAL;
659         }
660
661         switch (IPW_ORD_TABLE_ID_MASK & ord) {
662         case IPW_ORD_TABLE_0_MASK:
663                 /*
664                  * TABLE 0: Direct access to a table of 32 bit values
665                  *
666                  * This is a very simple table with the data directly
667                  * read from the table
668                  */
669
670                 /* remove the table id from the ordinal */
671                 ord &= IPW_ORD_TABLE_VALUE_MASK;
672
673                 /* boundary check */
674                 if (ord > priv->table0_len) {
675                         IPW_DEBUG_ORD("ordinal value (%i) longer then "
676                                       "max (%i)\n", ord, priv->table0_len);
677                         return -EINVAL;
678                 }
679
680                 /* verify we have enough room to store the value */
681                 if (*len < sizeof(u32)) {
682                         IPW_DEBUG_ORD("ordinal buffer length too small, "
683                                       "need %zd\n", sizeof(u32));
684                         return -EINVAL;
685                 }
686
687                 IPW_DEBUG_ORD("Reading TABLE0[%i] from offset 0x%08x\n",
688                               ord, priv->table0_addr + (ord << 2));
689
690                 *len = sizeof(u32);
691                 ord <<= 2;
692                 *((u32 *) val) = ipw_read32(priv, priv->table0_addr + ord);
693                 break;
694
695         case IPW_ORD_TABLE_1_MASK:
696                 /*
697                  * TABLE 1: Indirect access to a table of 32 bit values
698                  *
699                  * This is a fairly large table of u32 values each
700                  * representing starting addr for the data (which is
701                  * also a u32)
702                  */
703
704                 /* remove the table id from the ordinal */
705                 ord &= IPW_ORD_TABLE_VALUE_MASK;
706
707                 /* boundary check */
708                 if (ord > priv->table1_len) {
709                         IPW_DEBUG_ORD("ordinal value too long\n");
710                         return -EINVAL;
711                 }
712
713                 /* verify we have enough room to store the value */
714                 if (*len < sizeof(u32)) {
715                         IPW_DEBUG_ORD("ordinal buffer length too small, "
716                                       "need %zd\n", sizeof(u32));
717                         return -EINVAL;
718                 }
719
720                 *((u32 *) val) =
721                     ipw_read_reg32(priv, (priv->table1_addr + (ord << 2)));
722                 *len = sizeof(u32);
723                 break;
724
725         case IPW_ORD_TABLE_2_MASK:
726                 /*
727                  * TABLE 2: Indirect access to a table of variable sized values
728                  *
729                  * This table consist of six values, each containing
730                  *     - dword containing the starting offset of the data
731                  *     - dword containing the lengh in the first 16bits
732                  *       and the count in the second 16bits
733                  */
734
735                 /* remove the table id from the ordinal */
736                 ord &= IPW_ORD_TABLE_VALUE_MASK;
737
738                 /* boundary check */
739                 if (ord > priv->table2_len) {
740                         IPW_DEBUG_ORD("ordinal value too long\n");
741                         return -EINVAL;
742                 }
743
744                 /* get the address of statistic */
745                 addr = ipw_read_reg32(priv, priv->table2_addr + (ord << 3));
746
747                 /* get the second DW of statistics ;
748                  * two 16-bit words - first is length, second is count */
749                 field_info =
750                     ipw_read_reg32(priv,
751                                    priv->table2_addr + (ord << 3) +
752                                    sizeof(u32));
753
754                 /* get each entry length */
755                 field_len = *((u16 *) & field_info);
756
757                 /* get number of entries */
758                 field_count = *(((u16 *) & field_info) + 1);
759
760                 /* abort if not enought memory */
761                 total_len = field_len * field_count;
762                 if (total_len > *len) {
763                         *len = total_len;
764                         return -EINVAL;
765                 }
766
767                 *len = total_len;
768                 if (!total_len)
769                         return 0;
770
771                 IPW_DEBUG_ORD("addr = 0x%08x, total_len = %i, "
772                               "field_info = 0x%08x\n",
773                               addr, total_len, field_info);
774                 ipw_read_indirect(priv, addr, val, total_len);
775                 break;
776
777         default:
778                 IPW_DEBUG_ORD("Invalid ordinal!\n");
779                 return -EINVAL;
780
781         }
782
783         return 0;
784 }
785
786 static void ipw_init_ordinals(struct ipw_priv *priv)
787 {
788         priv->table0_addr = IPW_ORDINALS_TABLE_LOWER;
789         priv->table0_len = ipw_read32(priv, priv->table0_addr);
790
791         IPW_DEBUG_ORD("table 0 offset at 0x%08x, len = %i\n",
792                       priv->table0_addr, priv->table0_len);
793
794         priv->table1_addr = ipw_read32(priv, IPW_ORDINALS_TABLE_1);
795         priv->table1_len = ipw_read_reg32(priv, priv->table1_addr);
796
797         IPW_DEBUG_ORD("table 1 offset at 0x%08x, len = %i\n",
798                       priv->table1_addr, priv->table1_len);
799
800         priv->table2_addr = ipw_read32(priv, IPW_ORDINALS_TABLE_2);
801         priv->table2_len = ipw_read_reg32(priv, priv->table2_addr);
802         priv->table2_len &= 0x0000ffff; /* use first two bytes */
803
804         IPW_DEBUG_ORD("table 2 offset at 0x%08x, len = %i\n",
805                       priv->table2_addr, priv->table2_len);
806
807 }
808
809 static u32 ipw_register_toggle(u32 reg)
810 {
811         reg &= ~IPW_START_STANDBY;
812         if (reg & IPW_GATE_ODMA)
813                 reg &= ~IPW_GATE_ODMA;
814         if (reg & IPW_GATE_IDMA)
815                 reg &= ~IPW_GATE_IDMA;
816         if (reg & IPW_GATE_ADMA)
817                 reg &= ~IPW_GATE_ADMA;
818         return reg;
819 }
820
821 /*
822  * LED behavior:
823  * - On radio ON, turn on any LEDs that require to be on during start
824  * - On initialization, start unassociated blink
825  * - On association, disable unassociated blink
826  * - On disassociation, start unassociated blink
827  * - On radio OFF, turn off any LEDs started during radio on
828  *
829  */
830 #define LD_TIME_LINK_ON msecs_to_jiffies(300)
831 #define LD_TIME_LINK_OFF msecs_to_jiffies(2700)
832 #define LD_TIME_ACT_ON msecs_to_jiffies(250)
833
834 static void ipw_led_link_on(struct ipw_priv *priv)
835 {
836         unsigned long flags;
837         u32 led;
838
839         /* If configured to not use LEDs, or nic_type is 1,
840          * then we don't toggle a LINK led */
841         if (priv->config & CFG_NO_LED || priv->nic_type == EEPROM_NIC_TYPE_1)
842                 return;
843
844         spin_lock_irqsave(&priv->lock, flags);
845
846         if (!(priv->status & STATUS_RF_KILL_MASK) &&
847             !(priv->status & STATUS_LED_LINK_ON)) {
848                 IPW_DEBUG_LED("Link LED On\n");
849                 led = ipw_read_reg32(priv, IPW_EVENT_REG);
850                 led |= priv->led_association_on;
851
852                 led = ipw_register_toggle(led);
853
854                 IPW_DEBUG_LED("Reg: 0x%08X\n", led);
855                 ipw_write_reg32(priv, IPW_EVENT_REG, led);
856
857                 priv->status |= STATUS_LED_LINK_ON;
858
859                 /* If we aren't associated, schedule turning the LED off */
860                 if (!(priv->status & STATUS_ASSOCIATED))
861                         queue_delayed_work(priv->workqueue,
862                                            &priv->led_link_off,
863                                            LD_TIME_LINK_ON);
864         }
865
866         spin_unlock_irqrestore(&priv->lock, flags);
867 }
868
869 static void ipw_bg_led_link_on(void *data)
870 {
871         struct ipw_priv *priv = data;
872         mutex_lock(&priv->mutex);
873         ipw_led_link_on(data);
874         mutex_unlock(&priv->mutex);
875 }
876
877 static void ipw_led_link_off(struct ipw_priv *priv)
878 {
879         unsigned long flags;
880         u32 led;
881
882         /* If configured not to use LEDs, or nic type is 1,
883          * then we don't goggle the LINK led. */
884         if (priv->config & CFG_NO_LED || priv->nic_type == EEPROM_NIC_TYPE_1)
885                 return;
886
887         spin_lock_irqsave(&priv->lock, flags);
888
889         if (priv->status & STATUS_LED_LINK_ON) {
890                 led = ipw_read_reg32(priv, IPW_EVENT_REG);
891                 led &= priv->led_association_off;
892                 led = ipw_register_toggle(led);
893
894                 IPW_DEBUG_LED("Reg: 0x%08X\n", led);
895                 ipw_write_reg32(priv, IPW_EVENT_REG, led);
896
897                 IPW_DEBUG_LED("Link LED Off\n");
898
899                 priv->status &= ~STATUS_LED_LINK_ON;
900
901                 /* If we aren't associated and the radio is on, schedule
902                  * turning the LED on (blink while unassociated) */
903                 if (!(priv->status & STATUS_RF_KILL_MASK) &&
904                     !(priv->status & STATUS_ASSOCIATED))
905                         queue_delayed_work(priv->workqueue, &priv->led_link_on,
906                                            LD_TIME_LINK_OFF);
907
908         }
909
910         spin_unlock_irqrestore(&priv->lock, flags);
911 }
912
913 static void ipw_bg_led_link_off(void *data)
914 {
915         struct ipw_priv *priv = data;
916         mutex_lock(&priv->mutex);
917         ipw_led_link_off(data);
918         mutex_unlock(&priv->mutex);
919 }
920
921 static void __ipw_led_activity_on(struct ipw_priv *priv)
922 {
923         u32 led;
924
925         if (priv->config & CFG_NO_LED)
926                 return;
927
928         if (priv->status & STATUS_RF_KILL_MASK)
929                 return;
930
931         if (!(priv->status & STATUS_LED_ACT_ON)) {
932                 led = ipw_read_reg32(priv, IPW_EVENT_REG);
933                 led |= priv->led_activity_on;
934
935                 led = ipw_register_toggle(led);
936
937                 IPW_DEBUG_LED("Reg: 0x%08X\n", led);
938                 ipw_write_reg32(priv, IPW_EVENT_REG, led);
939
940                 IPW_DEBUG_LED("Activity LED On\n");
941
942                 priv->status |= STATUS_LED_ACT_ON;
943
944                 cancel_delayed_work(&priv->led_act_off);
945                 queue_delayed_work(priv->workqueue, &priv->led_act_off,
946                                    LD_TIME_ACT_ON);
947         } else {
948                 /* Reschedule LED off for full time period */
949                 cancel_delayed_work(&priv->led_act_off);
950                 queue_delayed_work(priv->workqueue, &priv->led_act_off,
951                                    LD_TIME_ACT_ON);
952         }
953 }
954
955 #if 0
956 void ipw_led_activity_on(struct ipw_priv *priv)
957 {
958         unsigned long flags;
959         spin_lock_irqsave(&priv->lock, flags);
960         __ipw_led_activity_on(priv);
961         spin_unlock_irqrestore(&priv->lock, flags);
962 }
963 #endif  /*  0  */
964
965 static void ipw_led_activity_off(struct ipw_priv *priv)
966 {
967         unsigned long flags;
968         u32 led;
969
970         if (priv->config & CFG_NO_LED)
971                 return;
972
973         spin_lock_irqsave(&priv->lock, flags);
974
975         if (priv->status & STATUS_LED_ACT_ON) {
976                 led = ipw_read_reg32(priv, IPW_EVENT_REG);
977                 led &= priv->led_activity_off;
978
979                 led = ipw_register_toggle(led);
980
981                 IPW_DEBUG_LED("Reg: 0x%08X\n", led);
982                 ipw_write_reg32(priv, IPW_EVENT_REG, led);
983
984                 IPW_DEBUG_LED("Activity LED Off\n");
985
986                 priv->status &= ~STATUS_LED_ACT_ON;
987         }
988
989         spin_unlock_irqrestore(&priv->lock, flags);
990 }
991
992 static void ipw_bg_led_activity_off(void *data)
993 {
994         struct ipw_priv *priv = data;
995         mutex_lock(&priv->mutex);
996         ipw_led_activity_off(data);
997         mutex_unlock(&priv->mutex);
998 }
999
1000 static void ipw_led_band_on(struct ipw_priv *priv)
1001 {
1002         unsigned long flags;
1003         u32 led;
1004
1005         /* Only nic type 1 supports mode LEDs */
1006         if (priv->config & CFG_NO_LED ||
1007             priv->nic_type != EEPROM_NIC_TYPE_1 || !priv->assoc_network)
1008                 return;
1009
1010         spin_lock_irqsave(&priv->lock, flags);
1011
1012         led = ipw_read_reg32(priv, IPW_EVENT_REG);
1013         if (priv->assoc_network->mode == IEEE_A) {
1014                 led |= priv->led_ofdm_on;
1015                 led &= priv->led_association_off;
1016                 IPW_DEBUG_LED("Mode LED On: 802.11a\n");
1017         } else if (priv->assoc_network->mode == IEEE_G) {
1018                 led |= priv->led_ofdm_on;
1019                 led |= priv->led_association_on;
1020                 IPW_DEBUG_LED("Mode LED On: 802.11g\n");
1021         } else {
1022                 led &= priv->led_ofdm_off;
1023                 led |= priv->led_association_on;
1024                 IPW_DEBUG_LED("Mode LED On: 802.11b\n");
1025         }
1026
1027         led = ipw_register_toggle(led);
1028
1029         IPW_DEBUG_LED("Reg: 0x%08X\n", led);
1030         ipw_write_reg32(priv, IPW_EVENT_REG, led);
1031
1032         spin_unlock_irqrestore(&priv->lock, flags);
1033 }
1034
1035 static void ipw_led_band_off(struct ipw_priv *priv)
1036 {
1037         unsigned long flags;
1038         u32 led;
1039
1040         /* Only nic type 1 supports mode LEDs */
1041         if (priv->config & CFG_NO_LED || priv->nic_type != EEPROM_NIC_TYPE_1)
1042                 return;
1043
1044         spin_lock_irqsave(&priv->lock, flags);
1045
1046         led = ipw_read_reg32(priv, IPW_EVENT_REG);
1047         led &= priv->led_ofdm_off;
1048         led &= priv->led_association_off;
1049
1050         led = ipw_register_toggle(led);
1051
1052         IPW_DEBUG_LED("Reg: 0x%08X\n", led);
1053         ipw_write_reg32(priv, IPW_EVENT_REG, led);
1054
1055         spin_unlock_irqrestore(&priv->lock, flags);
1056 }
1057
1058 static void ipw_led_radio_on(struct ipw_priv *priv)
1059 {
1060         ipw_led_link_on(priv);
1061 }
1062
1063 static void ipw_led_radio_off(struct ipw_priv *priv)
1064 {
1065         ipw_led_activity_off(priv);
1066         ipw_led_link_off(priv);
1067 }
1068
1069 static void ipw_led_link_up(struct ipw_priv *priv)
1070 {
1071         /* Set the Link Led on for all nic types */
1072         ipw_led_link_on(priv);
1073 }
1074
1075 static void ipw_led_link_down(struct ipw_priv *priv)
1076 {
1077         ipw_led_activity_off(priv);
1078         ipw_led_link_off(priv);
1079
1080         if (priv->status & STATUS_RF_KILL_MASK)
1081                 ipw_led_radio_off(priv);
1082 }
1083
1084 static void ipw_led_init(struct ipw_priv *priv)
1085 {
1086         priv->nic_type = priv->eeprom[EEPROM_NIC_TYPE];
1087
1088         /* Set the default PINs for the link and activity leds */
1089         priv->led_activity_on = IPW_ACTIVITY_LED;
1090         priv->led_activity_off = ~(IPW_ACTIVITY_LED);
1091
1092         priv->led_association_on = IPW_ASSOCIATED_LED;
1093         priv->led_association_off = ~(IPW_ASSOCIATED_LED);
1094
1095         /* Set the default PINs for the OFDM leds */
1096         priv->led_ofdm_on = IPW_OFDM_LED;
1097         priv->led_ofdm_off = ~(IPW_OFDM_LED);
1098
1099         switch (priv->nic_type) {
1100         case EEPROM_NIC_TYPE_1:
1101                 /* In this NIC type, the LEDs are reversed.... */
1102                 priv->led_activity_on = IPW_ASSOCIATED_LED;
1103                 priv->led_activity_off = ~(IPW_ASSOCIATED_LED);
1104                 priv->led_association_on = IPW_ACTIVITY_LED;
1105                 priv->led_association_off = ~(IPW_ACTIVITY_LED);
1106
1107                 if (!(priv->config & CFG_NO_LED))
1108                         ipw_led_band_on(priv);
1109
1110                 /* And we don't blink link LEDs for this nic, so
1111                  * just return here */
1112                 return;
1113
1114         case EEPROM_NIC_TYPE_3:
1115         case EEPROM_NIC_TYPE_2:
1116         case EEPROM_NIC_TYPE_4:
1117         case EEPROM_NIC_TYPE_0:
1118                 break;
1119
1120         default:
1121                 IPW_DEBUG_INFO("Unknown NIC type from EEPROM: %d\n",
1122                                priv->nic_type);
1123                 priv->nic_type = EEPROM_NIC_TYPE_0;
1124                 break;
1125         }
1126
1127         if (!(priv->config & CFG_NO_LED)) {
1128                 if (priv->status & STATUS_ASSOCIATED)
1129                         ipw_led_link_on(priv);
1130                 else
1131                         ipw_led_link_off(priv);
1132         }
1133 }
1134
1135 static void ipw_led_shutdown(struct ipw_priv *priv)
1136 {
1137         ipw_led_activity_off(priv);
1138         ipw_led_link_off(priv);
1139         ipw_led_band_off(priv);
1140         cancel_delayed_work(&priv->led_link_on);
1141         cancel_delayed_work(&priv->led_link_off);
1142         cancel_delayed_work(&priv->led_act_off);
1143 }
1144
1145 /*
1146  * The following adds a new attribute to the sysfs representation
1147  * of this device driver (i.e. a new file in /sys/bus/pci/drivers/ipw/)
1148  * used for controling the debug level.
1149  *
1150  * See the level definitions in ipw for details.
1151  */
1152 static ssize_t show_debug_level(struct device_driver *d, char *buf)
1153 {
1154         return sprintf(buf, "0x%08X\n", ipw_debug_level);
1155 }
1156
1157 static ssize_t store_debug_level(struct device_driver *d, const char *buf,
1158                                  size_t count)
1159 {
1160         char *p = (char *)buf;
1161         u32 val;
1162
1163         if (p[1] == 'x' || p[1] == 'X' || p[0] == 'x' || p[0] == 'X') {
1164                 p++;
1165                 if (p[0] == 'x' || p[0] == 'X')
1166                         p++;
1167                 val = simple_strtoul(p, &p, 16);
1168         } else
1169                 val = simple_strtoul(p, &p, 10);
1170         if (p == buf)
1171                 printk(KERN_INFO DRV_NAME
1172                        ": %s is not in hex or decimal form.\n", buf);
1173         else
1174                 ipw_debug_level = val;
1175
1176         return strnlen(buf, count);
1177 }
1178
1179 static DRIVER_ATTR(debug_level, S_IWUSR | S_IRUGO,
1180                    show_debug_level, store_debug_level);
1181
1182 static inline u32 ipw_get_event_log_len(struct ipw_priv *priv)
1183 {
1184         /* length = 1st dword in log */
1185         return ipw_read_reg32(priv, ipw_read32(priv, IPW_EVENT_LOG));
1186 }
1187
1188 static void ipw_capture_event_log(struct ipw_priv *priv,
1189                                   u32 log_len, struct ipw_event *log)
1190 {
1191         u32 base;
1192
1193         if (log_len) {
1194                 base = ipw_read32(priv, IPW_EVENT_LOG);
1195                 ipw_read_indirect(priv, base + sizeof(base) + sizeof(u32),
1196                                   (u8 *) log, sizeof(*log) * log_len);
1197         }
1198 }
1199
1200 static struct ipw_fw_error *ipw_alloc_error_log(struct ipw_priv *priv)
1201 {
1202         struct ipw_fw_error *error;
1203         u32 log_len = ipw_get_event_log_len(priv);
1204         u32 base = ipw_read32(priv, IPW_ERROR_LOG);
1205         u32 elem_len = ipw_read_reg32(priv, base);
1206
1207         error = kmalloc(sizeof(*error) +
1208                         sizeof(*error->elem) * elem_len +
1209                         sizeof(*error->log) * log_len, GFP_ATOMIC);
1210         if (!error) {
1211                 IPW_ERROR("Memory allocation for firmware error log "
1212                           "failed.\n");
1213                 return NULL;
1214         }
1215         error->jiffies = jiffies;
1216         error->status = priv->status;
1217         error->config = priv->config;
1218         error->elem_len = elem_len;
1219         error->log_len = log_len;
1220         error->elem = (struct ipw_error_elem *)error->payload;
1221         error->log = (struct ipw_event *)(error->elem + elem_len);
1222
1223         ipw_capture_event_log(priv, log_len, error->log);
1224
1225         if (elem_len)
1226                 ipw_read_indirect(priv, base + sizeof(base), (u8 *) error->elem,
1227                                   sizeof(*error->elem) * elem_len);
1228
1229         return error;
1230 }
1231
1232 static ssize_t show_event_log(struct device *d,
1233                               struct device_attribute *attr, char *buf)
1234 {
1235         struct ipw_priv *priv = dev_get_drvdata(d);
1236         u32 log_len = ipw_get_event_log_len(priv);
1237         struct ipw_event log[log_len];
1238         u32 len = 0, i;
1239
1240         ipw_capture_event_log(priv, log_len, log);
1241
1242         len += snprintf(buf + len, PAGE_SIZE - len, "%08X", log_len);
1243         for (i = 0; i < log_len; i++)
1244                 len += snprintf(buf + len, PAGE_SIZE - len,
1245                                 "\n%08X%08X%08X",
1246                                 log[i].time, log[i].event, log[i].data);
1247         len += snprintf(buf + len, PAGE_SIZE - len, "\n");
1248         return len;
1249 }
1250
1251 static DEVICE_ATTR(event_log, S_IRUGO, show_event_log, NULL);
1252
1253 static ssize_t show_error(struct device *d,
1254                           struct device_attribute *attr, char *buf)
1255 {
1256         struct ipw_priv *priv = dev_get_drvdata(d);
1257         u32 len = 0, i;
1258         if (!priv->error)
1259                 return 0;
1260         len += snprintf(buf + len, PAGE_SIZE - len,
1261                         "%08lX%08X%08X%08X",
1262                         priv->error->jiffies,
1263                         priv->error->status,
1264                         priv->error->config, priv->error->elem_len);
1265         for (i = 0; i < priv->error->elem_len; i++)
1266                 len += snprintf(buf + len, PAGE_SIZE - len,
1267                                 "\n%08X%08X%08X%08X%08X%08X%08X",
1268                                 priv->error->elem[i].time,
1269                                 priv->error->elem[i].desc,
1270                                 priv->error->elem[i].blink1,
1271                                 priv->error->elem[i].blink2,
1272                                 priv->error->elem[i].link1,
1273                                 priv->error->elem[i].link2,
1274                                 priv->error->elem[i].data);
1275
1276         len += snprintf(buf + len, PAGE_SIZE - len,
1277                         "\n%08X", priv->error->log_len);
1278         for (i = 0; i < priv->error->log_len; i++)
1279                 len += snprintf(buf + len, PAGE_SIZE - len,
1280                                 "\n%08X%08X%08X",
1281                                 priv->error->log[i].time,
1282                                 priv->error->log[i].event,
1283                                 priv->error->log[i].data);
1284         len += snprintf(buf + len, PAGE_SIZE - len, "\n");
1285         return len;
1286 }
1287
1288 static ssize_t clear_error(struct device *d,
1289                            struct device_attribute *attr,
1290                            const char *buf, size_t count)
1291 {
1292         struct ipw_priv *priv = dev_get_drvdata(d);
1293
1294         kfree(priv->error);
1295         priv->error = NULL;
1296         return count;
1297 }
1298
1299 static DEVICE_ATTR(error, S_IRUGO | S_IWUSR, show_error, clear_error);
1300
1301 static ssize_t show_cmd_log(struct device *d,
1302                             struct device_attribute *attr, char *buf)
1303 {
1304         struct ipw_priv *priv = dev_get_drvdata(d);
1305         u32 len = 0, i;
1306         if (!priv->cmdlog)
1307                 return 0;
1308         for (i = (priv->cmdlog_pos + 1) % priv->cmdlog_len;
1309              (i != priv->cmdlog_pos) && (PAGE_SIZE - len);
1310              i = (i + 1) % priv->cmdlog_len) {
1311                 len +=
1312                     snprintf(buf + len, PAGE_SIZE - len,
1313                              "\n%08lX%08X%08X%08X\n", priv->cmdlog[i].jiffies,
1314                              priv->cmdlog[i].retcode, priv->cmdlog[i].cmd.cmd,
1315                              priv->cmdlog[i].cmd.len);
1316                 len +=
1317                     snprintk_buf(buf + len, PAGE_SIZE - len,
1318                                  (u8 *) priv->cmdlog[i].cmd.param,
1319                                  priv->cmdlog[i].cmd.len);
1320                 len += snprintf(buf + len, PAGE_SIZE - len, "\n");
1321         }
1322         len += snprintf(buf + len, PAGE_SIZE - len, "\n");
1323         return len;
1324 }
1325
1326 static DEVICE_ATTR(cmd_log, S_IRUGO, show_cmd_log, NULL);
1327
1328 #ifdef CONFIG_IPW2200_PROMISCUOUS
1329 static void ipw_prom_free(struct ipw_priv *priv);
1330 static int ipw_prom_alloc(struct ipw_priv *priv);
1331 static ssize_t store_rtap_iface(struct device *d,
1332                          struct device_attribute *attr,
1333                          const char *buf, size_t count)
1334 {
1335         struct ipw_priv *priv = dev_get_drvdata(d);
1336         int rc = 0;
1337
1338         if (count < 1)
1339                 return -EINVAL;
1340
1341         switch (buf[0]) {
1342         case '0':
1343                 if (!rtap_iface)
1344                         return count;
1345
1346                 if (netif_running(priv->prom_net_dev)) {
1347                         IPW_WARNING("Interface is up.  Cannot unregister.\n");
1348                         return count;
1349                 }
1350
1351                 ipw_prom_free(priv);
1352                 rtap_iface = 0;
1353                 break;
1354
1355         case '1':
1356                 if (rtap_iface)
1357                         return count;
1358
1359                 rc = ipw_prom_alloc(priv);
1360                 if (!rc)
1361                         rtap_iface = 1;
1362                 break;
1363
1364         default:
1365                 return -EINVAL;
1366         }
1367
1368         if (rc) {
1369                 IPW_ERROR("Failed to register promiscuous network "
1370                           "device (error %d).\n", rc);
1371         }
1372
1373         return count;
1374 }
1375
1376 static ssize_t show_rtap_iface(struct device *d,
1377                         struct device_attribute *attr,
1378                         char *buf)
1379 {
1380         struct ipw_priv *priv = dev_get_drvdata(d);
1381         if (rtap_iface)
1382                 return sprintf(buf, "%s", priv->prom_net_dev->name);
1383         else {
1384                 buf[0] = '-';
1385                 buf[1] = '1';
1386                 buf[2] = '\0';
1387                 return 3;
1388         }
1389 }
1390
1391 static DEVICE_ATTR(rtap_iface, S_IWUSR | S_IRUSR, show_rtap_iface,
1392                    store_rtap_iface);
1393
1394 static ssize_t store_rtap_filter(struct device *d,
1395                          struct device_attribute *attr,
1396                          const char *buf, size_t count)
1397 {
1398         struct ipw_priv *priv = dev_get_drvdata(d);
1399
1400         if (!priv->prom_priv) {
1401                 IPW_ERROR("Attempting to set filter without "
1402                           "rtap_iface enabled.\n");
1403                 return -EPERM;
1404         }
1405
1406         priv->prom_priv->filter = simple_strtol(buf, NULL, 0);
1407
1408         IPW_DEBUG_INFO("Setting rtap filter to " BIT_FMT16 "\n",
1409                        BIT_ARG16(priv->prom_priv->filter));
1410
1411         return count;
1412 }
1413
1414 static ssize_t show_rtap_filter(struct device *d,
1415                         struct device_attribute *attr,
1416                         char *buf)
1417 {
1418         struct ipw_priv *priv = dev_get_drvdata(d);
1419         return sprintf(buf, "0x%04X",
1420                        priv->prom_priv ? priv->prom_priv->filter : 0);
1421 }
1422
1423 static DEVICE_ATTR(rtap_filter, S_IWUSR | S_IRUSR, show_rtap_filter,
1424                    store_rtap_filter);
1425 #endif
1426
1427 static ssize_t show_scan_age(struct device *d, struct device_attribute *attr,
1428                              char *buf)
1429 {
1430         struct ipw_priv *priv = dev_get_drvdata(d);
1431         return sprintf(buf, "%d\n", priv->ieee->scan_age);
1432 }
1433
1434 static ssize_t store_scan_age(struct device *d, struct device_attribute *attr,
1435                               const char *buf, size_t count)
1436 {
1437         struct ipw_priv *priv = dev_get_drvdata(d);
1438 #ifdef CONFIG_IPW2200_DEBUG
1439         struct net_device *dev = priv->net_dev;
1440 #endif
1441         char buffer[] = "00000000";
1442         unsigned long len =
1443             (sizeof(buffer) - 1) > count ? count : sizeof(buffer) - 1;
1444         unsigned long val;
1445         char *p = buffer;
1446
1447         IPW_DEBUG_INFO("enter\n");
1448
1449         strncpy(buffer, buf, len);
1450         buffer[len] = 0;
1451
1452         if (p[1] == 'x' || p[1] == 'X' || p[0] == 'x' || p[0] == 'X') {
1453                 p++;
1454                 if (p[0] == 'x' || p[0] == 'X')
1455                         p++;
1456                 val = simple_strtoul(p, &p, 16);
1457         } else
1458                 val = simple_strtoul(p, &p, 10);
1459         if (p == buffer) {
1460                 IPW_DEBUG_INFO("%s: user supplied invalid value.\n", dev->name);
1461         } else {
1462                 priv->ieee->scan_age = val;
1463                 IPW_DEBUG_INFO("set scan_age = %u\n", priv->ieee->scan_age);
1464         }
1465
1466         IPW_DEBUG_INFO("exit\n");
1467         return len;
1468 }
1469
1470 static DEVICE_ATTR(scan_age, S_IWUSR | S_IRUGO, show_scan_age, store_scan_age);
1471
1472 static ssize_t show_led(struct device *d, struct device_attribute *attr,
1473                         char *buf)
1474 {
1475         struct ipw_priv *priv = dev_get_drvdata(d);
1476         return sprintf(buf, "%d\n", (priv->config & CFG_NO_LED) ? 0 : 1);
1477 }
1478
1479 static ssize_t store_led(struct device *d, struct device_attribute *attr,
1480                          const char *buf, size_t count)
1481 {
1482         struct ipw_priv *priv = dev_get_drvdata(d);
1483
1484         IPW_DEBUG_INFO("enter\n");
1485
1486         if (count == 0)
1487                 return 0;
1488
1489         if (*buf == 0) {
1490                 IPW_DEBUG_LED("Disabling LED control.\n");
1491                 priv->config |= CFG_NO_LED;
1492                 ipw_led_shutdown(priv);
1493         } else {
1494                 IPW_DEBUG_LED("Enabling LED control.\n");
1495                 priv->config &= ~CFG_NO_LED;
1496                 ipw_led_init(priv);
1497         }
1498
1499         IPW_DEBUG_INFO("exit\n");
1500         return count;
1501 }
1502
1503 static DEVICE_ATTR(led, S_IWUSR | S_IRUGO, show_led, store_led);
1504
1505 static ssize_t show_status(struct device *d,
1506                            struct device_attribute *attr, char *buf)
1507 {
1508         struct ipw_priv *p = d->driver_data;
1509         return sprintf(buf, "0x%08x\n", (int)p->status);
1510 }
1511
1512 static DEVICE_ATTR(status, S_IRUGO, show_status, NULL);
1513
1514 static ssize_t show_cfg(struct device *d, struct device_attribute *attr,
1515                         char *buf)
1516 {
1517         struct ipw_priv *p = d->driver_data;
1518         return sprintf(buf, "0x%08x\n", (int)p->config);
1519 }
1520
1521 static DEVICE_ATTR(cfg, S_IRUGO, show_cfg, NULL);
1522
1523 static ssize_t show_nic_type(struct device *d,
1524                              struct device_attribute *attr, char *buf)
1525 {
1526         struct ipw_priv *priv = d->driver_data;
1527         return sprintf(buf, "TYPE: %d\n", priv->nic_type);
1528 }
1529
1530 static DEVICE_ATTR(nic_type, S_IRUGO, show_nic_type, NULL);
1531
1532 static ssize_t show_ucode_version(struct device *d,
1533                                   struct device_attribute *attr, char *buf)
1534 {
1535         u32 len = sizeof(u32), tmp = 0;
1536         struct ipw_priv *p = d->driver_data;
1537
1538         if (ipw_get_ordinal(p, IPW_ORD_STAT_UCODE_VERSION, &tmp, &len))
1539                 return 0;
1540
1541         return sprintf(buf, "0x%08x\n", tmp);
1542 }
1543
1544 static DEVICE_ATTR(ucode_version, S_IWUSR | S_IRUGO, show_ucode_version, NULL);
1545
1546 static ssize_t show_rtc(struct device *d, struct device_attribute *attr,
1547                         char *buf)
1548 {
1549         u32 len = sizeof(u32), tmp = 0;
1550         struct ipw_priv *p = d->driver_data;
1551
1552         if (ipw_get_ordinal(p, IPW_ORD_STAT_RTC, &tmp, &len))
1553                 return 0;
1554
1555         return sprintf(buf, "0x%08x\n", tmp);
1556 }
1557
1558 static DEVICE_ATTR(rtc, S_IWUSR | S_IRUGO, show_rtc, NULL);
1559
1560 /*
1561  * Add a device attribute to view/control the delay between eeprom
1562  * operations.
1563  */
1564 static ssize_t show_eeprom_delay(struct device *d,
1565                                  struct device_attribute *attr, char *buf)
1566 {
1567         int n = ((struct ipw_priv *)d->driver_data)->eeprom_delay;
1568         return sprintf(buf, "%i\n", n);
1569 }
1570 static ssize_t store_eeprom_delay(struct device *d,
1571                                   struct device_attribute *attr,
1572                                   const char *buf, size_t count)
1573 {
1574         struct ipw_priv *p = d->driver_data;
1575         sscanf(buf, "%i", &p->eeprom_delay);
1576         return strnlen(buf, count);
1577 }
1578
1579 static DEVICE_ATTR(eeprom_delay, S_IWUSR | S_IRUGO,
1580                    show_eeprom_delay, store_eeprom_delay);
1581
1582 static ssize_t show_command_event_reg(struct device *d,
1583                                       struct device_attribute *attr, char *buf)
1584 {
1585         u32 reg = 0;
1586         struct ipw_priv *p = d->driver_data;
1587
1588         reg = ipw_read_reg32(p, IPW_INTERNAL_CMD_EVENT);
1589         return sprintf(buf, "0x%08x\n", reg);
1590 }
1591 static ssize_t store_command_event_reg(struct device *d,
1592                                        struct device_attribute *attr,
1593                                        const char *buf, size_t count)
1594 {
1595         u32 reg;
1596         struct ipw_priv *p = d->driver_data;
1597
1598         sscanf(buf, "%x", &reg);
1599         ipw_write_reg32(p, IPW_INTERNAL_CMD_EVENT, reg);
1600         return strnlen(buf, count);
1601 }
1602
1603 static DEVICE_ATTR(command_event_reg, S_IWUSR | S_IRUGO,
1604                    show_command_event_reg, store_command_event_reg);
1605
1606 static ssize_t show_mem_gpio_reg(struct device *d,
1607                                  struct device_attribute *attr, char *buf)
1608 {
1609         u32 reg = 0;
1610         struct ipw_priv *p = d->driver_data;
1611
1612         reg = ipw_read_reg32(p, 0x301100);
1613         return sprintf(buf, "0x%08x\n", reg);
1614 }
1615 static ssize_t store_mem_gpio_reg(struct device *d,
1616                                   struct device_attribute *attr,
1617                                   const char *buf, size_t count)
1618 {
1619         u32 reg;
1620         struct ipw_priv *p = d->driver_data;
1621
1622         sscanf(buf, "%x", &reg);
1623         ipw_write_reg32(p, 0x301100, reg);
1624         return strnlen(buf, count);
1625 }
1626
1627 static DEVICE_ATTR(mem_gpio_reg, S_IWUSR | S_IRUGO,
1628                    show_mem_gpio_reg, store_mem_gpio_reg);
1629
1630 static ssize_t show_indirect_dword(struct device *d,
1631                                    struct device_attribute *attr, char *buf)
1632 {
1633         u32 reg = 0;
1634         struct ipw_priv *priv = d->driver_data;
1635
1636         if (priv->status & STATUS_INDIRECT_DWORD)
1637                 reg = ipw_read_reg32(priv, priv->indirect_dword);
1638         else
1639                 reg = 0;
1640
1641         return sprintf(buf, "0x%08x\n", reg);
1642 }
1643 static ssize_t store_indirect_dword(struct device *d,
1644                                     struct device_attribute *attr,
1645                                     const char *buf, size_t count)
1646 {
1647         struct ipw_priv *priv = d->driver_data;
1648
1649         sscanf(buf, "%x", &priv->indirect_dword);
1650         priv->status |= STATUS_INDIRECT_DWORD;
1651         return strnlen(buf, count);
1652 }
1653
1654 static DEVICE_ATTR(indirect_dword, S_IWUSR | S_IRUGO,
1655                    show_indirect_dword, store_indirect_dword);
1656
1657 static ssize_t show_indirect_byte(struct device *d,
1658                                   struct device_attribute *attr, char *buf)
1659 {
1660         u8 reg = 0;
1661         struct ipw_priv *priv = d->driver_data;
1662
1663         if (priv->status & STATUS_INDIRECT_BYTE)
1664                 reg = ipw_read_reg8(priv, priv->indirect_byte);
1665         else
1666                 reg = 0;
1667
1668         return sprintf(buf, "0x%02x\n", reg);
1669 }
1670 static ssize_t store_indirect_byte(struct device *d,
1671                                    struct device_attribute *attr,
1672                                    const char *buf, size_t count)
1673 {
1674         struct ipw_priv *priv = d->driver_data;
1675
1676         sscanf(buf, "%x", &priv->indirect_byte);
1677         priv->status |= STATUS_INDIRECT_BYTE;
1678         return strnlen(buf, count);
1679 }
1680
1681 static DEVICE_ATTR(indirect_byte, S_IWUSR | S_IRUGO,
1682                    show_indirect_byte, store_indirect_byte);
1683
1684 static ssize_t show_direct_dword(struct device *d,
1685                                  struct device_attribute *attr, char *buf)
1686 {
1687         u32 reg = 0;
1688         struct ipw_priv *priv = d->driver_data;
1689
1690         if (priv->status & STATUS_DIRECT_DWORD)
1691                 reg = ipw_read32(priv, priv->direct_dword);
1692         else
1693                 reg = 0;
1694
1695         return sprintf(buf, "0x%08x\n", reg);
1696 }
1697 static ssize_t store_direct_dword(struct device *d,
1698                                   struct device_attribute *attr,
1699                                   const char *buf, size_t count)
1700 {
1701         struct ipw_priv *priv = d->driver_data;
1702
1703         sscanf(buf, "%x", &priv->direct_dword);
1704         priv->status |= STATUS_DIRECT_DWORD;
1705         return strnlen(buf, count);
1706 }
1707
1708 static DEVICE_ATTR(direct_dword, S_IWUSR | S_IRUGO,
1709                    show_direct_dword, store_direct_dword);
1710
1711 static int rf_kill_active(struct ipw_priv *priv)
1712 {
1713         if (0 == (ipw_read32(priv, 0x30) & 0x10000))
1714                 priv->status |= STATUS_RF_KILL_HW;
1715         else
1716                 priv->status &= ~STATUS_RF_KILL_HW;
1717
1718         return (priv->status & STATUS_RF_KILL_HW) ? 1 : 0;
1719 }
1720
1721 static ssize_t show_rf_kill(struct device *d, struct device_attribute *attr,
1722                             char *buf)
1723 {
1724         /* 0 - RF kill not enabled
1725            1 - SW based RF kill active (sysfs)
1726            2 - HW based RF kill active
1727            3 - Both HW and SW baed RF kill active */
1728         struct ipw_priv *priv = d->driver_data;
1729         int val = ((priv->status & STATUS_RF_KILL_SW) ? 0x1 : 0x0) |
1730             (rf_kill_active(priv) ? 0x2 : 0x0);
1731         return sprintf(buf, "%i\n", val);
1732 }
1733
1734 static int ipw_radio_kill_sw(struct ipw_priv *priv, int disable_radio)
1735 {
1736         if ((disable_radio ? 1 : 0) ==
1737             ((priv->status & STATUS_RF_KILL_SW) ? 1 : 0))
1738                 return 0;
1739
1740         IPW_DEBUG_RF_KILL("Manual SW RF Kill set to: RADIO  %s\n",
1741                           disable_radio ? "OFF" : "ON");
1742
1743         if (disable_radio) {
1744                 priv->status |= STATUS_RF_KILL_SW;
1745
1746                 if (priv->workqueue)
1747                         cancel_delayed_work(&priv->request_scan);
1748                 queue_work(priv->workqueue, &priv->down);
1749         } else {
1750                 priv->status &= ~STATUS_RF_KILL_SW;
1751                 if (rf_kill_active(priv)) {
1752                         IPW_DEBUG_RF_KILL("Can not turn radio back on - "
1753                                           "disabled by HW switch\n");
1754                         /* Make sure the RF_KILL check timer is running */
1755                         cancel_delayed_work(&priv->rf_kill);
1756                         queue_delayed_work(priv->workqueue, &priv->rf_kill,
1757                                            2 * HZ);
1758                 } else
1759                         queue_work(priv->workqueue, &priv->up);
1760         }
1761
1762         return 1;
1763 }
1764
1765 static ssize_t store_rf_kill(struct device *d, struct device_attribute *attr,
1766                              const char *buf, size_t count)
1767 {
1768         struct ipw_priv *priv = d->driver_data;
1769
1770         ipw_radio_kill_sw(priv, buf[0] == '1');
1771
1772         return count;
1773 }
1774
1775 static DEVICE_ATTR(rf_kill, S_IWUSR | S_IRUGO, show_rf_kill, store_rf_kill);
1776
1777 static ssize_t show_speed_scan(struct device *d, struct device_attribute *attr,
1778                                char *buf)
1779 {
1780         struct ipw_priv *priv = (struct ipw_priv *)d->driver_data;
1781         int pos = 0, len = 0;
1782         if (priv->config & CFG_SPEED_SCAN) {
1783                 while (priv->speed_scan[pos] != 0)
1784                         len += sprintf(&buf[len], "%d ",
1785                                        priv->speed_scan[pos++]);
1786                 return len + sprintf(&buf[len], "\n");
1787         }
1788
1789         return sprintf(buf, "0\n");
1790 }
1791
1792 static ssize_t store_speed_scan(struct device *d, struct device_attribute *attr,
1793                                 const char *buf, size_t count)
1794 {
1795         struct ipw_priv *priv = (struct ipw_priv *)d->driver_data;
1796         int channel, pos = 0;
1797         const char *p = buf;
1798
1799         /* list of space separated channels to scan, optionally ending with 0 */
1800         while ((channel = simple_strtol(p, NULL, 0))) {
1801                 if (pos == MAX_SPEED_SCAN - 1) {
1802                         priv->speed_scan[pos] = 0;
1803                         break;
1804                 }
1805
1806                 if (ieee80211_is_valid_channel(priv->ieee, channel))
1807                         priv->speed_scan[pos++] = channel;
1808                 else
1809                         IPW_WARNING("Skipping invalid channel request: %d\n",
1810                                     channel);
1811                 p = strchr(p, ' ');
1812                 if (!p)
1813                         break;
1814                 while (*p == ' ' || *p == '\t')
1815                         p++;
1816         }
1817
1818         if (pos == 0)
1819                 priv->config &= ~CFG_SPEED_SCAN;
1820         else {
1821                 priv->speed_scan_pos = 0;
1822                 priv->config |= CFG_SPEED_SCAN;
1823         }
1824
1825         return count;
1826 }
1827
1828 static DEVICE_ATTR(speed_scan, S_IWUSR | S_IRUGO, show_speed_scan,
1829                    store_speed_scan);
1830
1831 static ssize_t show_net_stats(struct device *d, struct device_attribute *attr,
1832                               char *buf)
1833 {
1834         struct ipw_priv *priv = (struct ipw_priv *)d->driver_data;
1835         return sprintf(buf, "%c\n", (priv->config & CFG_NET_STATS) ? '1' : '0');
1836 }
1837
1838 static ssize_t store_net_stats(struct device *d, struct device_attribute *attr,
1839                                const char *buf, size_t count)
1840 {
1841         struct ipw_priv *priv = (struct ipw_priv *)d->driver_data;
1842         if (buf[0] == '1')
1843                 priv->config |= CFG_NET_STATS;
1844         else
1845                 priv->config &= ~CFG_NET_STATS;
1846
1847         return count;
1848 }
1849
1850 static DEVICE_ATTR(net_stats, S_IWUSR | S_IRUGO,
1851                    show_net_stats, store_net_stats);
1852
1853 static void notify_wx_assoc_event(struct ipw_priv *priv)
1854 {
1855         union iwreq_data wrqu;
1856         wrqu.ap_addr.sa_family = ARPHRD_ETHER;
1857         if (priv->status & STATUS_ASSOCIATED)
1858                 memcpy(wrqu.ap_addr.sa_data, priv->bssid, ETH_ALEN);
1859         else
1860                 memset(wrqu.ap_addr.sa_data, 0, ETH_ALEN);
1861         wireless_send_event(priv->net_dev, SIOCGIWAP, &wrqu, NULL);
1862 }
1863
1864 static void ipw_irq_tasklet(struct ipw_priv *priv)
1865 {
1866         u32 inta, inta_mask, handled = 0;
1867         unsigned long flags;
1868         int rc = 0;
1869
1870         spin_lock_irqsave(&priv->irq_lock, flags);
1871
1872         inta = ipw_read32(priv, IPW_INTA_RW);
1873         inta_mask = ipw_read32(priv, IPW_INTA_MASK_R);
1874         inta &= (IPW_INTA_MASK_ALL & inta_mask);
1875
1876         /* Add any cached INTA values that need to be handled */
1877         inta |= priv->isr_inta;
1878
1879         spin_unlock_irqrestore(&priv->irq_lock, flags);
1880
1881         spin_lock_irqsave(&priv->lock, flags);
1882
1883         /* handle all the justifications for the interrupt */
1884         if (inta & IPW_INTA_BIT_RX_TRANSFER) {
1885                 ipw_rx(priv);
1886                 handled |= IPW_INTA_BIT_RX_TRANSFER;
1887         }
1888
1889         if (inta & IPW_INTA_BIT_TX_CMD_QUEUE) {
1890                 IPW_DEBUG_HC("Command completed.\n");
1891                 rc = ipw_queue_tx_reclaim(priv, &priv->txq_cmd, -1);
1892                 priv->status &= ~STATUS_HCMD_ACTIVE;
1893                 wake_up_interruptible(&priv->wait_command_queue);
1894                 handled |= IPW_INTA_BIT_TX_CMD_QUEUE;
1895         }
1896
1897         if (inta & IPW_INTA_BIT_TX_QUEUE_1) {
1898                 IPW_DEBUG_TX("TX_QUEUE_1\n");
1899                 rc = ipw_queue_tx_reclaim(priv, &priv->txq[0], 0);
1900                 handled |= IPW_INTA_BIT_TX_QUEUE_1;
1901         }
1902
1903         if (inta & IPW_INTA_BIT_TX_QUEUE_2) {
1904                 IPW_DEBUG_TX("TX_QUEUE_2\n");
1905                 rc = ipw_queue_tx_reclaim(priv, &priv->txq[1], 1);
1906                 handled |= IPW_INTA_BIT_TX_QUEUE_2;
1907         }
1908
1909         if (inta & IPW_INTA_BIT_TX_QUEUE_3) {
1910                 IPW_DEBUG_TX("TX_QUEUE_3\n");
1911                 rc = ipw_queue_tx_reclaim(priv, &priv->txq[2], 2);
1912                 handled |= IPW_INTA_BIT_TX_QUEUE_3;
1913         }
1914
1915         if (inta & IPW_INTA_BIT_TX_QUEUE_4) {
1916                 IPW_DEBUG_TX("TX_QUEUE_4\n");
1917                 rc = ipw_queue_tx_reclaim(priv, &priv->txq[3], 3);
1918                 handled |= IPW_INTA_BIT_TX_QUEUE_4;
1919         }
1920
1921         if (inta & IPW_INTA_BIT_STATUS_CHANGE) {
1922                 IPW_WARNING("STATUS_CHANGE\n");
1923                 handled |= IPW_INTA_BIT_STATUS_CHANGE;
1924         }
1925
1926         if (inta & IPW_INTA_BIT_BEACON_PERIOD_EXPIRED) {
1927                 IPW_WARNING("TX_PERIOD_EXPIRED\n");
1928                 handled |= IPW_INTA_BIT_BEACON_PERIOD_EXPIRED;
1929         }
1930
1931         if (inta & IPW_INTA_BIT_SLAVE_MODE_HOST_CMD_DONE) {
1932                 IPW_WARNING("HOST_CMD_DONE\n");
1933                 handled |= IPW_INTA_BIT_SLAVE_MODE_HOST_CMD_DONE;
1934         }
1935
1936         if (inta & IPW_INTA_BIT_FW_INITIALIZATION_DONE) {
1937                 IPW_WARNING("FW_INITIALIZATION_DONE\n");
1938                 handled |= IPW_INTA_BIT_FW_INITIALIZATION_DONE;
1939         }
1940
1941         if (inta & IPW_INTA_BIT_FW_CARD_DISABLE_PHY_OFF_DONE) {
1942                 IPW_WARNING("PHY_OFF_DONE\n");
1943                 handled |= IPW_INTA_BIT_FW_CARD_DISABLE_PHY_OFF_DONE;
1944         }
1945
1946         if (inta & IPW_INTA_BIT_RF_KILL_DONE) {
1947                 IPW_DEBUG_RF_KILL("RF_KILL_DONE\n");
1948                 priv->status |= STATUS_RF_KILL_HW;
1949                 wake_up_interruptible(&priv->wait_command_queue);
1950                 priv->status &= ~(STATUS_ASSOCIATED | STATUS_ASSOCIATING);
1951                 cancel_delayed_work(&priv->request_scan);
1952                 schedule_work(&priv->link_down);
1953                 queue_delayed_work(priv->workqueue, &priv->rf_kill, 2 * HZ);
1954                 handled |= IPW_INTA_BIT_RF_KILL_DONE;
1955         }
1956
1957         if (inta & IPW_INTA_BIT_FATAL_ERROR) {
1958                 IPW_WARNING("Firmware error detected.  Restarting.\n");
1959                 if (priv->error) {
1960                         IPW_DEBUG_FW("Sysfs 'error' log already exists.\n");
1961 #ifdef CONFIG_IPW2200_DEBUG
1962                         if (ipw_debug_level & IPW_DL_FW_ERRORS) {
1963                                 struct ipw_fw_error *error =
1964                                     ipw_alloc_error_log(priv);
1965                                 ipw_dump_error_log(priv, error);
1966                                 kfree(error);
1967                         }
1968 #endif
1969                 } else {
1970                         priv->error = ipw_alloc_error_log(priv);
1971                         if (priv->error)
1972                                 IPW_DEBUG_FW("Sysfs 'error' log captured.\n");
1973                         else
1974                                 IPW_DEBUG_FW("Error allocating sysfs 'error' "
1975                                              "log.\n");
1976 #ifdef CONFIG_IPW2200_DEBUG
1977                         if (ipw_debug_level & IPW_DL_FW_ERRORS)
1978                                 ipw_dump_error_log(priv, priv->error);
1979 #endif
1980                 }
1981
1982                 /* XXX: If hardware encryption is for WPA/WPA2,
1983                  * we have to notify the supplicant. */
1984                 if (priv->ieee->sec.encrypt) {
1985                         priv->status &= ~STATUS_ASSOCIATED;
1986                         notify_wx_assoc_event(priv);
1987                 }
1988
1989                 /* Keep the restart process from trying to send host
1990                  * commands by clearing the INIT status bit */
1991                 priv->status &= ~STATUS_INIT;
1992
1993                 /* Cancel currently queued command. */
1994                 priv->status &= ~STATUS_HCMD_ACTIVE;
1995                 wake_up_interruptible(&priv->wait_command_queue);
1996
1997                 queue_work(priv->workqueue, &priv->adapter_restart);
1998                 handled |= IPW_INTA_BIT_FATAL_ERROR;
1999         }
2000
2001         if (inta & IPW_INTA_BIT_PARITY_ERROR) {
2002                 IPW_ERROR("Parity error\n");
2003                 handled |= IPW_INTA_BIT_PARITY_ERROR;
2004         }
2005
2006         if (handled != inta) {
2007                 IPW_ERROR("Unhandled INTA bits 0x%08x\n", inta & ~handled);
2008         }
2009
2010         spin_unlock_irqrestore(&priv->lock, flags);
2011
2012         /* enable all interrupts */
2013         ipw_enable_interrupts(priv);
2014 }
2015
2016 #define IPW_CMD(x) case IPW_CMD_ ## x : return #x
2017 static char *get_cmd_string(u8 cmd)
2018 {
2019         switch (cmd) {
2020                 IPW_CMD(HOST_COMPLETE);
2021                 IPW_CMD(POWER_DOWN);
2022                 IPW_CMD(SYSTEM_CONFIG);
2023                 IPW_CMD(MULTICAST_ADDRESS);
2024                 IPW_CMD(SSID);
2025                 IPW_CMD(ADAPTER_ADDRESS);
2026                 IPW_CMD(PORT_TYPE);
2027                 IPW_CMD(RTS_THRESHOLD);
2028                 IPW_CMD(FRAG_THRESHOLD);
2029                 IPW_CMD(POWER_MODE);
2030                 IPW_CMD(WEP_KEY);
2031                 IPW_CMD(TGI_TX_KEY);
2032                 IPW_CMD(SCAN_REQUEST);
2033                 IPW_CMD(SCAN_REQUEST_EXT);
2034                 IPW_CMD(ASSOCIATE);
2035                 IPW_CMD(SUPPORTED_RATES);
2036                 IPW_CMD(SCAN_ABORT);
2037                 IPW_CMD(TX_FLUSH);
2038                 IPW_CMD(QOS_PARAMETERS);
2039                 IPW_CMD(DINO_CONFIG);
2040                 IPW_CMD(RSN_CAPABILITIES);
2041                 IPW_CMD(RX_KEY);
2042                 IPW_CMD(CARD_DISABLE);
2043                 IPW_CMD(SEED_NUMBER);
2044                 IPW_CMD(TX_POWER);
2045                 IPW_CMD(COUNTRY_INFO);
2046                 IPW_CMD(AIRONET_INFO);
2047                 IPW_CMD(AP_TX_POWER);
2048                 IPW_CMD(CCKM_INFO);
2049                 IPW_CMD(CCX_VER_INFO);
2050                 IPW_CMD(SET_CALIBRATION);
2051                 IPW_CMD(SENSITIVITY_CALIB);
2052                 IPW_CMD(RETRY_LIMIT);
2053                 IPW_CMD(IPW_PRE_POWER_DOWN);
2054                 IPW_CMD(VAP_BEACON_TEMPLATE);
2055                 IPW_CMD(VAP_DTIM_PERIOD);
2056                 IPW_CMD(EXT_SUPPORTED_RATES);
2057                 IPW_CMD(VAP_LOCAL_TX_PWR_CONSTRAINT);
2058                 IPW_CMD(VAP_QUIET_INTERVALS);
2059                 IPW_CMD(VAP_CHANNEL_SWITCH);
2060                 IPW_CMD(VAP_MANDATORY_CHANNELS);
2061                 IPW_CMD(VAP_CELL_PWR_LIMIT);
2062                 IPW_CMD(VAP_CF_PARAM_SET);
2063                 IPW_CMD(VAP_SET_BEACONING_STATE);
2064                 IPW_CMD(MEASUREMENT);
2065                 IPW_CMD(POWER_CAPABILITY);
2066                 IPW_CMD(SUPPORTED_CHANNELS);
2067                 IPW_CMD(TPC_REPORT);
2068                 IPW_CMD(WME_INFO);
2069                 IPW_CMD(PRODUCTION_COMMAND);
2070         default:
2071                 return "UNKNOWN";
2072         }
2073 }
2074
2075 #define HOST_COMPLETE_TIMEOUT HZ
2076
2077 static int __ipw_send_cmd(struct ipw_priv *priv, struct host_cmd *cmd)
2078 {
2079         int rc = 0;
2080         unsigned long flags;
2081
2082         spin_lock_irqsave(&priv->lock, flags);
2083         if (priv->status & STATUS_HCMD_ACTIVE) {
2084                 IPW_ERROR("Failed to send %s: Already sending a command.\n",
2085                           get_cmd_string(cmd->cmd));
2086                 spin_unlock_irqrestore(&priv->lock, flags);
2087                 return -EAGAIN;
2088         }
2089
2090         priv->status |= STATUS_HCMD_ACTIVE;
2091
2092         if (priv->cmdlog) {
2093                 priv->cmdlog[priv->cmdlog_pos].jiffies = jiffies;
2094                 priv->cmdlog[priv->cmdlog_pos].cmd.cmd = cmd->cmd;
2095                 priv->cmdlog[priv->cmdlog_pos].cmd.len = cmd->len;
2096                 memcpy(priv->cmdlog[priv->cmdlog_pos].cmd.param, cmd->param,
2097                        cmd->len);
2098                 priv->cmdlog[priv->cmdlog_pos].retcode = -1;
2099         }
2100
2101         IPW_DEBUG_HC("%s command (#%d) %d bytes: 0x%08X\n",
2102                      get_cmd_string(cmd->cmd), cmd->cmd, cmd->len,
2103                      priv->status);
2104
2105 #ifndef DEBUG_CMD_WEP_KEY
2106         if (cmd->cmd == IPW_CMD_WEP_KEY)
2107                 IPW_DEBUG_HC("WEP_KEY command masked out for secure.\n");
2108         else
2109 #endif
2110                 printk_buf(IPW_DL_HOST_COMMAND, (u8 *) cmd->param, cmd->len);
2111
2112         rc = ipw_queue_tx_hcmd(priv, cmd->cmd, cmd->param, cmd->len, 0);
2113         if (rc) {
2114                 priv->status &= ~STATUS_HCMD_ACTIVE;
2115                 IPW_ERROR("Failed to send %s: Reason %d\n",
2116                           get_cmd_string(cmd->cmd), rc);
2117                 spin_unlock_irqrestore(&priv->lock, flags);
2118                 goto exit;
2119         }
2120         spin_unlock_irqrestore(&priv->lock, flags);
2121
2122         rc = wait_event_interruptible_timeout(priv->wait_command_queue,
2123                                               !(priv->
2124                                                 status & STATUS_HCMD_ACTIVE),
2125                                               HOST_COMPLETE_TIMEOUT);
2126         if (rc == 0) {
2127                 spin_lock_irqsave(&priv->lock, flags);
2128                 if (priv->status & STATUS_HCMD_ACTIVE) {
2129                         IPW_ERROR("Failed to send %s: Command timed out.\n",
2130                                   get_cmd_string(cmd->cmd));
2131                         priv->status &= ~STATUS_HCMD_ACTIVE;
2132                         spin_unlock_irqrestore(&priv->lock, flags);
2133                         rc = -EIO;
2134                         goto exit;
2135                 }
2136                 spin_unlock_irqrestore(&priv->lock, flags);
2137         } else
2138                 rc = 0;
2139
2140         if (priv->status & STATUS_RF_KILL_HW) {
2141                 IPW_ERROR("Failed to send %s: Aborted due to RF kill switch.\n",
2142                           get_cmd_string(cmd->cmd));
2143                 rc = -EIO;
2144                 goto exit;
2145         }
2146
2147       exit:
2148         if (priv->cmdlog) {
2149                 priv->cmdlog[priv->cmdlog_pos++].retcode = rc;
2150                 priv->cmdlog_pos %= priv->cmdlog_len;
2151         }
2152         return rc;
2153 }
2154
2155 static int ipw_send_cmd_simple(struct ipw_priv *priv, u8 command)
2156 {
2157         struct host_cmd cmd = {
2158                 .cmd = command,
2159         };
2160
2161         return __ipw_send_cmd(priv, &cmd);
2162 }
2163
2164 static int ipw_send_cmd_pdu(struct ipw_priv *priv, u8 command, u8 len,
2165                             void *data)
2166 {
2167         struct host_cmd cmd = {
2168                 .cmd = command,
2169                 .len = len,
2170                 .param = data,
2171         };
2172
2173         return __ipw_send_cmd(priv, &cmd);
2174 }
2175
2176 static int ipw_send_host_complete(struct ipw_priv *priv)
2177 {
2178         if (!priv) {
2179                 IPW_ERROR("Invalid args\n");
2180                 return -1;
2181         }
2182
2183         return ipw_send_cmd_simple(priv, IPW_CMD_HOST_COMPLETE);
2184 }
2185
2186 static int ipw_send_system_config(struct ipw_priv *priv)
2187 {
2188         return ipw_send_cmd_pdu(priv, IPW_CMD_SYSTEM_CONFIG,
2189                                 sizeof(priv->sys_config),
2190                                 &priv->sys_config);
2191 }
2192
2193 static int ipw_send_ssid(struct ipw_priv *priv, u8 * ssid, int len)
2194 {
2195         if (!priv || !ssid) {
2196                 IPW_ERROR("Invalid args\n");
2197                 return -1;
2198         }
2199
2200         return ipw_send_cmd_pdu(priv, IPW_CMD_SSID, min(len, IW_ESSID_MAX_SIZE),
2201                                 ssid);
2202 }
2203
2204 static int ipw_send_adapter_address(struct ipw_priv *priv, u8 * mac)
2205 {
2206         if (!priv || !mac) {
2207                 IPW_ERROR("Invalid args\n");
2208                 return -1;
2209         }
2210
2211         IPW_DEBUG_INFO("%s: Setting MAC to " MAC_FMT "\n",
2212                        priv->net_dev->name, MAC_ARG(mac));
2213
2214         return ipw_send_cmd_pdu(priv, IPW_CMD_ADAPTER_ADDRESS, ETH_ALEN, mac);
2215 }
2216
2217 /*
2218  * NOTE: This must be executed from our workqueue as it results in udelay
2219  * being called which may corrupt the keyboard if executed on default
2220  * workqueue
2221  */
2222 static void ipw_adapter_restart(void *adapter)
2223 {
2224         struct ipw_priv *priv = adapter;
2225
2226         if (priv->status & STATUS_RF_KILL_MASK)
2227                 return;
2228
2229         ipw_down(priv);
2230
2231         if (priv->assoc_network &&
2232             (priv->assoc_network->capability & WLAN_CAPABILITY_IBSS))
2233                 ipw_remove_current_network(priv);
2234
2235         if (ipw_up(priv)) {
2236                 IPW_ERROR("Failed to up device\n");
2237                 return;
2238         }
2239 }
2240
2241 static void ipw_bg_adapter_restart(void *data)
2242 {
2243         struct ipw_priv *priv = data;
2244         mutex_lock(&priv->mutex);
2245         ipw_adapter_restart(data);
2246         mutex_unlock(&priv->mutex);
2247 }
2248
2249 #define IPW_SCAN_CHECK_WATCHDOG (5 * HZ)
2250
2251 static void ipw_scan_check(void *data)
2252 {
2253         struct ipw_priv *priv = data;
2254         if (priv->status & (STATUS_SCANNING | STATUS_SCAN_ABORTING)) {
2255                 IPW_DEBUG_SCAN("Scan completion watchdog resetting "
2256                                "adapter after (%dms).\n",
2257                                jiffies_to_msecs(IPW_SCAN_CHECK_WATCHDOG));
2258                 queue_work(priv->workqueue, &priv->adapter_restart);
2259         }
2260 }
2261
2262 static void ipw_bg_scan_check(void *data)
2263 {
2264         struct ipw_priv *priv = data;
2265         mutex_lock(&priv->mutex);
2266         ipw_scan_check(data);
2267         mutex_unlock(&priv->mutex);
2268 }
2269
2270 static int ipw_send_scan_request_ext(struct ipw_priv *priv,
2271                                      struct ipw_scan_request_ext *request)
2272 {
2273         return ipw_send_cmd_pdu(priv, IPW_CMD_SCAN_REQUEST_EXT,
2274                                 sizeof(*request), request);
2275 }
2276
2277 static int ipw_send_scan_abort(struct ipw_priv *priv)
2278 {
2279         if (!priv) {
2280                 IPW_ERROR("Invalid args\n");
2281                 return -1;
2282         }
2283
2284         return ipw_send_cmd_simple(priv, IPW_CMD_SCAN_ABORT);
2285 }
2286
2287 static int ipw_set_sensitivity(struct ipw_priv *priv, u16 sens)
2288 {
2289         struct ipw_sensitivity_calib calib = {
2290                 .beacon_rssi_raw = sens,
2291         };
2292
2293         return ipw_send_cmd_pdu(priv, IPW_CMD_SENSITIVITY_CALIB, sizeof(calib),
2294                                 &calib);
2295 }
2296
2297 static int ipw_send_associate(struct ipw_priv *priv,
2298                               struct ipw_associate *associate)
2299 {
2300         struct ipw_associate tmp_associate;
2301
2302         if (!priv || !associate) {
2303                 IPW_ERROR("Invalid args\n");
2304                 return -1;
2305         }
2306
2307         memcpy(&tmp_associate, associate, sizeof(*associate));
2308         tmp_associate.policy_support =
2309             cpu_to_le16(tmp_associate.policy_support);
2310         tmp_associate.assoc_tsf_msw = cpu_to_le32(tmp_associate.assoc_tsf_msw);
2311         tmp_associate.assoc_tsf_lsw = cpu_to_le32(tmp_associate.assoc_tsf_lsw);
2312         tmp_associate.capability = cpu_to_le16(tmp_associate.capability);
2313         tmp_associate.listen_interval =
2314             cpu_to_le16(tmp_associate.listen_interval);
2315         tmp_associate.beacon_interval =
2316             cpu_to_le16(tmp_associate.beacon_interval);
2317         tmp_associate.atim_window = cpu_to_le16(tmp_associate.atim_window);
2318
2319         return ipw_send_cmd_pdu(priv, IPW_CMD_ASSOCIATE, sizeof(tmp_associate),
2320                                 &tmp_associate);
2321 }
2322
2323 static int ipw_send_supported_rates(struct ipw_priv *priv,
2324                                     struct ipw_supported_rates *rates)
2325 {
2326         if (!priv || !rates) {
2327                 IPW_ERROR("Invalid args\n");
2328                 return -1;
2329         }
2330
2331         return ipw_send_cmd_pdu(priv, IPW_CMD_SUPPORTED_RATES, sizeof(*rates),
2332                                 rates);
2333 }
2334
2335 static int ipw_set_random_seed(struct ipw_priv *priv)
2336 {
2337         u32 val;
2338
2339         if (!priv) {
2340                 IPW_ERROR("Invalid args\n");
2341                 return -1;
2342         }
2343
2344         get_random_bytes(&val, sizeof(val));
2345
2346         return ipw_send_cmd_pdu(priv, IPW_CMD_SEED_NUMBER, sizeof(val), &val);
2347 }
2348
2349 static int ipw_send_card_disable(struct ipw_priv *priv, u32 phy_off)
2350 {
2351         if (!priv) {
2352                 IPW_ERROR("Invalid args\n");
2353                 return -1;
2354         }
2355
2356         return ipw_send_cmd_pdu(priv, IPW_CMD_CARD_DISABLE, sizeof(phy_off),
2357                                 &phy_off);
2358 }
2359
2360 static int ipw_send_tx_power(struct ipw_priv *priv, struct ipw_tx_power *power)
2361 {
2362         if (!priv || !power) {
2363                 IPW_ERROR("Invalid args\n");
2364                 return -1;
2365         }
2366
2367         return ipw_send_cmd_pdu(priv, IPW_CMD_TX_POWER, sizeof(*power), power);
2368 }
2369
2370 static int ipw_set_tx_power(struct ipw_priv *priv)
2371 {
2372         const struct ieee80211_geo *geo = ieee80211_get_geo(priv->ieee);
2373         struct ipw_tx_power tx_power;
2374         s8 max_power;
2375         int i;
2376
2377         memset(&tx_power, 0, sizeof(tx_power));
2378
2379         /* configure device for 'G' band */
2380         tx_power.ieee_mode = IPW_G_MODE;
2381         tx_power.num_channels = geo->bg_channels;
2382         for (i = 0; i < geo->bg_channels; i++) {
2383                 max_power = geo->bg[i].max_power;
2384                 tx_power.channels_tx_power[i].channel_number =
2385                     geo->bg[i].channel;
2386                 tx_power.channels_tx_power[i].tx_power = max_power ?
2387                     min(max_power, priv->tx_power) : priv->tx_power;
2388         }
2389         if (ipw_send_tx_power(priv, &tx_power))
2390                 return -EIO;
2391
2392         /* configure device to also handle 'B' band */
2393         tx_power.ieee_mode = IPW_B_MODE;
2394         if (ipw_send_tx_power(priv, &tx_power))
2395                 return -EIO;
2396
2397         /* configure device to also handle 'A' band */
2398         if (priv->ieee->abg_true) {
2399                 tx_power.ieee_mode = IPW_A_MODE;
2400                 tx_power.num_channels = geo->a_channels;
2401                 for (i = 0; i < tx_power.num_channels; i++) {
2402                         max_power = geo->a[i].max_power;
2403                         tx_power.channels_tx_power[i].channel_number =
2404                             geo->a[i].channel;
2405                         tx_power.channels_tx_power[i].tx_power = max_power ?
2406                             min(max_power, priv->tx_power) : priv->tx_power;
2407                 }
2408                 if (ipw_send_tx_power(priv, &tx_power))
2409                         return -EIO;
2410         }
2411         return 0;
2412 }
2413
2414 static int ipw_send_rts_threshold(struct ipw_priv *priv, u16 rts)
2415 {
2416         struct ipw_rts_threshold rts_threshold = {
2417                 .rts_threshold = rts,
2418         };
2419
2420         if (!priv) {
2421                 IPW_ERROR("Invalid args\n");
2422                 return -1;
2423         }
2424
2425         return ipw_send_cmd_pdu(priv, IPW_CMD_RTS_THRESHOLD,
2426                                 sizeof(rts_threshold), &rts_threshold);
2427 }
2428
2429 static int ipw_send_frag_threshold(struct ipw_priv *priv, u16 frag)
2430 {
2431         struct ipw_frag_threshold frag_threshold = {
2432                 .frag_threshold = frag,
2433         };
2434
2435         if (!priv) {
2436                 IPW_ERROR("Invalid args\n");
2437                 return -1;
2438         }
2439
2440         return ipw_send_cmd_pdu(priv, IPW_CMD_FRAG_THRESHOLD,
2441                                 sizeof(frag_threshold), &frag_threshold);
2442 }
2443
2444 static int ipw_send_power_mode(struct ipw_priv *priv, u32 mode)
2445 {
2446         u32 param;
2447
2448         if (!priv) {
2449                 IPW_ERROR("Invalid args\n");
2450                 return -1;
2451         }
2452
2453         /* If on battery, set to 3, if AC set to CAM, else user
2454          * level */
2455         switch (mode) {
2456         case IPW_POWER_BATTERY:
2457                 param = IPW_POWER_INDEX_3;
2458                 break;
2459         case IPW_POWER_AC:
2460                 param = IPW_POWER_MODE_CAM;
2461                 break;
2462         default:
2463                 param = mode;
2464                 break;
2465         }
2466
2467         return ipw_send_cmd_pdu(priv, IPW_CMD_POWER_MODE, sizeof(param),
2468                                 &param);
2469 }
2470
2471 static int ipw_send_retry_limit(struct ipw_priv *priv, u8 slimit, u8 llimit)
2472 {
2473         struct ipw_retry_limit retry_limit = {
2474                 .short_retry_limit = slimit,
2475                 .long_retry_limit = llimit
2476         };
2477
2478         if (!priv) {
2479                 IPW_ERROR("Invalid args\n");
2480                 return -1;
2481         }
2482
2483         return ipw_send_cmd_pdu(priv, IPW_CMD_RETRY_LIMIT, sizeof(retry_limit),
2484                                 &retry_limit);
2485 }
2486
2487 /*
2488  * The IPW device contains a Microwire compatible EEPROM that stores
2489  * various data like the MAC address.  Usually the firmware has exclusive
2490  * access to the eeprom, but during device initialization (before the
2491  * device driver has sent the HostComplete command to the firmware) the
2492  * device driver has read access to the EEPROM by way of indirect addressing
2493  * through a couple of memory mapped registers.
2494  *
2495  * The following is a simplified implementation for pulling data out of the
2496  * the eeprom, along with some helper functions to find information in
2497  * the per device private data's copy of the eeprom.
2498  *
2499  * NOTE: To better understand how these functions work (i.e what is a chip
2500  *       select and why do have to keep driving the eeprom clock?), read
2501  *       just about any data sheet for a Microwire compatible EEPROM.
2502  */
2503
2504 /* write a 32 bit value into the indirect accessor register */
2505 static inline void eeprom_write_reg(struct ipw_priv *p, u32 data)
2506 {
2507         ipw_write_reg32(p, FW_MEM_REG_EEPROM_ACCESS, data);
2508
2509         /* the eeprom requires some time to complete the operation */
2510         udelay(p->eeprom_delay);
2511
2512         return;
2513 }
2514
2515 /* perform a chip select operation */
2516 static void eeprom_cs(struct ipw_priv *priv)
2517 {
2518         eeprom_write_reg(priv, 0);
2519         eeprom_write_reg(priv, EEPROM_BIT_CS);
2520         eeprom_write_reg(priv, EEPROM_BIT_CS | EEPROM_BIT_SK);
2521         eeprom_write_reg(priv, EEPROM_BIT_CS);
2522 }
2523
2524 /* perform a chip select operation */
2525 static void eeprom_disable_cs(struct ipw_priv *priv)
2526 {
2527         eeprom_write_reg(priv, EEPROM_BIT_CS);
2528         eeprom_write_reg(priv, 0);
2529         eeprom_write_reg(priv, EEPROM_BIT_SK);
2530 }
2531
2532 /* push a single bit down to the eeprom */
2533 static inline void eeprom_write_bit(struct ipw_priv *p, u8 bit)
2534 {
2535         int d = (bit ? EEPROM_BIT_DI : 0);
2536         eeprom_write_reg(p, EEPROM_BIT_CS | d);
2537         eeprom_write_reg(p, EEPROM_BIT_CS | d | EEPROM_BIT_SK);
2538 }
2539
2540 /* push an opcode followed by an address down to the eeprom */
2541 static void eeprom_op(struct ipw_priv *priv, u8 op, u8 addr)
2542 {
2543         int i;
2544
2545         eeprom_cs(priv);
2546         eeprom_write_bit(priv, 1);
2547         eeprom_write_bit(priv, op & 2);
2548         eeprom_write_bit(priv, op & 1);
2549         for (i = 7; i >= 0; i--) {
2550                 eeprom_write_bit(priv, addr & (1 << i));
2551         }
2552 }
2553
2554 /* pull 16 bits off the eeprom, one bit at a time */
2555 static u16 eeprom_read_u16(struct ipw_priv *priv, u8 addr)
2556 {
2557         int i;
2558         u16 r = 0;
2559
2560         /* Send READ Opcode */
2561         eeprom_op(priv, EEPROM_CMD_READ, addr);
2562
2563         /* Send dummy bit */
2564         eeprom_write_reg(priv, EEPROM_BIT_CS);
2565
2566         /* Read the byte off the eeprom one bit at a time */
2567         for (i = 0; i < 16; i++) {
2568                 u32 data = 0;
2569                 eeprom_write_reg(priv, EEPROM_BIT_CS | EEPROM_BIT_SK);
2570                 eeprom_write_reg(priv, EEPROM_BIT_CS);
2571                 data = ipw_read_reg32(priv, FW_MEM_REG_EEPROM_ACCESS);
2572                 r = (r << 1) | ((data & EEPROM_BIT_DO) ? 1 : 0);
2573         }
2574
2575         /* Send another dummy bit */
2576         eeprom_write_reg(priv, 0);
2577         eeprom_disable_cs(priv);
2578
2579         return r;
2580 }
2581
2582 /* helper function for pulling the mac address out of the private */
2583 /* data's copy of the eeprom data                                 */
2584 static void eeprom_parse_mac(struct ipw_priv *priv, u8 * mac)
2585 {
2586         memcpy(mac, &priv->eeprom[EEPROM_MAC_ADDRESS], 6);
2587 }
2588
2589 /*
2590  * Either the device driver (i.e. the host) or the firmware can
2591  * load eeprom data into the designated region in SRAM.  If neither
2592  * happens then the FW will shutdown with a fatal error.
2593  *
2594  * In order to signal the FW to load the EEPROM, the EEPROM_LOAD_DISABLE
2595  * bit needs region of shared SRAM needs to be non-zero.
2596  */
2597 static void ipw_eeprom_init_sram(struct ipw_priv *priv)
2598 {
2599         int i;
2600         u16 *eeprom = (u16 *) priv->eeprom;
2601
2602         IPW_DEBUG_TRACE(">>\n");
2603
2604         /* read entire contents of eeprom into private buffer */
2605         for (i = 0; i < 128; i++)
2606                 eeprom[i] = le16_to_cpu(eeprom_read_u16(priv, (u8) i));
2607
2608         /*
2609            If the data looks correct, then copy it to our private
2610            copy.  Otherwise let the firmware know to perform the operation
2611            on its own.
2612          */
2613         if (priv->eeprom[EEPROM_VERSION] != 0) {
2614                 IPW_DEBUG_INFO("Writing EEPROM data into SRAM\n");
2615
2616                 /* write the eeprom data to sram */
2617                 for (i = 0; i < IPW_EEPROM_IMAGE_SIZE; i++)
2618                         ipw_write8(priv, IPW_EEPROM_DATA + i, priv->eeprom[i]);
2619
2620                 /* Do not load eeprom data on fatal error or suspend */
2621                 ipw_write32(priv, IPW_EEPROM_LOAD_DISABLE, 0);
2622         } else {
2623                 IPW_DEBUG_INFO("Enabling FW initializationg of SRAM\n");
2624
2625                 /* Load eeprom data on fatal error or suspend */
2626                 ipw_write32(priv, IPW_EEPROM_LOAD_DISABLE, 1);
2627         }
2628
2629         IPW_DEBUG_TRACE("<<\n");
2630 }
2631
2632 static void ipw_zero_memory(struct ipw_priv *priv, u32 start, u32 count)
2633 {
2634         count >>= 2;
2635         if (!count)
2636                 return;
2637         _ipw_write32(priv, IPW_AUTOINC_ADDR, start);
2638         while (count--)
2639                 _ipw_write32(priv, IPW_AUTOINC_DATA, 0);
2640 }
2641
2642 static inline void ipw_fw_dma_reset_command_blocks(struct ipw_priv *priv)
2643 {
2644         ipw_zero_memory(priv, IPW_SHARED_SRAM_DMA_CONTROL,
2645                         CB_NUMBER_OF_ELEMENTS_SMALL *
2646                         sizeof(struct command_block));
2647 }
2648
2649 static int ipw_fw_dma_enable(struct ipw_priv *priv)
2650 {                               /* start dma engine but no transfers yet */
2651
2652         IPW_DEBUG_FW(">> : \n");
2653
2654         /* Start the dma */
2655         ipw_fw_dma_reset_command_blocks(priv);
2656
2657         /* Write CB base address */
2658         ipw_write_reg32(priv, IPW_DMA_I_CB_BASE, IPW_SHARED_SRAM_DMA_CONTROL);
2659
2660         IPW_DEBUG_FW("<< : \n");
2661         return 0;
2662 }
2663
2664 static void ipw_fw_dma_abort(struct ipw_priv *priv)
2665 {
2666         u32 control = 0;
2667
2668         IPW_DEBUG_FW(">> :\n");
2669
2670         /* set the Stop and Abort bit */
2671         control = DMA_CONTROL_SMALL_CB_CONST_VALUE | DMA_CB_STOP_AND_ABORT;
2672         ipw_write_reg32(priv, IPW_DMA_I_DMA_CONTROL, control);
2673         priv->sram_desc.last_cb_index = 0;
2674
2675         IPW_DEBUG_FW("<< \n");
2676 }
2677
2678 static int ipw_fw_dma_write_command_block(struct ipw_priv *priv, int index,
2679                                           struct command_block *cb)
2680 {
2681         u32 address =
2682             IPW_SHARED_SRAM_DMA_CONTROL +
2683             (sizeof(struct command_block) * index);
2684         IPW_DEBUG_FW(">> :\n");
2685
2686         ipw_write_indirect(priv, address, (u8 *) cb,
2687                            (int)sizeof(struct command_block));
2688
2689         IPW_DEBUG_FW("<< :\n");
2690         return 0;
2691
2692 }
2693
2694 static int ipw_fw_dma_kick(struct ipw_priv *priv)
2695 {
2696         u32 control = 0;
2697         u32 index = 0;
2698
2699         IPW_DEBUG_FW(">> :\n");
2700
2701         for (index = 0; index < priv->sram_desc.last_cb_index; index++)
2702                 ipw_fw_dma_write_command_block(priv, index,
2703                                                &priv->sram_desc.cb_list[index]);
2704
2705         /* Enable the DMA in the CSR register */
2706         ipw_clear_bit(priv, IPW_RESET_REG,
2707                       IPW_RESET_REG_MASTER_DISABLED |
2708                       IPW_RESET_REG_STOP_MASTER);
2709
2710         /* Set the Start bit. */
2711         control = DMA_CONTROL_SMALL_CB_CONST_VALUE | DMA_CB_START;
2712         ipw_write_reg32(priv, IPW_DMA_I_DMA_CONTROL, control);
2713
2714         IPW_DEBUG_FW("<< :\n");
2715         return 0;
2716 }
2717
2718 static void ipw_fw_dma_dump_command_block(struct ipw_priv *priv)
2719 {
2720         u32 address;
2721         u32 register_value = 0;
2722         u32 cb_fields_address = 0;
2723
2724         IPW_DEBUG_FW(">> :\n");
2725         address = ipw_read_reg32(priv, IPW_DMA_I_CURRENT_CB);
2726         IPW_DEBUG_FW_INFO("Current CB is 0x%x \n", address);
2727
2728         /* Read the DMA Controlor register */
2729         register_value = ipw_read_reg32(priv, IPW_DMA_I_DMA_CONTROL);
2730         IPW_DEBUG_FW_INFO("IPW_DMA_I_DMA_CONTROL is 0x%x \n", register_value);
2731
2732         /* Print the CB values */
2733         cb_fields_address = address;
2734         register_value = ipw_read_reg32(priv, cb_fields_address);
2735         IPW_DEBUG_FW_INFO("Current CB ControlField is 0x%x \n", register_value);
2736
2737         cb_fields_address += sizeof(u32);
2738         register_value = ipw_read_reg32(priv, cb_fields_address);
2739         IPW_DEBUG_FW_INFO("Current CB Source Field is 0x%x \n", register_value);
2740
2741         cb_fields_address += sizeof(u32);
2742         register_value = ipw_read_reg32(priv, cb_fields_address);
2743         IPW_DEBUG_FW_INFO("Current CB Destination Field is 0x%x \n",
2744                           register_value);
2745
2746         cb_fields_address += sizeof(u32);
2747         register_value = ipw_read_reg32(priv, cb_fields_address);
2748         IPW_DEBUG_FW_INFO("Current CB Status Field is 0x%x \n", register_value);
2749
2750         IPW_DEBUG_FW(">> :\n");
2751 }
2752
2753 static int ipw_fw_dma_command_block_index(struct ipw_priv *priv)
2754 {
2755         u32 current_cb_address = 0;
2756         u32 current_cb_index = 0;
2757
2758         IPW_DEBUG_FW("<< :\n");
2759         current_cb_address = ipw_read_reg32(priv, IPW_DMA_I_CURRENT_CB);
2760
2761         current_cb_index = (current_cb_address - IPW_SHARED_SRAM_DMA_CONTROL) /
2762             sizeof(struct command_block);
2763
2764         IPW_DEBUG_FW_INFO("Current CB index 0x%x address = 0x%X \n",
2765                           current_cb_index, current_cb_address);
2766
2767         IPW_DEBUG_FW(">> :\n");
2768         return current_cb_index;
2769
2770 }
2771
2772 static int ipw_fw_dma_add_command_block(struct ipw_priv *priv,
2773                                         u32 src_address,
2774                                         u32 dest_address,
2775                                         u32 length,
2776                                         int interrupt_enabled, int is_last)
2777 {
2778
2779         u32 control = CB_VALID | CB_SRC_LE | CB_DEST_LE | CB_SRC_AUTOINC |
2780             CB_SRC_IO_GATED | CB_DEST_AUTOINC | CB_SRC_SIZE_LONG |
2781             CB_DEST_SIZE_LONG;
2782         struct command_block *cb;
2783         u32 last_cb_element = 0;
2784
2785         IPW_DEBUG_FW_INFO("src_address=0x%x dest_address=0x%x length=0x%x\n",
2786                           src_address, dest_address, length);
2787
2788         if (priv->sram_desc.last_cb_index >= CB_NUMBER_OF_ELEMENTS_SMALL)
2789                 return -1;
2790
2791         last_cb_element = priv->sram_desc.last_cb_index;
2792         cb = &priv->sram_desc.cb_list[last_cb_element];
2793         priv->sram_desc.last_cb_index++;
2794
2795         /* Calculate the new CB control word */
2796         if (interrupt_enabled)
2797                 control |= CB_INT_ENABLED;
2798
2799         if (is_last)
2800                 control |= CB_LAST_VALID;
2801
2802         control |= length;
2803
2804         /* Calculate the CB Element's checksum value */
2805         cb->status = control ^ src_address ^ dest_address;
2806
2807         /* Copy the Source and Destination addresses */
2808         cb->dest_addr = dest_address;
2809         cb->source_addr = src_address;
2810
2811         /* Copy the Control Word last */
2812         cb->control = control;
2813
2814         return 0;
2815 }
2816
2817 static int ipw_fw_dma_add_buffer(struct ipw_priv *priv,
2818                                  u32 src_phys, u32 dest_address, u32 length)
2819 {
2820         u32 bytes_left = length;
2821         u32 src_offset = 0;
2822         u32 dest_offset = 0;
2823         int status = 0;
2824         IPW_DEBUG_FW(">> \n");
2825         IPW_DEBUG_FW_INFO("src_phys=0x%x dest_address=0x%x length=0x%x\n",
2826                           src_phys, dest_address, length);
2827         while (bytes_left > CB_MAX_LENGTH) {
2828                 status = ipw_fw_dma_add_command_block(priv,
2829                                                       src_phys + src_offset,
2830                                                       dest_address +
2831                                                       dest_offset,
2832                                                       CB_MAX_LENGTH, 0, 0);
2833                 if (status) {
2834                         IPW_DEBUG_FW_INFO(": Failed\n");
2835                         return -1;
2836                 } else
2837                         IPW_DEBUG_FW_INFO(": Added new cb\n");
2838
2839                 src_offset += CB_MAX_LENGTH;
2840                 dest_offset += CB_MAX_LENGTH;
2841                 bytes_left -= CB_MAX_LENGTH;
2842         }
2843
2844         /* add the buffer tail */
2845         if (bytes_left > 0) {
2846                 status =
2847                     ipw_fw_dma_add_command_block(priv, src_phys + src_offset,
2848                                                  dest_address + dest_offset,
2849                                                  bytes_left, 0, 0);
2850                 if (status) {
2851                         IPW_DEBUG_FW_INFO(": Failed on the buffer tail\n");
2852                         return -1;
2853                 } else
2854                         IPW_DEBUG_FW_INFO
2855                             (": Adding new cb - the buffer tail\n");
2856         }
2857
2858         IPW_DEBUG_FW("<< \n");
2859         return 0;
2860 }
2861
2862 static int ipw_fw_dma_wait(struct ipw_priv *priv)
2863 {
2864         u32 current_index = 0, previous_index;
2865         u32 watchdog = 0;
2866
2867         IPW_DEBUG_FW(">> : \n");
2868
2869         current_index = ipw_fw_dma_command_block_index(priv);
2870         IPW_DEBUG_FW_INFO("sram_desc.last_cb_index:0x%08X\n",
2871                           (int)priv->sram_desc.last_cb_index);
2872
2873         while (current_index < priv->sram_desc.last_cb_index) {
2874                 udelay(50);
2875                 previous_index = current_index;
2876                 current_index = ipw_fw_dma_command_block_index(priv);
2877
2878                 if (previous_index < current_index) {
2879                         watchdog = 0;
2880                         continue;
2881                 }
2882                 if (++watchdog > 400) {
2883                         IPW_DEBUG_FW_INFO("Timeout\n");
2884                         ipw_fw_dma_dump_command_block(priv);
2885                         ipw_fw_dma_abort(priv);
2886                         return -1;
2887                 }
2888         }
2889
2890         ipw_fw_dma_abort(priv);
2891
2892         /*Disable the DMA in the CSR register */
2893         ipw_set_bit(priv, IPW_RESET_REG,
2894                     IPW_RESET_REG_MASTER_DISABLED | IPW_RESET_REG_STOP_MASTER);
2895
2896         IPW_DEBUG_FW("<< dmaWaitSync \n");
2897         return 0;
2898 }
2899
2900 static void ipw_remove_current_network(struct ipw_priv *priv)
2901 {
2902         struct list_head *element, *safe;
2903         struct ieee80211_network *network = NULL;
2904         unsigned long flags;
2905
2906         spin_lock_irqsave(&priv->ieee->lock, flags);
2907         list_for_each_safe(element, safe, &priv->ieee->network_list) {
2908                 network = list_entry(element, struct ieee80211_network, list);
2909                 if (!memcmp(network->bssid, priv->bssid, ETH_ALEN)) {
2910                         list_del(element);
2911                         list_add_tail(&network->list,
2912                                       &priv->ieee->network_free_list);
2913                 }
2914         }
2915         spin_unlock_irqrestore(&priv->ieee->lock, flags);
2916 }
2917
2918 /**
2919  * Check that card is still alive.
2920  * Reads debug register from domain0.
2921  * If card is present, pre-defined value should
2922  * be found there.
2923  *
2924  * @param priv
2925  * @return 1 if card is present, 0 otherwise
2926  */
2927 static inline int ipw_alive(struct ipw_priv *priv)
2928 {
2929         return ipw_read32(priv, 0x90) == 0xd55555d5;
2930 }
2931
2932 /* timeout in msec, attempted in 10-msec quanta */
2933 static int ipw_poll_bit(struct ipw_priv *priv, u32 addr, u32 mask,
2934                                int timeout)
2935 {
2936         int i = 0;
2937
2938         do {
2939                 if ((ipw_read32(priv, addr) & mask) == mask)
2940                         return i;
2941                 mdelay(10);
2942                 i += 10;
2943         } while (i < timeout);
2944
2945         return -ETIME;
2946 }
2947
2948 /* These functions load the firmware and micro code for the operation of
2949  * the ipw hardware.  It assumes the buffer has all the bits for the
2950  * image and the caller is handling the memory allocation and clean up.
2951  */
2952
2953 static int ipw_stop_master(struct ipw_priv *priv)
2954 {
2955         int rc;
2956
2957         IPW_DEBUG_TRACE(">> \n");
2958         /* stop master. typical delay - 0 */
2959         ipw_set_bit(priv, IPW_RESET_REG, IPW_RESET_REG_STOP_MASTER);
2960
2961         /* timeout is in msec, polled in 10-msec quanta */
2962         rc = ipw_poll_bit(priv, IPW_RESET_REG,
2963                           IPW_RESET_REG_MASTER_DISABLED, 100);
2964         if (rc < 0) {
2965                 IPW_ERROR("wait for stop master failed after 100ms\n");
2966                 return -1;
2967         }
2968
2969         IPW_DEBUG_INFO("stop master %dms\n", rc);
2970
2971         return rc;
2972 }
2973
2974 static void ipw_arc_release(struct ipw_priv *priv)
2975 {
2976         IPW_DEBUG_TRACE(">> \n");
2977         mdelay(5);
2978
2979         ipw_clear_bit(priv, IPW_RESET_REG, CBD_RESET_REG_PRINCETON_RESET);
2980
2981         /* no one knows timing, for safety add some delay */
2982         mdelay(5);
2983 }
2984
2985 struct fw_chunk {
2986         u32 address;
2987         u32 length;
2988 };
2989
2990 static int ipw_load_ucode(struct ipw_priv *priv, u8 * data, size_t len)
2991 {
2992         int rc = 0, i, addr;
2993         u8 cr = 0;
2994         u16 *image;
2995
2996         image = (u16 *) data;
2997
2998         IPW_DEBUG_TRACE(">> \n");
2999
3000         rc = ipw_stop_master(priv);
3001
3002         if (rc < 0)
3003                 return rc;
3004
3005         for (addr = IPW_SHARED_LOWER_BOUND;
3006              addr < IPW_REGISTER_DOMAIN1_END; addr += 4) {
3007                 ipw_write32(priv, addr, 0);
3008         }
3009
3010         /* no ucode (yet) */
3011         memset(&priv->dino_alive, 0, sizeof(priv->dino_alive));
3012         /* destroy DMA queues */
3013         /* reset sequence */
3014
3015         ipw_write_reg32(priv, IPW_MEM_HALT_AND_RESET, IPW_BIT_HALT_RESET_ON);
3016         ipw_arc_release(priv);
3017         ipw_write_reg32(priv, IPW_MEM_HALT_AND_RESET, IPW_BIT_HALT_RESET_OFF);
3018         mdelay(1);
3019
3020         /* reset PHY */
3021         ipw_write_reg32(priv, IPW_INTERNAL_CMD_EVENT, IPW_BASEBAND_POWER_DOWN);
3022         mdelay(1);
3023
3024         ipw_write_reg32(priv, IPW_INTERNAL_CMD_EVENT, 0);
3025         mdelay(1);
3026
3027         /* enable ucode store */
3028         ipw_write_reg8(priv, IPW_BASEBAND_CONTROL_STATUS, 0x0);
3029         ipw_write_reg8(priv, IPW_BASEBAND_CONTROL_STATUS, DINO_ENABLE_CS);
3030         mdelay(1);
3031
3032         /* write ucode */
3033         /**
3034          * @bug
3035          * Do NOT set indirect address register once and then
3036          * store data to indirect data register in the loop.
3037          * It seems very reasonable, but in this case DINO do not
3038          * accept ucode. It is essential to set address each time.
3039          */
3040         /* load new ipw uCode */
3041         for (i = 0; i < len / 2; i++)
3042                 ipw_write_reg16(priv, IPW_BASEBAND_CONTROL_STORE,
3043                                 cpu_to_le16(image[i]));
3044
3045         /* enable DINO */
3046         ipw_write_reg8(priv, IPW_BASEBAND_CONTROL_STATUS, 0);
3047         ipw_write_reg8(priv, IPW_BASEBAND_CONTROL_STATUS, DINO_ENABLE_SYSTEM);
3048
3049         /* this is where the igx / win driver deveates from the VAP driver. */
3050
3051         /* wait for alive response */
3052         for (i = 0; i < 100; i++) {
3053                 /* poll for incoming data */
3054                 cr = ipw_read_reg8(priv, IPW_BASEBAND_CONTROL_STATUS);
3055                 if (cr & DINO_RXFIFO_DATA)
3056                         break;
3057                 mdelay(1);
3058         }
3059
3060         if (cr & DINO_RXFIFO_DATA) {
3061                 /* alive_command_responce size is NOT multiple of 4 */
3062                 u32 response_buffer[(sizeof(priv->dino_alive) + 3) / 4];
3063
3064                 for (i = 0; i < ARRAY_SIZE(response_buffer); i++)
3065                         response_buffer[i] =
3066                             le32_to_cpu(ipw_read_reg32(priv,
3067                                                        IPW_BASEBAND_RX_FIFO_READ));
3068                 memcpy(&priv->dino_alive, response_buffer,
3069                        sizeof(priv->dino_alive));
3070                 if (priv->dino_alive.alive_command == 1
3071                     && priv->dino_alive.ucode_valid == 1) {
3072                         rc = 0;
3073                         IPW_DEBUG_INFO
3074                             ("Microcode OK, rev. %d (0x%x) dev. %d (0x%x) "
3075                              "of %02d/%02d/%02d %02d:%02d\n",
3076                              priv->dino_alive.software_revision,
3077                              priv->dino_alive.software_revision,
3078                              priv->dino_alive.device_identifier,
3079                              priv->dino_alive.device_identifier,
3080                              priv->dino_alive.time_stamp[0],
3081                              priv->dino_alive.time_stamp[1],
3082                              priv->dino_alive.time_stamp[2],
3083                              priv->dino_alive.time_stamp[3],
3084                              priv->dino_alive.time_stamp[4]);
3085                 } else {
3086                         IPW_DEBUG_INFO("Microcode is not alive\n");
3087                         rc = -EINVAL;
3088                 }
3089         } else {
3090                 IPW_DEBUG_INFO("No alive response from DINO\n");
3091                 rc = -ETIME;
3092         }
3093
3094         /* disable DINO, otherwise for some reason
3095            firmware have problem getting alive resp. */
3096         ipw_write_reg8(priv, IPW_BASEBAND_CONTROL_STATUS, 0);
3097
3098         return rc;
3099 }
3100
3101 static int ipw_load_firmware(struct ipw_priv *priv, u8 * data, size_t len)
3102 {
3103         int rc = -1;
3104         int offset = 0;
3105         struct fw_chunk *chunk;
3106         dma_addr_t shared_phys;
3107         u8 *shared_virt;
3108
3109         IPW_DEBUG_TRACE("<< : \n");
3110         shared_virt = pci_alloc_consistent(priv->pci_dev, len, &shared_phys);
3111
3112         if (!shared_virt)
3113                 return -ENOMEM;
3114
3115         memmove(shared_virt, data, len);
3116
3117         /* Start the Dma */
3118         rc = ipw_fw_dma_enable(priv);
3119
3120         if (priv->sram_desc.last_cb_index > 0) {
3121                 /* the DMA is already ready this would be a bug. */
3122                 BUG();
3123                 goto out;
3124         }
3125
3126         do {
3127                 chunk = (struct fw_chunk *)(data + offset);
3128                 offset += sizeof(struct fw_chunk);
3129                 /* build DMA packet and queue up for sending */
3130                 /* dma to chunk->address, the chunk->length bytes from data +
3131                  * offeset*/
3132                 /* Dma loading */
3133                 rc = ipw_fw_dma_add_buffer(priv, shared_phys + offset,
3134                                            le32_to_cpu(chunk->address),
3135                                            le32_to_cpu(chunk->length));
3136                 if (rc) {
3137                         IPW_DEBUG_INFO("dmaAddBuffer Failed\n");
3138                         goto out;
3139                 }
3140
3141                 offset += le32_to_cpu(chunk->length);
3142         } while (offset < len);
3143
3144         /* Run the DMA and wait for the answer */
3145         rc = ipw_fw_dma_kick(priv);
3146         if (rc) {
3147                 IPW_ERROR("dmaKick Failed\n");
3148                 goto out;
3149         }
3150
3151         rc = ipw_fw_dma_wait(priv);
3152         if (rc) {
3153                 IPW_ERROR("dmaWaitSync Failed\n");
3154                 goto out;
3155         }
3156       out:
3157         pci_free_consistent(priv->pci_dev, len, shared_virt, shared_phys);
3158         return rc;
3159 }
3160
3161 /* stop nic */
3162 static int ipw_stop_nic(struct ipw_priv *priv)
3163 {
3164         int rc = 0;
3165
3166         /* stop */
3167         ipw_write32(priv, IPW_RESET_REG, IPW_RESET_REG_STOP_MASTER);
3168
3169         rc = ipw_poll_bit(priv, IPW_RESET_REG,
3170                           IPW_RESET_REG_MASTER_DISABLED, 500);
3171         if (rc < 0) {
3172                 IPW_ERROR("wait for reg master disabled failed after 500ms\n");
3173                 return rc;
3174         }
3175
3176         ipw_set_bit(priv, IPW_RESET_REG, CBD_RESET_REG_PRINCETON_RESET);
3177
3178         return rc;
3179 }
3180
3181 static void ipw_start_nic(struct ipw_priv *priv)
3182 {
3183         IPW_DEBUG_TRACE(">>\n");
3184
3185         /* prvHwStartNic  release ARC */
3186         ipw_clear_bit(priv, IPW_RESET_REG,
3187                       IPW_RESET_REG_MASTER_DISABLED |
3188                       IPW_RESET_REG_STOP_MASTER |
3189                       CBD_RESET_REG_PRINCETON_RESET);
3190
3191         /* enable power management */
3192         ipw_set_bit(priv, IPW_GP_CNTRL_RW,
3193                     IPW_GP_CNTRL_BIT_HOST_ALLOWS_STANDBY);
3194
3195         IPW_DEBUG_TRACE("<<\n");
3196 }
3197
3198 static int ipw_init_nic(struct ipw_priv *priv)
3199 {
3200         int rc;
3201
3202         IPW_DEBUG_TRACE(">>\n");
3203         /* reset */
3204         /*prvHwInitNic */
3205         /* set "initialization complete" bit to move adapter to D0 state */
3206         ipw_set_bit(priv, IPW_GP_CNTRL_RW, IPW_GP_CNTRL_BIT_INIT_DONE);
3207
3208         /* low-level PLL activation */
3209         ipw_write32(priv, IPW_READ_INT_REGISTER,
3210                     IPW_BIT_INT_HOST_SRAM_READ_INT_REGISTER);
3211
3212         /* wait for clock stabilization */
3213         rc = ipw_poll_bit(priv, IPW_GP_CNTRL_RW,
3214                           IPW_GP_CNTRL_BIT_CLOCK_READY, 250);
3215         if (rc < 0)
3216                 IPW_DEBUG_INFO("FAILED wait for clock stablization\n");
3217
3218         /* assert SW reset */
3219         ipw_set_bit(priv, IPW_RESET_REG, IPW_RESET_REG_SW_RESET);
3220
3221         udelay(10);
3222
3223         /* set "initialization complete" bit to move adapter to D0 state */
3224         ipw_set_bit(priv, IPW_GP_CNTRL_RW, IPW_GP_CNTRL_BIT_INIT_DONE);
3225
3226         IPW_DEBUG_TRACE(">>\n");
3227         return 0;
3228 }
3229
3230 /* Call this function from process context, it will sleep in request_firmware.
3231  * Probe is an ok place to call this from.
3232  */
3233 static int ipw_reset_nic(struct ipw_priv *priv)
3234 {
3235         int rc = 0;
3236         unsigned long flags;
3237
3238         IPW_DEBUG_TRACE(">>\n");
3239
3240         rc = ipw_init_nic(priv);
3241
3242         spin_lock_irqsave(&priv->lock, flags);
3243         /* Clear the 'host command active' bit... */
3244         priv->status &= ~STATUS_HCMD_ACTIVE;
3245         wake_up_interruptible(&priv->wait_command_queue);
3246         priv->status &= ~(STATUS_SCANNING | STATUS_SCAN_ABORTING);
3247         wake_up_interruptible(&priv->wait_state);
3248         spin_unlock_irqrestore(&priv->lock, flags);
3249
3250         IPW_DEBUG_TRACE("<<\n");
3251         return rc;
3252 }
3253
3254
3255 struct ipw_fw {
3256         __le32 ver;
3257         __le32 boot_size;
3258         __le32 ucode_size;
3259         __le32 fw_size;
3260         u8 data[0];
3261 };
3262
3263 static int ipw_get_fw(struct ipw_priv *priv,
3264                       const struct firmware **raw, const char *name)
3265 {
3266         struct ipw_fw *fw;
3267         int rc;
3268
3269         /* ask firmware_class module to get the boot firmware off disk */
3270         rc = request_firmware(raw, name, &priv->pci_dev->dev);
3271         if (rc < 0) {
3272                 IPW_ERROR("%s request_firmware failed: Reason %d\n", name, rc);
3273                 return rc;
3274         }
3275
3276         if ((*raw)->size < sizeof(*fw)) {
3277                 IPW_ERROR("%s is too small (%zd)\n", name, (*raw)->size);
3278                 return -EINVAL;
3279         }
3280
3281         fw = (void *)(*raw)->data;
3282
3283         if ((*raw)->size < sizeof(*fw) + le32_to_cpu(fw->boot_size) +
3284             le32_to_cpu(fw->ucode_size) + le32_to_cpu(fw->fw_size)) {
3285                 IPW_ERROR("%s is too small or corrupt (%zd)\n",
3286                           name, (*raw)->size);
3287                 return -EINVAL;
3288         }
3289
3290         IPW_DEBUG_INFO("Read firmware '%s' image v%d.%d (%zd bytes)\n",
3291                        name,
3292                        le32_to_cpu(fw->ver) >> 16,
3293                        le32_to_cpu(fw->ver) & 0xff,
3294                        (*raw)->size - sizeof(*fw));
3295         return 0;
3296 }
3297
3298 #define IPW_RX_BUF_SIZE (3000)
3299
3300 static void ipw_rx_queue_reset(struct ipw_priv *priv,
3301                                       struct ipw_rx_queue *rxq)
3302 {
3303         unsigned long flags;
3304         int i;
3305
3306         spin_lock_irqsave(&rxq->lock, flags);
3307
3308         INIT_LIST_HEAD(&rxq->rx_free);
3309         INIT_LIST_HEAD(&rxq->rx_used);
3310
3311         /* Fill the rx_used queue with _all_ of the Rx buffers */
3312         for (i = 0; i < RX_FREE_BUFFERS + RX_QUEUE_SIZE; i++) {
3313                 /* In the reset function, these buffers may have been allocated
3314                  * to an SKB, so we need to unmap and free potential storage */
3315                 if (rxq->pool[i].skb != NULL) {
3316                         pci_unmap_single(priv->pci_dev, rxq->pool[i].dma_addr,
3317                                          IPW_RX_BUF_SIZE, PCI_DMA_FROMDEVICE);