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[PATCH] Update version ipw2200 stamp to 1.2.2
[linux-2.6.git] / drivers / net / wireless / ipw2200.c
1 /******************************************************************************
2
3   Copyright(c) 2003 - 2006 Intel Corporation. All rights reserved.
4
5   802.11 status code portion of this file from ethereal-0.10.6:
6     Copyright 2000, Axis Communications AB
7     Ethereal - Network traffic analyzer
8     By Gerald Combs <gerald@ethereal.com>
9     Copyright 1998 Gerald Combs
10
11   This program is free software; you can redistribute it and/or modify it
12   under the terms of version 2 of the GNU General Public License as
13   published by the Free Software Foundation.
14
15   This program is distributed in the hope that it will be useful, but WITHOUT
16   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
17   FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
18   more details.
19
20   You should have received a copy of the GNU General Public License along with
21   this program; if not, write to the Free Software Foundation, Inc., 59
22   Temple Place - Suite 330, Boston, MA  02111-1307, USA.
23
24   The full GNU General Public License is included in this distribution in the
25   file called LICENSE.
26
27   Contact Information:
28   James P. Ketrenos <ipw2100-admin@linux.intel.com>
29   Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
30
31 ******************************************************************************/
32
33 #include "ipw2200.h"
34 #include <linux/version.h>
35
36
37 #ifndef KBUILD_EXTMOD
38 #define VK "k"
39 #else
40 #define VK
41 #endif
42
43 #ifdef CONFIG_IPW2200_DEBUG
44 #define VD "d"
45 #else
46 #define VD
47 #endif
48
49 #ifdef CONFIG_IPW2200_MONITOR
50 #define VM "m"
51 #else
52 #define VM
53 #endif
54
55 #ifdef CONFIG_IPW2200_PROMISCUOUS
56 #define VP "p"
57 #else
58 #define VP
59 #endif
60
61 #ifdef CONFIG_IPW2200_RADIOTAP
62 #define VR "r"
63 #else
64 #define VR
65 #endif
66
67 #ifdef CONFIG_IPW2200_QOS
68 #define VQ "q"
69 #else
70 #define VQ
71 #endif
72
73 #define IPW2200_VERSION "1.2.2" VK VD VM VP VR VQ
74 #define DRV_DESCRIPTION "Intel(R) PRO/Wireless 2200/2915 Network Driver"
75 #define DRV_COPYRIGHT   "Copyright(c) 2003-2006 Intel Corporation"
76 #define DRV_VERSION     IPW2200_VERSION
77
78 #define ETH_P_80211_STATS (ETH_P_80211_RAW + 1)
79
80 MODULE_DESCRIPTION(DRV_DESCRIPTION);
81 MODULE_VERSION(DRV_VERSION);
82 MODULE_AUTHOR(DRV_COPYRIGHT);
83 MODULE_LICENSE("GPL");
84
85 static int cmdlog = 0;
86 static int debug = 0;
87 static int channel = 0;
88 static int mode = 0;
89
90 static u32 ipw_debug_level;
91 static int associate = 1;
92 static int auto_create = 1;
93 static int led = 0;
94 static int disable = 0;
95 static int bt_coexist = 0;
96 static int hwcrypto = 0;
97 static int roaming = 1;
98 static const char ipw_modes[] = {
99         'a', 'b', 'g', '?'
100 };
101 static int antenna = CFG_SYS_ANTENNA_BOTH;
102
103 #ifdef CONFIG_IPW2200_PROMISCUOUS
104 static int rtap_iface = 0;     /* def: 0 -- do not create rtap interface */
105 #endif
106
107
108 #ifdef CONFIG_IPW2200_QOS
109 static int qos_enable = 0;
110 static int qos_burst_enable = 0;
111 static int qos_no_ack_mask = 0;
112 static int burst_duration_CCK = 0;
113 static int burst_duration_OFDM = 0;
114
115 static struct ieee80211_qos_parameters def_qos_parameters_OFDM = {
116         {QOS_TX0_CW_MIN_OFDM, QOS_TX1_CW_MIN_OFDM, QOS_TX2_CW_MIN_OFDM,
117          QOS_TX3_CW_MIN_OFDM},
118         {QOS_TX0_CW_MAX_OFDM, QOS_TX1_CW_MAX_OFDM, QOS_TX2_CW_MAX_OFDM,
119          QOS_TX3_CW_MAX_OFDM},
120         {QOS_TX0_AIFS, QOS_TX1_AIFS, QOS_TX2_AIFS, QOS_TX3_AIFS},
121         {QOS_TX0_ACM, QOS_TX1_ACM, QOS_TX2_ACM, QOS_TX3_ACM},
122         {QOS_TX0_TXOP_LIMIT_OFDM, QOS_TX1_TXOP_LIMIT_OFDM,
123          QOS_TX2_TXOP_LIMIT_OFDM, QOS_TX3_TXOP_LIMIT_OFDM}
124 };
125
126 static struct ieee80211_qos_parameters def_qos_parameters_CCK = {
127         {QOS_TX0_CW_MIN_CCK, QOS_TX1_CW_MIN_CCK, QOS_TX2_CW_MIN_CCK,
128          QOS_TX3_CW_MIN_CCK},
129         {QOS_TX0_CW_MAX_CCK, QOS_TX1_CW_MAX_CCK, QOS_TX2_CW_MAX_CCK,
130          QOS_TX3_CW_MAX_CCK},
131         {QOS_TX0_AIFS, QOS_TX1_AIFS, QOS_TX2_AIFS, QOS_TX3_AIFS},
132         {QOS_TX0_ACM, QOS_TX1_ACM, QOS_TX2_ACM, QOS_TX3_ACM},
133         {QOS_TX0_TXOP_LIMIT_CCK, QOS_TX1_TXOP_LIMIT_CCK, QOS_TX2_TXOP_LIMIT_CCK,
134          QOS_TX3_TXOP_LIMIT_CCK}
135 };
136
137 static struct ieee80211_qos_parameters def_parameters_OFDM = {
138         {DEF_TX0_CW_MIN_OFDM, DEF_TX1_CW_MIN_OFDM, DEF_TX2_CW_MIN_OFDM,
139          DEF_TX3_CW_MIN_OFDM},
140         {DEF_TX0_CW_MAX_OFDM, DEF_TX1_CW_MAX_OFDM, DEF_TX2_CW_MAX_OFDM,
141          DEF_TX3_CW_MAX_OFDM},
142         {DEF_TX0_AIFS, DEF_TX1_AIFS, DEF_TX2_AIFS, DEF_TX3_AIFS},
143         {DEF_TX0_ACM, DEF_TX1_ACM, DEF_TX2_ACM, DEF_TX3_ACM},
144         {DEF_TX0_TXOP_LIMIT_OFDM, DEF_TX1_TXOP_LIMIT_OFDM,
145          DEF_TX2_TXOP_LIMIT_OFDM, DEF_TX3_TXOP_LIMIT_OFDM}
146 };
147
148 static struct ieee80211_qos_parameters def_parameters_CCK = {
149         {DEF_TX0_CW_MIN_CCK, DEF_TX1_CW_MIN_CCK, DEF_TX2_CW_MIN_CCK,
150          DEF_TX3_CW_MIN_CCK},
151         {DEF_TX0_CW_MAX_CCK, DEF_TX1_CW_MAX_CCK, DEF_TX2_CW_MAX_CCK,
152          DEF_TX3_CW_MAX_CCK},
153         {DEF_TX0_AIFS, DEF_TX1_AIFS, DEF_TX2_AIFS, DEF_TX3_AIFS},
154         {DEF_TX0_ACM, DEF_TX1_ACM, DEF_TX2_ACM, DEF_TX3_ACM},
155         {DEF_TX0_TXOP_LIMIT_CCK, DEF_TX1_TXOP_LIMIT_CCK, DEF_TX2_TXOP_LIMIT_CCK,
156          DEF_TX3_TXOP_LIMIT_CCK}
157 };
158
159 static u8 qos_oui[QOS_OUI_LEN] = { 0x00, 0x50, 0xF2 };
160
161 static int from_priority_to_tx_queue[] = {
162         IPW_TX_QUEUE_1, IPW_TX_QUEUE_2, IPW_TX_QUEUE_2, IPW_TX_QUEUE_1,
163         IPW_TX_QUEUE_3, IPW_TX_QUEUE_3, IPW_TX_QUEUE_4, IPW_TX_QUEUE_4
164 };
165
166 static u32 ipw_qos_get_burst_duration(struct ipw_priv *priv);
167
168 static int ipw_send_qos_params_command(struct ipw_priv *priv, struct ieee80211_qos_parameters
169                                        *qos_param);
170 static int ipw_send_qos_info_command(struct ipw_priv *priv, struct ieee80211_qos_information_element
171                                      *qos_param);
172 #endif                          /* CONFIG_IPW2200_QOS */
173
174 static struct iw_statistics *ipw_get_wireless_stats(struct net_device *dev);
175 static void ipw_remove_current_network(struct ipw_priv *priv);
176 static void ipw_rx(struct ipw_priv *priv);
177 static int ipw_queue_tx_reclaim(struct ipw_priv *priv,
178                                 struct clx2_tx_queue *txq, int qindex);
179 static int ipw_queue_reset(struct ipw_priv *priv);
180
181 static int ipw_queue_tx_hcmd(struct ipw_priv *priv, int hcmd, void *buf,
182                              int len, int sync);
183
184 static void ipw_tx_queue_free(struct ipw_priv *);
185
186 static struct ipw_rx_queue *ipw_rx_queue_alloc(struct ipw_priv *);
187 static void ipw_rx_queue_free(struct ipw_priv *, struct ipw_rx_queue *);
188 static void ipw_rx_queue_replenish(void *);
189 static int ipw_up(struct ipw_priv *);
190 static void ipw_bg_up(struct work_struct *work);
191 static void ipw_down(struct ipw_priv *);
192 static void ipw_bg_down(struct work_struct *work);
193 static int ipw_config(struct ipw_priv *);
194 static int init_supported_rates(struct ipw_priv *priv,
195                                 struct ipw_supported_rates *prates);
196 static void ipw_set_hwcrypto_keys(struct ipw_priv *);
197 static void ipw_send_wep_keys(struct ipw_priv *, int);
198
199 static int snprint_line(char *buf, size_t count,
200                         const u8 * data, u32 len, u32 ofs)
201 {
202         int out, i, j, l;
203         char c;
204
205         out = snprintf(buf, count, "%08X", ofs);
206
207         for (l = 0, i = 0; i < 2; i++) {
208                 out += snprintf(buf + out, count - out, " ");
209                 for (j = 0; j < 8 && l < len; j++, l++)
210                         out += snprintf(buf + out, count - out, "%02X ",
211                                         data[(i * 8 + j)]);
212                 for (; j < 8; j++)
213                         out += snprintf(buf + out, count - out, "   ");
214         }
215
216         out += snprintf(buf + out, count - out, " ");
217         for (l = 0, i = 0; i < 2; i++) {
218                 out += snprintf(buf + out, count - out, " ");
219                 for (j = 0; j < 8 && l < len; j++, l++) {
220                         c = data[(i * 8 + j)];
221                         if (!isascii(c) || !isprint(c))
222                                 c = '.';
223
224                         out += snprintf(buf + out, count - out, "%c", c);
225                 }
226
227                 for (; j < 8; j++)
228                         out += snprintf(buf + out, count - out, " ");
229         }
230
231         return out;
232 }
233
234 static void printk_buf(int level, const u8 * data, u32 len)
235 {
236         char line[81];
237         u32 ofs = 0;
238         if (!(ipw_debug_level & level))
239                 return;
240
241         while (len) {
242                 snprint_line(line, sizeof(line), &data[ofs],
243                              min(len, 16U), ofs);
244                 printk(KERN_DEBUG "%s\n", line);
245                 ofs += 16;
246                 len -= min(len, 16U);
247         }
248 }
249
250 static int snprintk_buf(u8 * output, size_t size, const u8 * data, size_t len)
251 {
252         size_t out = size;
253         u32 ofs = 0;
254         int total = 0;
255
256         while (size && len) {
257                 out = snprint_line(output, size, &data[ofs],
258                                    min_t(size_t, len, 16U), ofs);
259
260                 ofs += 16;
261                 output += out;
262                 size -= out;
263                 len -= min_t(size_t, len, 16U);
264                 total += out;
265         }
266         return total;
267 }
268
269 /* alias for 32-bit indirect read (for SRAM/reg above 4K), with debug wrapper */
270 static u32 _ipw_read_reg32(struct ipw_priv *priv, u32 reg);
271 #define ipw_read_reg32(a, b) _ipw_read_reg32(a, b)
272
273 /* alias for 8-bit indirect read (for SRAM/reg above 4K), with debug wrapper */
274 static u8 _ipw_read_reg8(struct ipw_priv *ipw, u32 reg);
275 #define ipw_read_reg8(a, b) _ipw_read_reg8(a, b)
276
277 /* 8-bit indirect write (for SRAM/reg above 4K), with debug wrapper */
278 static void _ipw_write_reg8(struct ipw_priv *priv, u32 reg, u8 value);
279 static inline void ipw_write_reg8(struct ipw_priv *a, u32 b, u8 c)
280 {
281         IPW_DEBUG_IO("%s %d: write_indirect8(0x%08X, 0x%08X)\n", __FILE__,
282                      __LINE__, (u32) (b), (u32) (c));
283         _ipw_write_reg8(a, b, c);
284 }
285
286 /* 16-bit indirect write (for SRAM/reg above 4K), with debug wrapper */
287 static void _ipw_write_reg16(struct ipw_priv *priv, u32 reg, u16 value);
288 static inline void ipw_write_reg16(struct ipw_priv *a, u32 b, u16 c)
289 {
290         IPW_DEBUG_IO("%s %d: write_indirect16(0x%08X, 0x%08X)\n", __FILE__,
291                      __LINE__, (u32) (b), (u32) (c));
292         _ipw_write_reg16(a, b, c);
293 }
294
295 /* 32-bit indirect write (for SRAM/reg above 4K), with debug wrapper */
296 static void _ipw_write_reg32(struct ipw_priv *priv, u32 reg, u32 value);
297 static inline void ipw_write_reg32(struct ipw_priv *a, u32 b, u32 c)
298 {
299         IPW_DEBUG_IO("%s %d: write_indirect32(0x%08X, 0x%08X)\n", __FILE__,
300                      __LINE__, (u32) (b), (u32) (c));
301         _ipw_write_reg32(a, b, c);
302 }
303
304 /* 8-bit direct write (low 4K) */
305 #define _ipw_write8(ipw, ofs, val) writeb((val), (ipw)->hw_base + (ofs))
306
307 /* 8-bit direct write (for low 4K of SRAM/regs), with debug wrapper */
308 #define ipw_write8(ipw, ofs, val) \
309  IPW_DEBUG_IO("%s %d: write_direct8(0x%08X, 0x%08X)\n", __FILE__, __LINE__, (u32)(ofs), (u32)(val)); \
310  _ipw_write8(ipw, ofs, val)
311
312 /* 16-bit direct write (low 4K) */
313 #define _ipw_write16(ipw, ofs, val) writew((val), (ipw)->hw_base + (ofs))
314
315 /* 16-bit direct write (for low 4K of SRAM/regs), with debug wrapper */
316 #define ipw_write16(ipw, ofs, val) \
317  IPW_DEBUG_IO("%s %d: write_direct16(0x%08X, 0x%08X)\n", __FILE__, __LINE__, (u32)(ofs), (u32)(val)); \
318  _ipw_write16(ipw, ofs, val)
319
320 /* 32-bit direct write (low 4K) */
321 #define _ipw_write32(ipw, ofs, val) writel((val), (ipw)->hw_base + (ofs))
322
323 /* 32-bit direct write (for low 4K of SRAM/regs), with debug wrapper */
324 #define ipw_write32(ipw, ofs, val) \
325  IPW_DEBUG_IO("%s %d: write_direct32(0x%08X, 0x%08X)\n", __FILE__, __LINE__, (u32)(ofs), (u32)(val)); \
326  _ipw_write32(ipw, ofs, val)
327
328 /* 8-bit direct read (low 4K) */
329 #define _ipw_read8(ipw, ofs) readb((ipw)->hw_base + (ofs))
330
331 /* 8-bit direct read (low 4K), with debug wrapper */
332 static inline u8 __ipw_read8(char *f, u32 l, struct ipw_priv *ipw, u32 ofs)
333 {
334         IPW_DEBUG_IO("%s %d: read_direct8(0x%08X)\n", f, l, (u32) (ofs));
335         return _ipw_read8(ipw, ofs);
336 }
337
338 /* alias to 8-bit direct read (low 4K of SRAM/regs), with debug wrapper */
339 #define ipw_read8(ipw, ofs) __ipw_read8(__FILE__, __LINE__, ipw, ofs)
340
341 /* 16-bit direct read (low 4K) */
342 #define _ipw_read16(ipw, ofs) readw((ipw)->hw_base + (ofs))
343
344 /* 16-bit direct read (low 4K), with debug wrapper */
345 static inline u16 __ipw_read16(char *f, u32 l, struct ipw_priv *ipw, u32 ofs)
346 {
347         IPW_DEBUG_IO("%s %d: read_direct16(0x%08X)\n", f, l, (u32) (ofs));
348         return _ipw_read16(ipw, ofs);
349 }
350
351 /* alias to 16-bit direct read (low 4K of SRAM/regs), with debug wrapper */
352 #define ipw_read16(ipw, ofs) __ipw_read16(__FILE__, __LINE__, ipw, ofs)
353
354 /* 32-bit direct read (low 4K) */
355 #define _ipw_read32(ipw, ofs) readl((ipw)->hw_base + (ofs))
356
357 /* 32-bit direct read (low 4K), with debug wrapper */
358 static inline u32 __ipw_read32(char *f, u32 l, struct ipw_priv *ipw, u32 ofs)
359 {
360         IPW_DEBUG_IO("%s %d: read_direct32(0x%08X)\n", f, l, (u32) (ofs));
361         return _ipw_read32(ipw, ofs);
362 }
363
364 /* alias to 32-bit direct read (low 4K of SRAM/regs), with debug wrapper */
365 #define ipw_read32(ipw, ofs) __ipw_read32(__FILE__, __LINE__, ipw, ofs)
366
367 /* multi-byte read (above 4K), with debug wrapper */
368 static void _ipw_read_indirect(struct ipw_priv *, u32, u8 *, int);
369 static inline void __ipw_read_indirect(const char *f, int l,
370                                        struct ipw_priv *a, u32 b, u8 * c, int d)
371 {
372         IPW_DEBUG_IO("%s %d: read_indirect(0x%08X) %d bytes\n", f, l, (u32) (b),
373                      d);
374         _ipw_read_indirect(a, b, c, d);
375 }
376
377 /* alias to multi-byte read (SRAM/regs above 4K), with debug wrapper */
378 #define ipw_read_indirect(a, b, c, d) __ipw_read_indirect(__FILE__, __LINE__, a, b, c, d)
379
380 /* alias to multi-byte read (SRAM/regs above 4K), with debug wrapper */
381 static void _ipw_write_indirect(struct ipw_priv *priv, u32 addr, u8 * data,
382                                 int num);
383 #define ipw_write_indirect(a, b, c, d) \
384         IPW_DEBUG_IO("%s %d: write_indirect(0x%08X) %d bytes\n", __FILE__, __LINE__, (u32)(b), d); \
385         _ipw_write_indirect(a, b, c, d)
386
387 /* 32-bit indirect write (above 4K) */
388 static void _ipw_write_reg32(struct ipw_priv *priv, u32 reg, u32 value)
389 {
390         IPW_DEBUG_IO(" %p : reg = 0x%8X : value = 0x%8X\n", priv, reg, value);
391         _ipw_write32(priv, IPW_INDIRECT_ADDR, reg);
392         _ipw_write32(priv, IPW_INDIRECT_DATA, value);
393 }
394
395 /* 8-bit indirect write (above 4K) */
396 static void _ipw_write_reg8(struct ipw_priv *priv, u32 reg, u8 value)
397 {
398         u32 aligned_addr = reg & IPW_INDIRECT_ADDR_MASK;        /* dword align */
399         u32 dif_len = reg - aligned_addr;
400
401         IPW_DEBUG_IO(" reg = 0x%8X : value = 0x%8X\n", reg, value);
402         _ipw_write32(priv, IPW_INDIRECT_ADDR, aligned_addr);
403         _ipw_write8(priv, IPW_INDIRECT_DATA + dif_len, value);
404 }
405
406 /* 16-bit indirect write (above 4K) */
407 static void _ipw_write_reg16(struct ipw_priv *priv, u32 reg, u16 value)
408 {
409         u32 aligned_addr = reg & IPW_INDIRECT_ADDR_MASK;        /* dword align */
410         u32 dif_len = (reg - aligned_addr) & (~0x1ul);
411
412         IPW_DEBUG_IO(" reg = 0x%8X : value = 0x%8X\n", reg, value);
413         _ipw_write32(priv, IPW_INDIRECT_ADDR, aligned_addr);
414         _ipw_write16(priv, IPW_INDIRECT_DATA + dif_len, value);
415 }
416
417 /* 8-bit indirect read (above 4K) */
418 static u8 _ipw_read_reg8(struct ipw_priv *priv, u32 reg)
419 {
420         u32 word;
421         _ipw_write32(priv, IPW_INDIRECT_ADDR, reg & IPW_INDIRECT_ADDR_MASK);
422         IPW_DEBUG_IO(" reg = 0x%8X : \n", reg);
423         word = _ipw_read32(priv, IPW_INDIRECT_DATA);
424         return (word >> ((reg & 0x3) * 8)) & 0xff;
425 }
426
427 /* 32-bit indirect read (above 4K) */
428 static u32 _ipw_read_reg32(struct ipw_priv *priv, u32 reg)
429 {
430         u32 value;
431
432         IPW_DEBUG_IO("%p : reg = 0x%08x\n", priv, reg);
433
434         _ipw_write32(priv, IPW_INDIRECT_ADDR, reg);
435         value = _ipw_read32(priv, IPW_INDIRECT_DATA);
436         IPW_DEBUG_IO(" reg = 0x%4X : value = 0x%4x \n", reg, value);
437         return value;
438 }
439
440 /* General purpose, no alignment requirement, iterative (multi-byte) read, */
441 /*    for area above 1st 4K of SRAM/reg space */
442 static void _ipw_read_indirect(struct ipw_priv *priv, u32 addr, u8 * buf,
443                                int num)
444 {
445         u32 aligned_addr = addr & IPW_INDIRECT_ADDR_MASK;       /* dword align */
446         u32 dif_len = addr - aligned_addr;
447         u32 i;
448
449         IPW_DEBUG_IO("addr = %i, buf = %p, num = %i\n", addr, buf, num);
450
451         if (num <= 0) {
452                 return;
453         }
454
455         /* Read the first dword (or portion) byte by byte */
456         if (unlikely(dif_len)) {
457                 _ipw_write32(priv, IPW_INDIRECT_ADDR, aligned_addr);
458                 /* Start reading at aligned_addr + dif_len */
459                 for (i = dif_len; ((i < 4) && (num > 0)); i++, num--)
460                         *buf++ = _ipw_read8(priv, IPW_INDIRECT_DATA + i);
461                 aligned_addr += 4;
462         }
463
464         /* Read all of the middle dwords as dwords, with auto-increment */
465         _ipw_write32(priv, IPW_AUTOINC_ADDR, aligned_addr);
466         for (; num >= 4; buf += 4, aligned_addr += 4, num -= 4)
467                 *(u32 *) buf = _ipw_read32(priv, IPW_AUTOINC_DATA);
468
469         /* Read the last dword (or portion) byte by byte */
470         if (unlikely(num)) {
471                 _ipw_write32(priv, IPW_INDIRECT_ADDR, aligned_addr);
472                 for (i = 0; num > 0; i++, num--)
473                         *buf++ = ipw_read8(priv, IPW_INDIRECT_DATA + i);
474         }
475 }
476
477 /* General purpose, no alignment requirement, iterative (multi-byte) write, */
478 /*    for area above 1st 4K of SRAM/reg space */
479 static void _ipw_write_indirect(struct ipw_priv *priv, u32 addr, u8 * buf,
480                                 int num)
481 {
482         u32 aligned_addr = addr & IPW_INDIRECT_ADDR_MASK;       /* dword align */
483         u32 dif_len = addr - aligned_addr;
484         u32 i;
485
486         IPW_DEBUG_IO("addr = %i, buf = %p, num = %i\n", addr, buf, num);
487
488         if (num <= 0) {
489                 return;
490         }
491
492         /* Write the first dword (or portion) byte by byte */
493         if (unlikely(dif_len)) {
494                 _ipw_write32(priv, IPW_INDIRECT_ADDR, aligned_addr);
495                 /* Start writing at aligned_addr + dif_len */
496                 for (i = dif_len; ((i < 4) && (num > 0)); i++, num--, buf++)
497                         _ipw_write8(priv, IPW_INDIRECT_DATA + i, *buf);
498                 aligned_addr += 4;
499         }
500
501         /* Write all of the middle dwords as dwords, with auto-increment */
502         _ipw_write32(priv, IPW_AUTOINC_ADDR, aligned_addr);
503         for (; num >= 4; buf += 4, aligned_addr += 4, num -= 4)
504                 _ipw_write32(priv, IPW_AUTOINC_DATA, *(u32 *) buf);
505
506         /* Write the last dword (or portion) byte by byte */
507         if (unlikely(num)) {
508                 _ipw_write32(priv, IPW_INDIRECT_ADDR, aligned_addr);
509                 for (i = 0; num > 0; i++, num--, buf++)
510                         _ipw_write8(priv, IPW_INDIRECT_DATA + i, *buf);
511         }
512 }
513
514 /* General purpose, no alignment requirement, iterative (multi-byte) write, */
515 /*    for 1st 4K of SRAM/regs space */
516 static void ipw_write_direct(struct ipw_priv *priv, u32 addr, void *buf,
517                              int num)
518 {
519         memcpy_toio((priv->hw_base + addr), buf, num);
520 }
521
522 /* Set bit(s) in low 4K of SRAM/regs */
523 static inline void ipw_set_bit(struct ipw_priv *priv, u32 reg, u32 mask)
524 {
525         ipw_write32(priv, reg, ipw_read32(priv, reg) | mask);
526 }
527
528 /* Clear bit(s) in low 4K of SRAM/regs */
529 static inline void ipw_clear_bit(struct ipw_priv *priv, u32 reg, u32 mask)
530 {
531         ipw_write32(priv, reg, ipw_read32(priv, reg) & ~mask);
532 }
533
534 static inline void __ipw_enable_interrupts(struct ipw_priv *priv)
535 {
536         if (priv->status & STATUS_INT_ENABLED)
537                 return;
538         priv->status |= STATUS_INT_ENABLED;
539         ipw_write32(priv, IPW_INTA_MASK_R, IPW_INTA_MASK_ALL);
540 }
541
542 static inline void __ipw_disable_interrupts(struct ipw_priv *priv)
543 {
544         if (!(priv->status & STATUS_INT_ENABLED))
545                 return;
546         priv->status &= ~STATUS_INT_ENABLED;
547         ipw_write32(priv, IPW_INTA_MASK_R, ~IPW_INTA_MASK_ALL);
548 }
549
550 static inline void ipw_enable_interrupts(struct ipw_priv *priv)
551 {
552         unsigned long flags;
553
554         spin_lock_irqsave(&priv->irq_lock, flags);
555         __ipw_enable_interrupts(priv);
556         spin_unlock_irqrestore(&priv->irq_lock, flags);
557 }
558
559 static inline void ipw_disable_interrupts(struct ipw_priv *priv)
560 {
561         unsigned long flags;
562
563         spin_lock_irqsave(&priv->irq_lock, flags);
564         __ipw_disable_interrupts(priv);
565         spin_unlock_irqrestore(&priv->irq_lock, flags);
566 }
567
568 static char *ipw_error_desc(u32 val)
569 {
570         switch (val) {
571         case IPW_FW_ERROR_OK:
572                 return "ERROR_OK";
573         case IPW_FW_ERROR_FAIL:
574                 return "ERROR_FAIL";
575         case IPW_FW_ERROR_MEMORY_UNDERFLOW:
576                 return "MEMORY_UNDERFLOW";
577         case IPW_FW_ERROR_MEMORY_OVERFLOW:
578                 return "MEMORY_OVERFLOW";
579         case IPW_FW_ERROR_BAD_PARAM:
580                 return "BAD_PARAM";
581         case IPW_FW_ERROR_BAD_CHECKSUM:
582                 return "BAD_CHECKSUM";
583         case IPW_FW_ERROR_NMI_INTERRUPT:
584                 return "NMI_INTERRUPT";
585         case IPW_FW_ERROR_BAD_DATABASE:
586                 return "BAD_DATABASE";
587         case IPW_FW_ERROR_ALLOC_FAIL:
588                 return "ALLOC_FAIL";
589         case IPW_FW_ERROR_DMA_UNDERRUN:
590                 return "DMA_UNDERRUN";
591         case IPW_FW_ERROR_DMA_STATUS:
592                 return "DMA_STATUS";
593         case IPW_FW_ERROR_DINO_ERROR:
594                 return "DINO_ERROR";
595         case IPW_FW_ERROR_EEPROM_ERROR:
596                 return "EEPROM_ERROR";
597         case IPW_FW_ERROR_SYSASSERT:
598                 return "SYSASSERT";
599         case IPW_FW_ERROR_FATAL_ERROR:
600                 return "FATAL_ERROR";
601         default:
602                 return "UNKNOWN_ERROR";
603         }
604 }
605
606 static void ipw_dump_error_log(struct ipw_priv *priv,
607                                struct ipw_fw_error *error)
608 {
609         u32 i;
610
611         if (!error) {
612                 IPW_ERROR("Error allocating and capturing error log.  "
613                           "Nothing to dump.\n");
614                 return;
615         }
616
617         IPW_ERROR("Start IPW Error Log Dump:\n");
618         IPW_ERROR("Status: 0x%08X, Config: %08X\n",
619                   error->status, error->config);
620
621         for (i = 0; i < error->elem_len; i++)
622                 IPW_ERROR("%s %i 0x%08x  0x%08x  0x%08x  0x%08x  0x%08x\n",
623                           ipw_error_desc(error->elem[i].desc),
624                           error->elem[i].time,
625                           error->elem[i].blink1,
626                           error->elem[i].blink2,
627                           error->elem[i].link1,
628                           error->elem[i].link2, error->elem[i].data);
629         for (i = 0; i < error->log_len; i++)
630                 IPW_ERROR("%i\t0x%08x\t%i\n",
631                           error->log[i].time,
632                           error->log[i].data, error->log[i].event);
633 }
634
635 static inline int ipw_is_init(struct ipw_priv *priv)
636 {
637         return (priv->status & STATUS_INIT) ? 1 : 0;
638 }
639
640 static int ipw_get_ordinal(struct ipw_priv *priv, u32 ord, void *val, u32 * len)
641 {
642         u32 addr, field_info, field_len, field_count, total_len;
643
644         IPW_DEBUG_ORD("ordinal = %i\n", ord);
645
646         if (!priv || !val || !len) {
647                 IPW_DEBUG_ORD("Invalid argument\n");
648                 return -EINVAL;
649         }
650
651         /* verify device ordinal tables have been initialized */
652         if (!priv->table0_addr || !priv->table1_addr || !priv->table2_addr) {
653                 IPW_DEBUG_ORD("Access ordinals before initialization\n");
654                 return -EINVAL;
655         }
656
657         switch (IPW_ORD_TABLE_ID_MASK & ord) {
658         case IPW_ORD_TABLE_0_MASK:
659                 /*
660                  * TABLE 0: Direct access to a table of 32 bit values
661                  *
662                  * This is a very simple table with the data directly
663                  * read from the table
664                  */
665
666                 /* remove the table id from the ordinal */
667                 ord &= IPW_ORD_TABLE_VALUE_MASK;
668
669                 /* boundary check */
670                 if (ord > priv->table0_len) {
671                         IPW_DEBUG_ORD("ordinal value (%i) longer then "
672                                       "max (%i)\n", ord, priv->table0_len);
673                         return -EINVAL;
674                 }
675
676                 /* verify we have enough room to store the value */
677                 if (*len < sizeof(u32)) {
678                         IPW_DEBUG_ORD("ordinal buffer length too small, "
679                                       "need %zd\n", sizeof(u32));
680                         return -EINVAL;
681                 }
682
683                 IPW_DEBUG_ORD("Reading TABLE0[%i] from offset 0x%08x\n",
684                               ord, priv->table0_addr + (ord << 2));
685
686                 *len = sizeof(u32);
687                 ord <<= 2;
688                 *((u32 *) val) = ipw_read32(priv, priv->table0_addr + ord);
689                 break;
690
691         case IPW_ORD_TABLE_1_MASK:
692                 /*
693                  * TABLE 1: Indirect access to a table of 32 bit values
694                  *
695                  * This is a fairly large table of u32 values each
696                  * representing starting addr for the data (which is
697                  * also a u32)
698                  */
699
700                 /* remove the table id from the ordinal */
701                 ord &= IPW_ORD_TABLE_VALUE_MASK;
702
703                 /* boundary check */
704                 if (ord > priv->table1_len) {
705                         IPW_DEBUG_ORD("ordinal value too long\n");
706                         return -EINVAL;
707                 }
708
709                 /* verify we have enough room to store the value */
710                 if (*len < sizeof(u32)) {
711                         IPW_DEBUG_ORD("ordinal buffer length too small, "
712                                       "need %zd\n", sizeof(u32));
713                         return -EINVAL;
714                 }
715
716                 *((u32 *) val) =
717                     ipw_read_reg32(priv, (priv->table1_addr + (ord << 2)));
718                 *len = sizeof(u32);
719                 break;
720
721         case IPW_ORD_TABLE_2_MASK:
722                 /*
723                  * TABLE 2: Indirect access to a table of variable sized values
724                  *
725                  * This table consist of six values, each containing
726                  *     - dword containing the starting offset of the data
727                  *     - dword containing the lengh in the first 16bits
728                  *       and the count in the second 16bits
729                  */
730
731                 /* remove the table id from the ordinal */
732                 ord &= IPW_ORD_TABLE_VALUE_MASK;
733
734                 /* boundary check */
735                 if (ord > priv->table2_len) {
736                         IPW_DEBUG_ORD("ordinal value too long\n");
737                         return -EINVAL;
738                 }
739
740                 /* get the address of statistic */
741                 addr = ipw_read_reg32(priv, priv->table2_addr + (ord << 3));
742
743                 /* get the second DW of statistics ;
744                  * two 16-bit words - first is length, second is count */
745                 field_info =
746                     ipw_read_reg32(priv,
747                                    priv->table2_addr + (ord << 3) +
748                                    sizeof(u32));
749
750                 /* get each entry length */
751                 field_len = *((u16 *) & field_info);
752
753                 /* get number of entries */
754                 field_count = *(((u16 *) & field_info) + 1);
755
756                 /* abort if not enought memory */
757                 total_len = field_len * field_count;
758                 if (total_len > *len) {
759                         *len = total_len;
760                         return -EINVAL;
761                 }
762
763                 *len = total_len;
764                 if (!total_len)
765                         return 0;
766
767                 IPW_DEBUG_ORD("addr = 0x%08x, total_len = %i, "
768                               "field_info = 0x%08x\n",
769                               addr, total_len, field_info);
770                 ipw_read_indirect(priv, addr, val, total_len);
771                 break;
772
773         default:
774                 IPW_DEBUG_ORD("Invalid ordinal!\n");
775                 return -EINVAL;
776
777         }
778
779         return 0;
780 }
781
782 static void ipw_init_ordinals(struct ipw_priv *priv)
783 {
784         priv->table0_addr = IPW_ORDINALS_TABLE_LOWER;
785         priv->table0_len = ipw_read32(priv, priv->table0_addr);
786
787         IPW_DEBUG_ORD("table 0 offset at 0x%08x, len = %i\n",
788                       priv->table0_addr, priv->table0_len);
789
790         priv->table1_addr = ipw_read32(priv, IPW_ORDINALS_TABLE_1);
791         priv->table1_len = ipw_read_reg32(priv, priv->table1_addr);
792
793         IPW_DEBUG_ORD("table 1 offset at 0x%08x, len = %i\n",
794                       priv->table1_addr, priv->table1_len);
795
796         priv->table2_addr = ipw_read32(priv, IPW_ORDINALS_TABLE_2);
797         priv->table2_len = ipw_read_reg32(priv, priv->table2_addr);
798         priv->table2_len &= 0x0000ffff; /* use first two bytes */
799
800         IPW_DEBUG_ORD("table 2 offset at 0x%08x, len = %i\n",
801                       priv->table2_addr, priv->table2_len);
802
803 }
804
805 static u32 ipw_register_toggle(u32 reg)
806 {
807         reg &= ~IPW_START_STANDBY;
808         if (reg & IPW_GATE_ODMA)
809                 reg &= ~IPW_GATE_ODMA;
810         if (reg & IPW_GATE_IDMA)
811                 reg &= ~IPW_GATE_IDMA;
812         if (reg & IPW_GATE_ADMA)
813                 reg &= ~IPW_GATE_ADMA;
814         return reg;
815 }
816
817 /*
818  * LED behavior:
819  * - On radio ON, turn on any LEDs that require to be on during start
820  * - On initialization, start unassociated blink
821  * - On association, disable unassociated blink
822  * - On disassociation, start unassociated blink
823  * - On radio OFF, turn off any LEDs started during radio on
824  *
825  */
826 #define LD_TIME_LINK_ON msecs_to_jiffies(300)
827 #define LD_TIME_LINK_OFF msecs_to_jiffies(2700)
828 #define LD_TIME_ACT_ON msecs_to_jiffies(250)
829
830 static void ipw_led_link_on(struct ipw_priv *priv)
831 {
832         unsigned long flags;
833         u32 led;
834
835         /* If configured to not use LEDs, or nic_type is 1,
836          * then we don't toggle a LINK led */
837         if (priv->config & CFG_NO_LED || priv->nic_type == EEPROM_NIC_TYPE_1)
838                 return;
839
840         spin_lock_irqsave(&priv->lock, flags);
841
842         if (!(priv->status & STATUS_RF_KILL_MASK) &&
843             !(priv->status & STATUS_LED_LINK_ON)) {
844                 IPW_DEBUG_LED("Link LED On\n");
845                 led = ipw_read_reg32(priv, IPW_EVENT_REG);
846                 led |= priv->led_association_on;
847
848                 led = ipw_register_toggle(led);
849
850                 IPW_DEBUG_LED("Reg: 0x%08X\n", led);
851                 ipw_write_reg32(priv, IPW_EVENT_REG, led);
852
853                 priv->status |= STATUS_LED_LINK_ON;
854
855                 /* If we aren't associated, schedule turning the LED off */
856                 if (!(priv->status & STATUS_ASSOCIATED))
857                         queue_delayed_work(priv->workqueue,
858                                            &priv->led_link_off,
859                                            LD_TIME_LINK_ON);
860         }
861
862         spin_unlock_irqrestore(&priv->lock, flags);
863 }
864
865 static void ipw_bg_led_link_on(struct work_struct *work)
866 {
867         struct ipw_priv *priv =
868                 container_of(work, struct ipw_priv, led_link_on.work);
869         mutex_lock(&priv->mutex);
870         ipw_led_link_on(priv);
871         mutex_unlock(&priv->mutex);
872 }
873
874 static void ipw_led_link_off(struct ipw_priv *priv)
875 {
876         unsigned long flags;
877         u32 led;
878
879         /* If configured not to use LEDs, or nic type is 1,
880          * then we don't goggle the LINK led. */
881         if (priv->config & CFG_NO_LED || priv->nic_type == EEPROM_NIC_TYPE_1)
882                 return;
883
884         spin_lock_irqsave(&priv->lock, flags);
885
886         if (priv->status & STATUS_LED_LINK_ON) {
887                 led = ipw_read_reg32(priv, IPW_EVENT_REG);
888                 led &= priv->led_association_off;
889                 led = ipw_register_toggle(led);
890
891                 IPW_DEBUG_LED("Reg: 0x%08X\n", led);
892                 ipw_write_reg32(priv, IPW_EVENT_REG, led);
893
894                 IPW_DEBUG_LED("Link LED Off\n");
895
896                 priv->status &= ~STATUS_LED_LINK_ON;
897
898                 /* If we aren't associated and the radio is on, schedule
899                  * turning the LED on (blink while unassociated) */
900                 if (!(priv->status & STATUS_RF_KILL_MASK) &&
901                     !(priv->status & STATUS_ASSOCIATED))
902                         queue_delayed_work(priv->workqueue, &priv->led_link_on,
903                                            LD_TIME_LINK_OFF);
904
905         }
906
907         spin_unlock_irqrestore(&priv->lock, flags);
908 }
909
910 static void ipw_bg_led_link_off(struct work_struct *work)
911 {
912         struct ipw_priv *priv =
913                 container_of(work, struct ipw_priv, led_link_off.work);
914         mutex_lock(&priv->mutex);
915         ipw_led_link_off(priv);
916         mutex_unlock(&priv->mutex);
917 }
918
919 static void __ipw_led_activity_on(struct ipw_priv *priv)
920 {
921         u32 led;
922
923         if (priv->config & CFG_NO_LED)
924                 return;
925
926         if (priv->status & STATUS_RF_KILL_MASK)
927                 return;
928
929         if (!(priv->status & STATUS_LED_ACT_ON)) {
930                 led = ipw_read_reg32(priv, IPW_EVENT_REG);
931                 led |= priv->led_activity_on;
932
933                 led = ipw_register_toggle(led);
934
935                 IPW_DEBUG_LED("Reg: 0x%08X\n", led);
936                 ipw_write_reg32(priv, IPW_EVENT_REG, led);
937
938                 IPW_DEBUG_LED("Activity LED On\n");
939
940                 priv->status |= STATUS_LED_ACT_ON;
941
942                 cancel_delayed_work(&priv->led_act_off);
943                 queue_delayed_work(priv->workqueue, &priv->led_act_off,
944                                    LD_TIME_ACT_ON);
945         } else {
946                 /* Reschedule LED off for full time period */
947                 cancel_delayed_work(&priv->led_act_off);
948                 queue_delayed_work(priv->workqueue, &priv->led_act_off,
949                                    LD_TIME_ACT_ON);
950         }
951 }
952
953 #if 0
954 void ipw_led_activity_on(struct ipw_priv *priv)
955 {
956         unsigned long flags;
957         spin_lock_irqsave(&priv->lock, flags);
958         __ipw_led_activity_on(priv);
959         spin_unlock_irqrestore(&priv->lock, flags);
960 }
961 #endif  /*  0  */
962
963 static void ipw_led_activity_off(struct ipw_priv *priv)
964 {
965         unsigned long flags;
966         u32 led;
967
968         if (priv->config & CFG_NO_LED)
969                 return;
970
971         spin_lock_irqsave(&priv->lock, flags);
972
973         if (priv->status & STATUS_LED_ACT_ON) {
974                 led = ipw_read_reg32(priv, IPW_EVENT_REG);
975                 led &= priv->led_activity_off;
976
977                 led = ipw_register_toggle(led);
978
979                 IPW_DEBUG_LED("Reg: 0x%08X\n", led);
980                 ipw_write_reg32(priv, IPW_EVENT_REG, led);
981
982                 IPW_DEBUG_LED("Activity LED Off\n");
983
984                 priv->status &= ~STATUS_LED_ACT_ON;
985         }
986
987         spin_unlock_irqrestore(&priv->lock, flags);
988 }
989
990 static void ipw_bg_led_activity_off(struct work_struct *work)
991 {
992         struct ipw_priv *priv =
993                 container_of(work, struct ipw_priv, led_act_off.work);
994         mutex_lock(&priv->mutex);
995         ipw_led_activity_off(priv);
996         mutex_unlock(&priv->mutex);
997 }
998
999 static void ipw_led_band_on(struct ipw_priv *priv)
1000 {
1001         unsigned long flags;
1002         u32 led;
1003
1004         /* Only nic type 1 supports mode LEDs */
1005         if (priv->config & CFG_NO_LED ||
1006             priv->nic_type != EEPROM_NIC_TYPE_1 || !priv->assoc_network)
1007                 return;
1008
1009         spin_lock_irqsave(&priv->lock, flags);
1010
1011         led = ipw_read_reg32(priv, IPW_EVENT_REG);
1012         if (priv->assoc_network->mode == IEEE_A) {
1013                 led |= priv->led_ofdm_on;
1014                 led &= priv->led_association_off;
1015                 IPW_DEBUG_LED("Mode LED On: 802.11a\n");
1016         } else if (priv->assoc_network->mode == IEEE_G) {
1017                 led |= priv->led_ofdm_on;
1018                 led |= priv->led_association_on;
1019                 IPW_DEBUG_LED("Mode LED On: 802.11g\n");
1020         } else {
1021                 led &= priv->led_ofdm_off;
1022                 led |= priv->led_association_on;
1023                 IPW_DEBUG_LED("Mode LED On: 802.11b\n");
1024         }
1025
1026         led = ipw_register_toggle(led);
1027
1028         IPW_DEBUG_LED("Reg: 0x%08X\n", led);
1029         ipw_write_reg32(priv, IPW_EVENT_REG, led);
1030
1031         spin_unlock_irqrestore(&priv->lock, flags);
1032 }
1033
1034 static void ipw_led_band_off(struct ipw_priv *priv)
1035 {
1036         unsigned long flags;
1037         u32 led;
1038
1039         /* Only nic type 1 supports mode LEDs */
1040         if (priv->config & CFG_NO_LED || priv->nic_type != EEPROM_NIC_TYPE_1)
1041                 return;
1042
1043         spin_lock_irqsave(&priv->lock, flags);
1044
1045         led = ipw_read_reg32(priv, IPW_EVENT_REG);
1046         led &= priv->led_ofdm_off;
1047         led &= priv->led_association_off;
1048
1049         led = ipw_register_toggle(led);
1050
1051         IPW_DEBUG_LED("Reg: 0x%08X\n", led);
1052         ipw_write_reg32(priv, IPW_EVENT_REG, led);
1053
1054         spin_unlock_irqrestore(&priv->lock, flags);
1055 }
1056
1057 static void ipw_led_radio_on(struct ipw_priv *priv)
1058 {
1059         ipw_led_link_on(priv);
1060 }
1061
1062 static void ipw_led_radio_off(struct ipw_priv *priv)
1063 {
1064         ipw_led_activity_off(priv);
1065         ipw_led_link_off(priv);
1066 }
1067
1068 static void ipw_led_link_up(struct ipw_priv *priv)
1069 {
1070         /* Set the Link Led on for all nic types */
1071         ipw_led_link_on(priv);
1072 }
1073
1074 static void ipw_led_link_down(struct ipw_priv *priv)
1075 {
1076         ipw_led_activity_off(priv);
1077         ipw_led_link_off(priv);
1078
1079         if (priv->status & STATUS_RF_KILL_MASK)
1080                 ipw_led_radio_off(priv);
1081 }
1082
1083 static void ipw_led_init(struct ipw_priv *priv)
1084 {
1085         priv->nic_type = priv->eeprom[EEPROM_NIC_TYPE];
1086
1087         /* Set the default PINs for the link and activity leds */
1088         priv->led_activity_on = IPW_ACTIVITY_LED;
1089         priv->led_activity_off = ~(IPW_ACTIVITY_LED);
1090
1091         priv->led_association_on = IPW_ASSOCIATED_LED;
1092         priv->led_association_off = ~(IPW_ASSOCIATED_LED);
1093
1094         /* Set the default PINs for the OFDM leds */
1095         priv->led_ofdm_on = IPW_OFDM_LED;
1096         priv->led_ofdm_off = ~(IPW_OFDM_LED);
1097
1098         switch (priv->nic_type) {
1099         case EEPROM_NIC_TYPE_1:
1100                 /* In this NIC type, the LEDs are reversed.... */
1101                 priv->led_activity_on = IPW_ASSOCIATED_LED;
1102                 priv->led_activity_off = ~(IPW_ASSOCIATED_LED);
1103                 priv->led_association_on = IPW_ACTIVITY_LED;
1104                 priv->led_association_off = ~(IPW_ACTIVITY_LED);
1105
1106                 if (!(priv->config & CFG_NO_LED))
1107                         ipw_led_band_on(priv);
1108
1109                 /* And we don't blink link LEDs for this nic, so
1110                  * just return here */
1111                 return;
1112
1113         case EEPROM_NIC_TYPE_3:
1114         case EEPROM_NIC_TYPE_2:
1115         case EEPROM_NIC_TYPE_4:
1116         case EEPROM_NIC_TYPE_0:
1117                 break;
1118
1119         default:
1120                 IPW_DEBUG_INFO("Unknown NIC type from EEPROM: %d\n",
1121                                priv->nic_type);
1122                 priv->nic_type = EEPROM_NIC_TYPE_0;
1123                 break;
1124         }
1125
1126         if (!(priv->config & CFG_NO_LED)) {
1127                 if (priv->status & STATUS_ASSOCIATED)
1128                         ipw_led_link_on(priv);
1129                 else
1130                         ipw_led_link_off(priv);
1131         }
1132 }
1133
1134 static void ipw_led_shutdown(struct ipw_priv *priv)
1135 {
1136         ipw_led_activity_off(priv);
1137         ipw_led_link_off(priv);
1138         ipw_led_band_off(priv);
1139         cancel_delayed_work(&priv->led_link_on);
1140         cancel_delayed_work(&priv->led_link_off);
1141         cancel_delayed_work(&priv->led_act_off);
1142 }
1143
1144 /*
1145  * The following adds a new attribute to the sysfs representation
1146  * of this device driver (i.e. a new file in /sys/bus/pci/drivers/ipw/)
1147  * used for controling the debug level.
1148  *
1149  * See the level definitions in ipw for details.
1150  */
1151 static ssize_t show_debug_level(struct device_driver *d, char *buf)
1152 {
1153         return sprintf(buf, "0x%08X\n", ipw_debug_level);
1154 }
1155
1156 static ssize_t store_debug_level(struct device_driver *d, const char *buf,
1157                                  size_t count)
1158 {
1159         char *p = (char *)buf;
1160         u32 val;
1161
1162         if (p[1] == 'x' || p[1] == 'X' || p[0] == 'x' || p[0] == 'X') {
1163                 p++;
1164                 if (p[0] == 'x' || p[0] == 'X')
1165                         p++;
1166                 val = simple_strtoul(p, &p, 16);
1167         } else
1168                 val = simple_strtoul(p, &p, 10);
1169         if (p == buf)
1170                 printk(KERN_INFO DRV_NAME
1171                        ": %s is not in hex or decimal form.\n", buf);
1172         else
1173                 ipw_debug_level = val;
1174
1175         return strnlen(buf, count);
1176 }
1177
1178 static DRIVER_ATTR(debug_level, S_IWUSR | S_IRUGO,
1179                    show_debug_level, store_debug_level);
1180
1181 static inline u32 ipw_get_event_log_len(struct ipw_priv *priv)
1182 {
1183         /* length = 1st dword in log */
1184         return ipw_read_reg32(priv, ipw_read32(priv, IPW_EVENT_LOG));
1185 }
1186
1187 static void ipw_capture_event_log(struct ipw_priv *priv,
1188                                   u32 log_len, struct ipw_event *log)
1189 {
1190         u32 base;
1191
1192         if (log_len) {
1193                 base = ipw_read32(priv, IPW_EVENT_LOG);
1194                 ipw_read_indirect(priv, base + sizeof(base) + sizeof(u32),
1195                                   (u8 *) log, sizeof(*log) * log_len);
1196         }
1197 }
1198
1199 static struct ipw_fw_error *ipw_alloc_error_log(struct ipw_priv *priv)
1200 {
1201         struct ipw_fw_error *error;
1202         u32 log_len = ipw_get_event_log_len(priv);
1203         u32 base = ipw_read32(priv, IPW_ERROR_LOG);
1204         u32 elem_len = ipw_read_reg32(priv, base);
1205
1206         error = kmalloc(sizeof(*error) +
1207                         sizeof(*error->elem) * elem_len +
1208                         sizeof(*error->log) * log_len, GFP_ATOMIC);
1209         if (!error) {
1210                 IPW_ERROR("Memory allocation for firmware error log "
1211                           "failed.\n");
1212                 return NULL;
1213         }
1214         error->jiffies = jiffies;
1215         error->status = priv->status;
1216         error->config = priv->config;
1217         error->elem_len = elem_len;
1218         error->log_len = log_len;
1219         error->elem = (struct ipw_error_elem *)error->payload;
1220         error->log = (struct ipw_event *)(error->elem + elem_len);
1221
1222         ipw_capture_event_log(priv, log_len, error->log);
1223
1224         if (elem_len)
1225                 ipw_read_indirect(priv, base + sizeof(base), (u8 *) error->elem,
1226                                   sizeof(*error->elem) * elem_len);
1227
1228         return error;
1229 }
1230
1231 static ssize_t show_event_log(struct device *d,
1232                               struct device_attribute *attr, char *buf)
1233 {
1234         struct ipw_priv *priv = dev_get_drvdata(d);
1235         u32 log_len = ipw_get_event_log_len(priv);
1236         struct ipw_event log[log_len];
1237         u32 len = 0, i;
1238
1239         ipw_capture_event_log(priv, log_len, log);
1240
1241         len += snprintf(buf + len, PAGE_SIZE - len, "%08X", log_len);
1242         for (i = 0; i < log_len; i++)
1243                 len += snprintf(buf + len, PAGE_SIZE - len,
1244                                 "\n%08X%08X%08X",
1245                                 log[i].time, log[i].event, log[i].data);
1246         len += snprintf(buf + len, PAGE_SIZE - len, "\n");
1247         return len;
1248 }
1249
1250 static DEVICE_ATTR(event_log, S_IRUGO, show_event_log, NULL);
1251
1252 static ssize_t show_error(struct device *d,
1253                           struct device_attribute *attr, char *buf)
1254 {
1255         struct ipw_priv *priv = dev_get_drvdata(d);
1256         u32 len = 0, i;
1257         if (!priv->error)
1258                 return 0;
1259         len += snprintf(buf + len, PAGE_SIZE - len,
1260                         "%08lX%08X%08X%08X",
1261                         priv->error->jiffies,
1262                         priv->error->status,
1263                         priv->error->config, priv->error->elem_len);
1264         for (i = 0; i < priv->error->elem_len; i++)
1265                 len += snprintf(buf + len, PAGE_SIZE - len,
1266                                 "\n%08X%08X%08X%08X%08X%08X%08X",
1267                                 priv->error->elem[i].time,
1268                                 priv->error->elem[i].desc,
1269                                 priv->error->elem[i].blink1,
1270                                 priv->error->elem[i].blink2,
1271                                 priv->error->elem[i].link1,
1272                                 priv->error->elem[i].link2,
1273                                 priv->error->elem[i].data);
1274
1275         len += snprintf(buf + len, PAGE_SIZE - len,
1276                         "\n%08X", priv->error->log_len);
1277         for (i = 0; i < priv->error->log_len; i++)
1278                 len += snprintf(buf + len, PAGE_SIZE - len,
1279                                 "\n%08X%08X%08X",
1280                                 priv->error->log[i].time,
1281                                 priv->error->log[i].event,
1282                                 priv->error->log[i].data);
1283         len += snprintf(buf + len, PAGE_SIZE - len, "\n");
1284         return len;
1285 }
1286
1287 static ssize_t clear_error(struct device *d,
1288                            struct device_attribute *attr,
1289                            const char *buf, size_t count)
1290 {
1291         struct ipw_priv *priv = dev_get_drvdata(d);
1292
1293         kfree(priv->error);
1294         priv->error = NULL;
1295         return count;
1296 }
1297
1298 static DEVICE_ATTR(error, S_IRUGO | S_IWUSR, show_error, clear_error);
1299
1300 static ssize_t show_cmd_log(struct device *d,
1301                             struct device_attribute *attr, char *buf)
1302 {
1303         struct ipw_priv *priv = dev_get_drvdata(d);
1304         u32 len = 0, i;
1305         if (!priv->cmdlog)
1306                 return 0;
1307         for (i = (priv->cmdlog_pos + 1) % priv->cmdlog_len;
1308              (i != priv->cmdlog_pos) && (PAGE_SIZE - len);
1309              i = (i + 1) % priv->cmdlog_len) {
1310                 len +=
1311                     snprintf(buf + len, PAGE_SIZE - len,
1312                              "\n%08lX%08X%08X%08X\n", priv->cmdlog[i].jiffies,
1313                              priv->cmdlog[i].retcode, priv->cmdlog[i].cmd.cmd,
1314                              priv->cmdlog[i].cmd.len);
1315                 len +=
1316                     snprintk_buf(buf + len, PAGE_SIZE - len,
1317                                  (u8 *) priv->cmdlog[i].cmd.param,
1318                                  priv->cmdlog[i].cmd.len);
1319                 len += snprintf(buf + len, PAGE_SIZE - len, "\n");
1320         }
1321         len += snprintf(buf + len, PAGE_SIZE - len, "\n");
1322         return len;
1323 }
1324
1325 static DEVICE_ATTR(cmd_log, S_IRUGO, show_cmd_log, NULL);
1326
1327 #ifdef CONFIG_IPW2200_PROMISCUOUS
1328 static void ipw_prom_free(struct ipw_priv *priv);
1329 static int ipw_prom_alloc(struct ipw_priv *priv);
1330 static ssize_t store_rtap_iface(struct device *d,
1331                          struct device_attribute *attr,
1332                          const char *buf, size_t count)
1333 {
1334         struct ipw_priv *priv = dev_get_drvdata(d);
1335         int rc = 0;
1336
1337         if (count < 1)
1338                 return -EINVAL;
1339
1340         switch (buf[0]) {
1341         case '0':
1342                 if (!rtap_iface)
1343                         return count;
1344
1345                 if (netif_running(priv->prom_net_dev)) {
1346                         IPW_WARNING("Interface is up.  Cannot unregister.\n");
1347                         return count;
1348                 }
1349
1350                 ipw_prom_free(priv);
1351                 rtap_iface = 0;
1352                 break;
1353
1354         case '1':
1355                 if (rtap_iface)
1356                         return count;
1357
1358                 rc = ipw_prom_alloc(priv);
1359                 if (!rc)
1360                         rtap_iface = 1;
1361                 break;
1362
1363         default:
1364                 return -EINVAL;
1365         }
1366
1367         if (rc) {
1368                 IPW_ERROR("Failed to register promiscuous network "
1369                           "device (error %d).\n", rc);
1370         }
1371
1372         return count;
1373 }
1374
1375 static ssize_t show_rtap_iface(struct device *d,
1376                         struct device_attribute *attr,
1377                         char *buf)
1378 {
1379         struct ipw_priv *priv = dev_get_drvdata(d);
1380         if (rtap_iface)
1381                 return sprintf(buf, "%s", priv->prom_net_dev->name);
1382         else {
1383                 buf[0] = '-';
1384                 buf[1] = '1';
1385                 buf[2] = '\0';
1386                 return 3;
1387         }
1388 }
1389
1390 static DEVICE_ATTR(rtap_iface, S_IWUSR | S_IRUSR, show_rtap_iface,
1391                    store_rtap_iface);
1392
1393 static ssize_t store_rtap_filter(struct device *d,
1394                          struct device_attribute *attr,
1395                          const char *buf, size_t count)
1396 {
1397         struct ipw_priv *priv = dev_get_drvdata(d);
1398
1399         if (!priv->prom_priv) {
1400                 IPW_ERROR("Attempting to set filter without "
1401                           "rtap_iface enabled.\n");
1402                 return -EPERM;
1403         }
1404
1405         priv->prom_priv->filter = simple_strtol(buf, NULL, 0);
1406
1407         IPW_DEBUG_INFO("Setting rtap filter to " BIT_FMT16 "\n",
1408                        BIT_ARG16(priv->prom_priv->filter));
1409
1410         return count;
1411 }
1412
1413 static ssize_t show_rtap_filter(struct device *d,
1414                         struct device_attribute *attr,
1415                         char *buf)
1416 {
1417         struct ipw_priv *priv = dev_get_drvdata(d);
1418         return sprintf(buf, "0x%04X",
1419                        priv->prom_priv ? priv->prom_priv->filter : 0);
1420 }
1421
1422 static DEVICE_ATTR(rtap_filter, S_IWUSR | S_IRUSR, show_rtap_filter,
1423                    store_rtap_filter);
1424 #endif
1425
1426 static ssize_t show_scan_age(struct device *d, struct device_attribute *attr,
1427                              char *buf)
1428 {
1429         struct ipw_priv *priv = dev_get_drvdata(d);
1430         return sprintf(buf, "%d\n", priv->ieee->scan_age);
1431 }
1432
1433 static ssize_t store_scan_age(struct device *d, struct device_attribute *attr,
1434                               const char *buf, size_t count)
1435 {
1436         struct ipw_priv *priv = dev_get_drvdata(d);
1437         struct net_device *dev = priv->net_dev;
1438         char buffer[] = "00000000";
1439         unsigned long len =
1440             (sizeof(buffer) - 1) > count ? count : sizeof(buffer) - 1;
1441         unsigned long val;
1442         char *p = buffer;
1443
1444         IPW_DEBUG_INFO("enter\n");
1445
1446         strncpy(buffer, buf, len);
1447         buffer[len] = 0;
1448
1449         if (p[1] == 'x' || p[1] == 'X' || p[0] == 'x' || p[0] == 'X') {
1450                 p++;
1451                 if (p[0] == 'x' || p[0] == 'X')
1452                         p++;
1453                 val = simple_strtoul(p, &p, 16);
1454         } else
1455                 val = simple_strtoul(p, &p, 10);
1456         if (p == buffer) {
1457                 IPW_DEBUG_INFO("%s: user supplied invalid value.\n", dev->name);
1458         } else {
1459                 priv->ieee->scan_age = val;
1460                 IPW_DEBUG_INFO("set scan_age = %u\n", priv->ieee->scan_age);
1461         }
1462
1463         IPW_DEBUG_INFO("exit\n");
1464         return len;
1465 }
1466
1467 static DEVICE_ATTR(scan_age, S_IWUSR | S_IRUGO, show_scan_age, store_scan_age);
1468
1469 static ssize_t show_led(struct device *d, struct device_attribute *attr,
1470                         char *buf)
1471 {
1472         struct ipw_priv *priv = dev_get_drvdata(d);
1473         return sprintf(buf, "%d\n", (priv->config & CFG_NO_LED) ? 0 : 1);
1474 }
1475
1476 static ssize_t store_led(struct device *d, struct device_attribute *attr,
1477                          const char *buf, size_t count)
1478 {
1479         struct ipw_priv *priv = dev_get_drvdata(d);
1480
1481         IPW_DEBUG_INFO("enter\n");
1482
1483         if (count == 0)
1484                 return 0;
1485
1486         if (*buf == 0) {
1487                 IPW_DEBUG_LED("Disabling LED control.\n");
1488                 priv->config |= CFG_NO_LED;
1489                 ipw_led_shutdown(priv);
1490         } else {
1491                 IPW_DEBUG_LED("Enabling LED control.\n");
1492                 priv->config &= ~CFG_NO_LED;
1493                 ipw_led_init(priv);
1494         }
1495
1496         IPW_DEBUG_INFO("exit\n");
1497         return count;
1498 }
1499
1500 static DEVICE_ATTR(led, S_IWUSR | S_IRUGO, show_led, store_led);
1501
1502 static ssize_t show_status(struct device *d,
1503                            struct device_attribute *attr, char *buf)
1504 {
1505         struct ipw_priv *p = d->driver_data;
1506         return sprintf(buf, "0x%08x\n", (int)p->status);
1507 }
1508
1509 static DEVICE_ATTR(status, S_IRUGO, show_status, NULL);
1510
1511 static ssize_t show_cfg(struct device *d, struct device_attribute *attr,
1512                         char *buf)
1513 {
1514         struct ipw_priv *p = d->driver_data;
1515         return sprintf(buf, "0x%08x\n", (int)p->config);
1516 }
1517
1518 static DEVICE_ATTR(cfg, S_IRUGO, show_cfg, NULL);
1519
1520 static ssize_t show_nic_type(struct device *d,
1521                              struct device_attribute *attr, char *buf)
1522 {
1523         struct ipw_priv *priv = d->driver_data;
1524         return sprintf(buf, "TYPE: %d\n", priv->nic_type);
1525 }
1526
1527 static DEVICE_ATTR(nic_type, S_IRUGO, show_nic_type, NULL);
1528
1529 static ssize_t show_ucode_version(struct device *d,
1530                                   struct device_attribute *attr, char *buf)
1531 {
1532         u32 len = sizeof(u32), tmp = 0;
1533         struct ipw_priv *p = d->driver_data;
1534
1535         if (ipw_get_ordinal(p, IPW_ORD_STAT_UCODE_VERSION, &tmp, &len))
1536                 return 0;
1537
1538         return sprintf(buf, "0x%08x\n", tmp);
1539 }
1540
1541 static DEVICE_ATTR(ucode_version, S_IWUSR | S_IRUGO, show_ucode_version, NULL);
1542
1543 static ssize_t show_rtc(struct device *d, struct device_attribute *attr,
1544                         char *buf)
1545 {
1546         u32 len = sizeof(u32), tmp = 0;
1547         struct ipw_priv *p = d->driver_data;
1548
1549         if (ipw_get_ordinal(p, IPW_ORD_STAT_RTC, &tmp, &len))
1550                 return 0;
1551
1552         return sprintf(buf, "0x%08x\n", tmp);
1553 }
1554
1555 static DEVICE_ATTR(rtc, S_IWUSR | S_IRUGO, show_rtc, NULL);
1556
1557 /*
1558  * Add a device attribute to view/control the delay between eeprom
1559  * operations.
1560  */
1561 static ssize_t show_eeprom_delay(struct device *d,
1562                                  struct device_attribute *attr, char *buf)
1563 {
1564         int n = ((struct ipw_priv *)d->driver_data)->eeprom_delay;
1565         return sprintf(buf, "%i\n", n);
1566 }
1567 static ssize_t store_eeprom_delay(struct device *d,
1568                                   struct device_attribute *attr,
1569                                   const char *buf, size_t count)
1570 {
1571         struct ipw_priv *p = d->driver_data;
1572         sscanf(buf, "%i", &p->eeprom_delay);
1573         return strnlen(buf, count);
1574 }
1575
1576 static DEVICE_ATTR(eeprom_delay, S_IWUSR | S_IRUGO,
1577                    show_eeprom_delay, store_eeprom_delay);
1578
1579 static ssize_t show_command_event_reg(struct device *d,
1580                                       struct device_attribute *attr, char *buf)
1581 {
1582         u32 reg = 0;
1583         struct ipw_priv *p = d->driver_data;
1584
1585         reg = ipw_read_reg32(p, IPW_INTERNAL_CMD_EVENT);
1586         return sprintf(buf, "0x%08x\n", reg);
1587 }
1588 static ssize_t store_command_event_reg(struct device *d,
1589                                        struct device_attribute *attr,
1590                                        const char *buf, size_t count)
1591 {
1592         u32 reg;
1593         struct ipw_priv *p = d->driver_data;
1594
1595         sscanf(buf, "%x", &reg);
1596         ipw_write_reg32(p, IPW_INTERNAL_CMD_EVENT, reg);
1597         return strnlen(buf, count);
1598 }
1599
1600 static DEVICE_ATTR(command_event_reg, S_IWUSR | S_IRUGO,
1601                    show_command_event_reg, store_command_event_reg);
1602
1603 static ssize_t show_mem_gpio_reg(struct device *d,
1604                                  struct device_attribute *attr, char *buf)
1605 {
1606         u32 reg = 0;
1607         struct ipw_priv *p = d->driver_data;
1608
1609         reg = ipw_read_reg32(p, 0x301100);
1610         return sprintf(buf, "0x%08x\n", reg);
1611 }
1612 static ssize_t store_mem_gpio_reg(struct device *d,
1613                                   struct device_attribute *attr,
1614                                   const char *buf, size_t count)
1615 {
1616         u32 reg;
1617         struct ipw_priv *p = d->driver_data;
1618
1619         sscanf(buf, "%x", &reg);
1620         ipw_write_reg32(p, 0x301100, reg);
1621         return strnlen(buf, count);
1622 }
1623
1624 static DEVICE_ATTR(mem_gpio_reg, S_IWUSR | S_IRUGO,
1625                    show_mem_gpio_reg, store_mem_gpio_reg);
1626
1627 static ssize_t show_indirect_dword(struct device *d,
1628                                    struct device_attribute *attr, char *buf)
1629 {
1630         u32 reg = 0;
1631         struct ipw_priv *priv = d->driver_data;
1632
1633         if (priv->status & STATUS_INDIRECT_DWORD)
1634                 reg = ipw_read_reg32(priv, priv->indirect_dword);
1635         else
1636                 reg = 0;
1637
1638         return sprintf(buf, "0x%08x\n", reg);
1639 }
1640 static ssize_t store_indirect_dword(struct device *d,
1641                                     struct device_attribute *attr,
1642                                     const char *buf, size_t count)
1643 {
1644         struct ipw_priv *priv = d->driver_data;
1645
1646         sscanf(buf, "%x", &priv->indirect_dword);
1647         priv->status |= STATUS_INDIRECT_DWORD;
1648         return strnlen(buf, count);
1649 }
1650
1651 static DEVICE_ATTR(indirect_dword, S_IWUSR | S_IRUGO,
1652                    show_indirect_dword, store_indirect_dword);
1653
1654 static ssize_t show_indirect_byte(struct device *d,
1655                                   struct device_attribute *attr, char *buf)
1656 {
1657         u8 reg = 0;
1658         struct ipw_priv *priv = d->driver_data;
1659
1660         if (priv->status & STATUS_INDIRECT_BYTE)
1661                 reg = ipw_read_reg8(priv, priv->indirect_byte);
1662         else
1663                 reg = 0;
1664
1665         return sprintf(buf, "0x%02x\n", reg);
1666 }
1667 static ssize_t store_indirect_byte(struct device *d,
1668                                    struct device_attribute *attr,
1669                                    const char *buf, size_t count)
1670 {
1671         struct ipw_priv *priv = d->driver_data;
1672
1673         sscanf(buf, "%x", &priv->indirect_byte);
1674         priv->status |= STATUS_INDIRECT_BYTE;
1675         return strnlen(buf, count);
1676 }
1677
1678 static DEVICE_ATTR(indirect_byte, S_IWUSR | S_IRUGO,
1679                    show_indirect_byte, store_indirect_byte);
1680
1681 static ssize_t show_direct_dword(struct device *d,
1682                                  struct device_attribute *attr, char *buf)
1683 {
1684         u32 reg = 0;
1685         struct ipw_priv *priv = d->driver_data;
1686
1687         if (priv->status & STATUS_DIRECT_DWORD)
1688                 reg = ipw_read32(priv, priv->direct_dword);
1689         else
1690                 reg = 0;
1691
1692         return sprintf(buf, "0x%08x\n", reg);
1693 }
1694 static ssize_t store_direct_dword(struct device *d,
1695                                   struct device_attribute *attr,
1696                                   const char *buf, size_t count)
1697 {
1698         struct ipw_priv *priv = d->driver_data;
1699
1700         sscanf(buf, "%x", &priv->direct_dword);
1701         priv->status |= STATUS_DIRECT_DWORD;
1702         return strnlen(buf, count);
1703 }
1704
1705 static DEVICE_ATTR(direct_dword, S_IWUSR | S_IRUGO,
1706                    show_direct_dword, store_direct_dword);
1707
1708 static int rf_kill_active(struct ipw_priv *priv)
1709 {
1710         if (0 == (ipw_read32(priv, 0x30) & 0x10000))
1711                 priv->status |= STATUS_RF_KILL_HW;
1712         else
1713                 priv->status &= ~STATUS_RF_KILL_HW;
1714
1715         return (priv->status & STATUS_RF_KILL_HW) ? 1 : 0;
1716 }
1717
1718 static ssize_t show_rf_kill(struct device *d, struct device_attribute *attr,
1719                             char *buf)
1720 {
1721         /* 0 - RF kill not enabled
1722            1 - SW based RF kill active (sysfs)
1723            2 - HW based RF kill active
1724            3 - Both HW and SW baed RF kill active */
1725         struct ipw_priv *priv = d->driver_data;
1726         int val = ((priv->status & STATUS_RF_KILL_SW) ? 0x1 : 0x0) |
1727             (rf_kill_active(priv) ? 0x2 : 0x0);
1728         return sprintf(buf, "%i\n", val);
1729 }
1730
1731 static int ipw_radio_kill_sw(struct ipw_priv *priv, int disable_radio)
1732 {
1733         if ((disable_radio ? 1 : 0) ==
1734             ((priv->status & STATUS_RF_KILL_SW) ? 1 : 0))
1735                 return 0;
1736
1737         IPW_DEBUG_RF_KILL("Manual SW RF Kill set to: RADIO  %s\n",
1738                           disable_radio ? "OFF" : "ON");
1739
1740         if (disable_radio) {
1741                 priv->status |= STATUS_RF_KILL_SW;
1742
1743                 if (priv->workqueue)
1744                         cancel_delayed_work(&priv->request_scan);
1745                 queue_work(priv->workqueue, &priv->down);
1746         } else {
1747                 priv->status &= ~STATUS_RF_KILL_SW;
1748                 if (rf_kill_active(priv)) {
1749                         IPW_DEBUG_RF_KILL("Can not turn radio back on - "
1750                                           "disabled by HW switch\n");
1751                         /* Make sure the RF_KILL check timer is running */
1752                         cancel_delayed_work(&priv->rf_kill);
1753                         queue_delayed_work(priv->workqueue, &priv->rf_kill,
1754                                            round_jiffies(2 * HZ));
1755                 } else
1756                         queue_work(priv->workqueue, &priv->up);
1757         }
1758
1759         return 1;
1760 }
1761
1762 static ssize_t store_rf_kill(struct device *d, struct device_attribute *attr,
1763                              const char *buf, size_t count)
1764 {
1765         struct ipw_priv *priv = d->driver_data;
1766
1767         ipw_radio_kill_sw(priv, buf[0] == '1');
1768
1769         return count;
1770 }
1771
1772 static DEVICE_ATTR(rf_kill, S_IWUSR | S_IRUGO, show_rf_kill, store_rf_kill);
1773
1774 static ssize_t show_speed_scan(struct device *d, struct device_attribute *attr,
1775                                char *buf)
1776 {
1777         struct ipw_priv *priv = (struct ipw_priv *)d->driver_data;
1778         int pos = 0, len = 0;
1779         if (priv->config & CFG_SPEED_SCAN) {
1780                 while (priv->speed_scan[pos] != 0)
1781                         len += sprintf(&buf[len], "%d ",
1782                                        priv->speed_scan[pos++]);
1783                 return len + sprintf(&buf[len], "\n");
1784         }
1785
1786         return sprintf(buf, "0\n");
1787 }
1788
1789 static ssize_t store_speed_scan(struct device *d, struct device_attribute *attr,
1790                                 const char *buf, size_t count)
1791 {
1792         struct ipw_priv *priv = (struct ipw_priv *)d->driver_data;
1793         int channel, pos = 0;
1794         const char *p = buf;
1795
1796         /* list of space separated channels to scan, optionally ending with 0 */
1797         while ((channel = simple_strtol(p, NULL, 0))) {
1798                 if (pos == MAX_SPEED_SCAN - 1) {
1799                         priv->speed_scan[pos] = 0;
1800                         break;
1801                 }
1802
1803                 if (ieee80211_is_valid_channel(priv->ieee, channel))
1804                         priv->speed_scan[pos++] = channel;
1805                 else
1806                         IPW_WARNING("Skipping invalid channel request: %d\n",
1807                                     channel);
1808                 p = strchr(p, ' ');
1809                 if (!p)
1810                         break;
1811                 while (*p == ' ' || *p == '\t')
1812                         p++;
1813         }
1814
1815         if (pos == 0)
1816                 priv->config &= ~CFG_SPEED_SCAN;
1817         else {
1818                 priv->speed_scan_pos = 0;
1819                 priv->config |= CFG_SPEED_SCAN;
1820         }
1821
1822         return count;
1823 }
1824
1825 static DEVICE_ATTR(speed_scan, S_IWUSR | S_IRUGO, show_speed_scan,
1826                    store_speed_scan);
1827
1828 static ssize_t show_net_stats(struct device *d, struct device_attribute *attr,
1829                               char *buf)
1830 {
1831         struct ipw_priv *priv = (struct ipw_priv *)d->driver_data;
1832         return sprintf(buf, "%c\n", (priv->config & CFG_NET_STATS) ? '1' : '0');
1833 }
1834
1835 static ssize_t store_net_stats(struct device *d, struct device_attribute *attr,
1836                                const char *buf, size_t count)
1837 {
1838         struct ipw_priv *priv = (struct ipw_priv *)d->driver_data;
1839         if (buf[0] == '1')
1840                 priv->config |= CFG_NET_STATS;
1841         else
1842                 priv->config &= ~CFG_NET_STATS;
1843
1844         return count;
1845 }
1846
1847 static DEVICE_ATTR(net_stats, S_IWUSR | S_IRUGO,
1848                    show_net_stats, store_net_stats);
1849
1850 static ssize_t show_channels(struct device *d,
1851                              struct device_attribute *attr,
1852                              char *buf)
1853 {
1854         struct ipw_priv *priv = dev_get_drvdata(d);
1855         const struct ieee80211_geo *geo = ieee80211_get_geo(priv->ieee);
1856         int len = 0, i;
1857
1858         len = sprintf(&buf[len],
1859                       "Displaying %d channels in 2.4Ghz band "
1860                       "(802.11bg):\n", geo->bg_channels);
1861
1862         for (i = 0; i < geo->bg_channels; i++) {
1863                 len += sprintf(&buf[len], "%d: BSS%s%s, %s, Band %s.\n",
1864                                geo->bg[i].channel,
1865                                geo->bg[i].flags & IEEE80211_CH_RADAR_DETECT ?
1866                                " (radar spectrum)" : "",
1867                                ((geo->bg[i].flags & IEEE80211_CH_NO_IBSS) ||
1868                                 (geo->bg[i].flags & IEEE80211_CH_RADAR_DETECT))
1869                                ? "" : ", IBSS",
1870                                geo->bg[i].flags & IEEE80211_CH_PASSIVE_ONLY ?
1871                                "passive only" : "active/passive",
1872                                geo->bg[i].flags & IEEE80211_CH_B_ONLY ?
1873                                "B" : "B/G");
1874         }
1875
1876         len += sprintf(&buf[len],
1877                        "Displaying %d channels in 5.2Ghz band "
1878                        "(802.11a):\n", geo->a_channels);
1879         for (i = 0; i < geo->a_channels; i++) {
1880                 len += sprintf(&buf[len], "%d: BSS%s%s, %s.\n",
1881                                geo->a[i].channel,
1882                                geo->a[i].flags & IEEE80211_CH_RADAR_DETECT ?
1883                                " (radar spectrum)" : "",
1884                                ((geo->a[i].flags & IEEE80211_CH_NO_IBSS) ||
1885                                 (geo->a[i].flags & IEEE80211_CH_RADAR_DETECT))
1886                                ? "" : ", IBSS",
1887                                geo->a[i].flags & IEEE80211_CH_PASSIVE_ONLY ?
1888                                "passive only" : "active/passive");
1889         }
1890
1891         return len;
1892 }
1893
1894 static DEVICE_ATTR(channels, S_IRUSR, show_channels, NULL);
1895
1896 static void notify_wx_assoc_event(struct ipw_priv *priv)
1897 {
1898         union iwreq_data wrqu;
1899         wrqu.ap_addr.sa_family = ARPHRD_ETHER;
1900         if (priv->status & STATUS_ASSOCIATED)
1901                 memcpy(wrqu.ap_addr.sa_data, priv->bssid, ETH_ALEN);
1902         else
1903                 memset(wrqu.ap_addr.sa_data, 0, ETH_ALEN);
1904         wireless_send_event(priv->net_dev, SIOCGIWAP, &wrqu, NULL);
1905 }
1906
1907 static void ipw_irq_tasklet(struct ipw_priv *priv)
1908 {
1909         u32 inta, inta_mask, handled = 0;
1910         unsigned long flags;
1911         int rc = 0;
1912
1913         spin_lock_irqsave(&priv->irq_lock, flags);
1914
1915         inta = ipw_read32(priv, IPW_INTA_RW);
1916         inta_mask = ipw_read32(priv, IPW_INTA_MASK_R);
1917         inta &= (IPW_INTA_MASK_ALL & inta_mask);
1918
1919         /* Add any cached INTA values that need to be handled */
1920         inta |= priv->isr_inta;
1921
1922         spin_unlock_irqrestore(&priv->irq_lock, flags);
1923
1924         spin_lock_irqsave(&priv->lock, flags);
1925
1926         /* handle all the justifications for the interrupt */
1927         if (inta & IPW_INTA_BIT_RX_TRANSFER) {
1928                 ipw_rx(priv);
1929                 handled |= IPW_INTA_BIT_RX_TRANSFER;
1930         }
1931
1932         if (inta & IPW_INTA_BIT_TX_CMD_QUEUE) {
1933                 IPW_DEBUG_HC("Command completed.\n");
1934                 rc = ipw_queue_tx_reclaim(priv, &priv->txq_cmd, -1);
1935                 priv->status &= ~STATUS_HCMD_ACTIVE;
1936                 wake_up_interruptible(&priv->wait_command_queue);
1937                 handled |= IPW_INTA_BIT_TX_CMD_QUEUE;
1938         }
1939
1940         if (inta & IPW_INTA_BIT_TX_QUEUE_1) {
1941                 IPW_DEBUG_TX("TX_QUEUE_1\n");
1942                 rc = ipw_queue_tx_reclaim(priv, &priv->txq[0], 0);
1943                 handled |= IPW_INTA_BIT_TX_QUEUE_1;
1944         }
1945
1946         if (inta & IPW_INTA_BIT_TX_QUEUE_2) {
1947                 IPW_DEBUG_TX("TX_QUEUE_2\n");
1948                 rc = ipw_queue_tx_reclaim(priv, &priv->txq[1], 1);
1949                 handled |= IPW_INTA_BIT_TX_QUEUE_2;
1950         }
1951
1952         if (inta & IPW_INTA_BIT_TX_QUEUE_3) {
1953                 IPW_DEBUG_TX("TX_QUEUE_3\n");
1954                 rc = ipw_queue_tx_reclaim(priv, &priv->txq[2], 2);
1955                 handled |= IPW_INTA_BIT_TX_QUEUE_3;
1956         }
1957
1958         if (inta & IPW_INTA_BIT_TX_QUEUE_4) {
1959                 IPW_DEBUG_TX("TX_QUEUE_4\n");
1960                 rc = ipw_queue_tx_reclaim(priv, &priv->txq[3], 3);
1961                 handled |= IPW_INTA_BIT_TX_QUEUE_4;
1962         }
1963
1964         if (inta & IPW_INTA_BIT_STATUS_CHANGE) {
1965                 IPW_WARNING("STATUS_CHANGE\n");
1966                 handled |= IPW_INTA_BIT_STATUS_CHANGE;
1967         }
1968
1969         if (inta & IPW_INTA_BIT_BEACON_PERIOD_EXPIRED) {
1970                 IPW_WARNING("TX_PERIOD_EXPIRED\n");
1971                 handled |= IPW_INTA_BIT_BEACON_PERIOD_EXPIRED;
1972         }
1973
1974         if (inta & IPW_INTA_BIT_SLAVE_MODE_HOST_CMD_DONE) {
1975                 IPW_WARNING("HOST_CMD_DONE\n");
1976                 handled |= IPW_INTA_BIT_SLAVE_MODE_HOST_CMD_DONE;
1977         }
1978
1979         if (inta & IPW_INTA_BIT_FW_INITIALIZATION_DONE) {
1980                 IPW_WARNING("FW_INITIALIZATION_DONE\n");
1981                 handled |= IPW_INTA_BIT_FW_INITIALIZATION_DONE;
1982         }
1983
1984         if (inta & IPW_INTA_BIT_FW_CARD_DISABLE_PHY_OFF_DONE) {
1985                 IPW_WARNING("PHY_OFF_DONE\n");
1986                 handled |= IPW_INTA_BIT_FW_CARD_DISABLE_PHY_OFF_DONE;
1987         }
1988
1989         if (inta & IPW_INTA_BIT_RF_KILL_DONE) {
1990                 IPW_DEBUG_RF_KILL("RF_KILL_DONE\n");
1991                 priv->status |= STATUS_RF_KILL_HW;
1992                 wake_up_interruptible(&priv->wait_command_queue);
1993                 priv->status &= ~(STATUS_ASSOCIATED | STATUS_ASSOCIATING);
1994                 cancel_delayed_work(&priv->request_scan);
1995                 schedule_work(&priv->link_down);
1996                 queue_delayed_work(priv->workqueue, &priv->rf_kill, 2 * HZ);
1997                 handled |= IPW_INTA_BIT_RF_KILL_DONE;
1998         }
1999
2000         if (inta & IPW_INTA_BIT_FATAL_ERROR) {
2001                 IPW_WARNING("Firmware error detected.  Restarting.\n");
2002                 if (priv->error) {
2003                         IPW_DEBUG_FW("Sysfs 'error' log already exists.\n");
2004                         if (ipw_debug_level & IPW_DL_FW_ERRORS) {
2005                                 struct ipw_fw_error *error =
2006                                     ipw_alloc_error_log(priv);
2007                                 ipw_dump_error_log(priv, error);
2008                                 kfree(error);
2009                         }
2010                 } else {
2011                         priv->error = ipw_alloc_error_log(priv);
2012                         if (priv->error)
2013                                 IPW_DEBUG_FW("Sysfs 'error' log captured.\n");
2014                         else
2015                                 IPW_DEBUG_FW("Error allocating sysfs 'error' "
2016                                              "log.\n");
2017                         if (ipw_debug_level & IPW_DL_FW_ERRORS)
2018                                 ipw_dump_error_log(priv, priv->error);
2019                 }
2020
2021                 /* XXX: If hardware encryption is for WPA/WPA2,
2022                  * we have to notify the supplicant. */
2023                 if (priv->ieee->sec.encrypt) {
2024                         priv->status &= ~STATUS_ASSOCIATED;
2025                         notify_wx_assoc_event(priv);
2026                 }
2027
2028                 /* Keep the restart process from trying to send host
2029                  * commands by clearing the INIT status bit */
2030                 priv->status &= ~STATUS_INIT;
2031
2032                 /* Cancel currently queued command. */
2033                 priv->status &= ~STATUS_HCMD_ACTIVE;
2034                 wake_up_interruptible(&priv->wait_command_queue);
2035
2036                 queue_work(priv->workqueue, &priv->adapter_restart);
2037                 handled |= IPW_INTA_BIT_FATAL_ERROR;
2038         }
2039
2040         if (inta & IPW_INTA_BIT_PARITY_ERROR) {
2041                 IPW_ERROR("Parity error\n");
2042                 handled |= IPW_INTA_BIT_PARITY_ERROR;
2043         }
2044
2045         if (handled != inta) {
2046                 IPW_ERROR("Unhandled INTA bits 0x%08x\n", inta & ~handled);
2047         }
2048
2049         spin_unlock_irqrestore(&priv->lock, flags);
2050
2051         /* enable all interrupts */
2052         ipw_enable_interrupts(priv);
2053 }
2054
2055 #define IPW_CMD(x) case IPW_CMD_ ## x : return #x
2056 static char *get_cmd_string(u8 cmd)
2057 {
2058         switch (cmd) {
2059                 IPW_CMD(HOST_COMPLETE);
2060                 IPW_CMD(POWER_DOWN);
2061                 IPW_CMD(SYSTEM_CONFIG);
2062                 IPW_CMD(MULTICAST_ADDRESS);
2063                 IPW_CMD(SSID);
2064                 IPW_CMD(ADAPTER_ADDRESS);
2065                 IPW_CMD(PORT_TYPE);
2066                 IPW_CMD(RTS_THRESHOLD);
2067                 IPW_CMD(FRAG_THRESHOLD);
2068                 IPW_CMD(POWER_MODE);
2069                 IPW_CMD(WEP_KEY);
2070                 IPW_CMD(TGI_TX_KEY);
2071                 IPW_CMD(SCAN_REQUEST);
2072                 IPW_CMD(SCAN_REQUEST_EXT);
2073                 IPW_CMD(ASSOCIATE);
2074                 IPW_CMD(SUPPORTED_RATES);
2075                 IPW_CMD(SCAN_ABORT);
2076                 IPW_CMD(TX_FLUSH);
2077                 IPW_CMD(QOS_PARAMETERS);
2078                 IPW_CMD(DINO_CONFIG);
2079                 IPW_CMD(RSN_CAPABILITIES);
2080                 IPW_CMD(RX_KEY);
2081                 IPW_CMD(CARD_DISABLE);
2082                 IPW_CMD(SEED_NUMBER);
2083                 IPW_CMD(TX_POWER);
2084                 IPW_CMD(COUNTRY_INFO);
2085                 IPW_CMD(AIRONET_INFO);
2086                 IPW_CMD(AP_TX_POWER);
2087                 IPW_CMD(CCKM_INFO);
2088                 IPW_CMD(CCX_VER_INFO);
2089                 IPW_CMD(SET_CALIBRATION);
2090                 IPW_CMD(SENSITIVITY_CALIB);
2091                 IPW_CMD(RETRY_LIMIT);
2092                 IPW_CMD(IPW_PRE_POWER_DOWN);
2093                 IPW_CMD(VAP_BEACON_TEMPLATE);
2094                 IPW_CMD(VAP_DTIM_PERIOD);
2095                 IPW_CMD(EXT_SUPPORTED_RATES);
2096                 IPW_CMD(VAP_LOCAL_TX_PWR_CONSTRAINT);
2097                 IPW_CMD(VAP_QUIET_INTERVALS);
2098                 IPW_CMD(VAP_CHANNEL_SWITCH);
2099                 IPW_CMD(VAP_MANDATORY_CHANNELS);
2100                 IPW_CMD(VAP_CELL_PWR_LIMIT);
2101                 IPW_CMD(VAP_CF_PARAM_SET);
2102                 IPW_CMD(VAP_SET_BEACONING_STATE);
2103                 IPW_CMD(MEASUREMENT);
2104                 IPW_CMD(POWER_CAPABILITY);
2105                 IPW_CMD(SUPPORTED_CHANNELS);
2106                 IPW_CMD(TPC_REPORT);
2107                 IPW_CMD(WME_INFO);
2108                 IPW_CMD(PRODUCTION_COMMAND);
2109         default:
2110                 return "UNKNOWN";
2111         }
2112 }
2113
2114 #define HOST_COMPLETE_TIMEOUT HZ
2115
2116 static int __ipw_send_cmd(struct ipw_priv *priv, struct host_cmd *cmd)
2117 {
2118         int rc = 0;
2119         unsigned long flags;
2120
2121         spin_lock_irqsave(&priv->lock, flags);
2122         if (priv->status & STATUS_HCMD_ACTIVE) {
2123                 IPW_ERROR("Failed to send %s: Already sending a command.\n",
2124                           get_cmd_string(cmd->cmd));
2125                 spin_unlock_irqrestore(&priv->lock, flags);
2126                 return -EAGAIN;
2127         }
2128
2129         priv->status |= STATUS_HCMD_ACTIVE;
2130
2131         if (priv->cmdlog) {
2132                 priv->cmdlog[priv->cmdlog_pos].jiffies = jiffies;
2133                 priv->cmdlog[priv->cmdlog_pos].cmd.cmd = cmd->cmd;
2134                 priv->cmdlog[priv->cmdlog_pos].cmd.len = cmd->len;
2135                 memcpy(priv->cmdlog[priv->cmdlog_pos].cmd.param, cmd->param,
2136                        cmd->len);
2137                 priv->cmdlog[priv->cmdlog_pos].retcode = -1;
2138         }
2139
2140         IPW_DEBUG_HC("%s command (#%d) %d bytes: 0x%08X\n",
2141                      get_cmd_string(cmd->cmd), cmd->cmd, cmd->len,
2142                      priv->status);
2143
2144 #ifndef DEBUG_CMD_WEP_KEY
2145         if (cmd->cmd == IPW_CMD_WEP_KEY)
2146                 IPW_DEBUG_HC("WEP_KEY command masked out for secure.\n");
2147         else
2148 #endif
2149                 printk_buf(IPW_DL_HOST_COMMAND, (u8 *) cmd->param, cmd->len);
2150
2151         rc = ipw_queue_tx_hcmd(priv, cmd->cmd, cmd->param, cmd->len, 0);
2152         if (rc) {
2153                 priv->status &= ~STATUS_HCMD_ACTIVE;
2154                 IPW_ERROR("Failed to send %s: Reason %d\n",
2155                           get_cmd_string(cmd->cmd), rc);
2156                 spin_unlock_irqrestore(&priv->lock, flags);
2157                 goto exit;
2158         }
2159         spin_unlock_irqrestore(&priv->lock, flags);
2160
2161         rc = wait_event_interruptible_timeout(priv->wait_command_queue,
2162                                               !(priv->
2163                                                 status & STATUS_HCMD_ACTIVE),
2164                                               HOST_COMPLETE_TIMEOUT);
2165         if (rc == 0) {
2166                 spin_lock_irqsave(&priv->lock, flags);
2167                 if (priv->status & STATUS_HCMD_ACTIVE) {
2168                         IPW_ERROR("Failed to send %s: Command timed out.\n",
2169                                   get_cmd_string(cmd->cmd));
2170                         priv->status &= ~STATUS_HCMD_ACTIVE;
2171                         spin_unlock_irqrestore(&priv->lock, flags);
2172                         rc = -EIO;
2173                         goto exit;
2174                 }
2175                 spin_unlock_irqrestore(&priv->lock, flags);
2176         } else
2177                 rc = 0;
2178
2179         if (priv->status & STATUS_RF_KILL_HW) {
2180                 IPW_ERROR("Failed to send %s: Aborted due to RF kill switch.\n",
2181                           get_cmd_string(cmd->cmd));
2182                 rc = -EIO;
2183                 goto exit;
2184         }
2185
2186       exit:
2187         if (priv->cmdlog) {
2188                 priv->cmdlog[priv->cmdlog_pos++].retcode = rc;
2189                 priv->cmdlog_pos %= priv->cmdlog_len;
2190         }
2191         return rc;
2192 }
2193
2194 static int ipw_send_cmd_simple(struct ipw_priv *priv, u8 command)
2195 {
2196         struct host_cmd cmd = {
2197                 .cmd = command,
2198         };
2199
2200         return __ipw_send_cmd(priv, &cmd);
2201 }
2202
2203 static int ipw_send_cmd_pdu(struct ipw_priv *priv, u8 command, u8 len,
2204                             void *data)
2205 {
2206         struct host_cmd cmd = {
2207                 .cmd = command,
2208                 .len = len,
2209                 .param = data,
2210         };
2211
2212         return __ipw_send_cmd(priv, &cmd);
2213 }
2214
2215 static int ipw_send_host_complete(struct ipw_priv *priv)
2216 {
2217         if (!priv) {
2218                 IPW_ERROR("Invalid args\n");
2219                 return -1;
2220         }
2221
2222         return ipw_send_cmd_simple(priv, IPW_CMD_HOST_COMPLETE);
2223 }
2224
2225 static int ipw_send_system_config(struct ipw_priv *priv)
2226 {
2227         return ipw_send_cmd_pdu(priv, IPW_CMD_SYSTEM_CONFIG,
2228                                 sizeof(priv->sys_config),
2229                                 &priv->sys_config);
2230 }
2231
2232 static int ipw_send_ssid(struct ipw_priv *priv, u8 * ssid, int len)
2233 {
2234         if (!priv || !ssid) {
2235                 IPW_ERROR("Invalid args\n");
2236                 return -1;
2237         }
2238
2239         return ipw_send_cmd_pdu(priv, IPW_CMD_SSID, min(len, IW_ESSID_MAX_SIZE),
2240                                 ssid);
2241 }
2242
2243 static int ipw_send_adapter_address(struct ipw_priv *priv, u8 * mac)
2244 {
2245         if (!priv || !mac) {
2246                 IPW_ERROR("Invalid args\n");
2247                 return -1;
2248         }
2249
2250         IPW_DEBUG_INFO("%s: Setting MAC to " MAC_FMT "\n",
2251                        priv->net_dev->name, MAC_ARG(mac));
2252
2253         return ipw_send_cmd_pdu(priv, IPW_CMD_ADAPTER_ADDRESS, ETH_ALEN, mac);
2254 }
2255
2256 /*
2257  * NOTE: This must be executed from our workqueue as it results in udelay
2258  * being called which may corrupt the keyboard if executed on default
2259  * workqueue
2260  */
2261 static void ipw_adapter_restart(void *adapter)
2262 {
2263         struct ipw_priv *priv = adapter;
2264
2265         if (priv->status & STATUS_RF_KILL_MASK)
2266                 return;
2267
2268         ipw_down(priv);
2269
2270         if (priv->assoc_network &&
2271             (priv->assoc_network->capability & WLAN_CAPABILITY_IBSS))
2272                 ipw_remove_current_network(priv);
2273
2274         if (ipw_up(priv)) {
2275                 IPW_ERROR("Failed to up device\n");
2276                 return;
2277         }
2278 }
2279
2280 static void ipw_bg_adapter_restart(struct work_struct *work)
2281 {
2282         struct ipw_priv *priv =
2283                 container_of(work, struct ipw_priv, adapter_restart);
2284         mutex_lock(&priv->mutex);
2285         ipw_adapter_restart(priv);
2286         mutex_unlock(&priv->mutex);
2287 }
2288
2289 #define IPW_SCAN_CHECK_WATCHDOG (5 * HZ)
2290
2291 static void ipw_scan_check(void *data)
2292 {
2293         struct ipw_priv *priv = data;
2294         if (priv->status & (STATUS_SCANNING | STATUS_SCAN_ABORTING)) {
2295                 IPW_DEBUG_SCAN("Scan completion watchdog resetting "
2296                                "adapter after (%dms).\n",
2297                                jiffies_to_msecs(IPW_SCAN_CHECK_WATCHDOG));
2298                 queue_work(priv->workqueue, &priv->adapter_restart);
2299         }
2300 }
2301
2302 static void ipw_bg_scan_check(struct work_struct *work)
2303 {
2304         struct ipw_priv *priv =
2305                 container_of(work, struct ipw_priv, scan_check.work);
2306         mutex_lock(&priv->mutex);
2307         ipw_scan_check(priv);
2308         mutex_unlock(&priv->mutex);
2309 }
2310
2311 static int ipw_send_scan_request_ext(struct ipw_priv *priv,
2312                                      struct ipw_scan_request_ext *request)
2313 {
2314         return ipw_send_cmd_pdu(priv, IPW_CMD_SCAN_REQUEST_EXT,
2315                                 sizeof(*request), request);
2316 }
2317
2318 static int ipw_send_scan_abort(struct ipw_priv *priv)
2319 {
2320         if (!priv) {
2321                 IPW_ERROR("Invalid args\n");
2322                 return -1;
2323         }
2324
2325         return ipw_send_cmd_simple(priv, IPW_CMD_SCAN_ABORT);
2326 }
2327
2328 static int ipw_set_sensitivity(struct ipw_priv *priv, u16 sens)
2329 {
2330         struct ipw_sensitivity_calib calib = {
2331                 .beacon_rssi_raw = cpu_to_le16(sens),
2332         };
2333
2334         return ipw_send_cmd_pdu(priv, IPW_CMD_SENSITIVITY_CALIB, sizeof(calib),
2335                                 &calib);
2336 }
2337
2338 static int ipw_send_associate(struct ipw_priv *priv,
2339                               struct ipw_associate *associate)
2340 {
2341         struct ipw_associate tmp_associate;
2342
2343         if (!priv || !associate) {
2344                 IPW_ERROR("Invalid args\n");
2345                 return -1;
2346         }
2347
2348         memcpy(&tmp_associate, associate, sizeof(*associate));
2349         tmp_associate.policy_support =
2350             cpu_to_le16(tmp_associate.policy_support);
2351         tmp_associate.assoc_tsf_msw = cpu_to_le32(tmp_associate.assoc_tsf_msw);
2352         tmp_associate.assoc_tsf_lsw = cpu_to_le32(tmp_associate.assoc_tsf_lsw);
2353         tmp_associate.capability = cpu_to_le16(tmp_associate.capability);
2354         tmp_associate.listen_interval =
2355             cpu_to_le16(tmp_associate.listen_interval);
2356         tmp_associate.beacon_interval =
2357             cpu_to_le16(tmp_associate.beacon_interval);
2358         tmp_associate.atim_window = cpu_to_le16(tmp_associate.atim_window);
2359
2360         return ipw_send_cmd_pdu(priv, IPW_CMD_ASSOCIATE, sizeof(tmp_associate),
2361                                 &tmp_associate);
2362 }
2363
2364 static int ipw_send_supported_rates(struct ipw_priv *priv,
2365                                     struct ipw_supported_rates *rates)
2366 {
2367         if (!priv || !rates) {
2368                 IPW_ERROR("Invalid args\n");
2369                 return -1;
2370         }
2371
2372         return ipw_send_cmd_pdu(priv, IPW_CMD_SUPPORTED_RATES, sizeof(*rates),
2373                                 rates);
2374 }
2375
2376 static int ipw_set_random_seed(struct ipw_priv *priv)
2377 {
2378         u32 val;
2379
2380         if (!priv) {
2381                 IPW_ERROR("Invalid args\n");
2382                 return -1;
2383         }
2384
2385         get_random_bytes(&val, sizeof(val));
2386
2387         return ipw_send_cmd_pdu(priv, IPW_CMD_SEED_NUMBER, sizeof(val), &val);
2388 }
2389
2390 static int ipw_send_card_disable(struct ipw_priv *priv, u32 phy_off)
2391 {
2392         if (!priv) {
2393                 IPW_ERROR("Invalid args\n");
2394                 return -1;
2395         }
2396
2397         phy_off = cpu_to_le32(phy_off);
2398         return ipw_send_cmd_pdu(priv, IPW_CMD_CARD_DISABLE, sizeof(phy_off),
2399                                 &phy_off);
2400 }
2401
2402 static int ipw_send_tx_power(struct ipw_priv *priv, struct ipw_tx_power *power)
2403 {
2404         if (!priv || !power) {
2405                 IPW_ERROR("Invalid args\n");
2406                 return -1;
2407         }
2408
2409         return ipw_send_cmd_pdu(priv, IPW_CMD_TX_POWER, sizeof(*power), power);
2410 }
2411
2412 static int ipw_set_tx_power(struct ipw_priv *priv)
2413 {
2414         const struct ieee80211_geo *geo = ieee80211_get_geo(priv->ieee);
2415         struct ipw_tx_power tx_power;
2416         s8 max_power;
2417         int i;
2418
2419         memset(&tx_power, 0, sizeof(tx_power));
2420
2421         /* configure device for 'G' band */
2422         tx_power.ieee_mode = IPW_G_MODE;
2423         tx_power.num_channels = geo->bg_channels;
2424         for (i = 0; i < geo->bg_channels; i++) {
2425                 max_power = geo->bg[i].max_power;
2426                 tx_power.channels_tx_power[i].channel_number =
2427                     geo->bg[i].channel;
2428                 tx_power.channels_tx_power[i].tx_power = max_power ?
2429                     min(max_power, priv->tx_power) : priv->tx_power;
2430         }
2431         if (ipw_send_tx_power(priv, &tx_power))
2432                 return -EIO;
2433
2434         /* configure device to also handle 'B' band */
2435         tx_power.ieee_mode = IPW_B_MODE;
2436         if (ipw_send_tx_power(priv, &tx_power))
2437                 return -EIO;
2438
2439         /* configure device to also handle 'A' band */
2440         if (priv->ieee->abg_true) {
2441                 tx_power.ieee_mode = IPW_A_MODE;
2442                 tx_power.num_channels = geo->a_channels;
2443                 for (i = 0; i < tx_power.num_channels; i++) {
2444                         max_power = geo->a[i].max_power;
2445                         tx_power.channels_tx_power[i].channel_number =
2446                             geo->a[i].channel;
2447                         tx_power.channels_tx_power[i].tx_power = max_power ?
2448                             min(max_power, priv->tx_power) : priv->tx_power;
2449                 }
2450                 if (ipw_send_tx_power(priv, &tx_power))
2451                         return -EIO;
2452         }
2453         return 0;
2454 }
2455
2456 static int ipw_send_rts_threshold(struct ipw_priv *priv, u16 rts)
2457 {
2458         struct ipw_rts_threshold rts_threshold = {
2459                 .rts_threshold = cpu_to_le16(rts),
2460         };
2461
2462         if (!priv) {
2463                 IPW_ERROR("Invalid args\n");
2464                 return -1;
2465         }
2466
2467         return ipw_send_cmd_pdu(priv, IPW_CMD_RTS_THRESHOLD,
2468                                 sizeof(rts_threshold), &rts_threshold);
2469 }
2470
2471 static int ipw_send_frag_threshold(struct ipw_priv *priv, u16 frag)
2472 {
2473         struct ipw_frag_threshold frag_threshold = {
2474                 .frag_threshold = cpu_to_le16(frag),
2475         };
2476
2477         if (!priv) {
2478                 IPW_ERROR("Invalid args\n");
2479                 return -1;
2480         }
2481
2482         return ipw_send_cmd_pdu(priv, IPW_CMD_FRAG_THRESHOLD,
2483                                 sizeof(frag_threshold), &frag_threshold);
2484 }
2485
2486 static int ipw_send_power_mode(struct ipw_priv *priv, u32 mode)
2487 {
2488         u32 param;
2489
2490         if (!priv) {
2491                 IPW_ERROR("Invalid args\n");
2492                 return -1;
2493         }
2494
2495         /* If on battery, set to 3, if AC set to CAM, else user
2496          * level */
2497         switch (mode) {
2498         case IPW_POWER_BATTERY:
2499                 param = IPW_POWER_INDEX_3;
2500                 break;
2501         case IPW_POWER_AC:
2502                 param = IPW_POWER_MODE_CAM;
2503                 break;
2504         default:
2505                 param = mode;
2506                 break;
2507         }
2508
2509         param = cpu_to_le32(param);
2510         return ipw_send_cmd_pdu(priv, IPW_CMD_POWER_MODE, sizeof(param),
2511                                 &param);
2512 }
2513
2514 static int ipw_send_retry_limit(struct ipw_priv *priv, u8 slimit, u8 llimit)
2515 {
2516         struct ipw_retry_limit retry_limit = {
2517                 .short_retry_limit = slimit,
2518                 .long_retry_limit = llimit
2519         };
2520
2521         if (!priv) {
2522                 IPW_ERROR("Invalid args\n");
2523                 return -1;
2524         }
2525
2526         return ipw_send_cmd_pdu(priv, IPW_CMD_RETRY_LIMIT, sizeof(retry_limit),
2527                                 &retry_limit);
2528 }
2529
2530 /*
2531  * The IPW device contains a Microwire compatible EEPROM that stores
2532  * various data like the MAC address.  Usually the firmware has exclusive
2533  * access to the eeprom, but during device initialization (before the
2534  * device driver has sent the HostComplete command to the firmware) the
2535  * device driver has read access to the EEPROM by way of indirect addressing
2536  * through a couple of memory mapped registers.
2537  *
2538  * The following is a simplified implementation for pulling data out of the
2539  * the eeprom, along with some helper functions to find information in
2540  * the per device private data's copy of the eeprom.
2541  *
2542  * NOTE: To better understand how these functions work (i.e what is a chip
2543  *       select and why do have to keep driving the eeprom clock?), read
2544  *       just about any data sheet for a Microwire compatible EEPROM.
2545  */
2546
2547 /* write a 32 bit value into the indirect accessor register */
2548 static inline void eeprom_write_reg(struct ipw_priv *p, u32 data)
2549 {
2550         ipw_write_reg32(p, FW_MEM_REG_EEPROM_ACCESS, data);
2551
2552         /* the eeprom requires some time to complete the operation */
2553         udelay(p->eeprom_delay);
2554
2555         return;
2556 }
2557
2558 /* perform a chip select operation */
2559 static void eeprom_cs(struct ipw_priv *priv)
2560 {
2561         eeprom_write_reg(priv, 0);
2562         eeprom_write_reg(priv, EEPROM_BIT_CS);
2563         eeprom_write_reg(priv, EEPROM_BIT_CS | EEPROM_BIT_SK);
2564         eeprom_write_reg(priv, EEPROM_BIT_CS);
2565 }
2566
2567 /* perform a chip select operation */
2568 static void eeprom_disable_cs(struct ipw_priv *priv)
2569 {
2570         eeprom_write_reg(priv, EEPROM_BIT_CS);
2571         eeprom_write_reg(priv, 0);
2572         eeprom_write_reg(priv, EEPROM_BIT_SK);
2573 }
2574
2575 /* push a single bit down to the eeprom */
2576 static inline void eeprom_write_bit(struct ipw_priv *p, u8 bit)
2577 {
2578         int d = (bit ? EEPROM_BIT_DI : 0);
2579         eeprom_write_reg(p, EEPROM_BIT_CS | d);
2580         eeprom_write_reg(p, EEPROM_BIT_CS | d | EEPROM_BIT_SK);
2581 }
2582
2583 /* push an opcode followed by an address down to the eeprom */
2584 static void eeprom_op(struct ipw_priv *priv, u8 op, u8 addr)
2585 {
2586         int i;
2587
2588         eeprom_cs(priv);
2589         eeprom_write_bit(priv, 1);
2590         eeprom_write_bit(priv, op & 2);
2591         eeprom_write_bit(priv, op & 1);
2592         for (i = 7; i >= 0; i--) {
2593                 eeprom_write_bit(priv, addr & (1 << i));
2594         }
2595 }
2596
2597 /* pull 16 bits off the eeprom, one bit at a time */
2598 static u16 eeprom_read_u16(struct ipw_priv *priv, u8 addr)
2599 {
2600         int i;
2601         u16 r = 0;
2602
2603         /* Send READ Opcode */
2604         eeprom_op(priv, EEPROM_CMD_READ, addr);
2605
2606         /* Send dummy bit */
2607         eeprom_write_reg(priv, EEPROM_BIT_CS);
2608
2609         /* Read the byte off the eeprom one bit at a time */
2610         for (i = 0; i < 16; i++) {
2611                 u32 data = 0;
2612                 eeprom_write_reg(priv, EEPROM_BIT_CS | EEPROM_BIT_SK);
2613                 eeprom_write_reg(priv, EEPROM_BIT_CS);
2614                 data = ipw_read_reg32(priv, FW_MEM_REG_EEPROM_ACCESS);
2615                 r = (r << 1) | ((data & EEPROM_BIT_DO) ? 1 : 0);
2616         }
2617
2618         /* Send another dummy bit */
2619         eeprom_write_reg(priv, 0);
2620         eeprom_disable_cs(priv);
2621
2622         return r;
2623 }
2624
2625 /* helper function for pulling the mac address out of the private */
2626 /* data's copy of the eeprom data                                 */
2627 static void eeprom_parse_mac(struct ipw_priv *priv, u8 * mac)
2628 {
2629         memcpy(mac, &priv->eeprom[EEPROM_MAC_ADDRESS], 6);
2630 }
2631
2632 /*
2633  * Either the device driver (i.e. the host) or the firmware can
2634  * load eeprom data into the designated region in SRAM.  If neither
2635  * happens then the FW will shutdown with a fatal error.
2636  *
2637  * In order to signal the FW to load the EEPROM, the EEPROM_LOAD_DISABLE
2638  * bit needs region of shared SRAM needs to be non-zero.
2639  */
2640 static void ipw_eeprom_init_sram(struct ipw_priv *priv)
2641 {
2642         int i;
2643         u16 *eeprom = (u16 *) priv->eeprom;
2644
2645         IPW_DEBUG_TRACE(">>\n");
2646
2647         /* read entire contents of eeprom into private buffer */
2648         for (i = 0; i < 128; i++)
2649                 eeprom[i] = le16_to_cpu(eeprom_read_u16(priv, (u8) i));
2650
2651         /*
2652            If the data looks correct, then copy it to our private
2653            copy.  Otherwise let the firmware know to perform the operation
2654            on its own.
2655          */
2656         if (priv->eeprom[EEPROM_VERSION] != 0) {
2657                 IPW_DEBUG_INFO("Writing EEPROM data into SRAM\n");
2658
2659                 /* write the eeprom data to sram */
2660                 for (i = 0; i < IPW_EEPROM_IMAGE_SIZE; i++)
2661                         ipw_write8(priv, IPW_EEPROM_DATA + i, priv->eeprom[i]);
2662
2663                 /* Do not load eeprom data on fatal error or suspend */
2664                 ipw_write32(priv, IPW_EEPROM_LOAD_DISABLE, 0);
2665         } else {
2666                 IPW_DEBUG_INFO("Enabling FW initializationg of SRAM\n");
2667
2668                 /* Load eeprom data on fatal error or suspend */
2669                 ipw_write32(priv, IPW_EEPROM_LOAD_DISABLE, 1);
2670         }
2671
2672         IPW_DEBUG_TRACE("<<\n");
2673 }
2674
2675 static void ipw_zero_memory(struct ipw_priv *priv, u32 start, u32 count)
2676 {
2677         count >>= 2;
2678         if (!count)
2679                 return;
2680         _ipw_write32(priv, IPW_AUTOINC_ADDR, start);
2681         while (count--)
2682                 _ipw_write32(priv, IPW_AUTOINC_DATA, 0);
2683 }
2684
2685 static inline void ipw_fw_dma_reset_command_blocks(struct ipw_priv *priv)
2686 {
2687         ipw_zero_memory(priv, IPW_SHARED_SRAM_DMA_CONTROL,
2688                         CB_NUMBER_OF_ELEMENTS_SMALL *
2689                         sizeof(struct command_block));
2690 }
2691
2692 static int ipw_fw_dma_enable(struct ipw_priv *priv)
2693 {                               /* start dma engine but no transfers yet */
2694
2695         IPW_DEBUG_FW(">> : \n");
2696
2697         /* Start the dma */
2698         ipw_fw_dma_reset_command_blocks(priv);
2699
2700         /* Write CB base address */
2701         ipw_write_reg32(priv, IPW_DMA_I_CB_BASE, IPW_SHARED_SRAM_DMA_CONTROL);
2702
2703         IPW_DEBUG_FW("<< : \n");
2704         return 0;
2705 }
2706
2707 static void ipw_fw_dma_abort(struct ipw_priv *priv)
2708 {
2709         u32 control = 0;
2710
2711         IPW_DEBUG_FW(">> :\n");
2712
2713         /* set the Stop and Abort bit */
2714         control = DMA_CONTROL_SMALL_CB_CONST_VALUE | DMA_CB_STOP_AND_ABORT;
2715         ipw_write_reg32(priv, IPW_DMA_I_DMA_CONTROL, control);
2716         priv->sram_desc.last_cb_index = 0;
2717
2718         IPW_DEBUG_FW("<< \n");
2719 }
2720
2721 static int ipw_fw_dma_write_command_block(struct ipw_priv *priv, int index,
2722                                           struct command_block *cb)
2723 {
2724         u32 address =
2725             IPW_SHARED_SRAM_DMA_CONTROL +
2726             (sizeof(struct command_block) * index);
2727         IPW_DEBUG_FW(">> :\n");
2728
2729         ipw_write_indirect(priv, address, (u8 *) cb,
2730                            (int)sizeof(struct command_block));
2731
2732         IPW_DEBUG_FW("<< :\n");
2733         return 0;
2734
2735 }
2736
2737 static int ipw_fw_dma_kick(struct ipw_priv *priv)
2738 {
2739         u32 control = 0;
2740         u32 index = 0;
2741
2742         IPW_DEBUG_FW(">> :\n");
2743
2744         for (index = 0; index < priv->sram_desc.last_cb_index; index++)
2745                 ipw_fw_dma_write_command_block(priv, index,
2746                                                &priv->sram_desc.cb_list[index]);
2747
2748         /* Enable the DMA in the CSR register */
2749         ipw_clear_bit(priv, IPW_RESET_REG,
2750                       IPW_RESET_REG_MASTER_DISABLED |
2751                       IPW_RESET_REG_STOP_MASTER);
2752
2753         /* Set the Start bit. */
2754         control = DMA_CONTROL_SMALL_CB_CONST_VALUE | DMA_CB_START;
2755         ipw_write_reg32(priv, IPW_DMA_I_DMA_CONTROL, control);
2756
2757         IPW_DEBUG_FW("<< :\n");
2758         return 0;
2759 }
2760
2761 static void ipw_fw_dma_dump_command_block(struct ipw_priv *priv)
2762 {
2763         u32 address;
2764         u32 register_value = 0;
2765         u32 cb_fields_address = 0;
2766
2767         IPW_DEBUG_FW(">> :\n");
2768         address = ipw_read_reg32(priv, IPW_DMA_I_CURRENT_CB);
2769         IPW_DEBUG_FW_INFO("Current CB is 0x%x \n", address);
2770
2771         /* Read the DMA Controlor register */
2772         register_value = ipw_read_reg32(priv, IPW_DMA_I_DMA_CONTROL);
2773         IPW_DEBUG_FW_INFO("IPW_DMA_I_DMA_CONTROL is 0x%x \n", register_value);
2774
2775         /* Print the CB values */
2776         cb_fields_address = address;
2777         register_value = ipw_read_reg32(priv, cb_fields_address);
2778         IPW_DEBUG_FW_INFO("Current CB ControlField is 0x%x \n", register_value);
2779
2780         cb_fields_address += sizeof(u32);
2781         register_value = ipw_read_reg32(priv, cb_fields_address);
2782         IPW_DEBUG_FW_INFO("Current CB Source Field is 0x%x \n", register_value);
2783
2784         cb_fields_address += sizeof(u32);
2785         register_value = ipw_read_reg32(priv, cb_fields_address);
2786         IPW_DEBUG_FW_INFO("Current CB Destination Field is 0x%x \n",
2787                           register_value);
2788
2789         cb_fields_address += sizeof(u32);
2790         register_value = ipw_read_reg32(priv, cb_fields_address);
2791         IPW_DEBUG_FW_INFO("Current CB Status Field is 0x%x \n", register_value);
2792
2793         IPW_DEBUG_FW(">> :\n");
2794 }
2795
2796 static int ipw_fw_dma_command_block_index(struct ipw_priv *priv)
2797 {
2798         u32 current_cb_address = 0;
2799         u32 current_cb_index = 0;
2800
2801         IPW_DEBUG_FW("<< :\n");
2802         current_cb_address = ipw_read_reg32(priv, IPW_DMA_I_CURRENT_CB);
2803
2804         current_cb_index = (current_cb_address - IPW_SHARED_SRAM_DMA_CONTROL) /
2805             sizeof(struct command_block);
2806
2807         IPW_DEBUG_FW_INFO("Current CB index 0x%x address = 0x%X \n",
2808                           current_cb_index, current_cb_address);
2809
2810         IPW_DEBUG_FW(">> :\n");
2811         return current_cb_index;
2812
2813 }
2814
2815 static int ipw_fw_dma_add_command_block(struct ipw_priv *priv,
2816                                         u32 src_address,
2817                                         u32 dest_address,
2818                                         u32 length,
2819                                         int interrupt_enabled, int is_last)
2820 {
2821
2822         u32 control = CB_VALID | CB_SRC_LE | CB_DEST_LE | CB_SRC_AUTOINC |
2823             CB_SRC_IO_GATED | CB_DEST_AUTOINC | CB_SRC_SIZE_LONG |
2824             CB_DEST_SIZE_LONG;
2825         struct command_block *cb;
2826         u32 last_cb_element = 0;
2827
2828         IPW_DEBUG_FW_INFO("src_address=0x%x dest_address=0x%x length=0x%x\n",
2829                           src_address, dest_address, length);
2830
2831         if (priv->sram_desc.last_cb_index >= CB_NUMBER_OF_ELEMENTS_SMALL)
2832                 return -1;
2833
2834         last_cb_element = priv->sram_desc.last_cb_index;
2835         cb = &priv->sram_desc.cb_list[last_cb_element];
2836         priv->sram_desc.last_cb_index++;
2837
2838         /* Calculate the new CB control word */
2839         if (interrupt_enabled)
2840                 control |= CB_INT_ENABLED;
2841
2842         if (is_last)
2843                 control |= CB_LAST_VALID;
2844
2845         control |= length;
2846
2847         /* Calculate the CB Element's checksum value */
2848         cb->status = control ^ src_address ^ dest_address;
2849
2850         /* Copy the Source and Destination addresses */
2851         cb->dest_addr = dest_address;
2852         cb->source_addr = src_address;
2853
2854         /* Copy the Control Word last */
2855         cb->control = control;
2856
2857         return 0;
2858 }
2859
2860 static int ipw_fw_dma_add_buffer(struct ipw_priv *priv,
2861                                  u32 src_phys, u32 dest_address, u32 length)
2862 {
2863         u32 bytes_left = length;
2864         u32 src_offset = 0;
2865         u32 dest_offset = 0;
2866         int status = 0;
2867         IPW_DEBUG_FW(">> \n");
2868         IPW_DEBUG_FW_INFO("src_phys=0x%x dest_address=0x%x length=0x%x\n",
2869                           src_phys, dest_address, length);
2870         while (bytes_left > CB_MAX_LENGTH) {
2871                 status = ipw_fw_dma_add_command_block(priv,
2872                                                       src_phys + src_offset,
2873                                                       dest_address +
2874                                                       dest_offset,
2875                                                       CB_MAX_LENGTH, 0, 0);
2876                 if (status) {
2877                         IPW_DEBUG_FW_INFO(": Failed\n");
2878                         return -1;
2879                 } else
2880                         IPW_DEBUG_FW_INFO(": Added new cb\n");
2881
2882                 src_offset += CB_MAX_LENGTH;
2883                 dest_offset += CB_MAX_LENGTH;
2884                 bytes_left -= CB_MAX_LENGTH;
2885         }
2886
2887         /* add the buffer tail */
2888         if (bytes_left > 0) {
2889                 status =
2890                     ipw_fw_dma_add_command_block(priv, src_phys + src_offset,
2891                                                  dest_address + dest_offset,
2892                                                  bytes_left, 0, 0);
2893                 if (status) {
2894                         IPW_DEBUG_FW_INFO(": Failed on the buffer tail\n");
2895                         return -1;
2896                 } else
2897                         IPW_DEBUG_FW_INFO
2898                             (": Adding new cb - the buffer tail\n");
2899         }
2900
2901         IPW_DEBUG_FW("<< \n");
2902         return 0;
2903 }
2904
2905 static int ipw_fw_dma_wait(struct ipw_priv *priv)
2906 {
2907         u32 current_index = 0, previous_index;
2908         u32 watchdog = 0;
2909
2910         IPW_DEBUG_FW(">> : \n");
2911
2912         current_index = ipw_fw_dma_command_block_index(priv);
2913         IPW_DEBUG_FW_INFO("sram_desc.last_cb_index:0x%08X\n",
2914                           (int)priv->sram_desc.last_cb_index);
2915
2916         while (current_index < priv->sram_desc.last_cb_index) {
2917                 udelay(50);
2918                 previous_index = current_index;
2919                 current_index = ipw_fw_dma_command_block_index(priv);
2920
2921                 if (previous_index < current_index) {
2922                         watchdog = 0;
2923                         continue;
2924                 }
2925                 if (++watchdog > 400) {
2926                         IPW_DEBUG_FW_INFO("Timeout\n");
2927                         ipw_fw_dma_dump_command_block(priv);
2928                         ipw_fw_dma_abort(priv);
2929                         return -1;
2930                 }
2931         }
2932
2933         ipw_fw_dma_abort(priv);
2934
2935         /*Disable the DMA in the CSR register */
2936         ipw_set_bit(priv, IPW_RESET_REG,
2937                     IPW_RESET_REG_MASTER_DISABLED | IPW_RESET_REG_STOP_MASTER);
2938
2939         IPW_DEBUG_FW("<< dmaWaitSync \n");
2940         return 0;
2941 }
2942
2943 static void ipw_remove_current_network(struct ipw_priv *priv)
2944 {
2945         struct list_head *element, *safe;
2946         struct ieee80211_network *network = NULL;
2947         unsigned long flags;
2948
2949         spin_lock_irqsave(&priv->ieee->lock, flags);
2950         list_for_each_safe(element, safe, &priv->ieee->network_list) {
2951                 network = list_entry(element, struct ieee80211_network, list);
2952                 if (!memcmp(network->bssid, priv->bssid, ETH_ALEN)) {
2953                         list_del(element);
2954                         list_add_tail(&network->list,
2955                                       &priv->ieee->network_free_list);
2956                 }
2957         }
2958         spin_unlock_irqrestore(&priv->ieee->lock, flags);
2959 }
2960
2961 /**
2962  * Check that card is still alive.
2963  * Reads debug register from domain0.
2964  * If card is present, pre-defined value should
2965  * be found there.
2966  *
2967  * @param priv
2968  * @return 1 if card is present, 0 otherwise
2969  */
2970 static inline int ipw_alive(struct ipw_priv *priv)
2971 {
2972         return ipw_read32(priv, 0x90) == 0xd55555d5;
2973 }
2974
2975 /* timeout in msec, attempted in 10-msec quanta */
2976 static int ipw_poll_bit(struct ipw_priv *priv, u32 addr, u32 mask,
2977                                int timeout)
2978 {
2979         int i = 0;
2980
2981         do {
2982                 if ((ipw_read32(priv, addr) & mask) == mask)
2983                         return i;
2984                 mdelay(10);
2985                 i += 10;
2986         } while (i < timeout);
2987
2988         return -ETIME;
2989 }
2990
2991 /* These functions load the firmware and micro code for the operation of
2992  * the ipw hardware.  It assumes the buffer has all the bits for the
2993  * image and the caller is handling the memory allocation and clean up.
2994  */
2995
2996 static int ipw_stop_master(struct ipw_priv *priv)
2997 {
2998         int rc;
2999
3000         IPW_DEBUG_TRACE(">> \n");
3001         /* stop master. typical delay - 0 */
3002         ipw_set_bit(priv, IPW_RESET_REG, IPW_RESET_REG_STOP_MASTER);
3003
3004         /* timeout is in msec, polled in 10-msec quanta */
3005         rc = ipw_poll_bit(priv, IPW_RESET_REG,
3006                           IPW_RESET_REG_MASTER_DISABLED, 100);
3007         if (rc < 0) {
3008                 IPW_ERROR("wait for stop master failed after 100ms\n");
3009                 return -1;
3010         }
3011
3012         IPW_DEBUG_INFO("stop master %dms\n", rc);
3013
3014         return rc;
3015 }
3016
3017 static void ipw_arc_release(struct ipw_priv *priv)
3018 {
3019         IPW_DEBUG_TRACE(">> \n");
3020         mdelay(5);
3021
3022         ipw_clear_bit(priv, IPW_RESET_REG, CBD_RESET_REG_PRINCETON_RESET);
3023
3024         /* no one knows timing, for safety add some delay */
3025         mdelay(5);
3026 }
3027
3028 struct fw_chunk {
3029         u32 address;
3030         u32 length;
3031 };
3032
3033 static int ipw_load_ucode(struct ipw_priv *priv, u8 * data, size_t len)
3034 {
3035         int rc = 0, i, addr;
3036         u8 cr = 0;
3037         u16 *image;
3038
3039         image = (u16 *) data;
3040
3041         IPW_DEBUG_TRACE(">> \n");
3042
3043         rc = ipw_stop_master(priv);
3044
3045         if (rc < 0)
3046                 return rc;
3047
3048         for (addr = IPW_SHARED_LOWER_BOUND;
3049              addr < IPW_REGISTER_DOMAIN1_END; addr += 4) {
3050                 ipw_write32(priv, addr, 0);
3051         }
3052
3053         /* no ucode (yet) */
3054         memset(&priv->dino_alive, 0, sizeof(priv->dino_alive));
3055         /* destroy DMA queues */
3056         /* reset sequence */
3057
3058         ipw_write_reg32(priv, IPW_MEM_HALT_AND_RESET, IPW_BIT_HALT_RESET_ON);
3059         ipw_arc_release(priv);
3060         ipw_write_reg32(priv, IPW_MEM_HALT_AND_RESET, IPW_BIT_HALT_RESET_OFF);
3061         mdelay(1);
3062
3063         /* reset PHY */
3064         ipw_write_reg32(priv, IPW_INTERNAL_CMD_EVENT, IPW_BASEBAND_POWER_DOWN);
3065         mdelay(1);
3066
3067         ipw_write_reg32(priv, IPW_INTERNAL_CMD_EVENT, 0);
3068         mdelay(1);
3069
3070         /* enable ucode store */
3071         ipw_write_reg8(priv, IPW_BASEBAND_CONTROL_STATUS, 0x0);
3072         ipw_write_reg8(priv, IPW_BASEBAND_CONTROL_STATUS, DINO_ENABLE_CS);
3073         mdelay(1);
3074
3075         /* write ucode */
3076         /**
3077          * @bug
3078          * Do NOT set indirect address register once and then
3079          * store data to indirect data register in the loop.
3080          * It seems very reasonable, but in this case DINO do not
3081          * accept ucode. It is essential to set address each time.
3082          */
3083         /* load new ipw uCode */
3084         for (i = 0; i < len / 2; i++)
3085                 ipw_write_reg16(priv, IPW_BASEBAND_CONTROL_STORE,
3086                                 cpu_to_le16(image[i]));
3087
3088         /* enable DINO */
3089         ipw_write_reg8(priv, IPW_BASEBAND_CONTROL_STATUS, 0);
3090         ipw_write_reg8(priv, IPW_BASEBAND_CONTROL_STATUS, DINO_ENABLE_SYSTEM);
3091
3092         /* this is where the igx / win driver deveates from the VAP driver. */
3093
3094         /* wait for alive response */
3095         for (i = 0; i < 100; i++) {
3096                 /* poll for incoming data */
3097                 cr = ipw_read_reg8(priv, IPW_BASEBAND_CONTROL_STATUS);
3098                 if (cr & DINO_RXFIFO_DATA)
3099                         break;
3100                 mdelay(1);
3101         }
3102
3103         if (cr & DINO_RXFIFO_DATA) {
3104                 /* alive_command_responce size is NOT multiple of 4 */
3105                 u32 response_buffer[(sizeof(priv->dino_alive) + 3) / 4];
3106
3107                 for (i = 0; i < ARRAY_SIZE(response_buffer); i++)
3108                         response_buffer[i] =
3109                             le32_to_cpu(ipw_read_reg32(priv,
3110                                                        IPW_BASEBAND_RX_FIFO_READ));
3111                 memcpy(&priv->dino_alive, response_buffer,
3112                        sizeof(priv->dino_alive));
3113                 if (priv->dino_alive.alive_command == 1
3114                     && priv->dino_alive.ucode_valid == 1) {
3115                         rc = 0;
3116                         IPW_DEBUG_INFO
3117                             ("Microcode OK, rev. %d (0x%x) dev. %d (0x%x) "
3118                              "of %02d/%02d/%02d %02d:%02d\n",
3119                              priv->dino_alive.software_revision,
3120                              priv->dino_alive.software_revision,
3121                              priv->dino_alive.device_identifier,
3122                              priv->dino_alive.device_identifier,
3123                              priv->dino_alive.time_stamp[0],
3124                              priv->dino_alive.time_stamp[1],
3125                              priv->dino_alive.time_stamp[2],
3126                              priv->dino_alive.time_stamp[3],
3127                              priv->dino_alive.time_stamp[4]);
3128                 } else {
3129                         IPW_DEBUG_INFO("Microcode is not alive\n");
3130                         rc = -EINVAL;
3131                 }
3132         } else {
3133                 IPW_DEBUG_INFO("No alive response from DINO\n");
3134                 rc = -ETIME;
3135         }
3136
3137         /* disable DINO, otherwise for some reason
3138            firmware have problem getting alive resp. */
3139         ipw_write_reg8(priv, IPW_BASEBAND_CONTROL_STATUS, 0);
3140
3141         return rc;
3142 }
3143
3144 static int ipw_load_firmware(struct ipw_priv *priv, u8 * data, size_t len)
3145 {
3146         int rc = -1;
3147         int offset = 0;
3148         struct fw_chunk *chunk;
3149         dma_addr_t shared_phys;
3150         u8 *shared_virt;
3151
3152         IPW_DEBUG_TRACE("<< : \n");
3153         shared_virt = pci_alloc_consistent(priv->pci_dev, len, &shared_phys);
3154
3155         if (!shared_virt)
3156                 return -ENOMEM;
3157
3158         memmove(shared_virt, data, len);
3159
3160         /* Start the Dma */
3161         rc = ipw_fw_dma_enable(priv);
3162
3163         if (priv->sram_desc.last_cb_index > 0) {
3164                 /* the DMA is already ready this would be a bug. */
3165                 BUG();
3166                 goto out;
3167         }
3168
3169         do {
3170                 chunk = (struct fw_chunk *)(data + offset);
3171                 offset += sizeof(struct fw_chunk);
3172                 /* build DMA packet and queue up for sending */
3173                 /* dma to chunk->address, the chunk->length bytes from data +
3174                  * offeset*/
3175                 /* Dma loading */
3176                 rc = ipw_fw_dma_add_buffer(priv, shared_phys + offset,
3177                                            le32_to_cpu(chunk->address),
3178                                            le32_to_cpu(chunk->length));
3179                 if (rc) {
3180                         IPW_DEBUG_INFO("dmaAddBuffer Failed\n");
3181                         goto out;
3182                 }
3183
3184                 offset += le32_to_cpu(chunk->length);
3185         } while (offset < len);
3186
3187         /* Run the DMA and wait for the answer */
3188         rc = ipw_fw_dma_kick(priv);
3189         if (rc) {
3190                 IPW_ERROR("dmaKick Failed\n");
3191                 goto out;
3192         }
3193
3194         rc = ipw_fw_dma_wait(priv);
3195         if (rc) {
3196                 IPW_ERROR("dmaWaitSync Failed\n");
3197                 goto out;
3198         }
3199       out:
3200         pci_free_consistent(priv->pci_dev, len, shared_virt, shared_phys);
3201         return rc;
3202 }
3203
3204 /* stop nic */
3205 static int ipw_stop_nic(struct ipw_priv *priv)
3206 {
3207         int rc = 0;
3208
3209         /* stop */
3210         ipw_write32(priv, IPW_RESET_REG, IPW_RESET_REG_STOP_MASTER);
3211
3212         rc = ipw_poll_bit(priv, IPW_RESET_REG,
3213                           IPW_RESET_REG_MASTER_DISABLED, 500);
3214         if (rc < 0) {
3215                 IPW_ERROR("wait for reg master disabled failed after 500ms\n");
3216                 return rc;
3217         }
3218
3219         ipw_set_bit(priv, IPW_RESET_REG, CBD_RESET_REG_PRINCETON_RESET);
3220
3221         return rc;
3222 }
3223
3224 static void ipw_start_nic(struct ipw_priv *priv)
3225 {
3226         IPW_DEBUG_TRACE(">>\n");
3227
3228         /* prvHwStartNic  release ARC */
3229         ipw_clear_bit(priv, IPW_RESET_REG,
3230                       IPW_RESET_REG_MASTER_DISABLED |
3231                       IPW_RESET_REG_STOP_MASTER |
3232                       CBD_RESET_REG_PRINCETON_RESET);
3233
3234         /* enable power management */
3235         ipw_set_bit(priv, IPW_GP_CNTRL_RW,
3236                     IPW_GP_CNTRL_BIT_HOST_ALLOWS_STANDBY);
3237
3238         IPW_DEBUG_TRACE("<<\n");
3239 }
3240
3241 static int ipw_init_nic(struct ipw_priv *priv)
3242 {
3243         int rc;
3244
3245         IPW_DEBUG_TRACE(">>\n");
3246         /* reset */
3247         /*prvHwInitNic */
3248         /* set "initialization complete" bit to move adapter to D0 state */
3249         ipw_set_bit(priv, IPW_GP_CNTRL_RW, IPW_GP_CNTRL_BIT_INIT_DONE);
3250
3251         /* low-level PLL activation */
3252         ipw_write32(priv, IPW_READ_INT_REGISTER,
3253                     IPW_BIT_INT_HOST_SRAM_READ_INT_REGISTER);
3254
3255         /* wait for clock stabilization */
3256         rc = ipw_poll_bit(priv, IPW_GP_CNTRL_RW,
3257                           IPW_GP_CNTRL_BIT_CLOCK_READY, 250);
3258         if (rc < 0)
3259                 IPW_DEBUG_INFO("FAILED wait for clock stablization\n");
3260
3261         /* assert SW reset */
3262         ipw_set_bit(priv, IPW_RESET_REG, IPW_RESET_REG_SW_RESET);
3263
3264         udelay(10);
3265
3266         /* set "initialization complete" bit to move adapter to D0 state */
3267         ipw_set_bit(priv, IPW_GP_CNTRL_RW, IPW_GP_CNTRL_BIT_INIT_DONE);
3268
3269         IPW_DEBUG_TRACE(">>\n");
3270         return 0;
3271 }
3272
3273 /* Call this function from process context, it will sleep in request_firmware.
3274  * Probe is an ok place to call this from.
3275  */
3276 static int ipw_reset_nic(struct ipw_priv *priv)
3277 {
3278         int rc = 0;
3279         unsigned long flags;
3280
3281         IPW_DEBUG_TRACE(">>\n");
3282
3283         rc = ipw_init_nic(priv);
3284
3285         spin_lock_irqsave(&priv->lock, flags);
3286         /* Clear the 'host command active' bit... */
3287         priv->status &= ~STATUS_HCMD_ACTIVE;
3288         wake_up_interruptible(&priv->wait_command_queue);
3289         priv->status &= ~(STATUS_SCANNING | STATUS_SCAN_ABORTING);
3290         wake_up_interruptible(&priv->wait_state);
3291         spin_unlock_irqrestore(&priv->lock, flags);
3292
3293         IPW_DEBUG_TRACE("<<\n");
3294         return rc;
3295 }
3296
3297
3298 struct ipw_fw {
3299         __le32 ver;
3300         __le32 boot_size;
3301         __le32 ucode_size;
3302         __le32 fw_size;
3303         u8 data[0];
3304 };
3305
3306 static int ipw_get_fw(struct ipw_priv *priv,