drivers/net/wireless/ipw2200.c

   1 /******************************************************************************
   2
   3   Copyright(c) 2003 - 2006 Intel Corporation. All rights reserved.
   4
   5   802.11 status code portion of this file from ethereal-0.10.6:
   6     Copyright 2000, Axis Communications AB
   7     Ethereal - Network traffic analyzer
   8     By Gerald Combs <gerald@ethereal.com>
   9     Copyright 1998 Gerald Combs
  10
  11   This program is free software; you can redistribute it and/or modify it
  12   under the terms of version 2 of the GNU General Public License as
  13   published by the Free Software Foundation.
  14
  15   This program is distributed in the hope that it will be useful, but WITHOUT
  16   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  17   FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  18   more details.
  19
  20   You should have received a copy of the GNU General Public License along with
  21   this program; if not, write to the Free Software Foundation, Inc., 59
  22   Temple Place - Suite 330, Boston, MA  02111-1307, USA.
  23
  24   The full GNU General Public License is included in this distribution in the
  25   file called LICENSE.
  26
  27   Contact Information:
  28   James P. Ketrenos <ipw2100-admin@linux.intel.com>
  29   Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
  30
  31 ******************************************************************************/
  32
  33 #include "ipw2200.h"
  34 #include <linux/version.h>
  35
  36
  37 #ifndef KBUILD_EXTMOD
  38 #define VK "k"
  39 #else
  40 #define VK
  41 #endif
  42
  43 #ifdef CONFIG_IPW2200_DEBUG
  44 #define VD "d"
  45 #else
  46 #define VD
  47 #endif
  48
  49 #ifdef CONFIG_IPW2200_MONITOR
  50 #define VM "m"
  51 #else
  52 #define VM
  53 #endif
  54
  55 #ifdef CONFIG_IPW2200_PROMISCUOUS
  56 #define VP "p"
  57 #else
  58 #define VP
  59 #endif
  60
  61 #ifdef CONFIG_IPW2200_RADIOTAP
  62 #define VR "r"
  63 #else
  64 #define VR
  65 #endif
  66
  67 #ifdef CONFIG_IPW2200_QOS
  68 #define VQ "q"
  69 #else
  70 #define VQ
  71 #endif
  72
  73 #define IPW2200_VERSION "1.1.2" VK VD VM VP VR VQ
  74 #define DRV_DESCRIPTION "Intel(R) PRO/Wireless 2200/2915 Network Driver"
  75 #define DRV_COPYRIGHT   "Copyright(c) 2003-2006 Intel Corporation"
  76 #define DRV_VERSION     IPW2200_VERSION
  77
  78 #define ETH_P_80211_STATS (ETH_P_80211_RAW + 1)
  79
  80 MODULE_DESCRIPTION(DRV_DESCRIPTION);
  81 MODULE_VERSION(DRV_VERSION);
  82 MODULE_AUTHOR(DRV_COPYRIGHT);
  83 MODULE_LICENSE("GPL");
  84
  85 static int cmdlog = 0;
  86 #ifdef CONFIG_IPW2200_DEBUG
  87 static int debug = 0;
  88 #endif
  89 static int channel = 0;
  90 static int mode = 0;
  91
  92 static u32 ipw_debug_level;
  93 static int associate = 1;
  94 static int auto_create = 1;
  95 static int led = 0;
  96 static int disable = 0;
  97 static int bt_coexist = 0;
  98 static int hwcrypto = 0;
  99 static int roaming = 1;
 100 static const char ipw_modes[] = {
 101         'a', 'b', 'g', '?'
 102 };
 103 static int antenna = CFG_SYS_ANTENNA_BOTH;
 104
 105 #ifdef CONFIG_IPW2200_PROMISCUOUS
 106 static int rtap_iface = 0;     /* def: 0 -- do not create rtap interface */
 107 #endif
 108
 109
 110 #ifdef CONFIG_IPW2200_QOS
 111 static int qos_enable = 0;
 112 static int qos_burst_enable = 0;
 113 static int qos_no_ack_mask = 0;
 114 static int burst_duration_CCK = 0;
 115 static int burst_duration_OFDM = 0;
 116
 117 static struct ieee80211_qos_parameters def_qos_parameters_OFDM = {
 118         {QOS_TX0_CW_MIN_OFDM, QOS_TX1_CW_MIN_OFDM, QOS_TX2_CW_MIN_OFDM,
 119          QOS_TX3_CW_MIN_OFDM},
 120         {QOS_TX0_CW_MAX_OFDM, QOS_TX1_CW_MAX_OFDM, QOS_TX2_CW_MAX_OFDM,
 121          QOS_TX3_CW_MAX_OFDM},
 122         {QOS_TX0_AIFS, QOS_TX1_AIFS, QOS_TX2_AIFS, QOS_TX3_AIFS},
 123         {QOS_TX0_ACM, QOS_TX1_ACM, QOS_TX2_ACM, QOS_TX3_ACM},
 124         {QOS_TX0_TXOP_LIMIT_OFDM, QOS_TX1_TXOP_LIMIT_OFDM,
 125          QOS_TX2_TXOP_LIMIT_OFDM, QOS_TX3_TXOP_LIMIT_OFDM}
 126 };
 127
 128 static struct ieee80211_qos_parameters def_qos_parameters_CCK = {
 129         {QOS_TX0_CW_MIN_CCK, QOS_TX1_CW_MIN_CCK, QOS_TX2_CW_MIN_CCK,
 130          QOS_TX3_CW_MIN_CCK},
 131         {QOS_TX0_CW_MAX_CCK, QOS_TX1_CW_MAX_CCK, QOS_TX2_CW_MAX_CCK,
 132          QOS_TX3_CW_MAX_CCK},
 133         {QOS_TX0_AIFS, QOS_TX1_AIFS, QOS_TX2_AIFS, QOS_TX3_AIFS},
 134         {QOS_TX0_ACM, QOS_TX1_ACM, QOS_TX2_ACM, QOS_TX3_ACM},
 135         {QOS_TX0_TXOP_LIMIT_CCK, QOS_TX1_TXOP_LIMIT_CCK, QOS_TX2_TXOP_LIMIT_CCK,
 136          QOS_TX3_TXOP_LIMIT_CCK}
 137 };
 138
 139 static struct ieee80211_qos_parameters def_parameters_OFDM = {
 140         {DEF_TX0_CW_MIN_OFDM, DEF_TX1_CW_MIN_OFDM, DEF_TX2_CW_MIN_OFDM,
 141          DEF_TX3_CW_MIN_OFDM},
 142         {DEF_TX0_CW_MAX_OFDM, DEF_TX1_CW_MAX_OFDM, DEF_TX2_CW_MAX_OFDM,
 143          DEF_TX3_CW_MAX_OFDM},
 144         {DEF_TX0_AIFS, DEF_TX1_AIFS, DEF_TX2_AIFS, DEF_TX3_AIFS},
 145         {DEF_TX0_ACM, DEF_TX1_ACM, DEF_TX2_ACM, DEF_TX3_ACM},
 146         {DEF_TX0_TXOP_LIMIT_OFDM, DEF_TX1_TXOP_LIMIT_OFDM,
 147          DEF_TX2_TXOP_LIMIT_OFDM, DEF_TX3_TXOP_LIMIT_OFDM}
 148 };
 149
 150 static struct ieee80211_qos_parameters def_parameters_CCK = {
 151         {DEF_TX0_CW_MIN_CCK, DEF_TX1_CW_MIN_CCK, DEF_TX2_CW_MIN_CCK,
 152          DEF_TX3_CW_MIN_CCK},
 153         {DEF_TX0_CW_MAX_CCK, DEF_TX1_CW_MAX_CCK, DEF_TX2_CW_MAX_CCK,
 154          DEF_TX3_CW_MAX_CCK},
 155         {DEF_TX0_AIFS, DEF_TX1_AIFS, DEF_TX2_AIFS, DEF_TX3_AIFS},
 156         {DEF_TX0_ACM, DEF_TX1_ACM, DEF_TX2_ACM, DEF_TX3_ACM},
 157         {DEF_TX0_TXOP_LIMIT_CCK, DEF_TX1_TXOP_LIMIT_CCK, DEF_TX2_TXOP_LIMIT_CCK,
 158          DEF_TX3_TXOP_LIMIT_CCK}
 159 };
 160
 161 static u8 qos_oui[QOS_OUI_LEN] = { 0x00, 0x50, 0xF2 };
 162
 163 static int from_priority_to_tx_queue[] = {
 164         IPW_TX_QUEUE_1, IPW_TX_QUEUE_2, IPW_TX_QUEUE_2, IPW_TX_QUEUE_1,
 165         IPW_TX_QUEUE_3, IPW_TX_QUEUE_3, IPW_TX_QUEUE_4, IPW_TX_QUEUE_4
 166 };
 167
 168 static u32 ipw_qos_get_burst_duration(struct ipw_priv *priv);
 169
 170 static int ipw_send_qos_params_command(struct ipw_priv *priv, struct ieee80211_qos_parameters
 171                                        *qos_param);
 172 static int ipw_send_qos_info_command(struct ipw_priv *priv, struct ieee80211_qos_information_element
 173                                      *qos_param);
 174 #endif                          /* CONFIG_IPW2200_QOS */
 175
 176 static struct iw_statistics *ipw_get_wireless_stats(struct net_device *dev);
 177 static void ipw_remove_current_network(struct ipw_priv *priv);
 178 static void ipw_rx(struct ipw_priv *priv);
 179 static int ipw_queue_tx_reclaim(struct ipw_priv *priv,
 180                                 struct clx2_tx_queue *txq, int qindex);
 181 static int ipw_queue_reset(struct ipw_priv *priv);
 182
 183 static int ipw_queue_tx_hcmd(struct ipw_priv *priv, int hcmd, void *buf,
 184                              int len, int sync);
 185
 186 static void ipw_tx_queue_free(struct ipw_priv *);
 187
 188 static struct ipw_rx_queue *ipw_rx_queue_alloc(struct ipw_priv *);
 189 static void ipw_rx_queue_free(struct ipw_priv *, struct ipw_rx_queue *);
 190 static void ipw_rx_queue_replenish(void *);
 191 static int ipw_up(struct ipw_priv *);
 192 static void ipw_bg_up(void *);
 193 static void ipw_down(struct ipw_priv *);
 194 static void ipw_bg_down(void *);
 195 static int ipw_config(struct ipw_priv *);
 196 static int init_supported_rates(struct ipw_priv *priv,
 197                                 struct ipw_supported_rates *prates);
 198 static void ipw_set_hwcrypto_keys(struct ipw_priv *);
 199 static void ipw_send_wep_keys(struct ipw_priv *, int);
 200
 201 static int snprint_line(char *buf, size_t count,
 202                         const u8 * data, u32 len, u32 ofs)
 203 {
 204         int out, i, j, l;
 205         char c;
 206
 207         out = snprintf(buf, count, "%08X", ofs);
 208
 209         for (l = 0, i = 0; i < 2; i++) {
 210                 out += snprintf(buf + out, count - out, " ");
 211                 for (j = 0; j < 8 && l < len; j++, l++)
 212                         out += snprintf(buf + out, count - out, "%02X ",
 213                                         data[(i * 8 + j)]);
 214                 for (; j < 8; j++)
 215                         out += snprintf(buf + out, count - out, "   ");
 216         }
 217
 218         out += snprintf(buf + out, count - out, " ");
 219         for (l = 0, i = 0; i < 2; i++) {
 220                 out += snprintf(buf + out, count - out, " ");
 221                 for (j = 0; j < 8 && l < len; j++, l++) {
 222                         c = data[(i * 8 + j)];
 223                         if (!isascii(c) || !isprint(c))
 224                                 c = '.';
 225
 226                         out += snprintf(buf + out, count - out, "%c", c);
 227                 }
 228
 229                 for (; j < 8; j++)
 230                         out += snprintf(buf + out, count - out, " ");
 231         }
 232
 233         return out;
 234 }
 235
 236 static void printk_buf(int level, const u8 * data, u32 len)
 237 {
 238         char line[81];
 239         u32 ofs = 0;
 240         if (!(ipw_debug_level & level))
 241                 return;
 242
 243         while (len) {
 244                 snprint_line(line, sizeof(line), &data[ofs],
 245                              min(len, 16U), ofs);
 246                 printk(KERN_DEBUG "%s\n", line);
 247                 ofs += 16;
 248                 len -= min(len, 16U);
 249         }
 250 }
 251
 252 static int snprintk_buf(u8 * output, size_t size, const u8 * data, size_t len)
 253 {
 254         size_t out = size;
 255         u32 ofs = 0;
 256         int total = 0;
 257
 258         while (size && len) {
 259                 out = snprint_line(output, size, &data[ofs],
 260                                    min_t(size_t, len, 16U), ofs);
 261
 262                 ofs += 16;
 263                 output += out;
 264                 size -= out;
 265                 len -= min_t(size_t, len, 16U);
 266                 total += out;
 267         }
 268         return total;
 269 }
 270
 271 /* alias for 32-bit indirect read (for SRAM/reg above 4K), with debug wrapper */
 272 static u32 _ipw_read_reg32(struct ipw_priv *priv, u32 reg);
 273 #define ipw_read_reg32(a, b) _ipw_read_reg32(a, b)
 274
 275 /* alias for 8-bit indirect read (for SRAM/reg above 4K), with debug wrapper */
 276 static u8 _ipw_read_reg8(struct ipw_priv *ipw, u32 reg);
 277 #define ipw_read_reg8(a, b) _ipw_read_reg8(a, b)
 278
 279 /* 8-bit indirect write (for SRAM/reg above 4K), with debug wrapper */
 280 static void _ipw_write_reg8(struct ipw_priv *priv, u32 reg, u8 value);
 281 static inline void ipw_write_reg8(struct ipw_priv *a, u32 b, u8 c)
 282 {
 283         IPW_DEBUG_IO("%s %d: write_indirect8(0x%08X, 0x%08X)\n", __FILE__,
 284                      __LINE__, (u32) (b), (u32) (c));
 285         _ipw_write_reg8(a, b, c);
 286 }
 287
 288 /* 16-bit indirect write (for SRAM/reg above 4K), with debug wrapper */
 289 static void _ipw_write_reg16(struct ipw_priv *priv, u32 reg, u16 value);
 290 static inline void ipw_write_reg16(struct ipw_priv *a, u32 b, u16 c)
 291 {
 292         IPW_DEBUG_IO("%s %d: write_indirect16(0x%08X, 0x%08X)\n", __FILE__,
 293                      __LINE__, (u32) (b), (u32) (c));
 294         _ipw_write_reg16(a, b, c);
 295 }
 296
 297 /* 32-bit indirect write (for SRAM/reg above 4K), with debug wrapper */
 298 static void _ipw_write_reg32(struct ipw_priv *priv, u32 reg, u32 value);
 299 static inline void ipw_write_reg32(struct ipw_priv *a, u32 b, u32 c)
 300 {
 301         IPW_DEBUG_IO("%s %d: write_indirect32(0x%08X, 0x%08X)\n", __FILE__,
 302                      __LINE__, (u32) (b), (u32) (c));
 303         _ipw_write_reg32(a, b, c);
 304 }
 305
 306 /* 8-bit direct write (low 4K) */
 307 #define _ipw_write8(ipw, ofs, val) writeb((val), (ipw)->hw_base + (ofs))
 308
 309 /* 8-bit direct write (for low 4K of SRAM/regs), with debug wrapper */
 310 #define ipw_write8(ipw, ofs, val) \
 311  IPW_DEBUG_IO("%s %d: write_direct8(0x%08X, 0x%08X)\n", __FILE__, __LINE__, (u32)(ofs), (u32)(val)); \
 312  _ipw_write8(ipw, ofs, val)
 313
 314 /* 16-bit direct write (low 4K) */
 315 #define _ipw_write16(ipw, ofs, val) writew((val), (ipw)->hw_base + (ofs))
 316
 317 /* 16-bit direct write (for low 4K of SRAM/regs), with debug wrapper */
 318 #define ipw_write16(ipw, ofs, val) \
 319  IPW_DEBUG_IO("%s %d: write_direct16(0x%08X, 0x%08X)\n", __FILE__, __LINE__, (u32)(ofs), (u32)(val)); \
 320  _ipw_write16(ipw, ofs, val)
 321
 322 /* 32-bit direct write (low 4K) */
 323 #define _ipw_write32(ipw, ofs, val) writel((val), (ipw)->hw_base + (ofs))
 324
 325 /* 32-bit direct write (for low 4K of SRAM/regs), with debug wrapper */
 326 #define ipw_write32(ipw, ofs, val) \
 327  IPW_DEBUG_IO("%s %d: write_direct32(0x%08X, 0x%08X)\n", __FILE__, __LINE__, (u32)(ofs), (u32)(val)); \
 328  _ipw_write32(ipw, ofs, val)
 329
 330 /* 8-bit direct read (low 4K) */
 331 #define _ipw_read8(ipw, ofs) readb((ipw)->hw_base + (ofs))
 332
 333 /* 8-bit direct read (low 4K), with debug wrapper */
 334 static inline u8 __ipw_read8(char *f, u32 l, struct ipw_priv *ipw, u32 ofs)
 335 {
 336         IPW_DEBUG_IO("%s %d: read_direct8(0x%08X)\n", f, l, (u32) (ofs));
 337         return _ipw_read8(ipw, ofs);
 338 }
 339
 340 /* alias to 8-bit direct read (low 4K of SRAM/regs), with debug wrapper */
 341 #define ipw_read8(ipw, ofs) __ipw_read8(__FILE__, __LINE__, ipw, ofs)
 342
 343 /* 16-bit direct read (low 4K) */
 344 #define _ipw_read16(ipw, ofs) readw((ipw)->hw_base + (ofs))
 345
 346 /* 16-bit direct read (low 4K), with debug wrapper */
 347 static inline u16 __ipw_read16(char *f, u32 l, struct ipw_priv *ipw, u32 ofs)
 348 {
 349         IPW_DEBUG_IO("%s %d: read_direct16(0x%08X)\n", f, l, (u32) (ofs));
 350         return _ipw_read16(ipw, ofs);
 351 }
 352
 353 /* alias to 16-bit direct read (low 4K of SRAM/regs), with debug wrapper */
 354 #define ipw_read16(ipw, ofs) __ipw_read16(__FILE__, __LINE__, ipw, ofs)
 355
 356 /* 32-bit direct read (low 4K) */
 357 #define _ipw_read32(ipw, ofs) readl((ipw)->hw_base + (ofs))
 358
 359 /* 32-bit direct read (low 4K), with debug wrapper */
 360 static inline u32 __ipw_read32(char *f, u32 l, struct ipw_priv *ipw, u32 ofs)
 361 {
 362         IPW_DEBUG_IO("%s %d: read_direct32(0x%08X)\n", f, l, (u32) (ofs));
 363         return _ipw_read32(ipw, ofs);
 364 }
 365
 366 /* alias to 32-bit direct read (low 4K of SRAM/regs), with debug wrapper */
 367 #define ipw_read32(ipw, ofs) __ipw_read32(__FILE__, __LINE__, ipw, ofs)
 368
 369 /* multi-byte read (above 4K), with debug wrapper */
 370 static void _ipw_read_indirect(struct ipw_priv *, u32, u8 *, int);
 371 static inline void __ipw_read_indirect(const char *f, int l,
 372                                        struct ipw_priv *a, u32 b, u8 * c, int d)
 373 {
 374         IPW_DEBUG_IO("%s %d: read_indirect(0x%08X) %d bytes\n", f, l, (u32) (b),
 375                      d);
 376         _ipw_read_indirect(a, b, c, d);
 377 }
 378
 379 /* alias to multi-byte read (SRAM/regs above 4K), with debug wrapper */
 380 #define ipw_read_indirect(a, b, c, d) __ipw_read_indirect(__FILE__, __LINE__, a, b, c, d)
 381
 382 /* alias to multi-byte read (SRAM/regs above 4K), with debug wrapper */
 383 static void _ipw_write_indirect(struct ipw_priv *priv, u32 addr, u8 * data,
 384                                 int num);
 385 #define ipw_write_indirect(a, b, c, d) \
 386         IPW_DEBUG_IO("%s %d: write_indirect(0x%08X) %d bytes\n", __FILE__, __LINE__, (u32)(b), d); \
 387         _ipw_write_indirect(a, b, c, d)
 388
 389 /* 32-bit indirect write (above 4K) */
 390 static void _ipw_write_reg32(struct ipw_priv *priv, u32 reg, u32 value)
 391 {
 392         IPW_DEBUG_IO(" %p : reg = 0x%8X : value = 0x%8X\n", priv, reg, value);
 393         _ipw_write32(priv, IPW_INDIRECT_ADDR, reg);
 394         _ipw_write32(priv, IPW_INDIRECT_DATA, value);
 395 }
 396
 397 /* 8-bit indirect write (above 4K) */
 398 static void _ipw_write_reg8(struct ipw_priv *priv, u32 reg, u8 value)
 399 {
 400         u32 aligned_addr = reg & IPW_INDIRECT_ADDR_MASK;        /* dword align */
 401         u32 dif_len = reg - aligned_addr;
 402
 403         IPW_DEBUG_IO(" reg = 0x%8X : value = 0x%8X\n", reg, value);
 404         _ipw_write32(priv, IPW_INDIRECT_ADDR, aligned_addr);
 405         _ipw_write8(priv, IPW_INDIRECT_DATA + dif_len, value);
 406 }
 407
 408 /* 16-bit indirect write (above 4K) */
 409 static void _ipw_write_reg16(struct ipw_priv *priv, u32 reg, u16 value)
 410 {
 411         u32 aligned_addr = reg & IPW_INDIRECT_ADDR_MASK;        /* dword align */
 412         u32 dif_len = (reg - aligned_addr) & (~0x1ul);
 413
 414         IPW_DEBUG_IO(" reg = 0x%8X : value = 0x%8X\n", reg, value);
 415         _ipw_write32(priv, IPW_INDIRECT_ADDR, aligned_addr);
 416         _ipw_write16(priv, IPW_INDIRECT_DATA + dif_len, value);
 417 }
 418
 419 /* 8-bit indirect read (above 4K) */
 420 static u8 _ipw_read_reg8(struct ipw_priv *priv, u32 reg)
 421 {
 422         u32 word;
 423         _ipw_write32(priv, IPW_INDIRECT_ADDR, reg & IPW_INDIRECT_ADDR_MASK);
 424         IPW_DEBUG_IO(" reg = 0x%8X : \n", reg);
 425         word = _ipw_read32(priv, IPW_INDIRECT_DATA);
 426         return (word >> ((reg & 0x3) * 8)) & 0xff;
 427 }
 428
 429 /* 32-bit indirect read (above 4K) */
 430 static u32 _ipw_read_reg32(struct ipw_priv *priv, u32 reg)
 431 {
 432         u32 value;
 433
 434         IPW_DEBUG_IO("%p : reg = 0x%08x\n", priv, reg);
 435
 436         _ipw_write32(priv, IPW_INDIRECT_ADDR, reg);
 437         value = _ipw_read32(priv, IPW_INDIRECT_DATA);
 438         IPW_DEBUG_IO(" reg = 0x%4X : value = 0x%4x \n", reg, value);
 439         return value;
 440 }
 441
 442 /* General purpose, no alignment requirement, iterative (multi-byte) read, */
 443 /*    for area above 1st 4K of SRAM/reg space */
 444 static void _ipw_read_indirect(struct ipw_priv *priv, u32 addr, u8 * buf,
 445                                int num)
 446 {
 447         u32 aligned_addr = addr & IPW_INDIRECT_ADDR_MASK;       /* dword align */
 448         u32 dif_len = addr - aligned_addr;
 449         u32 i;
 450
 451         IPW_DEBUG_IO("addr = %i, buf = %p, num = %i\n", addr, buf, num);
 452
 453         if (num <= 0) {
 454                 return;
 455         }
 456
 457         /* Read the first dword (or portion) byte by byte */
 458         if (unlikely(dif_len)) {
 459                 _ipw_write32(priv, IPW_INDIRECT_ADDR, aligned_addr);
 460                 /* Start reading at aligned_addr + dif_len */
 461                 for (i = dif_len; ((i < 4) && (num > 0)); i++, num--)
 462                         *buf++ = _ipw_read8(priv, IPW_INDIRECT_DATA + i);
 463                 aligned_addr += 4;
 464         }
 465
 466         /* Read all of the middle dwords as dwords, with auto-increment */
 467         _ipw_write32(priv, IPW_AUTOINC_ADDR, aligned_addr);
 468         for (; num >= 4; buf += 4, aligned_addr += 4, num -= 4)
 469                 *(u32 *) buf = _ipw_read32(priv, IPW_AUTOINC_DATA);
 470
 471         /* Read the last dword (or portion) byte by byte */
 472         if (unlikely(num)) {
 473                 _ipw_write32(priv, IPW_INDIRECT_ADDR, aligned_addr);
 474                 for (i = 0; num > 0; i++, num--)
 475                         *buf++ = ipw_read8(priv, IPW_INDIRECT_DATA + i);
 476         }
 477 }
 478
 479 /* General purpose, no alignment requirement, iterative (multi-byte) write, */
 480 /*    for area above 1st 4K of SRAM/reg space */
 481 static void _ipw_write_indirect(struct ipw_priv *priv, u32 addr, u8 * buf,
 482                                 int num)
 483 {
 484         u32 aligned_addr = addr & IPW_INDIRECT_ADDR_MASK;       /* dword align */
 485         u32 dif_len = addr - aligned_addr;
 486         u32 i;
 487
 488         IPW_DEBUG_IO("addr = %i, buf = %p, num = %i\n", addr, buf, num);
 489
 490         if (num <= 0) {
 491                 return;
 492         }
 493
 494         /* Write the first dword (or portion) byte by byte */
 495         if (unlikely(dif_len)) {
 496                 _ipw_write32(priv, IPW_INDIRECT_ADDR, aligned_addr);
 497                 /* Start writing at aligned_addr + dif_len */
 498                 for (i = dif_len; ((i < 4) && (num > 0)); i++, num--, buf++)
 499                         _ipw_write8(priv, IPW_INDIRECT_DATA + i, *buf);
 500                 aligned_addr += 4;
 501         }
 502
 503         /* Write all of the middle dwords as dwords, with auto-increment */
 504         _ipw_write32(priv, IPW_AUTOINC_ADDR, aligned_addr);
 505         for (; num >= 4; buf += 4, aligned_addr += 4, num -= 4)
 506                 _ipw_write32(priv, IPW_AUTOINC_DATA, *(u32 *) buf);
 507
 508         /* Write the last dword (or portion) byte by byte */
 509         if (unlikely(num)) {
 510                 _ipw_write32(priv, IPW_INDIRECT_ADDR, aligned_addr);
 511                 for (i = 0; num > 0; i++, num--, buf++)
 512                         _ipw_write8(priv, IPW_INDIRECT_DATA + i, *buf);
 513         }
 514 }
 515
 516 /* General purpose, no alignment requirement, iterative (multi-byte) write, */
 517 /*    for 1st 4K of SRAM/regs space */
 518 static void ipw_write_direct(struct ipw_priv *priv, u32 addr, void *buf,
 519                              int num)
 520 {
 521         memcpy_toio((priv->hw_base + addr), buf, num);
 522 }
 523
 524 /* Set bit(s) in low 4K of SRAM/regs */
 525 static inline void ipw_set_bit(struct ipw_priv *priv, u32 reg, u32 mask)
 526 {
 527         ipw_write32(priv, reg, ipw_read32(priv, reg) | mask);
 528 }
 529
 530 /* Clear bit(s) in low 4K of SRAM/regs */
 531 static inline void ipw_clear_bit(struct ipw_priv *priv, u32 reg, u32 mask)
 532 {
 533         ipw_write32(priv, reg, ipw_read32(priv, reg) & ~mask);
 534 }
 535
 536 static inline void __ipw_enable_interrupts(struct ipw_priv *priv)
 537 {
 538         if (priv->status & STATUS_INT_ENABLED)
 539                 return;
 540         priv->status |= STATUS_INT_ENABLED;
 541         ipw_write32(priv, IPW_INTA_MASK_R, IPW_INTA_MASK_ALL);
 542 }
 543
 544 static inline void __ipw_disable_interrupts(struct ipw_priv *priv)
 545 {
 546         if (!(priv->status & STATUS_INT_ENABLED))
 547                 return;
 548         priv->status &= ~STATUS_INT_ENABLED;
 549         ipw_write32(priv, IPW_INTA_MASK_R, ~IPW_INTA_MASK_ALL);
 550 }
 551
 552 static inline void ipw_enable_interrupts(struct ipw_priv *priv)
 553 {
 554         unsigned long flags;
 555
 556         spin_lock_irqsave(&priv->irq_lock, flags);
 557         __ipw_enable_interrupts(priv);
 558         spin_unlock_irqrestore(&priv->irq_lock, flags);
 559 }
 560
 561 static inline void ipw_disable_interrupts(struct ipw_priv *priv)
 562 {
 563         unsigned long flags;
 564
 565         spin_lock_irqsave(&priv->irq_lock, flags);
 566         __ipw_disable_interrupts(priv);
 567         spin_unlock_irqrestore(&priv->irq_lock, flags);
 568 }
 569
 570 #ifdef CONFIG_IPW2200_DEBUG
 571 static char *ipw_error_desc(u32 val)
 572 {
 573         switch (val) {
 574         case IPW_FW_ERROR_OK:
 575                 return "ERROR_OK";
 576         case IPW_FW_ERROR_FAIL:
 577                 return "ERROR_FAIL";
 578         case IPW_FW_ERROR_MEMORY_UNDERFLOW:
 579                 return "MEMORY_UNDERFLOW";
 580         case IPW_FW_ERROR_MEMORY_OVERFLOW:
 581                 return "MEMORY_OVERFLOW";
 582         case IPW_FW_ERROR_BAD_PARAM:
 583                 return "BAD_PARAM";
 584         case IPW_FW_ERROR_BAD_CHECKSUM:
 585                 return "BAD_CHECKSUM";
 586         case IPW_FW_ERROR_NMI_INTERRUPT:
 587                 return "NMI_INTERRUPT";
 588         case IPW_FW_ERROR_BAD_DATABASE:
 589                 return "BAD_DATABASE";
 590         case IPW_FW_ERROR_ALLOC_FAIL:
 591                 return "ALLOC_FAIL";
 592         case IPW_FW_ERROR_DMA_UNDERRUN:
 593                 return "DMA_UNDERRUN";
 594         case IPW_FW_ERROR_DMA_STATUS:
 595                 return "DMA_STATUS";
 596         case IPW_FW_ERROR_DINO_ERROR:
 597                 return "DINO_ERROR";
 598         case IPW_FW_ERROR_EEPROM_ERROR:
 599                 return "EEPROM_ERROR";
 600         case IPW_FW_ERROR_SYSASSERT:
 601                 return "SYSASSERT";
 602         case IPW_FW_ERROR_FATAL_ERROR:
 603                 return "FATAL_ERROR";
 604         default:
 605                 return "UNKNOWN_ERROR";
 606         }
 607 }
 608
 609 static void ipw_dump_error_log(struct ipw_priv *priv,
 610                                struct ipw_fw_error *error)
 611 {
 612         u32 i;
 613
 614         if (!error) {
 615                 IPW_ERROR("Error allocating and capturing error log.  "
 616                           "Nothing to dump.\n");
 617                 return;
 618         }
 619
 620         IPW_ERROR("Start IPW Error Log Dump:\n");
 621         IPW_ERROR("Status: 0x%08X, Config: %08X\n",
 622                   error->status, error->config);
 623
 624         for (i = 0; i < error->elem_len; i++)
 625                 IPW_ERROR("%s %i 0x%08x  0x%08x  0x%08x  0x%08x  0x%08x\n",
 626                           ipw_error_desc(error->elem[i].desc),
 627                           error->elem[i].time,
 628                           error->elem[i].blink1,
 629                           error->elem[i].blink2,
 630                           error->elem[i].link1,
 631                           error->elem[i].link2, error->elem[i].data);
 632         for (i = 0; i < error->log_len; i++)
 633                 IPW_ERROR("%i\t0x%08x\t%i\n",
 634                           error->log[i].time,
 635                           error->log[i].data, error->log[i].event);
 636 }
 637 #endif
 638
 639 static inline int ipw_is_init(struct ipw_priv *priv)
 640 {
 641         return (priv->status & STATUS_INIT) ? 1 : 0;
 642 }
 643
 644 static int ipw_get_ordinal(struct ipw_priv *priv, u32 ord, void *val, u32 * len)
 645 {
 646         u32 addr, field_info, field_len, field_count, total_len;
 647
 648         IPW_DEBUG_ORD("ordinal = %i\n", ord);
 649
 650         if (!priv || !val || !len) {
 651                 IPW_DEBUG_ORD("Invalid argument\n");
 652                 return -EINVAL;
 653         }
 654
 655         /* verify device ordinal tables have been initialized */
 656         if (!priv->table0_addr || !priv->table1_addr || !priv->table2_addr) {
 657                 IPW_DEBUG_ORD("Access ordinals before initialization\n");
 658                 return -EINVAL;
 659         }
 660
 661         switch (IPW_ORD_TABLE_ID_MASK & ord) {
 662         case IPW_ORD_TABLE_0_MASK:
 663                 /*
 664                  * TABLE 0: Direct access to a table of 32 bit values
 665                  *
 666                  * This is a very simple table with the data directly
 667                  * read from the table
 668                  */
 669
 670                 /* remove the table id from the ordinal */
 671                 ord &= IPW_ORD_TABLE_VALUE_MASK;
 672
 673                 /* boundary check */
 674                 if (ord > priv->table0_len) {
 675                         IPW_DEBUG_ORD("ordinal value (%i) longer then "
 676                                       "max (%i)\n", ord, priv->table0_len);
 677                         return -EINVAL;
 678                 }
 679
 680                 /* verify we have enough room to store the value */
 681                 if (*len < sizeof(u32)) {
 682                         IPW_DEBUG_ORD("ordinal buffer length too small, "
 683                                       "need %zd\n", sizeof(u32));
 684                         return -EINVAL;
 685                 }
 686
 687                 IPW_DEBUG_ORD("Reading TABLE0[%i] from offset 0x%08x\n",
 688                               ord, priv->table0_addr + (ord << 2));
 689
 690                 *len = sizeof(u32);
 691                 ord <<= 2;
 692                 *((u32 *) val) = ipw_read32(priv, priv->table0_addr + ord);
 693                 break;
 694
 695         case IPW_ORD_TABLE_1_MASK:
 696                 /*
 697                  * TABLE 1: Indirect access to a table of 32 bit values
 698                  *
 699                  * This is a fairly large table of u32 values each
 700                  * representing starting addr for the data (which is
 701                  * also a u32)
 702                  */
 703
 704                 /* remove the table id from the ordinal */
 705                 ord &= IPW_ORD_TABLE_VALUE_MASK;
 706
 707                 /* boundary check */
 708                 if (ord > priv->table1_len) {
 709                         IPW_DEBUG_ORD("ordinal value too long\n");
 710                         return -EINVAL;
 711                 }
 712
 713                 /* verify we have enough room to store the value */
 714                 if (*len < sizeof(u32)) {
 715                         IPW_DEBUG_ORD("ordinal buffer length too small, "
 716                                       "need %zd\n", sizeof(u32));
 717                         return -EINVAL;
 718                 }
 719
 720                 *((u32 *) val) =
 721                     ipw_read_reg32(priv, (priv->table1_addr + (ord << 2)));
 722                 *len = sizeof(u32);
 723                 break;
 724
 725         case IPW_ORD_TABLE_2_MASK:
 726                 /*
 727                  * TABLE 2: Indirect access to a table of variable sized values
 728                  *
 729                  * This table consist of six values, each containing
 730                  *     - dword containing the starting offset of the data
 731                  *     - dword containing the lengh in the first 16bits
 732                  *       and the count in the second 16bits
 733                  */
 734
 735                 /* remove the table id from the ordinal */
 736                 ord &= IPW_ORD_TABLE_VALUE_MASK;
 737
 738                 /* boundary check */
 739                 if (ord > priv->table2_len) {
 740                         IPW_DEBUG_ORD("ordinal value too long\n");
 741                         return -EINVAL;
 742                 }
 743
 744                 /* get the address of statistic */
 745                 addr = ipw_read_reg32(priv, priv->table2_addr + (ord << 3));
 746
 747                 /* get the second DW of statistics ;
 748                  * two 16-bit words - first is length, second is count */
 749                 field_info =
 750                     ipw_read_reg32(priv,
 751                                    priv->table2_addr + (ord << 3) +
 752                                    sizeof(u32));
 753
 754                 /* get each entry length */
 755                 field_len = *((u16 *) & field_info);
 756
 757                 /* get number of entries */
 758                 field_count = *(((u16 *) & field_info) + 1);
 759
 760                 /* abort if not enought memory */
 761                 total_len = field_len * field_count;
 762                 if (total_len > *len) {
 763                         *len = total_len;
 764                         return -EINVAL;
 765                 }
 766
 767                 *len = total_len;
 768                 if (!total_len)
 769                         return 0;
 770
 771                 IPW_DEBUG_ORD("addr = 0x%08x, total_len = %i, "
 772                               "field_info = 0x%08x\n",
 773                               addr, total_len, field_info);
 774                 ipw_read_indirect(priv, addr, val, total_len);
 775                 break;
 776
 777         default:
 778                 IPW_DEBUG_ORD("Invalid ordinal!\n");
 779                 return -EINVAL;
 780
 781         }
 782
 783         return 0;
 784 }
 785
 786 static void ipw_init_ordinals(struct ipw_priv *priv)
 787 {
 788         priv->table0_addr = IPW_ORDINALS_TABLE_LOWER;
 789         priv->table0_len = ipw_read32(priv, priv->table0_addr);
 790
 791         IPW_DEBUG_ORD("table 0 offset at 0x%08x, len = %i\n",
 792                       priv->table0_addr, priv->table0_len);
 793
 794         priv->table1_addr = ipw_read32(priv, IPW_ORDINALS_TABLE_1);
 795         priv->table1_len = ipw_read_reg32(priv, priv->table1_addr);
 796
 797         IPW_DEBUG_ORD("table 1 offset at 0x%08x, len = %i\n",
 798                       priv->table1_addr, priv->table1_len);
 799
 800         priv->table2_addr = ipw_read32(priv, IPW_ORDINALS_TABLE_2);
 801         priv->table2_len = ipw_read_reg32(priv, priv->table2_addr);
 802         priv->table2_len &= 0x0000ffff; /* use first two bytes */
 803
 804         IPW_DEBUG_ORD("table 2 offset at 0x%08x, len = %i\n",
 805                       priv->table2_addr, priv->table2_len);
 806
 807 }
 808
 809 static u32 ipw_register_toggle(u32 reg)
 810 {
 811         reg &= ~IPW_START_STANDBY;
 812         if (reg & IPW_GATE_ODMA)
 813                 reg &= ~IPW_GATE_ODMA;
 814         if (reg & IPW_GATE_IDMA)
 815                 reg &= ~IPW_GATE_IDMA;
 816         if (reg & IPW_GATE_ADMA)
 817                 reg &= ~IPW_GATE_ADMA;
 818         return reg;
 819 }
 820
 821 /*
 822  * LED behavior:
 823  * - On radio ON, turn on any LEDs that require to be on during start
 824  * - On initialization, start unassociated blink
 825  * - On association, disable unassociated blink
 826  * - On disassociation, start unassociated blink
 827  * - On radio OFF, turn off any LEDs started during radio on
 828  *
 829  */
 830 #define LD_TIME_LINK_ON msecs_to_jiffies(300)
 831 #define LD_TIME_LINK_OFF msecs_to_jiffies(2700)
 832 #define LD_TIME_ACT_ON msecs_to_jiffies(250)
 833
 834 static void ipw_led_link_on(struct ipw_priv *priv)
 835 {
 836         unsigned long flags;
 837         u32 led;
 838
 839         /* If configured to not use LEDs, or nic_type is 1,
 840          * then we don't toggle a LINK led */
 841         if (priv->config & CFG_NO_LED || priv->nic_type == EEPROM_NIC_TYPE_1)
 842                 return;
 843
 844         spin_lock_irqsave(&priv->lock, flags);
 845
 846         if (!(priv->status & STATUS_RF_KILL_MASK) &&
 847             !(priv->status & STATUS_LED_LINK_ON)) {
 848                 IPW_DEBUG_LED("Link LED On\n");
 849                 led = ipw_read_reg32(priv, IPW_EVENT_REG);
 850                 led |= priv->led_association_on;
 851
 852                 led = ipw_register_toggle(led);
 853
 854                 IPW_DEBUG_LED("Reg: 0x%08X\n", led);
 855                 ipw_write_reg32(priv, IPW_EVENT_REG, led);
 856
 857                 priv->status |= STATUS_LED_LINK_ON;
 858
 859                 /* If we aren't associated, schedule turning the LED off */
 860                 if (!(priv->status & STATUS_ASSOCIATED))
 861                         queue_delayed_work(priv->workqueue,
 862                                            &priv->led_link_off,
 863                                            LD_TIME_LINK_ON);
 864         }
 865
 866         spin_unlock_irqrestore(&priv->lock, flags);
 867 }
 868
 869 static void ipw_bg_led_link_on(void *data)
 870 {
 871         struct ipw_priv *priv = data;
 872         mutex_lock(&priv->mutex);
 873         ipw_led_link_on(data);
 874         mutex_unlock(&priv->mutex);
 875 }
 876
 877 static void ipw_led_link_off(struct ipw_priv *priv)
 878 {
 879         unsigned long flags;
 880         u32 led;
 881
 882         /* If configured not to use LEDs, or nic type is 1,
 883          * then we don't goggle the LINK led. */
 884         if (priv->config & CFG_NO_LED || priv->nic_type == EEPROM_NIC_TYPE_1)
 885                 return;
 886
 887         spin_lock_irqsave(&priv->lock, flags);
 888
 889         if (priv->status & STATUS_LED_LINK_ON) {
 890                 led = ipw_read_reg32(priv, IPW_EVENT_REG);
 891                 led &= priv->led_association_off;
 892                 led = ipw_register_toggle(led);
 893
 894                 IPW_DEBUG_LED("Reg: 0x%08X\n", led);
 895                 ipw_write_reg32(priv, IPW_EVENT_REG, led);
 896
 897                 IPW_DEBUG_LED("Link LED Off\n");
 898
 899                 priv->status &= ~STATUS_LED_LINK_ON;
 900
 901                 /* If we aren't associated and the radio is on, schedule
 902                  * turning the LED on (blink while unassociated) */
 903                 if (!(priv->status & STATUS_RF_KILL_MASK) &&
 904                     !(priv->status & STATUS_ASSOCIATED))
 905                         queue_delayed_work(priv->workqueue, &priv->led_link_on,
 906                                            LD_TIME_LINK_OFF);
 907
 908         }
 909
 910         spin_unlock_irqrestore(&priv->lock, flags);
 911 }
 912
 913 static void ipw_bg_led_link_off(void *data)
 914 {
 915         struct ipw_priv *priv = data;
 916         mutex_lock(&priv->mutex);
 917         ipw_led_link_off(data);
 918         mutex_unlock(&priv->mutex);
 919 }
 920
 921 static void __ipw_led_activity_on(struct ipw_priv *priv)
 922 {
 923         u32 led;
 924
 925         if (priv->config & CFG_NO_LED)
 926                 return;
 927
 928         if (priv->status & STATUS_RF_KILL_MASK)
 929                 return;
 930
 931         if (!(priv->status & STATUS_LED_ACT_ON)) {
 932                 led = ipw_read_reg32(priv, IPW_EVENT_REG);
 933                 led |= priv->led_activity_on;
 934
 935                 led = ipw_register_toggle(led);
 936
 937                 IPW_DEBUG_LED("Reg: 0x%08X\n", led);
 938                 ipw_write_reg32(priv, IPW_EVENT_REG, led);
 939
 940                 IPW_DEBUG_LED("Activity LED On\n");
 941
 942                 priv->status |= STATUS_LED_ACT_ON;
 943
 944                 cancel_delayed_work(&priv->led_act_off);
 945                 queue_delayed_work(priv->workqueue, &priv->led_act_off,
 946                                    LD_TIME_ACT_ON);
 947         } else {
 948                 /* Reschedule LED off for full time period */
 949                 cancel_delayed_work(&priv->led_act_off);
 950                 queue_delayed_work(priv->workqueue, &priv->led_act_off,
 951                                    LD_TIME_ACT_ON);
 952         }
 953 }
 954
 955 #if 0
 956 void ipw_led_activity_on(struct ipw_priv *priv)
 957 {
 958         unsigned long flags;
 959         spin_lock_irqsave(&priv->lock, flags);
 960         __ipw_led_activity_on(priv);
 961         spin_unlock_irqrestore(&priv->lock, flags);
 962 }
 963 #endif  /*  0  */
 964
 965 static void ipw_led_activity_off(struct ipw_priv *priv)
 966 {
 967         unsigned long flags;
 968         u32 led;
 969
 970         if (priv->config & CFG_NO_LED)
 971                 return;
 972
 973         spin_lock_irqsave(&priv->lock, flags);
 974
 975         if (priv->status & STATUS_LED_ACT_ON) {
 976                 led = ipw_read_reg32(priv, IPW_EVENT_REG);
 977                 led &= priv->led_activity_off;
 978
 979                 led = ipw_register_toggle(led);
 980
 981                 IPW_DEBUG_LED("Reg: 0x%08X\n", led);
 982                 ipw_write_reg32(priv, IPW_EVENT_REG, led);
 983
 984                 IPW_DEBUG_LED("Activity LED Off\n");
 985
 986                 priv->status &= ~STATUS_LED_ACT_ON;
 987         }
 988
 989         spin_unlock_irqrestore(&priv->lock, flags);
 990 }
 991
 992 static void ipw_bg_led_activity_off(void *data)
 993 {
 994         struct ipw_priv *priv = data;
 995         mutex_lock(&priv->mutex);
 996         ipw_led_activity_off(data);
 997         mutex_unlock(&priv->mutex);
 998 }
 999
1000 static void ipw_led_band_on(struct ipw_priv *priv)
1001 {
1002         unsigned long flags;
1003         u32 led;
1004
1005         /* Only nic type 1 supports mode LEDs */
1006         if (priv->config & CFG_NO_LED ||
1007             priv->nic_type != EEPROM_NIC_TYPE_1 || !priv->assoc_network)
1008                 return;
1009
1010         spin_lock_irqsave(&priv->lock, flags);
1011
1012         led = ipw_read_reg32(priv, IPW_EVENT_REG);
1013         if (priv->assoc_network->mode == IEEE_A) {
1014                 led |= priv->led_ofdm_on;
1015                 led &= priv->led_association_off;
1016                 IPW_DEBUG_LED("Mode LED On: 802.11a\n");
1017         } else if (priv->assoc_network->mode == IEEE_G) {
1018                 led |= priv->led_ofdm_on;
1019                 led |= priv->led_association_on;
1020                 IPW_DEBUG_LED("Mode LED On: 802.11g\n");
1021         } else {
1022                 led &= priv->led_ofdm_off;
1023                 led |= priv->led_association_on;
1024                 IPW_DEBUG_LED("Mode LED On: 802.11b\n");
1025         }
1026
1027         led = ipw_register_toggle(led);
1028
1029         IPW_DEBUG_LED("Reg: 0x%08X\n", led);
1030         ipw_write_reg32(priv, IPW_EVENT_REG, led);
1031
1032         spin_unlock_irqrestore(&priv->lock, flags);
1033 }
1034
1035 static void ipw_led_band_off(struct ipw_priv *priv)
1036 {
1037         unsigned long flags;
1038         u32 led;
1039
1040         /* Only nic type 1 supports mode LEDs */
1041         if (priv->config & CFG_NO_LED || priv->nic_type != EEPROM_NIC_TYPE_1)
1042                 return;
1043
1044         spin_lock_irqsave(&priv->lock, flags);
1045
1046         led = ipw_read_reg32(priv, IPW_EVENT_REG);
1047         led &= priv->led_ofdm_off;
1048         led &= priv->led_association_off;
1049
1050         led = ipw_register_toggle(led);
1051
1052         IPW_DEBUG_LED("Reg: 0x%08X\n", led);
1053         ipw_write_reg32(priv, IPW_EVENT_REG, led);
1054
1055         spin_unlock_irqrestore(&priv->lock, flags);
1056 }
1057
1058 static void ipw_led_radio_on(struct ipw_priv *priv)
1059 {
1060         ipw_led_link_on(priv);
1061 }
1062
1063 static void ipw_led_radio_off(struct ipw_priv *priv)
1064 {
1065         ipw_led_activity_off(priv);
1066         ipw_led_link_off(priv);
1067 }
1068
1069 static void ipw_led_link_up(struct ipw_priv *priv)
1070 {
1071         /* Set the Link Led on for all nic types */
1072         ipw_led_link_on(priv);
1073 }
1074
1075 static void ipw_led_link_down(struct ipw_priv *priv)
1076 {
1077         ipw_led_activity_off(priv);
1078         ipw_led_link_off(priv);
1079
1080         if (priv->status & STATUS_RF_KILL_MASK)
1081                 ipw_led_radio_off(priv);
1082 }
1083
1084 static void ipw_led_init(struct ipw_priv *priv)
1085 {
1086         priv->nic_type = priv->eeprom[EEPROM_NIC_TYPE];
1087
1088         /* Set the default PINs for the link and activity leds */
1089         priv->led_activity_on = IPW_ACTIVITY_LED;
1090         priv->led_activity_off = ~(IPW_ACTIVITY_LED);
1091
1092         priv->led_association_on = IPW_ASSOCIATED_LED;
1093         priv->led_association_off = ~(IPW_ASSOCIATED_LED);
1094
1095         /* Set the default PINs for the OFDM leds */
1096         priv->led_ofdm_on = IPW_OFDM_LED;
1097         priv->led_ofdm_off = ~(IPW_OFDM_LED);
1098
1099         switch (priv->nic_type) {
1100         case EEPROM_NIC_TYPE_1:
1101                 /* In this NIC type, the LEDs are reversed.... */
1102                 priv->led_activity_on = IPW_ASSOCIATED_LED;
1103                 priv->led_activity_off = ~(IPW_ASSOCIATED_LED);
1104                 priv->led_association_on = IPW_ACTIVITY_LED;
1105                 priv->led_association_off = ~(IPW_ACTIVITY_LED);
1106
1107                 if (!(priv->config & CFG_NO_LED))
1108                         ipw_led_band_on(priv);
1109
1110                 /* And we don't blink link LEDs for this nic, so
1111                  * just return here */
1112                 return;
1113
1114         case EEPROM_NIC_TYPE_3:
1115         case EEPROM_NIC_TYPE_2:
1116         case EEPROM_NIC_TYPE_4:
1117         case EEPROM_NIC_TYPE_0:
1118                 break;
1119
1120         default:
1121                 IPW_DEBUG_INFO("Unknown NIC type from EEPROM: %d\n",
1122                                priv->nic_type);
1123                 priv->nic_type = EEPROM_NIC_TYPE_0;
1124                 break;
1125         }
1126
1127         if (!(priv->config & CFG_NO_LED)) {
1128                 if (priv->status & STATUS_ASSOCIATED)
1129                         ipw_led_link_on(priv);
1130                 else
1131                         ipw_led_link_off(priv);
1132         }
1133 }
1134
1135 static void ipw_led_shutdown(struct ipw_priv *priv)
1136 {
1137         ipw_led_activity_off(priv);
1138         ipw_led_link_off(priv);
1139         ipw_led_band_off(priv);
1140         cancel_delayed_work(&priv->led_link_on);
1141         cancel_delayed_work(&priv->led_link_off);
1142         cancel_delayed_work(&priv->led_act_off);
1143 }
1144
1145 /*
1146  * The following adds a new attribute to the sysfs representation
1147  * of this device driver (i.e. a new file in /sys/bus/pci/drivers/ipw/)
1148  * used for controling the debug level.
1149  *
1150  * See the level definitions in ipw for details.
1151  */
1152 static ssize_t show_debug_level(struct device_driver *d, char *buf)
1153 {
1154         return sprintf(buf, "0x%08X\n", ipw_debug_level);
1155 }
1156
1157 static ssize_t store_debug_level(struct device_driver *d, const char *buf,
1158                                  size_t count)
1159 {
1160         char *p = (char *)buf;
1161         u32 val;
1162
1163         if (p[1] == 'x' || p[1] == 'X' || p[0] == 'x' || p[0] == 'X') {
1164                 p++;
1165                 if (p[0] == 'x' || p[0] == 'X')
1166                         p++;
1167                 val = simple_strtoul(p, &p, 16);
1168         } else
1169                 val = simple_strtoul(p, &p, 10);
1170         if (p == buf)
1171                 printk(KERN_INFO DRV_NAME
1172                        ": %s is not in hex or decimal form.\n", buf);
1173         else
1174                 ipw_debug_level = val;
1175
1176         return strnlen(buf, count);
1177 }
1178
1179 static DRIVER_ATTR(debug_level, S_IWUSR | S_IRUGO,
1180                    show_debug_level, store_debug_level);
1181
1182 static inline u32 ipw_get_event_log_len(struct ipw_priv *priv)
1183 {
1184         /* length = 1st dword in log */
1185         return ipw_read_reg32(priv, ipw_read32(priv, IPW_EVENT_LOG));
1186 }
1187
1188 static void ipw_capture_event_log(struct ipw_priv *priv,
1189                                   u32 log_len, struct ipw_event *log)
1190 {
1191         u32 base;
1192
1193         if (log_len) {
1194                 base = ipw_read32(priv, IPW_EVENT_LOG);
1195                 ipw_read_indirect(priv, base + sizeof(base) + sizeof(u32),
1196                                   (u8 *) log, sizeof(*log) * log_len);
1197         }
1198 }
1199
1200 static struct ipw_fw_error *ipw_alloc_error_log(struct ipw_priv *priv)
1201 {
1202         struct ipw_fw_error *error;
1203         u32 log_len = ipw_get_event_log_len(priv);
1204         u32 base = ipw_read32(priv, IPW_ERROR_LOG);
1205         u32 elem_len = ipw_read_reg32(priv, base);
1206
1207         error = kmalloc(sizeof(*error) +
1208                         sizeof(*error->elem) * elem_len +
1209                         sizeof(*error->log) * log_len, GFP_ATOMIC);
1210         if (!error) {
1211                 IPW_ERROR("Memory allocation for firmware error log "
1212                           "failed.\n");
1213                 return NULL;
1214         }
1215         error->jiffies = jiffies;
1216         error->status = priv->status;
1217         error->config = priv->config;
1218         error->elem_len = elem_len;
1219         error->log_len = log_len;
1220         error->elem = (struct ipw_error_elem *)error->payload;
1221         error->log = (struct ipw_event *)(error->elem + elem_len);
1222
1223         ipw_capture_event_log(priv, log_len, error->log);
1224
1225         if (elem_len)
1226                 ipw_read_indirect(priv, base + sizeof(base), (u8 *) error->elem,
1227                                   sizeof(*error->elem) * elem_len);
1228
1229         return error;
1230 }
1231
1232 static void ipw_free_error_log(struct ipw_fw_error *error)
1233 {
1234         if (error)
1235                 kfree(error);
1236 }
1237
1238 static ssize_t show_event_log(struct device *d,
1239                               struct device_attribute *attr, char *buf)
1240 {
1241         struct ipw_priv *priv = dev_get_drvdata(d);
1242         u32 log_len = ipw_get_event_log_len(priv);
1243         struct ipw_event log[log_len];
1244         u32 len = 0, i;
1245
1246         ipw_capture_event_log(priv, log_len, log);
1247
1248         len += snprintf(buf + len, PAGE_SIZE - len, "%08X", log_len);
1249         for (i = 0; i < log_len; i++)
1250                 len += snprintf(buf + len, PAGE_SIZE - len,
1251                                 "\n%08X%08X%08X",
1252                                 log[i].time, log[i].event, log[i].data);
1253         len += snprintf(buf + len, PAGE_SIZE - len, "\n");
1254         return len;
1255 }
1256
1257 static DEVICE_ATTR(event_log, S_IRUGO, show_event_log, NULL);
1258
1259 static ssize_t show_error(struct device *d,
1260                           struct device_attribute *attr, char *buf)
1261 {
1262         struct ipw_priv *priv = dev_get_drvdata(d);
1263         u32 len = 0, i;
1264         if (!priv->error)
1265                 return 0;
1266         len += snprintf(buf + len, PAGE_SIZE - len,
1267                         "%08lX%08X%08X%08X",
1268                         priv->error->jiffies,
1269                         priv->error->status,
1270                         priv->error->config, priv->error->elem_len);
1271         for (i = 0; i < priv->error->elem_len; i++)
1272                 len += snprintf(buf + len, PAGE_SIZE - len,
1273                                 "\n%08X%08X%08X%08X%08X%08X%08X",
1274                                 priv->error->elem[i].time,
1275                                 priv->error->elem[i].desc,
1276                                 priv->error->elem[i].blink1,
1277                                 priv->error->elem[i].blink2,
1278                                 priv->error->elem[i].link1,
1279                                 priv->error->elem[i].link2,
1280                                 priv->error->elem[i].data);
1281
1282         len += snprintf(buf + len, PAGE_SIZE - len,
1283                         "\n%08X", priv->error->log_len);
1284         for (i = 0; i < priv->error->log_len; i++)
1285                 len += snprintf(buf + len, PAGE_SIZE - len,
1286                                 "\n%08X%08X%08X",
1287                                 priv->error->log[i].time,
1288                                 priv->error->log[i].event,
1289                                 priv->error->log[i].data);
1290         len += snprintf(buf + len, PAGE_SIZE - len, "\n");
1291         return len;
1292 }
1293
1294 static ssize_t clear_error(struct device *d,
1295                            struct device_attribute *attr,
1296                            const char *buf, size_t count)
1297 {
1298         struct ipw_priv *priv = dev_get_drvdata(d);
1299         if (priv->error) {
1300                 ipw_free_error_log(priv->error);
1301                 priv->error = NULL;
1302         }
1303         return count;
1304 }
1305
1306 static DEVICE_ATTR(error, S_IRUGO | S_IWUSR, show_error, clear_error);
1307
1308 static ssize_t show_cmd_log(struct device *d,
1309                             struct device_attribute *attr, char *buf)
1310 {
1311         struct ipw_priv *priv = dev_get_drvdata(d);
1312         u32 len = 0, i;
1313         if (!priv->cmdlog)
1314                 return 0;
1315         for (i = (priv->cmdlog_pos + 1) % priv->cmdlog_len;
1316              (i != priv->cmdlog_pos) && (PAGE_SIZE - len);
1317              i = (i + 1) % priv->cmdlog_len) {
1318                 len +=
1319                     snprintf(buf + len, PAGE_SIZE - len,
1320                              "\n%08lX%08X%08X%08X\n", priv->cmdlog[i].jiffies,
1321                              priv->cmdlog[i].retcode, priv->cmdlog[i].cmd.cmd,
1322                              priv->cmdlog[i].cmd.len);
1323                 len +=
1324                     snprintk_buf(buf + len, PAGE_SIZE - len,
1325                                  (u8 *) priv->cmdlog[i].cmd.param,
1326                                  priv->cmdlog[i].cmd.len);
1327                 len += snprintf(buf + len, PAGE_SIZE - len, "\n");
1328         }
1329         len += snprintf(buf + len, PAGE_SIZE - len, "\n");
1330         return len;
1331 }
1332
1333 static DEVICE_ATTR(cmd_log, S_IRUGO, show_cmd_log, NULL);
1334
1335 #ifdef CONFIG_IPW2200_PROMISCUOUS
1336 static void ipw_prom_free(struct ipw_priv *priv);
1337 static int ipw_prom_alloc(struct ipw_priv *priv);
1338 static ssize_t store_rtap_iface(struct device *d,
1339                          struct device_attribute *attr,
1340                          const char *buf, size_t count)
1341 {
1342         struct ipw_priv *priv = dev_get_drvdata(d);
1343         int rc = 0;
1344
1345         if (count < 1)
1346                 return -EINVAL;
1347
1348         switch (buf[0]) {
1349         case '0':
1350                 if (!rtap_iface)
1351                         return count;
1352
1353                 if (netif_running(priv->prom_net_dev)) {
1354                         IPW_WARNING("Interface is up.  Cannot unregister.\n");
1355                         return count;
1356                 }
1357
1358                 ipw_prom_free(priv);
1359                 rtap_iface = 0;
1360                 break;
1361
1362         case '1':
1363                 if (rtap_iface)
1364                         return count;
1365
1366                 rc = ipw_prom_alloc(priv);
1367                 if (!rc)
1368                         rtap_iface = 1;
1369                 break;
1370
1371         default:
1372                 return -EINVAL;
1373         }
1374
1375         if (rc) {
1376                 IPW_ERROR("Failed to register promiscuous network "
1377                           "device (error %d).\n", rc);
1378         }
1379
1380         return count;
1381 }
1382
1383 static ssize_t show_rtap_iface(struct device *d,
1384                         struct device_attribute *attr,
1385                         char *buf)
1386 {
1387         struct ipw_priv *priv = dev_get_drvdata(d);
1388         if (rtap_iface)
1389                 return sprintf(buf, "%s", priv->prom_net_dev->name);
1390         else {
1391                 buf[0] = '-';
1392                 buf[1] = '1';
1393                 buf[2] = '\0';
1394                 return 3;
1395         }
1396 }
1397
1398 static DEVICE_ATTR(rtap_iface, S_IWUSR | S_IRUSR, show_rtap_iface,
1399                    store_rtap_iface);
1400
1401 static ssize_t store_rtap_filter(struct device *d,
1402                          struct device_attribute *attr,
1403                          const char *buf, size_t count)
1404 {
1405         struct ipw_priv *priv = dev_get_drvdata(d);
1406
1407         if (!priv->prom_priv) {
1408                 IPW_ERROR("Attempting to set filter without "
1409                           "rtap_iface enabled.\n");
1410                 return -EPERM;
1411         }
1412
1413         priv->prom_priv->filter = simple_strtol(buf, NULL, 0);
1414
1415         IPW_DEBUG_INFO("Setting rtap filter to " BIT_FMT16 "\n",
1416                        BIT_ARG16(priv->prom_priv->filter));
1417
1418         return count;
1419 }
1420
1421 static ssize_t show_rtap_filter(struct device *d,
1422                         struct device_attribute *attr,
1423                         char *buf)
1424 {
1425         struct ipw_priv *priv = dev_get_drvdata(d);
1426         return sprintf(buf, "0x%04X",
1427                        priv->prom_priv ? priv->prom_priv->filter : 0);
1428 }
1429
1430 static DEVICE_ATTR(rtap_filter, S_IWUSR | S_IRUSR, show_rtap_filter,
1431                    store_rtap_filter);
1432 #endif
1433
1434 static ssize_t show_scan_age(struct device *d, struct device_attribute *attr,
1435                              char *buf)
1436 {
1437         struct ipw_priv *priv = dev_get_drvdata(d);
1438         return sprintf(buf, "%d\n", priv->ieee->scan_age);
1439 }
1440
1441 static ssize_t store_scan_age(struct device *d, struct device_attribute *attr,
1442                               const char *buf, size_t count)
1443 {
1444         struct ipw_priv *priv = dev_get_drvdata(d);
1445 #ifdef CONFIG_IPW2200_DEBUG
1446         struct net_device *dev = priv->net_dev;
1447 #endif
1448         char buffer[] = "00000000";
1449         unsigned long len =
1450             (sizeof(buffer) - 1) > count ? count : sizeof(buffer) - 1;
1451         unsigned long val;
1452         char *p = buffer;
1453
1454         IPW_DEBUG_INFO("enter\n");
1455
1456         strncpy(buffer, buf, len);
1457         buffer[len] = 0;
1458
1459         if (p[1] == 'x' || p[1] == 'X' || p[0] == 'x' || p[0] == 'X') {
1460                 p++;
1461                 if (p[0] == 'x' || p[0] == 'X')
1462                         p++;
1463                 val = simple_strtoul(p, &p, 16);
1464         } else
1465                 val = simple_strtoul(p, &p, 10);
1466         if (p == buffer) {
1467                 IPW_DEBUG_INFO("%s: user supplied invalid value.\n", dev->name);
1468         } else {
1469                 priv->ieee->scan_age = val;
1470                 IPW_DEBUG_INFO("set scan_age = %u\n", priv->ieee->scan_age);
1471         }
1472
1473         IPW_DEBUG_INFO("exit\n");
1474         return len;
1475 }
1476
1477 static DEVICE_ATTR(scan_age, S_IWUSR | S_IRUGO, show_scan_age, store_scan_age);
1478
1479 static ssize_t show_led(struct device *d, struct device_attribute *attr,
1480                         char *buf)
1481 {
1482         struct ipw_priv *priv = dev_get_drvdata(d);
1483         return sprintf(buf, "%d\n", (priv->config & CFG_NO_LED) ? 0 : 1);
1484 }
1485
1486 static ssize_t store_led(struct device *d, struct device_attribute *attr,
1487                          const char *buf, size_t count)
1488 {
1489         struct ipw_priv *priv = dev_get_drvdata(d);
1490
1491         IPW_DEBUG_INFO("enter\n");
1492
1493         if (count == 0)
1494                 return 0;
1495
1496         if (*buf == 0) {
1497                 IPW_DEBUG_LED("Disabling LED control.\n");
1498                 priv->config |= CFG_NO_LED;
1499                 ipw_led_shutdown(priv);
1500         } else {
1501                 IPW_DEBUG_LED("Enabling LED control.\n");
1502                 priv->config &= ~CFG_NO_LED;
1503                 ipw_led_init(priv);
1504         }
1505
1506         IPW_DEBUG_INFO("exit\n");
1507         return count;
1508 }
1509
1510 static DEVICE_ATTR(led, S_IWUSR | S_IRUGO, show_led, store_led);
1511
1512 static ssize_t show_status(struct device *d,
1513                            struct device_attribute *attr, char *buf)
1514 {
1515         struct ipw_priv *p = d->driver_data;
1516         return sprintf(buf, "0x%08x\n", (int)p->status);
1517 }
1518
1519 static DEVICE_ATTR(status, S_IRUGO, show_status, NULL);
1520
1521 static ssize_t show_cfg(struct device *d, struct device_attribute *attr,
1522                         char *buf)
1523 {
1524         struct ipw_priv *p = d->driver_data;
1525         return sprintf(buf, "0x%08x\n", (int)p->config);
1526 }
1527
1528 static DEVICE_ATTR(cfg, S_IRUGO, show_cfg, NULL);
1529
1530 static ssize_t show_nic_type(struct device *d,
1531                              struct device_attribute *attr, char *buf)
1532 {
1533         struct ipw_priv *priv = d->driver_data;
1534         return sprintf(buf, "TYPE: %d\n", priv->nic_type);
1535 }
1536
1537 static DEVICE_ATTR(nic_type, S_IRUGO, show_nic_type, NULL);
1538
1539 static ssize_t show_ucode_version(struct device *d,
1540                                   struct device_attribute *attr, char *buf)
1541 {
1542         u32 len = sizeof(u32), tmp = 0;
1543         struct ipw_priv *p = d->driver_data;
1544
1545         if (ipw_get_ordinal(p, IPW_ORD_STAT_UCODE_VERSION, &tmp, &len))
1546                 return 0;
1547
1548         return sprintf(buf, "0x%08x\n", tmp);
1549 }
1550
1551 static DEVICE_ATTR(ucode_version, S_IWUSR | S_IRUGO, show_ucode_version, NULL);
1552
1553 static ssize_t show_rtc(struct device *d, struct device_attribute *attr,
1554                         char *buf)
1555 {
1556         u32 len = sizeof(u32), tmp = 0;
1557         struct ipw_priv *p = d->driver_data;
1558
1559         if (ipw_get_ordinal(p, IPW_ORD_STAT_RTC, &tmp, &len))
1560                 return 0;
1561
1562         return sprintf(buf, "0x%08x\n", tmp);
1563 }
1564
1565 static DEVICE_ATTR(rtc, S_IWUSR | S_IRUGO, show_rtc, NULL);
1566
1567 /*
1568  * Add a device attribute to view/control the delay between eeprom
1569  * operations.
1570  */
1571 static ssize_t show_eeprom_delay(struct device *d,
1572                                  struct device_attribute *attr, char *buf)
1573 {
1574         int n = ((struct ipw_priv *)d->driver_data)->eeprom_delay;
1575         return sprintf(buf, "%i\n", n);
1576 }
1577 static ssize_t store_eeprom_delay(struct device *d,
1578                                   struct device_attribute *attr,
1579                                   const char *buf, size_t count)
1580 {
1581         struct ipw_priv *p = d->driver_data;
1582         sscanf(buf, "%i", &p->eeprom_delay);
1583         return strnlen(buf, count);
1584 }
1585
1586 static DEVICE_ATTR(eeprom_delay, S_IWUSR | S_IRUGO,
1587                    show_eeprom_delay, store_eeprom_delay);
1588
1589 static ssize_t show_command_event_reg(struct device *d,
1590                                       struct device_attribute *attr, char *buf)
1591 {
1592         u32 reg = 0;
1593         struct ipw_priv *p = d->driver_data;
1594
1595         reg = ipw_read_reg32(p, IPW_INTERNAL_CMD_EVENT);
1596         return sprintf(buf, "0x%08x\n", reg);
1597 }
1598 static ssize_t store_command_event_reg(struct device *d,
1599                                        struct device_attribute *attr,
1600                                        const char *buf, size_t count)
1601 {
1602         u32 reg;
1603         struct ipw_priv *p = d->driver_data;
1604
1605         sscanf(buf, "%x", &reg);
1606         ipw_write_reg32(p, IPW_INTERNAL_CMD_EVENT, reg);
1607         return strnlen(buf, count);
1608 }
1609
1610 static DEVICE_ATTR(command_event_reg, S_IWUSR | S_IRUGO,
1611                    show_command_event_reg, store_command_event_reg);
1612
1613 static ssize_t show_mem_gpio_reg(struct device *d,
1614                                  struct device_attribute *attr, char *buf)
1615 {
1616         u32 reg = 0;
1617         struct ipw_priv *p = d->driver_data;
1618
1619         reg = ipw_read_reg32(p, 0x301100);
1620         return sprintf(buf, "0x%08x\n", reg);
1621 }
1622 static ssize_t store_mem_gpio_reg(struct device *d,
1623                                   struct device_attribute *attr,
1624                                   const char *buf, size_t count)
1625 {
1626         u32 reg;
1627         struct ipw_priv *p = d->driver_data;
1628
1629         sscanf(buf, "%x", &reg);
1630         ipw_write_reg32(p, 0x301100, reg);
1631         return strnlen(buf, count);
1632 }
1633
1634 static DEVICE_ATTR(mem_gpio_reg, S_IWUSR | S_IRUGO,
1635                    show_mem_gpio_reg, store_mem_gpio_reg);
1636
1637 static ssize_t show_indirect_dword(struct device *d,
1638                                    struct device_attribute *attr, char *buf)
1639 {
1640         u32 reg = 0;
1641         struct ipw_priv *priv = d->driver_data;
1642
1643         if (priv->status & STATUS_INDIRECT_DWORD)
1644                 reg = ipw_read_reg32(priv, priv->indirect_dword);
1645         else
1646                 reg = 0;
1647
1648         return sprintf(buf, "0x%08x\n", reg);
1649 }
1650 static ssize_t store_indirect_dword(struct device *d,
1651                                     struct device_attribute *attr,
1652                                     const char *buf, size_t count)
1653 {
1654         struct ipw_priv *priv = d->driver_data;
1655
1656         sscanf(buf, "%x", &priv->indirect_dword);
1657         priv->status |= STATUS_INDIRECT_DWORD;
1658         return strnlen(buf, count);
1659 }
1660
1661 static DEVICE_ATTR(indirect_dword, S_IWUSR | S_IRUGO,
1662                    show_indirect_dword, store_indirect_dword);
1663
1664 static ssize_t show_indirect_byte(struct device *d,
1665                                   struct device_attribute *attr, char *buf)
1666 {
1667         u8 reg = 0;
1668         struct ipw_priv *priv = d->driver_data;
1669
1670         if (priv->status & STATUS_INDIRECT_BYTE)
1671                 reg = ipw_read_reg8(priv, priv->indirect_byte);
1672         else
1673                 reg = 0;
1674
1675         return sprintf(buf, "0x%02x\n", reg);
1676 }
1677 static ssize_t store_indirect_byte(struct device *d,
1678                                    struct device_attribute *attr,
1679                                    const char *buf, size_t count)
1680 {
1681         struct ipw_priv *priv = d->driver_data;
1682
1683         sscanf(buf, "%x", &priv->indirect_byte);
1684         priv->status |= STATUS_INDIRECT_BYTE;
1685         return strnlen(buf, count);
1686 }
1687
1688 static DEVICE_ATTR(indirect_byte, S_IWUSR | S_IRUGO,
1689                    show_indirect_byte, store_indirect_byte);
1690
1691 static ssize_t show_direct_dword(struct device *d,
1692                                  struct device_attribute *attr, char *buf)
1693 {
1694         u32 reg = 0;
1695         struct ipw_priv *priv = d->driver_data;
1696
1697         if (priv->status & STATUS_DIRECT_DWORD)
1698                 reg = ipw_read32(priv, priv->direct_dword);
1699         else
1700                 reg = 0;
1701
1702         return sprintf(buf, "0x%08x\n", reg);
1703 }
1704 static ssize_t store_direct_dword(struct device *d,
1705                                   struct device_attribute *attr,
1706                                   const char *buf, size_t count)
1707 {
1708         struct ipw_priv *priv = d->driver_data;
1709
1710         sscanf(buf, "%x", &priv->direct_dword);
1711         priv->status |= STATUS_DIRECT_DWORD;
1712         return strnlen(buf, count);
1713 }
1714
1715 static DEVICE_ATTR(direct_dword, S_IWUSR | S_IRUGO,
1716                    show_direct_dword, store_direct_dword);
1717
1718 static int rf_kill_active(struct ipw_priv *priv)
1719 {
1720         if (0 == (ipw_read32(priv, 0x30) & 0x10000))
1721                 priv->status |= STATUS_RF_KILL_HW;
1722         else
1723                 priv->status &= ~STATUS_RF_KILL_HW;
1724
1725         return (priv->status & STATUS_RF_KILL_HW) ? 1 : 0;
1726 }
1727
1728 static ssize_t show_rf_kill(struct device *d, struct device_attribute *attr,
1729                             char *buf)
1730 {
1731         /* 0 - RF kill not enabled
1732            1 - SW based RF kill active (sysfs)
1733            2 - HW based RF kill active
1734            3 - Both HW and SW baed RF kill active */
1735         struct ipw_priv *priv = d->driver_data;
1736         int val = ((priv->status & STATUS_RF_KILL_SW) ? 0x1 : 0x0) |
1737             (rf_kill_active(priv) ? 0x2 : 0x0);
1738         return sprintf(buf, "%i\n", val);
1739 }
1740
1741 static int ipw_radio_kill_sw(struct ipw_priv *priv, int disable_radio)
1742 {
1743         if ((disable_radio ? 1 : 0) ==
1744             ((priv->status & STATUS_RF_KILL_SW) ? 1 : 0))
1745                 return 0;
1746
1747         IPW_DEBUG_RF_KILL("Manual SW RF Kill set to: RADIO  %s\n",
1748                           disable_radio ? "OFF" : "ON");
1749
1750         if (disable_radio) {
1751                 priv->status |= STATUS_RF_KILL_SW;
1752
1753                 if (priv->workqueue)
1754                         cancel_delayed_work(&priv->request_scan);
1755                 queue_work(priv->workqueue, &priv->down);
1756         } else {
1757                 priv->status &= ~STATUS_RF_KILL_SW;
1758                 if (rf_kill_active(priv)) {
1759                         IPW_DEBUG_RF_KILL("Can not turn radio back on - "
1760                                           "disabled by HW switch\n");
1761                         /* Make sure the RF_KILL check timer is running */
1762                         cancel_delayed_work(&priv->rf_kill);
1763                         queue_delayed_work(priv->workqueue, &priv->rf_kill,
1764                                            2 * HZ);
1765                 } else
1766                         queue_work(priv->workqueue, &priv->up);
1767         }
1768
1769         return 1;
1770 }
1771
1772 static ssize_t store_rf_kill(struct device *d, struct device_attribute *attr,
1773                              const char *buf, size_t count)
1774 {
1775         struct ipw_priv *priv = d->driver_data;
1776
1777         ipw_radio_kill_sw(priv, buf[0] == '1');
1778
1779         return count;
1780 }
1781
1782 static DEVICE_ATTR(rf_kill, S_IWUSR | S_IRUGO, show_rf_kill, store_rf_kill);
1783
1784 static ssize_t show_speed_scan(struct device *d, struct device_attribute *attr,
1785                                char *buf)
1786 {
1787         struct ipw_priv *priv = (struct ipw_priv *)d->driver_data;
1788         int pos = 0, len = 0;
1789         if (priv->config & CFG_SPEED_SCAN) {
1790                 while (priv->speed_scan[pos] != 0)
1791                         len += sprintf(&buf[len], "%d ",
1792                                        priv->speed_scan[pos++]);
1793                 return len + sprintf(&buf[len], "\n");
1794         }
1795
1796         return sprintf(buf, "0\n");
1797 }
1798
1799 static ssize_t store_speed_scan(struct device *d, struct device_attribute *attr,
1800                                 const char *buf, size_t count)
1801 {
1802         struct ipw_priv *priv = (struct ipw_priv *)d->driver_data;
1803         int channel, pos = 0;
1804         const char *p = buf;
1805
1806         /* list of space separated channels to scan, optionally ending with 0 */
1807         while ((channel = simple_strtol(p, NULL, 0))) {
1808                 if (pos == MAX_SPEED_SCAN - 1) {
1809                         priv->speed_scan[pos] = 0;
1810                         break;
1811                 }
1812
1813                 if (ieee80211_is_valid_channel(priv->ieee, channel))
1814                         priv->speed_scan[pos++] = channel;
1815                 else
1816                         IPW_WARNING("Skipping invalid channel request: %d\n",
1817                                     channel);
1818                 p = strchr(p, ' ');
1819                 if (!p)
1820                         break;
1821                 while (*p == ' ' || *p == '\t')
1822                         p++;
1823         }
1824
1825         if (pos == 0)
1826                 priv->config &= ~CFG_SPEED_SCAN;
1827         else {
1828                 priv->speed_scan_pos = 0;
1829                 priv->config |= CFG_SPEED_SCAN;
1830         }
1831
1832         return count;
1833 }
1834
1835 static DEVICE_ATTR(speed_scan, S_IWUSR | S_IRUGO, show_speed_scan,
1836                    store_speed_scan);
1837
1838 static ssize_t show_net_stats(struct device *d, struct device_attribute *attr,
1839                               char *buf)
1840 {
1841         struct ipw_priv *priv = (struct ipw_priv *)d->driver_data;
1842         return sprintf(buf, "%c\n", (priv->config & CFG_NET_STATS) ? '1' : '0');
1843 }
1844
1845 static ssize_t store_net_stats(struct device *d, struct device_attribute *attr,
1846                                const char *buf, size_t count)
1847 {
1848         struct ipw_priv *priv = (struct ipw_priv *)d->driver_data;
1849         if (buf[0] == '1')
1850                 priv->config |= CFG_NET_STATS;
1851         else
1852                 priv->config &= ~CFG_NET_STATS;
1853
1854         return count;
1855 }
1856
1857 static DEVICE_ATTR(net_stats, S_IWUSR | S_IRUGO,
1858                    show_net_stats, store_net_stats);
1859
1860 static void notify_wx_assoc_event(struct ipw_priv *priv)
1861 {
1862         union iwreq_data wrqu;
1863         wrqu.ap_addr.sa_family = ARPHRD_ETHER;
1864         if (priv->status & STATUS_ASSOCIATED)
1865                 memcpy(wrqu.ap_addr.sa_data, priv->bssid, ETH_ALEN);
1866         else
1867                 memset(wrqu.ap_addr.sa_data, 0, ETH_ALEN);
1868         wireless_send_event(priv->net_dev, SIOCGIWAP, &wrqu, NULL);
1869 }
1870
1871 static void ipw_irq_tasklet(struct ipw_priv *priv)
1872 {
1873         u32 inta, inta_mask, handled = 0;
1874         unsigned long flags;
1875         int rc = 0;
1876
1877         spin_lock_irqsave(&priv->irq_lock, flags);
1878
1879         inta = ipw_read32(priv, IPW_INTA_RW);
1880         inta_mask = ipw_read32(priv, IPW_INTA_MASK_R);
1881         inta &= (IPW_INTA_MASK_ALL & inta_mask);
1882
1883         /* Add any cached INTA values that need to be handled */
1884         inta |= priv->isr_inta;
1885
1886         spin_unlock_irqrestore(&priv->irq_lock, flags);
1887
1888         spin_lock_irqsave(&priv->lock, flags);
1889
1890         /* handle all the justifications for the interrupt */
1891         if (inta & IPW_INTA_BIT_RX_TRANSFER) {
1892                 ipw_rx(priv);
1893                 handled |= IPW_INTA_BIT_RX_TRANSFER;
1894         }
1895
1896         if (inta & IPW_INTA_BIT_TX_CMD_QUEUE) {
1897                 IPW_DEBUG_HC("Command completed.\n");
1898                 rc = ipw_queue_tx_reclaim(priv, &priv->txq_cmd, -1);
1899                 priv->status &= ~STATUS_HCMD_ACTIVE;
1900                 wake_up_interruptible(&priv->wait_command_queue);
1901                 handled |= IPW_INTA_BIT_TX_CMD_QUEUE;
1902         }
1903
1904         if (inta & IPW_INTA_BIT_TX_QUEUE_1) {
1905                 IPW_DEBUG_TX("TX_QUEUE_1\n");
1906                 rc = ipw_queue_tx_reclaim(priv, &priv->txq[0], 0);
1907                 handled |= IPW_INTA_BIT_TX_QUEUE_1;
1908         }
1909
1910         if (inta & IPW_INTA_BIT_TX_QUEUE_2) {
1911                 IPW_DEBUG_TX("TX_QUEUE_2\n");
1912                 rc = ipw_queue_tx_reclaim(priv, &priv->txq[1], 1);
1913                 handled |= IPW_INTA_BIT_TX_QUEUE_2;
1914         }
1915
1916         if (inta & IPW_INTA_BIT_TX_QUEUE_3) {
1917                 IPW_DEBUG_TX("TX_QUEUE_3\n");
1918                 rc = ipw_queue_tx_reclaim(priv, &priv->txq[2], 2);
1919                 handled |= IPW_INTA_BIT_TX_QUEUE_3;
1920         }
1921
1922         if (inta & IPW_INTA_BIT_TX_QUEUE_4) {
1923                 IPW_DEBUG_TX("TX_QUEUE_4\n");
1924                 rc = ipw_queue_tx_reclaim(priv, &priv->txq[3], 3);
1925                 handled |= IPW_INTA_BIT_TX_QUEUE_4;
1926         }
1927
1928         if (inta & IPW_INTA_BIT_STATUS_CHANGE) {
1929                 IPW_WARNING("STATUS_CHANGE\n");
1930                 handled |= IPW_INTA_BIT_STATUS_CHANGE;
1931         }
1932
1933         if (inta & IPW_INTA_BIT_BEACON_PERIOD_EXPIRED) {
1934                 IPW_WARNING("TX_PERIOD_EXPIRED\n");
1935                 handled |= IPW_INTA_BIT_BEACON_PERIOD_EXPIRED;
1936         }
1937
1938         if (inta & IPW_INTA_BIT_SLAVE_MODE_HOST_CMD_DONE) {
1939                 IPW_WARNING("HOST_CMD_DONE\n");
1940                 handled |= IPW_INTA_BIT_SLAVE_MODE_HOST_CMD_DONE;
1941         }
1942
1943         if (inta & IPW_INTA_BIT_FW_INITIALIZATION_DONE) {
1944                 IPW_WARNING("FW_INITIALIZATION_DONE\n");
1945                 handled |= IPW_INTA_BIT_FW_INITIALIZATION_DONE;
1946         }
1947
1948         if (inta & IPW_INTA_BIT_FW_CARD_DISABLE_PHY_OFF_DONE) {
1949                 IPW_WARNING("PHY_OFF_DONE\n");
1950                 handled |= IPW_INTA_BIT_FW_CARD_DISABLE_PHY_OFF_DONE;
1951         }
1952
1953         if (inta & IPW_INTA_BIT_RF_KILL_DONE) {
1954                 IPW_DEBUG_RF_KILL("RF_KILL_DONE\n");
1955                 priv->status |= STATUS_RF_KILL_HW;
1956                 wake_up_interruptible(&priv->wait_command_queue);
1957                 priv->status &= ~(STATUS_ASSOCIATED | STATUS_ASSOCIATING);
1958                 cancel_delayed_work(&priv->request_scan);
1959                 schedule_work(&priv->link_down);
1960                 queue_delayed_work(priv->workqueue, &priv->rf_kill, 2 * HZ);
1961                 handled |= IPW_INTA_BIT_RF_KILL_DONE;
1962         }
1963
1964         if (inta & IPW_INTA_BIT_FATAL_ERROR) {
1965                 IPW_WARNING("Firmware error detected.  Restarting.\n");
1966                 if (priv->error) {
1967                         IPW_DEBUG_FW("Sysfs 'error' log already exists.\n");
1968 #ifdef CONFIG_IPW2200_DEBUG
1969                         if (ipw_debug_level & IPW_DL_FW_ERRORS) {
1970                                 struct ipw_fw_error *error =
1971                                     ipw_alloc_error_log(priv);
1972                                 ipw_dump_error_log(priv, error);
1973                                 if (error)
1974                                         ipw_free_error_log(error);
1975                         }
1976 #endif
1977                 } else {
1978                         priv->error = ipw_alloc_error_log(priv);
1979                         if (priv->error)
1980                                 IPW_DEBUG_FW("Sysfs 'error' log captured.\n");
1981                         else
1982                                 IPW_DEBUG_FW("Error allocating sysfs 'error' "
1983                                              "log.\n");
1984 #ifdef CONFIG_IPW2200_DEBUG
1985                         if (ipw_debug_level & IPW_DL_FW_ERRORS)
1986                                 ipw_dump_error_log(priv, priv->error);
1987 #endif
1988                 }
1989
1990                 /* XXX: If hardware encryption is for WPA/WPA2,
1991                  * we have to notify the supplicant. */
1992                 if (priv->ieee->sec.encrypt) {
1993                         priv->status &= ~STATUS_ASSOCIATED;
1994                         notify_wx_assoc_event(priv);
1995                 }
1996
1997                 /* Keep the restart process from trying to send host
1998                  * commands by clearing the INIT status bit */
1999                 priv->status &= ~STATUS_INIT;
2000
2001                 /* Cancel currently queued command. */
2002                 priv->status &= ~STATUS_HCMD_ACTIVE;
2003                 wake_up_interruptible(&priv->wait_command_queue);
2004
2005                 queue_work(priv->workqueue, &priv->adapter_restart);
2006                 handled |= IPW_INTA_BIT_FATAL_ERROR;
2007         }
2008
2009         if (inta & IPW_INTA_BIT_PARITY_ERROR) {
2010                 IPW_ERROR("Parity error\n");
2011                 handled |= IPW_INTA_BIT_PARITY_ERROR;
2012         }
2013
2014         if (handled != inta) {
2015                 IPW_ERROR("Unhandled INTA bits 0x%08x\n", inta & ~handled);
2016         }
2017
2018         spin_unlock_irqrestore(&priv->lock, flags);
2019
2020         /* enable all interrupts */
2021         ipw_enable_interrupts(priv);
2022 }
2023
2024 #define IPW_CMD(x) case IPW_CMD_ ## x : return #x
2025 static char *get_cmd_string(u8 cmd)
2026 {
2027         switch (cmd) {
2028                 IPW_CMD(HOST_COMPLETE);
2029                 IPW_CMD(POWER_DOWN);
2030                 IPW_CMD(SYSTEM_CONFIG);
2031                 IPW_CMD(MULTICAST_ADDRESS);
2032                 IPW_CMD(SSID);
2033                 IPW_CMD(ADAPTER_ADDRESS);
2034                 IPW_CMD(PORT_TYPE);
2035                 IPW_CMD(RTS_THRESHOLD);
2036                 IPW_CMD(FRAG_THRESHOLD);
2037                 IPW_CMD(POWER_MODE);
2038                 IPW_CMD(WEP_KEY);
2039                 IPW_CMD(TGI_TX_KEY);
2040                 IPW_CMD(SCAN_REQUEST);
2041                 IPW_CMD(SCAN_REQUEST_EXT);
2042                 IPW_CMD(ASSOCIATE);
2043                 IPW_CMD(SUPPORTED_RATES);
2044                 IPW_CMD(SCAN_ABORT);
2045                 IPW_CMD(TX_FLUSH);
2046                 IPW_CMD(QOS_PARAMETERS);
2047                 IPW_CMD(DINO_CONFIG);
2048                 IPW_CMD(RSN_CAPABILITIES);
2049                 IPW_CMD(RX_KEY);
2050                 IPW_CMD(CARD_DISABLE);
2051                 IPW_CMD(SEED_NUMBER);
2052                 IPW_CMD(TX_POWER);
2053                 IPW_CMD(COUNTRY_INFO);
2054                 IPW_CMD(AIRONET_INFO);
2055                 IPW_CMD(AP_TX_POWER);
2056                 IPW_CMD(CCKM_INFO);
2057                 IPW_CMD(CCX_VER_INFO);
2058                 IPW_CMD(SET_CALIBRATION);
2059                 IPW_CMD(SENSITIVITY_CALIB);
2060                 IPW_CMD(RETRY_LIMIT);
2061                 IPW_CMD(IPW_PRE_POWER_DOWN);
2062                 IPW_CMD(VAP_BEACON_TEMPLATE);
2063                 IPW_CMD(VAP_DTIM_PERIOD);
2064                 IPW_CMD(EXT_SUPPORTED_RATES);
2065                 IPW_CMD(VAP_LOCAL_TX_PWR_CONSTRAINT);
2066                 IPW_CMD(VAP_QUIET_INTERVALS);
2067                 IPW_CMD(VAP_CHANNEL_SWITCH);
2068                 IPW_CMD(VAP_MANDATORY_CHANNELS);
2069                 IPW_CMD(VAP_CELL_PWR_LIMIT);
2070                 IPW_CMD(VAP_CF_PARAM_SET);
2071                 IPW_CMD(VAP_SET_BEACONING_STATE);
2072                 IPW_CMD(MEASUREMENT);
2073                 IPW_CMD(POWER_CAPABILITY);
2074                 IPW_CMD(SUPPORTED_CHANNELS);
2075                 IPW_CMD(TPC_REPORT);
2076                 IPW_CMD(WME_INFO);
2077                 IPW_CMD(PRODUCTION_COMMAND);
2078         default:
2079                 return "UNKNOWN";
2080         }
2081 }
2082
2083 #define HOST_COMPLETE_TIMEOUT HZ
2084
2085 static int __ipw_send_cmd(struct ipw_priv *priv, struct host_cmd *cmd)
2086 {
2087         int rc = 0;
2088         unsigned long flags;
2089
2090         spin_lock_irqsave(&priv->lock, flags);
2091         if (priv->status & STATUS_HCMD_ACTIVE) {
2092                 IPW_ERROR("Failed to send %s: Already sending a command.\n",
2093                           get_cmd_string(cmd->cmd));
2094                 spin_unlock_irqrestore(&priv->lock, flags);
2095                 return -EAGAIN;
2096         }
2097
2098         priv->status |= STATUS_HCMD_ACTIVE;
2099
2100         if (priv->cmdlog) {
2101                 priv->cmdlog[priv->cmdlog_pos].jiffies = jiffies;
2102                 priv->cmdlog[priv->cmdlog_pos].cmd.cmd = cmd->cmd;
2103                 priv->cmdlog[priv->cmdlog_pos].cmd.len = cmd->len;
2104                 memcpy(priv->cmdlog[priv->cmdlog_pos].cmd.param, cmd->param,
2105                        cmd->len);
2106                 priv->cmdlog[priv->cmdlog_pos].retcode = -1;
2107         }
2108
2109         IPW_DEBUG_HC("%s command (#%d) %d bytes: 0x%08X\n",
2110                      get_cmd_string(cmd->cmd), cmd->cmd, cmd->len,
2111                      priv->status);
2112
2113 #ifndef DEBUG_CMD_WEP_KEY
2114         if (cmd->cmd == IPW_CMD_WEP_KEY)
2115                 IPW_DEBUG_HC("WEP_KEY command masked out for secure.\n");
2116         else
2117 #endif
2118                 printk_buf(IPW_DL_HOST_COMMAND, (u8 *) cmd->param, cmd->len);
2119
2120         rc = ipw_queue_tx_hcmd(priv, cmd->cmd, cmd->param, cmd->len, 0);
2121         if (rc) {
2122                 priv->status &= ~STATUS_HCMD_ACTIVE;
2123                 IPW_ERROR("Failed to send %s: Reason %d\n",
2124                           get_cmd_string(cmd->cmd), rc);
2125                 spin_unlock_irqrestore(&priv->lock, flags);
2126                 goto exit;
2127         }
2128         spin_unlock_irqrestore(&priv->lock, flags);
2129
2130         rc = wait_event_interruptible_timeout(priv->wait_command_queue,
2131                                               !(priv->
2132                                                 status & STATUS_HCMD_ACTIVE),
2133                                               HOST_COMPLETE_TIMEOUT);
2134         if (rc == 0) {
2135                 spin_lock_irqsave(&priv->lock, flags);
2136                 if (priv->status & STATUS_HCMD_ACTIVE) {
2137                         IPW_ERROR("Failed to send %s: Command timed out.\n",
2138                                   get_cmd_string(cmd->cmd));
2139                         priv->status &= ~STATUS_HCMD_ACTIVE;
2140                         spin_unlock_irqrestore(&priv->lock, flags);
2141                         rc = -EIO;
2142                         goto exit;
2143                 }
2144                 spin_unlock_irqrestore(&priv->lock, flags);
2145         } else
2146                 rc = 0;
2147
2148         if (priv->status & STATUS_RF_KILL_HW) {
2149                 IPW_ERROR("Failed to send %s: Aborted due to RF kill switch.\n",
2150                           get_cmd_string(cmd->cmd));
2151                 rc = -EIO;
2152                 goto exit;
2153         }
2154
2155       exit:
2156         if (priv->cmdlog) {
2157                 priv->cmdlog[priv->cmdlog_pos++].retcode = rc;
2158                 priv->cmdlog_pos %= priv->cmdlog_len;
2159         }
2160         return rc;
2161 }
2162
2163 static int ipw_send_cmd_simple(struct ipw_priv *priv, u8 command)
2164 {
2165         struct host_cmd cmd = {
2166                 .cmd = command,
2167         };
2168
2169         return __ipw_send_cmd(priv, &cmd);
2170 }
2171
2172 static int ipw_send_cmd_pdu(struct ipw_priv *priv, u8 command, u8 len,
2173                             void *data)
2174 {
2175         struct host_cmd cmd = {
2176                 .cmd = command,
2177                 .len = len,
2178                 .param = data,
2179         };
2180
2181         return __ipw_send_cmd(priv, &cmd);
2182 }
2183
2184 static int ipw_send_host_complete(struct ipw_priv *priv)
2185 {
2186         if (!priv) {
2187                 IPW_ERROR("Invalid args\n");
2188                 return -1;
2189         }
2190
2191         return ipw_send_cmd_simple(priv, IPW_CMD_HOST_COMPLETE);
2192 }
2193
2194 static int ipw_send_system_config(struct ipw_priv *priv)
2195 {
2196         return ipw_send_cmd_pdu(priv, IPW_CMD_SYSTEM_CONFIG,
2197                                 sizeof(priv->sys_config),
2198                                 &priv->sys_config);
2199 }
2200
2201 static int ipw_send_ssid(struct ipw_priv *priv, u8 * ssid, int len)
2202 {
2203         if (!priv || !ssid) {
2204                 IPW_ERROR("Invalid args\n");
2205                 return -1;
2206         }
2207
2208         return ipw_send_cmd_pdu(priv, IPW_CMD_SSID, min(len, IW_ESSID_MAX_SIZE),
2209                                 ssid);
2210 }
2211
2212 static int ipw_send_adapter_address(struct ipw_priv *priv, u8 * mac)
2213 {
2214         if (!priv || !mac) {
2215                 IPW_ERROR("Invalid args\n");
2216                 return -1;
2217         }
2218
2219         IPW_DEBUG_INFO("%s: Setting MAC to " MAC_FMT "\n",
2220                        priv->net_dev->name, MAC_ARG(mac));
2221
2222         return ipw_send_cmd_pdu(priv, IPW_CMD_ADAPTER_ADDRESS, ETH_ALEN, mac);
2223 }
2224
2225 /*
2226  * NOTE: This must be executed from our workqueue as it results in udelay
2227  * being called which may corrupt the keyboard if executed on default
2228  * workqueue
2229  */
2230 static void ipw_adapter_restart(void *adapter)
2231 {
2232         struct ipw_priv *priv = adapter;
2233
2234         if (priv->status & STATUS_RF_KILL_MASK)
2235                 return;
2236
2237         ipw_down(priv);
2238
2239         if (priv->assoc_network &&
2240             (priv->assoc_network->capability & WLAN_CAPABILITY_IBSS))
2241                 ipw_remove_current_network(priv);
2242
2243         if (ipw_up(priv)) {
2244                 IPW_ERROR("Failed to up device\n");
2245                 return;
2246         }
2247 }
2248
2249 static void ipw_bg_adapter_restart(void *data)
2250 {
2251         struct ipw_priv *priv = data;
2252         mutex_lock(&priv->mutex);
2253         ipw_adapter_restart(data);
2254         mutex_unlock(&priv->mutex);
2255 }
2256
2257 #define IPW_SCAN_CHECK_WATCHDOG (5 * HZ)
2258
2259 static void ipw_scan_check(void *data)
2260 {
2261         struct ipw_priv *priv = data;
2262         if (priv->status & (STATUS_SCANNING | STATUS_SCAN_ABORTING)) {
2263                 IPW_DEBUG_SCAN("Scan completion watchdog resetting "
2264                                "adapter after (%dms).\n",
2265                                jiffies_to_msecs(IPW_SCAN_CHECK_WATCHDOG));
2266                 queue_work(priv->workqueue, &priv->adapter_restart);
2267         }
2268 }
2269
2270 static void ipw_bg_scan_check(void *data)
2271 {
2272         struct ipw_priv *priv = data;
2273         mutex_lock(&priv->mutex);
2274         ipw_scan_check(data);
2275         mutex_unlock(&priv->mutex);
2276 }
2277
2278 static int ipw_send_scan_request_ext(struct ipw_priv *priv,
2279                                      struct ipw_scan_request_ext *request)
2280 {
2281         return ipw_send_cmd_pdu(priv, IPW_CMD_SCAN_REQUEST_EXT,
2282                                 sizeof(*request), request);
2283 }
2284
2285 static int ipw_send_scan_abort(struct ipw_priv *priv)
2286 {
2287         if (!priv) {
2288                 IPW_ERROR("Invalid args\n");
2289                 return -1;
2290         }
2291
2292         return ipw_send_cmd_simple(priv, IPW_CMD_SCAN_ABORT);
2293 }
2294
2295 static int ipw_set_sensitivity(struct ipw_priv *priv, u16 sens)
2296 {
2297         struct ipw_sensitivity_calib calib = {
2298                 .beacon_rssi_raw = sens,
2299         };
2300
2301         return ipw_send_cmd_pdu(priv, IPW_CMD_SENSITIVITY_CALIB, sizeof(calib),
2302                                 &calib);
2303 }
2304
2305 static int ipw_send_associate(struct ipw_priv *priv,
2306                               struct ipw_associate *associate)
2307 {
2308         struct ipw_associate tmp_associate;
2309
2310         if (!priv || !associate) {
2311                 IPW_ERROR("Invalid args\n");
2312                 return -1;
2313         }
2314
2315         memcpy(&tmp_associate, associate, sizeof(*associate));
2316         tmp_associate.policy_support =
2317             cpu_to_le16(tmp_associate.policy_support);
2318         tmp_associate.assoc_tsf_msw = cpu_to_le32(tmp_associate.assoc_tsf_msw);
2319         tmp_associate.assoc_tsf_lsw = cpu_to_le32(tmp_associate.assoc_tsf_lsw);
2320         tmp_associate.capability = cpu_to_le16(tmp_associate.capability);
2321         tmp_associate.listen_interval =
2322             cpu_to_le16(tmp_associate.listen_interval);
2323         tmp_associate.beacon_interval =
2324             cpu_to_le16(tmp_associate.beacon_interval);
2325         tmp_associate.atim_window = cpu_to_le16(tmp_associate.atim_window);
2326
2327         return ipw_send_cmd_pdu(priv, IPW_CMD_ASSOCIATE, sizeof(tmp_associate),
2328                                 &tmp_associate);
2329 }
2330
2331 static int ipw_send_supported_rates(struct ipw_priv *priv,
2332                                     struct ipw_supported_rates *rates)
2333 {
2334         if (!priv || !rates) {
2335                 IPW_ERROR("Invalid args\n");
2336                 return -1;
2337         }
2338
2339         return ipw_send_cmd_pdu(priv, IPW_CMD_SUPPORTED_RATES, sizeof(*rates),
2340                                 rates);
2341 }
2342
2343 static int ipw_set_random_seed(struct ipw_priv *priv)
2344 {
2345         u32 val;
2346
2347         if (!priv) {
2348                 IPW_ERROR("Invalid args\n");
2349                 return -1;
2350         }
2351
2352         get_random_bytes(&val, sizeof(val));
2353
2354         return ipw_send_cmd_pdu(priv, IPW_CMD_SEED_NUMBER, sizeof(val), &val);
2355 }
2356
2357 static int ipw_send_card_disable(struct ipw_priv *priv, u32 phy_off)
2358 {
2359         if (!priv) {
2360                 IPW_ERROR("Invalid args\n");
2361                 return -1;
2362         }
2363
2364         return ipw_send_cmd_pdu(priv, IPW_CMD_CARD_DISABLE, sizeof(phy_off),
2365                                 &phy_off);
2366 }
2367
2368 static int ipw_send_tx_power(struct ipw_priv *priv, struct ipw_tx_power *power)
2369 {
2370         if (!priv || !power) {
2371                 IPW_ERROR("Invalid args\n");
2372                 return -1;
2373         }
2374
2375         return ipw_send_cmd_pdu(priv, IPW_CMD_TX_POWER, sizeof(*power), power);
2376 }
2377
2378 static int ipw_set_tx_power(struct ipw_priv *priv)
2379 {
2380         const struct ieee80211_geo *geo = ieee80211_get_geo(priv->ieee);
2381         struct ipw_tx_power tx_power;
2382         s8 max_power;
2383         int i;
2384
2385         memset(&tx_power, 0, sizeof(tx_power));
2386
2387         /* configure device for 'G' band */
2388         tx_power.ieee_mode = IPW_G_MODE;
2389         tx_power.num_channels = geo->bg_channels;
2390         for (i = 0; i < geo->bg_channels; i++) {
2391                 max_power = geo->bg[i].max_power;
2392                 tx_power.channels_tx_power[i].channel_number =
2393                     geo->bg[i].channel;
2394                 tx_power.channels_tx_power[i].tx_power = max_power ?
2395                     min(max_power, priv->tx_power) : priv->tx_power;
2396         }
2397         if (ipw_send_tx_power(priv, &tx_power))
2398                 return -EIO;
2399
2400         /* configure device to also handle 'B' band */
2401         tx_power.ieee_mode = IPW_B_MODE;
2402         if (ipw_send_tx_power(priv, &tx_power))
2403                 return -EIO;
2404
2405         /* configure device to also handle 'A' band */
2406         if (priv->ieee->abg_true) {
2407                 tx_power.ieee_mode = IPW_A_MODE;
2408                 tx_power.num_channels = geo->a_channels;
2409                 for (i = 0; i < tx_power.num_channels; i++) {
2410                         max_power = geo->a[i].max_power;
2411                         tx_power.channels_tx_power[i].channel_number =
2412                             geo->a[i].channel;
2413                         tx_power.channels_tx_power[i].tx_power = max_power ?
2414                             min(max_power, priv->tx_power) : priv->tx_power;
2415                 }
2416                 if (ipw_send_tx_power(priv, &tx_power))
2417                         return -EIO;
2418         }
2419         return 0;
2420 }
2421
2422 static int ipw_send_rts_threshold(struct ipw_priv *priv, u16 rts)
2423 {
2424         struct ipw_rts_threshold rts_threshold = {
2425                 .rts_threshold = rts,
2426         };
2427
2428         if (!priv) {
2429                 IPW_ERROR("Invalid args\n");
2430                 return -1;
2431         }
2432
2433         return ipw_send_cmd_pdu(priv, IPW_CMD_RTS_THRESHOLD,
2434                                 sizeof(rts_threshold), &rts_threshold);
2435 }
2436
2437 static int ipw_send_frag_threshold(struct ipw_priv *priv, u16 frag)
2438 {
2439         struct ipw_frag_threshold frag_threshold = {
2440                 .frag_threshold = frag,
2441         };
2442
2443         if (!priv) {
2444                 IPW_ERROR("Invalid args\n");
2445                 return -1;
2446         }
2447
2448         return ipw_send_cmd_pdu(priv, IPW_CMD_FRAG_THRESHOLD,
2449                                 sizeof(frag_threshold), &frag_threshold);
2450 }
2451
2452 static int ipw_send_power_mode(struct ipw_priv *priv, u32 mode)
2453 {
2454         u32 param;
2455
2456         if (!priv) {
2457                 IPW_ERROR("Invalid args\n");
2458                 return -1;
2459         }
2460
2461         /* If on battery, set to 3, if AC set to CAM, else user
2462          * level */
2463         switch (mode) {
2464         case IPW_POWER_BATTERY:
2465                 param = IPW_POWER_INDEX_3;
2466                 break;
2467         case IPW_POWER_AC:
2468                 param = IPW_POWER_MODE_CAM;
2469                 break;
2470         default:
2471                 param = mode;
2472                 break;
2473         }
2474
2475         return ipw_send_cmd_pdu(priv, IPW_CMD_POWER_MODE, sizeof(param),
2476                                 &param);
2477 }
2478
2479 static int ipw_send_retry_limit(struct ipw_priv *priv, u8 slimit, u8 llimit)
2480 {
2481         struct ipw_retry_limit retry_limit = {
2482                 .short_retry_limit = slimit,
2483                 .long_retry_limit = llimit
2484         };
2485
2486         if (!priv) {
2487                 IPW_ERROR("Invalid args\n");
2488                 return -1;
2489         }
2490
2491         return ipw_send_cmd_pdu(priv, IPW_CMD_RETRY_LIMIT, sizeof(retry_limit),
2492                                 &retry_limit);
2493 }
2494
2495 /*
2496  * The IPW device contains a Microwire compatible EEPROM that stores
2497  * various data like the MAC address.  Usually the firmware has exclusive
2498  * access to the eeprom, but during device initialization (before the
2499  * device driver has sent the HostComplete command to the firmware) the
2500  * device driver has read access to the EEPROM by way of indirect addressing
2501  * through a couple of memory mapped registers.
2502  *
2503  * The following is a simplified implementation for pulling data out of the
2504  * the eeprom, along with some helper functions to find information in
2505  * the per device private data's copy of the eeprom.
2506  *
2507  * NOTE: To better understand how these functions work (i.e what is a chip
2508  *       select and why do have to keep driving the eeprom clock?), read
2509  *       just about any data sheet for a Microwire compatible EEPROM.
2510  */
2511
2512 /* write a 32 bit value into the indirect accessor register */
2513 static inline void eeprom_write_reg(struct ipw_priv *p, u32 data)
2514 {
2515         ipw_write_reg32(p, FW_MEM_REG_EEPROM_ACCESS, data);
2516
2517         /* the eeprom requires some time to complete the operation */
2518         udelay(p->eeprom_delay);
2519
2520         return;
2521 }
2522
2523 /* perform a chip select operation */
2524 static void eeprom_cs(struct ipw_priv *priv)
2525 {
2526         eeprom_write_reg(priv, 0);
2527         eeprom_write_reg(priv, EEPROM_BIT_CS);
2528         eeprom_write_reg(priv, EEPROM_BIT_CS | EEPROM_BIT_SK);
2529         eeprom_write_reg(priv, EEPROM_BIT_CS);
2530 }
2531
2532 /* perform a chip select operation */
2533 static void eeprom_disable_cs(struct ipw_priv *priv)
2534 {
2535         eeprom_write_reg(priv, EEPROM_BIT_CS);
2536         eeprom_write_reg(priv, 0);
2537         eeprom_write_reg(priv, EEPROM_BIT_SK);
2538 }
2539
2540 /* push a single bit down to the eeprom */
2541 static inline void eeprom_write_bit(struct ipw_priv *p, u8 bit)
2542 {
2543         int d = (bit ? EEPROM_BIT_DI : 0);
2544         eeprom_write_reg(p, EEPROM_BIT_CS | d);
2545         eeprom_write_reg(p, EEPROM_BIT_CS | d | EEPROM_BIT_SK);
2546 }
2547
2548 /* push an opcode followed by an address down to the eeprom */
2549 static void eeprom_op(struct ipw_priv *priv, u8 op, u8 addr)
2550 {
2551         int i;
2552
2553         eeprom_cs(priv);
2554         eeprom_write_bit(priv, 1);
2555         eeprom_write_bit(priv, op & 2);
2556         eeprom_write_bit(priv, op & 1);
2557         for (i = 7; i >= 0; i--) {
2558                 eeprom_write_bit(priv, addr & (1 << i));
2559         }
2560 }
2561
2562 /* pull 16 bits off the eeprom, one bit at a time */
2563 static u16 eeprom_read_u16(struct ipw_priv *priv, u8 addr)
2564 {
2565         int i;
2566         u16 r = 0;
2567
2568         /* Send READ Opcode */
2569         eeprom_op(priv, EEPROM_CMD_READ, addr);
2570
2571         /* Send dummy bit */
2572         eeprom_write_reg(priv, EEPROM_BIT_CS);
2573
2574         /* Read the byte off the eeprom one bit at a time */
2575         for (i = 0; i < 16; i++) {
2576                 u32 data = 0;
2577                 eeprom_write_reg(priv, EEPROM_BIT_CS | EEPROM_BIT_SK);
2578                 eeprom_write_reg(priv, EEPROM_BIT_CS);
2579                 data = ipw_read_reg32(priv, FW_MEM_REG_EEPROM_ACCESS);
2580                 r = (r << 1) | ((data & EEPROM_BIT_DO) ? 1 : 0);
2581         }
2582
2583         /* Send another dummy bit */
2584         eeprom_write_reg(priv, 0);
2585         eeprom_disable_cs(priv);
2586
2587         return r;
2588 }
2589
2590 /* helper function for pulling the mac address out of the private */
2591 /* data's copy of the eeprom data                                 */
2592 static void eeprom_parse_mac(struct ipw_priv *priv, u8 * mac)
2593 {
2594         memcpy(mac, &priv->eeprom[EEPROM_MAC_ADDRESS], 6);
2595 }
2596
2597 /*
2598  * Either the device driver (i.e. the host) or the firmware can
2599  * load eeprom data into the designated region in SRAM.  If neither
2600  * happens then the FW will shutdown with a fatal error.
2601  *
2602  * In order to signal the FW to load the EEPROM, the EEPROM_LOAD_DISABLE
2603  * bit needs region of shared SRAM needs to be non-zero.
2604  */
2605 static void ipw_eeprom_init_sram(struct ipw_priv *priv)
2606 {
2607         int i;
2608         u16 *eeprom = (u16 *) priv->eeprom;
2609
2610         IPW_DEBUG_TRACE(">>\n");
2611
2612         /* read entire contents of eeprom into private buffer */
2613         for (i = 0; i < 128; i++)
2614                 eeprom[i] = le16_to_cpu(eeprom_read_u16(priv, (u8) i));
2615
2616         /*
2617            If the data looks correct, then copy it to our private
2618            copy.  Otherwise let the firmware know to perform the operation
2619            on its own.
2620          */
2621         if (priv->eeprom[EEPROM_VERSION] != 0) {
2622                 IPW_DEBUG_INFO("Writing EEPROM data into SRAM\n");
2623
2624                 /* write the eeprom data to sram */
2625                 for (i = 0; i < IPW_EEPROM_IMAGE_SIZE; i++)
2626                         ipw_write8(priv, IPW_EEPROM_DATA + i, priv->eeprom[i]);
2627
2628                 /* Do not load eeprom data on fatal error or suspend */
2629                 ipw_write32(priv, IPW_EEPROM_LOAD_DISABLE, 0);
2630         } else {
2631                 IPW_DEBUG_INFO("Enabling FW initializationg of SRAM\n");
2632
2633                 /* Load eeprom data on fatal error or suspend */
2634                 ipw_write32(priv, IPW_EEPROM_LOAD_DISABLE, 1);
2635         }
2636
2637         IPW_DEBUG_TRACE("<<\n");
2638 }
2639
2640 static void ipw_zero_memory(struct ipw_priv *priv, u32 start, u32 count)
2641 {
2642         count >>= 2;
2643         if (!count)
2644                 return;
2645         _ipw_write32(priv, IPW_AUTOINC_ADDR, start);
2646         while (count--)
2647                 _ipw_write32(priv, IPW_AUTOINC_DATA, 0);
2648 }
2649
2650 static inline void ipw_fw_dma_reset_command_blocks(struct ipw_priv *priv)
2651 {
2652         ipw_zero_memory(priv, IPW_SHARED_SRAM_DMA_CONTROL,
2653                         CB_NUMBER_OF_ELEMENTS_SMALL *
2654                         sizeof(struct command_block));
2655 }
2656
2657 static int ipw_fw_dma_enable(struct ipw_priv *priv)
2658 {                               /* start dma engine but no transfers yet */
2659
2660         IPW_DEBUG_FW(">> : \n");
2661
2662         /* Start the dma */
2663         ipw_fw_dma_reset_command_blocks(priv);
2664
2665         /* Write CB base address */
2666         ipw_write_reg32(priv, IPW_DMA_I_CB_BASE, IPW_SHARED_SRAM_DMA_CONTROL);
2667
2668         IPW_DEBUG_FW("<< : \n");
2669         return 0;
2670 }
2671
2672 static void ipw_fw_dma_abort(struct ipw_priv *priv)
2673 {
2674         u32 control = 0;
2675
2676         IPW_DEBUG_FW(">> :\n");
2677
2678         //set the Stop and Abort bit
2679         control = DMA_CONTROL_SMALL_CB_CONST_VALUE | DMA_CB_STOP_AND_ABORT;
2680         ipw_write_reg32(priv, IPW_DMA_I_DMA_CONTROL, control);
2681         priv->sram_desc.last_cb_index = 0;
2682
2683         IPW_DEBUG_FW("<< \n");
2684 }
2685
2686 static int ipw_fw_dma_write_command_block(struct ipw_priv *priv, int index,
2687                                           struct command_block *cb)
2688 {
2689         u32 address =
2690             IPW_SHARED_SRAM_DMA_CONTROL +
2691             (sizeof(struct command_block) * index);
2692         IPW_DEBUG_FW(">> :\n");
2693
2694         ipw_write_indirect(priv, address, (u8 *) cb,
2695                            (int)sizeof(struct command_block));
2696
2697         IPW_DEBUG_FW("<< :\n");
2698         return 0;
2699
2700 }
2701
2702 static int ipw_fw_dma_kick(struct ipw_priv *priv)
2703 {
2704         u32 control = 0;
2705         u32 index = 0;
2706
2707         IPW_DEBUG_FW(">> :\n");
2708
2709         for (index = 0; index < priv->sram_desc.last_cb_index; index++)
2710                 ipw_fw_dma_write_command_block(priv, index,
2711                                                &priv->sram_desc.cb_list[index]);
2712
2713         /* Enable the DMA in the CSR register */
2714         ipw_clear_bit(priv, IPW_RESET_REG,
2715                       IPW_RESET_REG_MASTER_DISABLED |
2716                       IPW_RESET_REG_STOP_MASTER);
2717
2718         /* Set the Start bit. */
2719         control = DMA_CONTROL_SMALL_CB_CONST_VALUE | DMA_CB_START;
2720         ipw_write_reg32(priv, IPW_DMA_I_DMA_CONTROL, control);
2721
2722         IPW_DEBUG_FW("<< :\n");
2723         return 0;
2724 }
2725
2726 static void ipw_fw_dma_dump_command_block(struct ipw_priv *priv)
2727 {
2728         u32 address;
2729         u32 register_value = 0;
2730         u32 cb_fields_address = 0;
2731
2732         IPW_DEBUG_FW(">> :\n");
2733         address = ipw_read_reg32(priv, IPW_DMA_I_CURRENT_CB);
2734         IPW_DEBUG_FW_INFO("Current CB is 0x%x \n", address);
2735
2736         /* Read the DMA Controlor register */
2737         register_value = ipw_read_reg32(priv, IPW_DMA_I_DMA_CONTROL);
2738         IPW_DEBUG_FW_INFO("IPW_DMA_I_DMA_CONTROL is 0x%x \n", register_value);
2739
2740         /* Print the CB values */
2741         cb_fields_address = address;
2742         register_value = ipw_read_reg32(priv, cb_fields_address);
2743         IPW_DEBUG_FW_INFO("Current CB ControlField is 0x%x \n", register_value);
2744
2745         cb_fields_address += sizeof(u32);
2746         register_value = ipw_read_reg32(priv, cb_fields_address);
2747         IPW_DEBUG_FW_INFO("Current CB Source Field is 0x%x \n", register_value);
2748
2749         cb_fields_address += sizeof(u32);
2750         register_value = ipw_read_reg32(priv, cb_fields_address);
2751         IPW_DEBUG_FW_INFO("Current CB Destination Field is 0x%x \n",
2752                           register_value);
2753
2754         cb_fields_address += sizeof(u32);
2755         register_value = ipw_read_reg32(priv, cb_fields_address);
2756         IPW_DEBUG_FW_INFO("Current CB Status Field is 0x%x \n", register_value);
2757
2758         IPW_DEBUG_FW(">> :\n");
2759 }
2760
2761 static int ipw_fw_dma_command_block_index(struct ipw_priv *priv)
2762 {
2763         u32 current_cb_address = 0;
2764         u32 current_cb_index = 0;
2765
2766         IPW_DEBUG_FW("<< :\n");
2767         current_cb_address = ipw_read_reg32(priv, IPW_DMA_I_CURRENT_CB);
2768
2769         current_cb_index = (current_cb_address - IPW_SHARED_SRAM_DMA_CONTROL) /
2770             sizeof(struct command_block);
2771
2772         IPW_DEBUG_FW_INFO("Current CB index 0x%x address = 0x%X \n",
2773                           current_cb_index, current_cb_address);
2774
2775         IPW_DEBUG_FW(">> :\n");
2776         return current_cb_index;
2777
2778 }
2779
2780 static int ipw_fw_dma_add_command_block(struct ipw_priv *priv,
2781                                         u32 src_address,
2782                                         u32 dest_address,
2783                                         u32 length,
2784                                         int interrupt_enabled, int is_last)
2785 {
2786
2787         u32 control = CB_VALID | CB_SRC_LE | CB_DEST_LE | CB_SRC_AUTOINC |
2788             CB_SRC_IO_GATED | CB_DEST_AUTOINC | CB_SRC_SIZE_LONG |
2789             CB_DEST_SIZE_LONG;
2790         struct command_block *cb;
2791         u32 last_cb_element = 0;
2792
2793         IPW_DEBUG_FW_INFO("src_address=0x%x dest_address=0x%x length=0x%x\n",
2794                           src_address, dest_address, length);
2795
2796         if (priv->sram_desc.last_cb_index >= CB_NUMBER_OF_ELEMENTS_SMALL)
2797                 return -1;
2798
2799         last_cb_element = priv->sram_desc.last_cb_index;
2800         cb = &priv->sram_desc.cb_list[last_cb_element];
2801         priv->sram_desc.last_cb_index++;
2802
2803         /* Calculate the new CB control word */
2804         if (interrupt_enabled)
2805                 control |= CB_INT_ENABLED;
2806
2807         if (is_last)
2808                 control |= CB_LAST_VALID;
2809
2810         control |= length;
2811
2812         /* Calculate the CB Element's checksum value */
2813         cb->status = control ^ src_address ^ dest_address;
2814
2815         /* Copy the Source and Destination addresses */
2816         cb->dest_addr = dest_address;
2817         cb->source_addr = src_address;
2818
2819         /* Copy the Control Word last */
2820         cb->control = control;
2821
2822         return 0;
2823 }
2824
2825 static int ipw_fw_dma_add_buffer(struct ipw_priv *priv,
2826                                  u32 src_phys, u32 dest_address, u32 length)
2827 {
2828         u32 bytes_left = length;
2829         u32 src_offset = 0;
2830         u32 dest_offset = 0;
2831         int status = 0;
2832         IPW_DEBUG_FW(">> \n");
2833         IPW_DEBUG_FW_INFO("src_phys=0x%x dest_address=0x%x length=0x%x\n",
2834                           src_phys, dest_address, length);
2835         while (bytes_left > CB_MAX_LENGTH) {
2836                 status = ipw_fw_dma_add_command_block(priv,
2837                                                       src_phys + src_offset,
2838                                                       dest_address +
2839                                                       dest_offset,
2840                                                       CB_MAX_LENGTH, 0, 0);
2841                 if (status) {
2842                         IPW_DEBUG_FW_INFO(": Failed\n");
2843                         return -1;
2844                 } else
2845                         IPW_DEBUG_FW_INFO(": Added new cb\n");
2846
2847                 src_offset += CB_MAX_LENGTH;
2848                 dest_offset += CB_MAX_LENGTH;
2849                 bytes_left -= CB_MAX_LENGTH;
2850         }
2851
2852         /* add the buffer tail */
2853         if (bytes_left > 0) {
2854                 status =
2855                     ipw_fw_dma_add_command_block(priv, src_phys + src_offset,
2856                                                  dest_address + dest_offset,
2857                                                  bytes_left, 0, 0);
2858                 if (status) {
2859                         IPW_DEBUG_FW_INFO(": Failed on the buffer tail\n");
2860                         return -1;
2861                 } else
2862                         IPW_DEBUG_FW_INFO
2863                             (": Adding new cb - the buffer tail\n");
2864         }
2865
2866         IPW_DEBUG_FW("<< \n");
2867         return 0;
2868 }
2869
2870 static int ipw_fw_dma_wait(struct ipw_priv *priv)
2871 {
2872         u32 current_index = 0, previous_index;
2873         u32 watchdog = 0;
2874
2875         IPW_DEBUG_FW(">> : \n");
2876
2877         current_index = ipw_fw_dma_command_block_index(priv);
2878         IPW_DEBUG_FW_INFO("sram_desc.last_cb_index:0x%08X\n",
2879                           (int)priv->sram_desc.last_cb_index);
2880
2881         while (current_index < priv->sram_desc.last_cb_index) {
2882                 udelay(50);
2883                 previous_index = current_index;
2884                 current_index = ipw_fw_dma_command_block_index(priv);
2885
2886                 if (previous_index < current_index) {
2887                         watchdog = 0;
2888                         continue;
2889                 }
2890                 if (++watchdog > 400) {
2891                         IPW_DEBUG_FW_INFO("Timeout\n");
2892                         ipw_fw_dma_dump_command_block(priv);
2893                         ipw_fw_dma_abort(priv);
2894                         return -1;
2895                 }
2896         }
2897
2898         ipw_fw_dma_abort(priv);
2899
2900         /*Disable the DMA in the CSR register */
2901         ipw_set_bit(priv, IPW_RESET_REG,
2902                     IPW_RESET_REG_MASTER_DISABLED | IPW_RESET_REG_STOP_MASTER);
2903
2904         IPW_DEBUG_FW("<< dmaWaitSync \n");
2905         return 0;
2906 }
2907
2908 static void ipw_remove_current_network(struct ipw_priv *priv)
2909 {
2910         struct list_head *element, *safe;
2911         struct ieee80211_network *network = NULL;
2912         unsigned long flags;
2913
2914         spin_lock_irqsave(&priv->ieee->lock, flags);
2915         list_for_each_safe(element, safe, &priv->ieee->network_list) {
2916                 network = list_entry(element, struct ieee80211_network, list);
2917                 if (!memcmp(network->bssid, priv->bssid, ETH_ALEN)) {
2918                         list_del(element);
2919                         list_add_tail(&network->list,
2920                                       &priv->ieee->network_free_list);
2921                 }
2922         }
2923         spin_unlock_irqrestore(&priv->ieee->lock, flags);
2924 }
2925
2926 /**
2927  * Check that card is still alive.
2928  * Reads debug register from domain0.
2929  * If card is present, pre-defined value should
2930  * be found there.
2931  *
2932  * @param priv
2933  * @return 1 if card is present, 0 otherwise
2934  */
2935 static inline int ipw_alive(struct ipw_priv *priv)
2936 {
2937         return ipw_read32(priv, 0x90) == 0xd55555d5;
2938 }
2939
2940 /* timeout in msec, attempted in 10-msec quanta */
2941 static int ipw_poll_bit(struct ipw_priv *priv, u32 addr, u32 mask,
2942                                int timeout)
2943 {
2944         int i = 0;
2945
2946         do {
2947                 if ((ipw_read32(priv, addr) & mask) == mask)
2948                         return i;
2949                 mdelay(10);
2950                 i += 10;
2951         } while (i < timeout);
2952
2953         return -ETIME;
2954 }
2955
2956 /* These functions load the firmware and micro code for the operation of
2957  * the ipw hardware.  It assumes the buffer has all the bits for the
2958  * image and the caller is handling the memory allocation and clean up.
2959  */
2960
2961 static int ipw_stop_master(struct ipw_priv *priv)
2962 {
2963         int rc;
2964
2965         IPW_DEBUG_TRACE(">> \n");
2966         /* stop master. typical delay - 0 */
2967         ipw_set_bit(priv, IPW_RESET_REG, IPW_RESET_REG_STOP_MASTER);
2968
2969         /* timeout is in msec, polled in 10-msec quanta */
2970         rc = ipw_poll_bit(priv, IPW_RESET_REG,
2971                           IPW_RESET_REG_MASTER_DISABLED, 100);
2972         if (rc < 0) {
2973                 IPW_ERROR("wait for stop master failed after 100ms\n");
2974                 return -1;
2975         }
2976
2977         IPW_DEBUG_INFO("stop master %dms\n", rc);
2978
2979         return rc;
2980 }
2981
2982 static void ipw_arc_release(struct ipw_priv *priv)
2983 {
2984         IPW_DEBUG_TRACE(">> \n");
2985         mdelay(5);
2986
2987         ipw_clear_bit(priv, IPW_RESET_REG, CBD_RESET_REG_PRINCETON_RESET);
2988
2989         /* no one knows timing, for safety add some delay */
2990         mdelay(5);
2991 }
2992
2993 struct fw_chunk {
2994         u32 address;
2995         u32 length;
2996 };
2997
2998 static int ipw_load_ucode(struct ipw_priv *priv, u8 * data, size_t len)
2999 {
3000         int rc = 0, i, addr;
3001         u8 cr = 0;
3002         u16 *image;
3003
3004         image = (u16 *) data;
3005
3006         IPW_DEBUG_TRACE(">> \n");
3007
3008         rc = ipw_stop_master(priv);
3009
3010         if (rc < 0)
3011                 return rc;
3012
3013 //      spin_lock_irqsave(&priv->lock, flags);
3014
3015         for (addr = IPW_SHARED_LOWER_BOUND;
3016              addr < IPW_REGISTER_DOMAIN1_END; addr += 4) {
3017                 ipw_write32(priv, addr, 0);
3018         }
3019
3020         /* no ucode (yet) */
3021         memset(&priv->dino_alive, 0, sizeof(priv->dino_alive));
3022         /* destroy DMA queues */
3023         /* reset sequence */
3024
3025         ipw_write_reg32(priv, IPW_MEM_HALT_AND_RESET, IPW_BIT_HALT_RESET_ON);
3026         ipw_arc_release(priv);
3027         ipw_write_reg32(priv, IPW_MEM_HALT_AND_RESET, IPW_BIT_HALT_RESET_OFF);
3028         mdelay(1);
3029
3030         /* reset PHY */
3031         ipw_write_reg32(priv, IPW_INTERNAL_CMD_EVENT, IPW_BASEBAND_POWER_DOWN);
3032         mdelay(1);
3033
3034         ipw_write_reg32(priv, IPW_INTERNAL_CMD_EVENT, 0);
3035         mdelay(1);
3036
3037         /* enable ucode store */
3038         ipw_write_reg8(priv, IPW_BASEBAND_CONTROL_STATUS, 0x0);
3039         ipw_write_reg8(priv, IPW_BASEBAND_CONTROL_STATUS, DINO_ENABLE_CS);
3040         mdelay(1);
3041
3042         /* write ucode */
3043         /**
3044          * @bug
3045          * Do NOT set indirect address register once and then
3046          * store data to indirect data register in the loop.
3047          * It seems very reasonable, but in this case DINO do not
3048          * accept ucode. It is essential to set address each time.
3049          */
3050         /* load new ipw uCode */
3051         for (i = 0; i < len / 2; i++)
3052                 ipw_write_reg16(priv, IPW_BASEBAND_CONTROL_STORE,
3053                                 cpu_to_le16(image[i]));
3054
3055         /* enable DINO */
3056         ipw_write_reg8(priv, IPW_BASEBAND_CONTROL_STATUS, 0);
3057         ipw_write_reg8(priv, IPW_BASEBAND_CONTROL_STATUS, DINO_ENABLE_SYSTEM);
3058
3059         /* this is where the igx / win driver deveates from the VAP driver. */
3060
3061         /* wait for alive response */
3062         for (i = 0; i < 100; i++) {
3063                 /* poll for incoming data */
3064                 cr = ipw_read_reg8(priv, IPW_BASEBAND_CONTROL_STATUS);
3065                 if (cr & DINO_RXFIFO_DATA)
3066                         break;
3067                 mdelay(1);
3068         }
3069
3070         if (cr & DINO_RXFIFO_DATA) {
3071                 /* alive_command_responce size is NOT multiple of 4 */
3072                 u32 response_buffer[(sizeof(priv->dino_alive) + 3) / 4];
3073
3074                 for (i = 0; i < ARRAY_SIZE(response_buffer); i++)
3075                         response_buffer[i] =
3076                             le32_to_cpu(ipw_read_reg32(priv,
3077                                                        IPW_BASEBAND_RX_FIFO_READ));
3078                 memcpy(&priv->dino_alive, response_buffer,
3079                        sizeof(priv->dino_alive));
3080                 if (priv->dino_alive.alive_command == 1
3081                     && priv->dino_alive.ucode_valid == 1) {
3082                         rc = 0;
3083                         IPW_DEBUG_INFO
3084                             ("Microcode OK, rev. %d (0x%x) dev. %d (0x%x) "
3085                              "of %02d/%02d/%02d %02d:%02d\n",
3086                              priv->dino_alive.software_revision,
3087                              priv->dino_alive.software_revision,
3088                              priv->dino_alive.device_identifier,
3089                              priv->dino_alive.device_identifier,
3090                              priv->dino_alive.time_stamp[0],
3091                              priv->dino_alive.time_stamp[1],
3092                              priv->dino_alive.time_stamp[2],
3093                              priv->dino_alive.time_stamp[3],
3094                              priv->dino_alive.time_stamp[4]);
3095                 } else {
3096                         IPW_DEBUG_INFO("Microcode is not alive\n");
3097                         rc = -EINVAL;
3098                 }
3099         } else {
3100                 IPW_DEBUG_INFO("No alive response from DINO\n");
3101                 rc = -ETIME;
3102         }
3103
3104         /* disable DINO, otherwise for some reason
3105            firmware have problem getting alive resp. */
3106         ipw_write_reg8(priv, IPW_BASEBAND_CONTROL_STATUS, 0);
3107
3108 //      spin_unlock_irqrestore(&priv->lock, flags);
3109
3110         return rc;
3111 }
3112
3113 static int ipw_load_firmware(struct ipw_priv *priv, u8 * data, size_t len)
3114 {
3115         int rc = -1;
3116         int offset = 0;
3117         struct fw_chunk *chunk;
3118         dma_addr_t shared_phys;
3119         u8 *shared_virt;
3120
3121         IPW_DEBUG_TRACE("<< : \n");
3122         shared_virt = pci_alloc_consistent(priv->pci_dev, len, &shared_phys);
3123
3124         if (!shared_virt)
3125                 return -ENOMEM;
3126
3127         memmove(shared_virt, data, len);
3128
3129         /* Start the Dma */
3130         rc = ipw_fw_dma_enable(priv);
3131
3132         if (priv->sram_desc.last_cb_index > 0) {
3133                 /* the DMA is already ready this would be a bug. */
3134                 BUG();
3135                 goto out;
3136         }
3137
3138         do {
3139                 chunk = (struct fw_chunk *)(data + offset);
3140                 offset += sizeof(struct fw_chunk);
3141                 /* build DMA packet and queue up for sending */
3142                 /* dma to chunk->address, the chunk->length bytes from data +
3143                  * offeset*/
3144                 /* Dma loading */
3145                 rc = ipw_fw_dma_add_buffer(priv, shared_phys + offset,
3146                                            le32_to_cpu(chunk->address),
3147                                            le32_to_cpu(chunk->length));
3148                 if (rc) {
3149                         IPW_DEBUG_INFO("dmaAddBuffer Failed\n");
3150                         goto out;
3151                 }
3152
3153                 offset += le32_to_cpu(chunk->length);
3154         } while (offset < len);
3155
3156         /* Run the DMA and wait for the answer */
3157         rc = ipw_fw_dma_kick(priv);
3158         if (rc) {
3159                 IPW_ERROR("dmaKick Failed\n");
3160                 goto out;
3161         }
3162
3163         rc = ipw_fw_dma_wait(priv);
3164         if (rc) {
3165                 IPW_ERROR("dmaWaitSync Failed\n");
3166                 goto out;
3167         }
3168       out:
3169         pci_free_consistent(priv->pci_dev, len, shared_virt, shared_phys);
3170         return rc;
3171 }
3172
3173 /* stop nic */
3174 static int ipw_stop_nic(struct ipw_priv *priv)
3175 {
3176         int rc = 0;
3177
3178         /* stop */
3179         ipw_write32(priv, IPW_RESET_REG, IPW_RESET_REG_STOP_MASTER);
3180
3181         rc = ipw_poll_bit(priv, IPW_RESET_REG,
3182                           IPW_RESET_REG_MASTER_DISABLED, 500);
3183         if (rc < 0) {
3184                 IPW_ERROR("wait for reg master disabled failed after 500ms\n");
3185                 return rc;
3186         }
3187
3188         ipw_set_bit(priv, IPW_RESET_REG, CBD_RESET_REG_PRINCETON_RESET);
3189
3190         return rc;
3191 }
3192
3193 static void ipw_start_nic(struct ipw_priv *priv)
3194 {
3195         IPW_DEBUG_TRACE(">>\n");
3196
3197         /* prvHwStartNic  release ARC */
3198         ipw_clear_bit(priv, IPW_RESET_REG,
3199                       IPW_RESET_REG_MASTER_DISABLED |
3200                       IPW_RESET_REG_STOP_MASTER |
3201                       CBD_RESET_REG_PRINCETON_RESET);
3202
3203         /* enable power management */
3204         ipw_set_bit(priv, IPW_GP_CNTRL_RW,
3205                     IPW_GP_CNTRL_BIT_HOST_ALLOWS_STANDBY);
3206
3207         IPW_DEBUG_TRACE("<<\n");
3208 }
3209
3210 static int ipw_init_nic(struct ipw_priv *priv)
3211 {
3212         int rc;
3213
3214         IPW_DEBUG_TRACE(">>\n");
3215         /* reset */
3216         /*prvHwInitNic */
3217         /* set "initialization complete" bit to move adapter to D0 state */
3218         ipw_set_bit(priv, IPW_GP_CNTRL_RW, IPW_GP_CNTRL_BIT_INIT_DONE);
3219
3220         /* low-level PLL activation */
3221         ipw_write32(priv, IPW_READ_INT_REGISTER,
3222                     IPW_BIT_INT_HOST_SRAM_READ_INT_REGISTER);
3223
3224         /* wait for clock stabilization */
3225         rc = ipw_poll_bit(priv, IPW_GP_CNTRL_RW,
3226                           IPW_GP_CNTRL_BIT_CLOCK_READY, 250);
3227         if (rc < 0)
3228                 IPW_DEBUG_INFO("FAILED wait for clock stablization\n");
3229
3230         /* assert SW reset */
3231         ipw_set_bit(priv, IPW_RESET_REG, IPW_RESET_REG_SW_RESET);
3232
3233         udelay(10);
3234
3235         /* set "initialization complete" bit to move adapter to D0 state */
3236         ipw_set_bit(priv, IPW_GP_CNTRL_RW, IPW_GP_CNTRL_BIT_INIT_DONE);
3237
3238         IPW_DEBUG_TRACE(">>\n");
3239         return 0;
3240 }
3241
3242 /* Call this function from process context, it will sleep in request_firmware.
3243  * Probe is an ok place to call this from.
3244  */
3245 static int ipw_reset_nic(struct ipw_priv *priv)
3246 {
3247         int rc = 0;
3248         unsigned long flags;
3249
3250         IPW_DEBUG_TRACE(">>\n");
3251
3252         rc = ipw_init_nic(priv);
3253
3254         spin_lock_irqsave(&priv->lock, flags);
3255         /* Clear the 'host command active' bit... */
3256         priv->status &= ~STATUS_HCMD_ACTIVE;
3257         wake_up_interruptible(&priv->wait_command_queue);
3258         priv->status &= ~(STATUS_SCANNING | STATUS_SCAN_ABORTING);
3259         wake_up_interruptible(&priv->wait_state);
3260         spin_unlock_irqrestore(&priv->lock, flags);
3261
3262         IPW_DEBUG_TRACE("<<\n");
3263         return rc;
3264 }
3265
3266
3267 struct ipw_fw {
3268         __le32 ver;
3269         __le32 boot_size;
3270         __le32 ucode_size;
3271         __le32 fw_size;
3272         u8 data[0];
3273 };
3274
3275 static int ipw_get_fw(struct ipw_priv *priv,
3276                       const struct firmware **raw, const char *name)
3277 {
3278         struct ipw_fw *fw;
3279         int rc;
3280
3281         /* ask firmware_class module to get the boot firmware off disk */
3282         rc = request_firmware(raw, name, &priv->pci_dev->dev);
3283         if (rc < 0) {
3284                 IPW_ERROR("%s request_firmware failed: Reason %d\n", name, rc);
3285                 return rc;
3286         }
3287
3288         if ((*raw)->size < sizeof(*fw)) {
3289                 IPW_ERROR("%s is too small (%zd)\n", name, (*raw)->size);
3290                 return -EINVAL;
3291         }
3292
3293         fw = (void *)(*raw)->data;
3294
3295         if ((*raw)->size < sizeof(*fw) + le32_to_cpu(fw->boot_size) +
3296             le32_to_cpu(fw->ucode_size) + le32_to_cpu(fw->fw_size)) {
3297                 IPW_ERROR("%s is too small or corrupt (%zd)\n",
3298                           name, (*raw)->size);
3299                 return -EINVAL;
3300         }
3301
3302         IPW_DEBUG_INFO("Read firmware '%s' image v%d.%d (%zd bytes)\n",
3303                        name,
3304                        le32_to_cpu(fw->ver) >> 16,
3305                        le32_to_cpu(fw->ver) & 0xff,
3306                        (*raw)->size - sizeof(*fw));
3307         return 0;
3308 }
3309
3310 #define IPW_RX_BUF_SIZE (3000)
3311
3312 static void ipw_rx_queue_reset(struct ipw_priv *priv,
3313                                       struct ipw_rx_queue *rxq)
3314 {
3315         unsigned long flags;
3316         int i;
3317
3318         spin_lock_irqsave(&rxq->lock, flags);
3319
3320   &nb